CN107341083A - A kind of verification method of interface controller and checking system - Google Patents
A kind of verification method of interface controller and checking system Download PDFInfo
- Publication number
- CN107341083A CN107341083A CN201710518313.XA CN201710518313A CN107341083A CN 107341083 A CN107341083 A CN 107341083A CN 201710518313 A CN201710518313 A CN 201710518313A CN 107341083 A CN107341083 A CN 107341083A
- Authority
- CN
- China
- Prior art keywords
- data
- test
- controller
- interface
- test data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
The invention discloses a kind of verification method of interface controller and checking system, methods described includes：When either interface controller is verified in chip under test, the initial testing data of generation are sent to mirror controller corresponding to the interface controller using simple driver, triggering mirror controller carries out Data Format Transform to initial testing data and obtains the first test data and be sent to chip under test；Receive the 4th test data that mirror controller returns, 4th test data is that mirror controller handles what is obtained to the 3rd test data progress Data Format Transform, and the 3rd test data is that interface controller performs what Data Format Transform obtained again to the second test data in chip under test；Compare initial testing data and the 4th test data；According to comparative result, the result of the interface controller is determined.Thus achieve the interface controller of the data verification different agreement using simple protocol.
Description
Technical field
The present invention relates to data communication technology field, more particularly to a kind of verification method of interface controller and checking to be
System.
Background technology
In chip design process, it will usually multiple interfaces are configured for the chip, with SOC (System On Chip, on piece
System) exemplified by illustrate, with reference to shown in figure 1, the SOC is provided with UART Controller (Universal
Asynchronous Receiver/Transmitter Controller, universal asynchronous receiving-transmitting transmitter interface controller),
SPI (Serial Peripheral Interface Controller, Serial Peripheral Interface (SPI) controller) and I2C (Inter-
Integrated Circuit Controller, internal integrated circuit interface controller).When designing the SOC, need
Three interface controllers built in it are verified, the agreement followed yet with different interfaces is different, therefore, right
, it is necessary to be verified according to the agreement of the interface to its controller when interface controller is verified, that is, need for different
Interface writes different driver procedures and monitor program etc., thus can increase checking workload etc..
In the prior art when interface controller different in SOC is verified, the checking shown in Fig. 1 is referred to
Principle schematic, verification process is substantially：The test platform is connected by distinct interface with SOC, to verify URAT interface controls
Illustrated exemplified by device processed, the test program that checking URAT interface controllers are write on test platform obtains the survey of UART forms
Data are tried, and test data is sent to UART interface controller, UART interface control by uart test interfaces through UART interface
After device receives test data, the test data form of UART forms is converted into the test data of APB forms and through APB
(Advanced Peripheral Bus, peripheral bus) bus is sent to CPU (Central Processing Unit, center
Processor)；CPU is received and the test data of the APB forms is returned into UART interface control after the test datas of APB forms
Device, UART interface controller are again converted to the test data form of the APB forms test data and warp of UART forms
UART interface feeds back to the uart test interfaces in test platform, and uart test interfaces are by the test number of the UART forms received
According to compared with the test data of the UART forms of transmission, if comparative result is identical, show to the UART interface control
Device processed is verified.If likewise, when being verified to other two interface controllers, it is also desirable to write corresponding test journey
Sequence, then perform above-mentioned verification process.
In summary, because three interface controllers built in SOC connect, it is necessary to write three test programs to these three respectively
Mouth controller is verified, and different interface protocols are different, cause the test program complexity difference write, so as to checking
Personnel bring work load, therefore, how using the unified simple test program checking distinct interface controller of sequential, and then
The workload for reducing checking personnel is one of technical problem urgently to be resolved hurrily.
The content of the invention
The embodiment of the present invention provides a kind of verification method of interface controller and checking system, to utilize unified sequential
Simple test program verifies different interface controllers, and then reduces the workload of checking personnel.
The embodiment of the present invention provides a kind of checking system of interface controller, including：Test platform and at least one mirror image
Controller, each mirror controller are the type configuration of interface controller included according to chip under test, and the mirror image control
Device processed is connected with its type identical interface controller, and the mirror controller is also connected with the test platform, wherein：
The test platform, for when either interface controller is verified in chip under test, generating initial testing
Data, and the initial testing data are sent to mirror image corresponding to the interface controller using simple driver and controlled
Device；And receive the 4th test data that the mirror controller returns；Compare the initial testing data to survey with the described 4th
Try data；And according to comparative result, determine the result of the interface controller；
The mirror controller, for after the initial testing data are received, being carried out to the initial testing data
Data Format Transform obtains the first test data；And first test data is sent to the chip under test；And receive
The 3rd test data that the chip under test is sent, and Data Format Transform is carried out to the 3rd test data and handles to obtain the
Four test datas, and the 4th test data is sent to the test platform, wherein, the 3rd test data is described
Chip under test performs what Data Format Transform obtained to the second test data again, and second test data is the tested core
Piece performs data format inverse conversion to first test data received and handles what is obtained.
The embodiment of the present invention provides a kind of verification method of test platform side interface controller, including：
When either interface controller is verified in chip under test, initial testing data are generated；And
The initial testing data are sent into mirror image corresponding to the interface controller using simple driver to control
Device, trigger the mirror controller and the first test number is obtained to the initial testing data progress Data Format Transform received
According to, and first test data is sent into the chip under test；And
The 4th test data that the mirror controller returns is received, wherein the 4th test data is the mirror image control
Device processed is carried out at Data Format Transform after the 3rd test data of the chip under test transmission is received to the 3rd test data
What reason obtained, the 3rd test data is that the chip under test performs Data Format Transform again to second test data
Obtain, second test data is that the chip under test performs the processing of data format inverse conversion to first test data
Obtain；
Compare the initial testing data and the 4th test data；And
According to comparative result, the result of the interface controller is determined.
The embodiment of the present invention provides a kind of verification method of mirror controller side interface controller, including：
After the initial testing data that test platform is sent using simple driver are received, to the initial testing
Data carry out Data Format Transform and obtain the first test data, and the initial testing data are the test platform to being tested core
Either interface controller is verified that when generates in piece；
First test data is sent to chip under test；And
The 3rd test data that the chip under test is sent is received, and data format is carried out to the 3rd test data and turned
Change processing and obtain the 4th test data, the second test data is held again wherein the 3rd test data is the chip under test
Row data format is converted to, and second test data is that the chip under test performs data to first test data
Form inverse conversion handles what is obtained；And
4th test data is sent to the test platform, the test platform is triggered and tests number by the described 4th
According to compared with the initial testing data, and according to comparative result, the result of the interface controller is determined.
Beneficial effects of the present invention：
The verification method and checking system of interface controller provided in an embodiment of the present invention, it is any in chip under test to connect
When mouth controller is verified, initial testing data are generated；And the initial testing data are sent out using simple driver
Mirror controller corresponding to giving the interface controller, the mirror controller is triggered to the initial testing data that receive
Carry out Data Format Transform and obtain the first test data, and first test data is sent into the chip under test；And connect
The 4th test data that the mirror controller returns is received, is being received wherein the 4th test data is the mirror controller
Data Format Transform is carried out to the 3rd test data after the 3rd test data sent to the chip under test and handles what is obtained, institute
State the 3rd test data chip under test Data Format Transform is performed again to second test data and obtain, it is described
The second test data chip under test performs data format inverse conversion to first test data and handles to obtain；Compare
The initial testing data and the 4th test data；And according to comparative result, determine the result of the interface controller.
Using method provided by the invention, the unified test data of interface protocol can be utilized to realize to different types of interface controller
Checking, and used agreement is simpler relative to the interface protocol sequential in chip under test, is easy to write, debugs drive
Dynamic and capture program, the verification efficiency of interface controller is effectively increased, reduce the workload of checking personnel, improve identifier
Member's experience；In addition, the mirror controller is realized with interface controller by identical code, it is not necessary to it is separately encoded for its, because
This increase mirror controller will not equally increase the workload of checking personnel.
Other features and advantages of the present invention will be illustrated in the following description, also, partly becomes from specification
Obtain it is clear that or being understood by implementing the present invention.The purpose of the present invention and other advantages can be by the explanations write
Specifically noted structure is realized and obtained in book, claims and accompanying drawing.
Brief description of the drawings
Accompanying drawing described herein is used for providing a further understanding of the present invention, forms the part of the present invention, this hair
Bright schematic description and description is used to explain the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings：
Fig. 1 is the principle schematic verified in the prior art to multiple interface controllers in ASIC；
Fig. 2 a are one of structural representation of checking system of interface controller that the embodiment of the present invention one provides；
Fig. 2 b are the two of the structural representation of the checking system for the interface controller that the embodiment of the present invention one provides；
Fig. 2 c are the three of the structural representation of the checking system for the interface controller that the embodiment of the present invention one provides；
Fig. 2 d are the schematic diagram of annexation between the interface controller and mirror controller that the embodiment of the present invention one provides；
Fig. 3 is that the checking system for the interface controller that the embodiment of the present invention one provides is verified to the interface that ASIC is included
Structural representation；
Fig. 4 is what the checking system for the interface controller that the embodiment of the present invention one provides was verified to SERDES controllers
Structural representation；
Fig. 5 is the schematic flow sheet of the verification method for the test platform side interface controller that the embodiment of the present invention two provides；
Fig. 6 is the flow signal of the verification method for the mirror controller side interface controller that the embodiment of the present invention three provides
Figure；
Fig. 7 is the schematic flow sheet of the verification method for the chip under test side interface controller that the embodiment of the present invention four provides.
Embodiment
The embodiment of the present invention provides a kind of verification method of interface controller and checking system, to utilize unified sequential
Simple test program verifies different interface controllers, and then reduces the workload of checking personnel.
The preferred embodiments of the present invention are illustrated below in conjunction with Figure of description, it will be appreciated that described herein
Preferred embodiment is merely to illustrate and explain the present invention, and is not intended to limit the present invention, and in the case where not conflicting, this hair
The feature in embodiment and embodiment in bright can be mutually combined.
Herein, it is to be understood that in involved term：
1st, initial testing data：The data are that sequential caused by test platform is simpler relative to the agreement of interface to be measured
The test data of unified interface agreement.
2nd, the first test data：It can be understood as controlling when initial test data enters mirror image corresponding to interface controller
After device, after the initial testing data conversion, will be obtained by mirror controller can be in the interface controller of chip under test and this
The test data transmitted between mirror controller corresponding to interface controller.
3rd, the second test data：It can be understood as the interface controller being input to when the first test data in chip under test
Afterwards, the test data by interface controller by first test data conversion for the better simply unified interface agreement of sequential.
4th, the 3rd test data：It can be understood as when the second test data is transferred to such as CPU chips inner joint controller
After connected module, CPU transmits it to the interface controller again after carrying out a series of verifications to second test data
Afterwards, second test data performs to obtain after Data Format Transform can be in interface controller again by the interface controller
What is transmitted between mirror controller meets the test data of interface controller agreement to be measured.
5th, the 4th test data：It can be understood as the 3rd test data to input to mirror controller, by mirror controller
It is can be transmitted between mirror controller and test platform, the better simply unification of sequential by the 3rd test data conversion
The test data of interface protocol.
Embodiment one
As shown in Figure 2 a, the structural representation of the checking system of the interface controller provided for the embodiment of the present invention one, bag
Include：Test platform 1 and at least one mirror controller 2i (i is between 1 between n), each mirror controller 2i are according to tested
The type configuration for the interface controller 3i that chip 3 includes, and the mirror controller 2i and its type identical Interface Controller
Device 3i is connected, and the mirror controller is also connected with the test platform 1, wherein：
The test platform 1, in chip under test 3 either interface controller 3i (i is between 1 between n) carry out
During checking, initial testing data are generated, and the initial testing data are sent to the interface control using simple driver
Mirror controller 2i corresponding to device 3i processed；And receive the 4th test data that the mirror controller 2i is returned；Compare described
Initial testing data and the 4th test data；And according to comparative result, determine the result of the interface controller；
When it is implemented, for different interface controllers, test platform 1 can utilize the relatively simple unified interface of sequential
Protocol-driven initial testing data, for the test program of the interface controller used in the prior art, the present invention carries
The method of confession avoids the program that different agreement is write for every kind of interface controller to be measured first, the interface protocol one secondly used
As sequential it is simpler, it is easier to write driving and capture program, can effectively mitigate the workload of checking personnel.
In addition, for different chip under test, simple driver that test platform 1 utilizes can with it is identical can not also
Together, depending on the interface controller type included with specific reference to chip under test.
The mirror controller 2i, for after the initial testing data are received, entering to the initial testing data
Row data format is converted to the first test data；And first test data is sent to the chip under test 3；And connect
The 3rd test data that the chip under test 3 is sent is received, and Data Format Transform is carried out to the 3rd test data and handled
The test platform 1 is sent to the 4th test data, and by the 4th test data, wherein, the 3rd test data
Interface controller 3i performs Data Format Transform to the second test data and obtained again in the chip under test 3, and described
Two test datas are that interface controller 3i performs data format to first test data received in the chip under test
Inverse conversion handles what is obtained.
When it is implemented, the mirror controller in the embodiment of the present invention one corresponds with interface controller, i.e., according to quilt
Survey each interface controller for including in chip and configure a type identical mirror controller, and each interface controller and its
Type identical mirror controller is connected.
When it is implemented, the test platform 1, if specifically for the comparative result be the initial testing data with
4th test data is consistent, it is determined that interface controller 3i is verified；If the comparative result is described initial
Test data and the 4th test data are inconsistent, it is determined that interface controller 3i checkings do not pass through.
Specifically, mirror controller corresponding to each interface controller, its structure is identical with interface controller structure, function
It is corresponding to interface controller, such as during this data transfer to interface controller, the function of interface controller is to perform data lattice
Formula by A to B conversion, when the data transfer after by conversion to mirror controller, the function of mirror controller be perform from B to
A conversion.
Specifically, the data type that either interface controller inputs with mirror controller and output requires is different, therefore
The data type that can be transmitted the Data Format Transform of input into output by interface controller or mirror controller is needed, such as will
Data of the mirror controller by the Data Format Transform of APB forms into UART forms, or UART interface controller is by UART lattice
Data for being converted into APB forms of formula etc..
It is preferred that the external interface 4 with uniform protocol is provided between the test platform 1 and mirror controller；With
And mirror controller 2i passes through the external interface 4 with uniform protocol and the test platform corresponding to each interface controller 3i
1 is connected；With reference to shown in figure 2b,
The test platform 1, specifically for when either interface controller 3i is verified in chip under test, will generate
Initial testing data be sent to the Interface Controller using the simple driver warp external interface 4 with uniform protocol
Mirror controller 2i corresponding to device 3i；And receive the mirror controller 2i and returned through the external interface 4 with uniform protocol
The 4th test data.
Specifically, the external interface with uniform protocol can be, but not limited to as APB buses, AHB (Advanced
High-performance Bus, high performance bus) bus etc..
When it is implemented, each mirror controller is connected to test platform 1 by the external interface 4 with uniform protocol
When, test platform 1 can be that each mirror controller distributes unique port numbers, thus distinguish each mirror controller, and mirror
As controller is connected with interface controller again, therefore, when being verified to either interface controller, can by port numbers to
Mirror controller corresponding to port numbers sends initial testing data.It is of course also possible to the same time is right respectively to multiple port numbers
The mirror controller answered sends initial testing data, realizes the checking to multiple interface controllers.
Further, the interface controller 3i controls at least one interface, mirror image corresponding to the interface controller 3i
Controller 2i controls at least one mirror image interface, wherein each interface in the interface controller 3i, for utilizing signal wire
Interface type identical mirror image interface is connected in mirror controller 2i corresponding with the interface controller 3i, the mirror image control
The corresponding interface controller of device is realized by identical code, with reference to shown in figure 2c：
When it is implemented, at least one interface shown in Fig. 2 c can be understood as comprising the control of each interface controller
At least one interface that mirror controller corresponding at least one interface, each interface controls, and controlled for connecting interface
The signal wire of the interface of the interface mirror controller control corresponding with interface controller of device control, can be with interface controller 31
Illustrated exemplified by connection between corresponding mirror controller 21, its at least one interface controlled can be by Fig. 2 d tables
Show.
Specifically, for the interface class of the either interface of interface controller 31, and connected mirror controller 21
Type is identical, and model is consistent.If for example, the interface controller be SERDES (be Serializer serializers with
The abbreviation of Deserializer deserializers), the SERDES controls two interfaces, respectively sgmii interfaces and xaui interfaces, with it
The mirror image SERDES of connection two interfaces also should be sgmii interfaces and xaui interfaces, and the sgmii interfaces of SERDES controls with
The sgmii of mirror image SERDES controls is connected using the signal wire of sgmii types；The xaui interface and mirror image of same SERDES controls
The xaui interfaces of SERDES controls are connected using the signal wire of xaui types.
It is preferred that include the situation of at least one interface for interface controller, due to interface controller include it is each
The interface protocol of interface is different, therefore, when being verified to the interface controller comprising multiple interfaces, it is necessary to through each interface
The checking of interface controller is completed, and the interface protocol of each interface is possible to different, therefore test platform 1 is needed by caused by
Each initial testing data are sent to the external interface with uniform protocol using different drivers, according still further to said process
Achieve a butt joint the checking of mouthful controller.
For example, because SERDES controllers have two interfaces, when being verified to SERDES controllers, it is necessary to set
Two external interfaces with simple protocol, respectively sgmii interfaces and xaui interfaces；Then be utilized respectively sgmii interfaces and
Xaui interfaces verify to SERDES controllers, and because sgmii interfaces and xaui interfaces belong to different types of interface, need
Caused initial testing data under respective interface protocol are sent to mirror image SERDES using different drivers, to realize
Checking to SERDES controllers, specific verification method are subsequently described in detail.
It is preferred that the corresponding interface controller of the mirror controller is realized by identical code, that is to say, that
In practical application scene, for the code phase of the code and the interface controller of the mirror controller of each interface controller configuration
Together, only need to dissolve a mirror controller using the interface controller example, and in chip under test interface controller code
Have to write, therefore newly-increased mirror controller only needs to replicate the code of the interface controller and example obtains, no
Need to write the code of mirror controller again, i.e., using method provided by the invention, although having increased mirror controller newly, by
In its code replicated from interface controller, without verifying that personnel write again, alleviate checking personnel writes burden；
Further, since mirror controller is increased newly so that when docking port controller is verified, need to only use sequential simply and uniformly
Agreement caused by test program the interface controller is verified by mirror controller, greatly reduce the work of checking personnel
Amount, improve the operating efficiency of checking personnel.
When it is implemented, the mirror controller 2i, is surveyed specifically for the mirror image interface controlled by it by described first
The interface that examination data are sent in the chip under test 3, are connected with the mirror image interface；And in the reception chip under test 3,
The 3rd test data that the interface being connected with the mirror image interface is sent, wherein the 3rd test data is the chip under test
3 pair of second test data performs what Data Format Transform obtained again, and second test data is the chip under test 3
Data format is performed to first test data using the interface controller 3i after first test data is received
Inverse conversion handles what is obtained.
Further, the 3rd test data is the chip under test 3 leading to second test data execution
Code check, and/or frame length verification, and/or CRC (Cyclic Redundancy Check, CRC) processing, and
The leading code check, and/or frame length verification are determined, and/or the check results of CRC check are after verifying correctly, to institute
State the second test data and perform what Data Format Transform obtained again.
Specifically, chip under test 3 also includes CPU and the internal interface with uniform protocol in Fig. 2 c, wherein：
The internal interface with uniform protocol, the second test number sent for receiving the interface controller 3i
According to, and it is sent to the CPU；And
The CPU, for after second test data is received, lead code school to be performed to second test data
Test, and/or frame length verification, and/or cyclic redundancy check (CRC) processing, and when verifying successfully, by second test data
The interface controller 3i is sent to through the internal interface with uniform protocol, is surveyed by the interface controller 3i to described second
Examination data carry out Data Format Transform and obtain second test data being sent to mirror controller 2i again.
It should be noted that when CPU is performing checking procedure to the second test data, without determining the second test data
Verification it is correct after, then the second test data fed back into interface controller, for example, due to the second test data may have it is some
Individual data packet group is into when verifying unsuccessful, CPU only need to be by unsuccessful data packet discarding, then by remaining packet weight
Newly it is defined as the second test data and feeds back to interface controller, subsequent treatment is performed by interface controller.In addition, when the second survey
When the packet that examination packet contains verifies unsuccessfully, a verification failure command can be fed back to interface controller, through mirror image control
Device processed sends test platform to, when test platform receives the inspection failure command, you can be shown to checking personnel so that checking
Personnel's docking port controller is safeguarded.
For a better understanding of the present invention, the embodiment of the present invention one illustrates so that chip under test is SOC as an example, and this is sent out
The method of bright offer is applied to verify three interface controllers including in SOC, its structural representation as shown in figure 3,
Including test platform, the external interface with uniform protocol being connected with test platform, in chip under test SOC comprising CPU, have
Internal interface and UART interface controller UART Controller, the SPI interface controller SPI of uniform protocol
Controller and I2C interface controller I2C Controller, each interface controller control an interface, such as UART interface
Controller controls UART interface, SPI interface controller control SPI interface and I2C interface controller control I2C interface；
In addition, three mirror controllers are respectively configured for three interface controllers that SOC is included, it is specially：Connect for UART
Mouth controller configures mirror image UART interface controller BFM UART Controller, configures one for SPI interface controller
Mirror image SPI interface controller BFM SPI Controller, and configure a mirror image I2C interface control for I2C interface controller
Device BFM I2C Controller processed.
Illustrated so that UART interface controller during test platform is to SOC is verified as an example, test platform generation
Initial testing data, then initial testing data are passed through with unified using simple and unified driver using port numbers
The external interface of agreement is sent to mirror image UART interface controller corresponding to port numbers.
It is preferred that because the UART interface, SPI interface and the I2C interface that are included in SOC are low-speed interface, and APB
Bus, compared with AHB and asb bus, relatively it is applied to transmission low speed data, therefore, there is the internal interface of uniform protocol in SOC
Usually APB buses.Correspondingly, when interface controller is verified in SOC, the tool in checking system provided by the invention
The external interface for having uniform protocol should be APB buses.
Illustrated by taking APB buses as an example, mirror image UART interface controller is when receiving initial testing data, due to this
Initial testing data are APB forms, in order to transmit the initial survey, it is necessary to by the APB forms on UART data wires
Try data and carry out Data Format Transform into the first test data of UART forms, be then sent to UART interface control through UART interface
Device processed, after the UART interface controller receives the first test data, due to there is unification in UART interface controller and SOC
The internal interface connection of agreement, in order to the internal interface agreement that meets there is uniform protocol, it is necessary to again by UART forms
The first test data conversion into APB forms the second test data, and by second test data through having uniform protocol
Internal interface be sent to CPU, CPU performs lead code school after the second test data is received, to second test data
Test, and/or frame length verification, and/or cyclic redundancy check (CRC) processing, and determining the leading code check, and/or frame
Length check, and/or the CRC check check results it is correct when, second test data is passed through with uniform protocol
Internal interface is sent to UART interface controller again；Again, UART interface controller is receiving second test data
Afterwards, in order to being transmitted on UART data wires, it is also necessary to which second test data conversion is surveyed into the 3rd of UART forms
Data are tried, and the 3rd test data of the UART forms is sent to mirror image UART interface controller by UART interface.
The mirror image UART interface controller after the 3rd test data of the UART forms is received, in order to
Transmitted in mirror image APB buses, the 4th test data by the 3rd test data conversion of the UART forms into APB forms, so
The 4th test data of the APB forms is sent to test platform afterwards.
The test platform produces the 4th test data and test platform after the 4th test data is received
Raw initial testing data are compared, if it is determined that it is identical with the initial testing data to go out the 4th test data, then
It is determined that the interface controller is verified；Otherwise determine not pass through interface controller checking.
Similarly, test platform can generate initial testing data corresponding to other two interface controllers, then right respectively
Other two interface controllers are verified in SOC, it is achieved thereby that producing initial survey using unified and simple interface routine
Data are tried, and the checking to multiple interfaces controller is realized using initial testing data, avoid checking personnel for different
Interface controller writes the generation of the higher problem of workload caused by different test programs.
It is preferred that in order to fully understand the external interface with uniform protocol set in the embodiment of the present invention and mirror image control
The function of device processed, there is unified external interface by using provided by the invention, the simple interface testing of agreement can be utilized
The complicated interface of agreement, specifically illustrated so that interface controller is SERDES controllers as an example, the SERDES controllers include
Two interfaces, sgmii interfaces and xaui interfaces, wherein, xaui interfaces and sgmii interfaces are the interface of complex protocol, and it is surveyed
It is complex to try program, by using method provided by the invention, two sequential can be set simple and with uniform protocol
External interface, the gmii interfaces respectively with uniform protocol and the xgmii interfaces with uniform protocol are simpler using agreement
Interface gmii corresponding to the complicated sgmii interfaces of initial testing data test agreement, and utilize the better simply interface of agreement
The complicated xaui interfaces of initial testing data test agreement corresponding to xgmii, realize the checking of SERDES controllers.
Specifically, Fig. 4 is that interface controller SERDES controls the interface controller of two interfaces to verify that the structure of system is shown
It is intended to, specifically utilizes the checking system checking SERDES controllers of interface controller provided by the invention.SERDES controllers should
In certain three-tier switch chip MAC, the SERDES controllers in exchanger chip are verified.The interface controller
Multiple GE (1G) and XG (20G) Ethernet interface can be controlled.In addition, ge_phy uses sgmii interfaces, xg phy use xaui
Interface, and because SERDES controllers include multiple interfaces, and the complex time degree that corresponding different interface is write is different, uses
When prior art is verified to SERDES controllers, realize that difficulty is higher, to verifying that the work load of personnel brings pressure.
And when being verified using checking system provided by the invention to SERDES controllers, only need test platform to write one
The individual simple interface routine of sequential is that the checking to SERDES controllers can be achieved, and is specially：It is outside in Fig. 4 with reference to shown in figure 4
Gmii and xgmii interface sequences for sgmii it is simple, it is easy to accomplish (using port numbers distinguish gmii and xgmii,
For example, port numbers corresponding to gmii are port 1), illustrated, tested exemplified by verifying SERDES controllers by gmii interfaces
Caused initial testing data are sent to mirror image SERDES controller BFM SERDES by platform through gmii corresponding to port 1；Such as
The ge_sds0 being sent in BFM SERDES, parallel serial conversion processing is performed by ge_sds0, and by the initial testing of gmii forms
Data carry out Data Format Transform into the first test data of sgmii forms；And by first test data through sgmii interfaces
The SERDES controllers being sent to inside exchanger chip；Ge_sds0 in SERDES controllers is receiving the first test number
According to rear, serial to parallel conversion processing is performed to first test data, and performs inverse conversion processing, i.e., by the first of sgmii forms
Test data conversion is the second test data of gmii forms, and is sent to GE_MAC, and GE_MAC is to second test data
Leading code check, and/or frame length verification, and/or CRC check are performed, and when it is correct to determine check results, by described in
Second test data feeds back to the ge_sds0 in SERDES again, and parallel serial conversion processing is performed to the second test data by ge_sds0
The 3rd test data of sgmii forms is obtained with data conversion treatment, and sends the 3rd test data through sgmii interfaces
Serial to parallel conversion sum is performed to the ge_sds0 in BFM SERDES controllers, then by the ge_sds0 in BFM SERDES controllers
The 4th test data of gmii forms is obtained according to conversion process, is then sent to test platform, what test platform relatively received
Whether the 4th test data and caused initial testing data are consistent, determine to lead to SERDES controller verifications if consistent
Cross；Otherwise determine not pass through SERDES controller verifications.
Equally, when being verified using the better simply xgmii interfaces of sequential to SERDES, test platform can also utilize
Initial testing data are verified by xgmii interfaces to SERDES controllers, detailed process and the verification process of gmii interfaces
It is identical, no longer describe herein, so far initial testing data corresponding to the simple interface of sequential can be utilized to realize to complex time
Interface controller checking, effectively reduce the workload of checking personnel.
It should be noted that when being verified respectively to SERDES controllers by gmii and xgmii respectively, it is necessary to profit
Respective initial testing data are sent to mirror image through gmii interfaces or xgmii interfaces respectively with different but simple driver
SERDES controllers, and then the checking to SERDES controllers is realized respectively, although make use of different drivers, due to
The interface protocol of gmii interfaces and xgmii interfaces is simple relative to the interface protocol of sgmii and xaui interfaces, is realized and is based on this
Caused initial testing data realize the checking to SERDES controllers under simple interface agreement.
The checking system for the interface controller that the embodiment of the present invention one provides, including：Test platform, be provided with it is at least one
The chip under test of interface controller, and for each interface controller configure a mirror controller, the mirror controller with
Its corresponding interface controller is connected, and the mirror controller is also connected with the test platform, wherein：The test is flat
Platform, initially surveyed for when either interface controller is verified in chip under test, generating initial testing data, and by described
Examination data are sent to mirror controller corresponding to the interface controller using simple driver；And receive the mirror image control
The 4th test data that device processed returns；Compare the initial testing data and the 4th test data；And according to comparative result,
Determine the result of the interface controller；The mirror controller, for after the initial testing data are received, to institute
State initial testing data progress Data Format Transform and obtain the first test data；And first test data is sent to described
Chip under test；And the 3rd test data that the chip under test is sent is received, and data are carried out to the 3rd test data
Format conversion processing obtains the 4th test data, and the 4th test data is sent into the test platform；It is described tested
Chip, for after first test data is received, data format inverse conversion to be performed to the first test data received
Processing, obtain the second test data；And second test data is performed into Data Format Transform again and obtains the 3rd test
Data Concurrent gives the mirror controller.Using checking system provided by the invention, avoid checking personnel and be directed to complexity
Different interface controllers need to write different test programs the occurrence of, only need to be write simply using unified interface agreement
Test program various interface controllers are verified, not only reduce the complexity for verifying each interface controller, also have
The workload of checking personnel is reduced to effect, while also improves the flexibility of checking, more improves the working body of checking personnel
Test.
Embodiment two
As shown in figure 5, the flow of the verification method of the test platform side interface controller provided for the embodiment of the present invention two
Schematic diagram, it may comprise steps of：
S11, when either interface controller is verified in chip under test, generate initial testing data.
S12, the initial testing data are sent to mirror image corresponding to the interface controller using simple driver
Controller.
When it is implemented, when the initial testing data are sent into mirror controller, the mirror image control can be triggered
Device processed carries out Data Format Transform to the initial testing data received and obtains the first test data, and described first is surveyed
Examination data are sent to mirror controller corresponding to the interface controller.
S13, receive the 4th test data that the mirror controller returns.
Wherein, the 4th test data is that the mirror controller is surveyed in receive the chip under test transmission the 3rd
Data Format Transform is carried out to the 3rd test data after examination data and handles what is obtained, the 3rd test data is the tested core
Piece performs what Data Format Transform obtained again to second test data, and second test data is the chip under test
Data format inverse conversion is performed to first test data and handles what is obtained.
Initial testing data described in S14, comparison and the 4th test data.
S15, according to comparative result, determine the result of the interface controller.
When it is implemented, according to comparative result, the result of the interface controller is determined, is specifically included：
If the comparative result is that the initial testing data are consistent with the 4th test data, it is determined that the interface
Controller verification passes through；
If the comparative result is that the initial testing data and the 4th test data are inconsistent, it is determined that this connects
Mouth controller verification does not pass through.
Further, the initial testing data are sent to mirror controller corresponding to the interface controller, specific bag
Include：
The initial testing data are passed through into the external interface with uniform protocol using simple driver and are sent to this
Mirror controller corresponding to interface controller；And
The 4th test data that the mirror controller returns is received, is specifically included：
Receive the mirror controller and pass through the 4th test data that the external interface with uniform protocol returns.
When it is implemented, step S11~S15 execution may be referred in the embodiment of the present invention one in the embodiment of the present invention two
Implementation, repeat part repeat no more.
The verification method for the interface controller that the embodiment of the present invention two provides, the either interface controller in chip under test
When being verified, initial testing data are generated；And the initial testing data are sent to this using simple driver and connect
Mirror controller corresponding to mouth controller, trigger the mirror controller and data are carried out to the initial testing data received
Form is converted to the first test data, and first test data is sent into the chip under test；And receive the mirror
As the 4th test data that controller returns, wherein the 4th test data, which is the mirror controller, is receiving the quilt
Survey after the 3rd test data that chip is sent and what is obtained is handled to the 3rd test data progress Data Format Transform, the described 3rd surveys
The examination data chip under test performs Data Format Transform to second test data and obtained again, second test
The data chip under test performs data format inverse conversion to first test data and handles to obtain；Compare described initial
Test data and the 4th test data；And according to comparative result, determine the result of the interface controller.Using this hair
The method of bright offer, it can be based on producing the simple test data realization of sequential under unified interface agreement to different types of interface
The checking of controller, and used agreement is simpler relative to the interface protocol sequential in chip under test, be easy to write,
Debugging driving and capture program, the verification efficiency of interface controller is effectively increased, avoiding checking personnel needs for difference
Interface write different test programs the occurrence of, largely reduce the workload of checking personnel, improve identifier
Member's experience.
Embodiment three
As shown in fig. 6, the stream of the verification method of the mirror controller side interface controller provided for the embodiment of the present invention three
Journey schematic diagram, may comprise steps of：
S21, after the initial testing data that test platform is sent using simple driver are received, to described initial
Test data carries out Data Format Transform and obtains the first test data.
Wherein, the initial testing data are that test platform either interface controller in chip under test is tested
Generated during card.
S22, first test data is sent to chip under test.
S23, the 3rd test data that the chip under test is sent is received, and data lattice are carried out to the 3rd test data
Formula conversion process obtains the 4th test data.
Wherein, the 3rd test data is that the chip under test performs Data Format Transform again to the second test data
Obtain, second test data is that the chip under test performs the processing of data format inverse conversion to first test data
Obtain.
S24, the 4th test data is sent to the test platform.
When it is implemented, when performing step S24, trigger the test platform by the 4th test data with it is described just
Beginning test data is compared, and according to comparative result, determines the result of the interface controller.
When it is implemented, step S21~S24 implementation may be referred in the embodiment of the present invention one in the embodiment of the present invention three
Implementation procedure, repeat part repeat no more.
The verification method of mirror controller side interface controller provided in an embodiment of the present invention, receiving test platform profit
After the initial testing data sent with simple driver, Data Format Transform is carried out to the initial testing data and obtains the
One test data, the initial testing data are that test platform either interface controller in chip under test is verified
Shi Shengcheng's；First test data is sent to chip under test；And receive the 3rd test that the chip under test is sent
Data, and Data Format Transform is carried out to the 3rd test data and handles to obtain the 4th test data, wherein the described 3rd surveys
The examination data chip under test performs Data Format Transform to the second test data and obtained again, second test data
The chip under test performs data format inverse conversion to first test data and handles to obtain；And the described 4th is tested
Data are sent to the test platform, trigger the test platform and enter the 4th test data with the initial testing data
Row compares, and according to comparative result, determines the result of the interface controller.The side provided using the embodiment of the present invention three
Method, by setting a mirror controller to each interface controller in chip under test, it can be write based on unified interface agreement
Initial testing data caused by the simple test program of sequential realize the checking to different types of interface controller, and are adopted
Agreement is simpler relative to the interface protocol sequential in chip under test, is easy to write, debugs driving and capture program, has
Effect improves the verification efficiency of interface controller, while also reduces the complexity for verifying each interface controller and reduce and test
The workload of witness person.
Example IV
As shown in fig. 7, the flow of the verification method of the chip under test side interface controller provided for the embodiment of the present invention four
Schematic diagram, it may comprise steps of：
S31, receive the first test data that mirror controller is sent.
Wherein, first test data is that the mirror controller is receiving test platform using simple driving journey
It is converted to after the initial testing data that sequence is sent, and the initial testing data are the test platform to quilt
Survey either interface controller in chip and verified that when generates, the mirror controller is corresponding with the interface controller.
S32, inverse conversion processing is performed to the first test data received, obtain the second test data.
S33, perform Data Format Transform again to second test data and obtain the 3rd test data and be sent to institute
State mirror controller.
When it is implemented, step S32 and S33 are performed by interface controller in chip under test, to realize in chip under test
The checking of interface controller.
When it is implemented, after the 3rd test data is sent into mirror controller, the mirror controller pair is triggered
The 3rd test data received carries out Data Format Transform and handles to obtain the 4th test data, and the described 4th is tested
Data are sent to the test platform, trigger the test platform and enter the 4th test data with the initial testing data
Row compares, and according to comparative result, determines the result of the interface controller.
It is preferred that obtain the 3rd test data second test data is performed into Data Format Transform again and send
Before the mirror controller, in addition to：
Leading code check, and/or frame length verification, and/or cyclic redundancy check (CRC) are performed to second test data
Processing；And
The leading code check, and/or frame length verification, and/or the check results of CRC check are determined to verify correctly.
When it is implemented, step S31~S33 implementation may be referred in the embodiment of the present invention one in the embodiment of the present invention four
Implementation procedure, repeat part repeat no more.
The verification method for the chip under test side interface controller that the embodiment of the present invention four provides, receive mirror controller and send
The first test data, wherein first test data, which is the mirror controller, is receiving test platform using simple
It is converted to after the initial testing data that driver is sent, and the initial testing data are the test platform
Verify that when generates in either interface controller in chip under test, the mirror controller and the interface controller pair
Should；Inverse conversion processing is performed to the first test data received, obtains the second test data；And test number by described second
According to being converted to the 3rd test data again and be sent to the mirror controller, the mirror controller is triggered to receiving
3rd test data carries out conversion process and obtains the 4th test data, and the 4th test data is sent into the survey
Try platform, trigger the test platform by the 4th test data compared with the initial testing data, and according to than
Relatively result, determine the result of the interface controller.The method provided using the embodiment of the present invention four, it can not only be based on system
One interface protocol is write initial testing data caused by the simple test program of sequential and realized to different types of interface controller
Checking, also effectively increase the verification efficiency of interface controller, meanwhile, also reduce the complexity for verifying each interface controller
Spend and reduce the workload of checking personnel.
It should be understood by those skilled in the art that, embodiments of the invention can be provided as method, system or computer program
Product.Therefore, the present invention can use the reality in terms of complete hardware embodiment, complete software embodiment or combination software and hardware
Apply the form of example.Moreover, the present invention can use the computer for wherein including computer usable program code in one or more
The computer program production that usable storage medium is implemented on (including but is not limited to magnetic disk storage, CD-ROM, optical memory etc.)
The form of product.
The present invention is the flow with reference to method according to embodiments of the present invention, equipment (system) and computer program product
Figure and/or block diagram describe.It should be understood that can be by every first-class in computer program instructions implementation process figure and/or block diagram
Journey and/or the flow in square frame and flow chart and/or block diagram and/or the combination of square frame.These computer programs can be provided
The processors of all-purpose computer, special-purpose computer, Embedded Processor or other programmable data processing devices is instructed to produce
A raw machine so that produced by the instruction of computer or the computing device of other programmable data processing devices for real
The device for the function of being specified in present one flow of flow chart or one square frame of multiple flows and/or block diagram or multiple square frames.
These computer program instructions, which may be alternatively stored in, can guide computer or other programmable data processing devices with spy
Determine in the computer-readable memory that mode works so that the instruction being stored in the computer-readable memory, which produces, to be included referring to
Make the manufacture of device, the command device realize in one flow of flow chart or multiple flows and/or one square frame of block diagram or
The function of being specified in multiple square frames.
These computer program instructions can be also loaded into computer or other programmable data processing devices so that counted
Series of operation steps is performed on calculation machine or other programmable devices to produce computer implemented processing, so as in computer or
The instruction performed on other programmable devices is provided for realizing in one flow of flow chart or multiple flows and/or block diagram one
The step of function of being specified in individual square frame or multiple square frames.
Although preferred embodiments of the present invention have been described, but those skilled in the art once know basic creation
Property concept, then can make other change and modification to these embodiments.So appended claims be intended to be construed to include it is excellent
Select embodiment and fall into having altered and changing for the scope of the invention.
Obviously, those skilled in the art can carry out the essence of various changes and modification without departing from the present invention to the present invention
God and scope.So, if these modifications and variations of the present invention belong to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprising including these changes and modification.
Claims (10)
- A kind of 1. checking system of interface controller, it is characterised in that including：Test platform and at least one mirror controller, Each mirror controller is the type configuration of interface controller included according to chip under test, and the mirror controller and its Type identical interface controller is connected, and the mirror controller is also connected with the test platform, wherein：The test platform, for when either interface controller is verified in chip under test, generating initial testing data, And the initial testing data are sent to mirror controller corresponding to the interface controller using simple driver；And Receive the 4th test data that the mirror controller returns；Compare the initial testing data and the 4th test data； And according to comparative result, determine the result of the interface controller；The mirror controller, for after the initial testing data are received, data to be carried out to the initial testing data Form is converted to the first test data；And first test data is sent to the chip under test；And described in receiving The 3rd test data that chip under test is sent, and Data Format Transform is carried out to the 3rd test data and handles to obtain the 4th survey Data are tried, and the 4th test data is sent to the test platform, wherein, the 3rd test data is described tested Interface controller performs what Data Format Transform obtained to the second test data again in chip, and second test data is institute State interface controller in chip under test and what is obtained is handled to first test data execution data format inverse conversion received.
- 2. the system as claimed in claim 1, it is characterised in thatThe test platform, if being the initial testing data and the 4th test data specifically for the comparative result Unanimously, it is determined that the interface controller is verified；If the comparative result is the initial testing data and the described 4th Test data is inconsistent, it is determined that interface controller checking does not pass through.
- 3. the system as claimed in claim 1, it is characterised in that being provided between the test platform and mirror controller has The external interface of uniform protocol；And mirror controller is connect by the outside with uniform protocol corresponding to each interface controller Mouth is connected with the test platform；AndThe test platform, specifically for when either interface controller is verified in chip under test, by the initial of generation Test data is sent to the interface controller using the simple driver warp external interface with uniform protocol and corresponded to Mirror controller；And receive the mirror controller and pass through the 4th test number that the external interface with uniform protocol returns According to.
- 4. system as claimed in claim 2, it is characterised in that the interface controller controls at least one interface, described to connect Mirror controller corresponding to mouth controller controls at least one mirror image interface, wherein each interface in the interface controller, For being connected using interface type identical mirror image interface in signal wire mirror controller corresponding with the interface controller, institute The corresponding interface controller of mirror controller is stated to realize by identical code；AndThe mirror controller, first test data is sent to the quilt specifically for the mirror image interface controlled by it The interface survey in chip, being connected with the mirror image interface；And receive in the chip under test, be connected with the mirror image interface The 3rd test data that interface is sent, the second test data is held again wherein the 3rd test data is the chip under test Row data format is converted to, and second test data is that the chip under test is receiving the first test number What is obtained is handled to first test data execution data format inverse conversion using the interface controller according to rear.
- 5. system as claimed in claim 4, it is characterised in that3rd test data is that the chip under test is performing leading code check, and/or frame to second test data Length check, and/or cyclic redundancy check (CRC) processing, and the leading code check is determined, and/or frame length verification, and/or After the check results of CRC check is checkings correctly, what Data Format Transform obtained is performed again to second test data.
- A kind of 6. verification method of interface controller, it is characterised in that including：When either interface controller is verified in chip under test, initial testing data are generated；AndThe initial testing data are sent to mirror controller corresponding to the interface controller using simple driver, touched Send out mirror controller described Data Format Transform is carried out to the initial testing data that receive and obtain the first test data, and First test data is sent to the chip under test；AndThe 4th test data that the mirror controller returns is received, wherein the 4th test data is the mirror controller Data Format Transform is carried out after the 3rd test data of the chip under test transmission is received to the 3rd test data to handle Arriving, the 3rd test data chip under test performs Data Format Transform to the second test data and obtained again, The second test data chip under test performs data format inverse conversion to first test data and handles to obtain；Compare the initial testing data and the 4th test data；AndAccording to comparative result, the result of the interface controller is determined.
- 7. method as claimed in claim 6, it is characterised in that according to comparative result, determine the checking knot of the interface controller Fruit, specifically include：If the comparative result is that the initial testing data are consistent with the 4th test data, it is determined that the Interface Controller Device is verified；If the comparative result is that the initial testing data and the 4th test data are inconsistent, it is determined that the interface control Device checking processed does not pass through.
- 8. method as claimed in claim 6, it is characterised in that the initial testing data are sent to the interface controller pair The mirror controller answered, is specifically included：The initial testing data are passed through into the external interface with uniform protocol using simple driver and are sent to the interface Mirror controller corresponding to controller；AndThe 4th test data that the mirror controller returns is received, is specifically included：Receive the mirror controller and pass through the 4th test data that the external interface with uniform protocol returns.
- A kind of 9. verification method of interface controller, it is characterised in that including：After the initial testing data that test platform is sent using simple driver are received, to the initial testing data Carry out Data Format Transform and obtain the first test data, the initial testing data are the test platform in chip under test Either interface controller is verified that when generates；First test data is sent to chip under test；AndThe 3rd test data that the chip under test is sent is received, and the 3rd test data is carried out at Data Format Transform Reason obtains the 4th test data, wherein the 3rd test data is the chip under test performs number again to the second test data It is converted to according to form, second test data is that the chip under test performs data format to first test data Inverse conversion handles what is obtained；And4th test data is sent to the test platform, trigger the test platform by the 4th test data with The initial testing data are compared, and according to comparative result, determine the result of the interface controller.
- 10. method as claimed in claim 9, it is characterised in that receive what test platform was sent using simple driver Initial testing data, are specifically included：Receive the initial testing data that test platform passes through the external interface transmission with uniform protocol using simple driver； And4th test data is sent to the test platform, specifically included：The external interface with uniform protocol is sent to the test platform by the 4th test data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710518313.XA CN107341083B (en) | 2017-06-29 | 2017-06-29 | Interface controller verification method and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710518313.XA CN107341083B (en) | 2017-06-29 | 2017-06-29 | Interface controller verification method and system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107341083A true CN107341083A (en) | 2017-11-10 |
| CN107341083B CN107341083B (en) | 2020-08-11 |
Family
ID=60218110
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710518313.XA Active CN107341083B (en) | 2017-06-29 | 2017-06-29 | Interface controller verification method and system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107341083B (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108763743A (en) * | 2018-05-28 | 2018-11-06 | 天津芯海创科技有限公司 | Verification platform, method and electronic equipment |
| CN108763676A (en) * | 2018-05-15 | 2018-11-06 | 天津芯海创科技有限公司 | Driving source and function verification method |
| CN108829592A (en) * | 2018-06-01 | 2018-11-16 | 天津芯海创科技有限公司 | The quickly verification method of access register and list item, device and verifying equipment |
| CN109381856A (en) * | 2018-09-12 | 2019-02-26 | 深圳闪电鸟网络科技有限公司 | Device, method, electronic equipment and the storage medium that game host is controlled |
| CN110134099A (en) * | 2018-02-08 | 2019-08-16 | 中车株洲电力机车研究所有限公司 | A kind of test macro and method controlling software |
| CN111355634A (en) * | 2020-02-20 | 2020-06-30 | 北京华力创通科技股份有限公司 | Network interface testing method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101369001A (en) * | 2008-10-17 | 2009-02-18 | 北京星网锐捷网络技术有限公司 | Apparatus used for debugging programmable chip and field programmable gate array chip |
| CN102117070A (en) * | 2011-01-12 | 2011-07-06 | 福州瑞芯微电子有限公司 | Method for testing functions of HIF controller |
| CN102542110A (en) * | 2011-12-29 | 2012-07-04 | 北京时代民芯科技有限公司 | Emulation verification method applied to mobile storage SOC (system on chip) chip |
| US20140244204A1 (en) * | 2013-02-28 | 2014-08-28 | Advantest Corporation | Tester with acceleration for packet building within a fpga block |
-
2017
- 2017-06-29 CN CN201710518313.XA patent/CN107341083B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101369001A (en) * | 2008-10-17 | 2009-02-18 | 北京星网锐捷网络技术有限公司 | Apparatus used for debugging programmable chip and field programmable gate array chip |
| CN102117070A (en) * | 2011-01-12 | 2011-07-06 | 福州瑞芯微电子有限公司 | Method for testing functions of HIF controller |
| CN102542110A (en) * | 2011-12-29 | 2012-07-04 | 北京时代民芯科技有限公司 | Emulation verification method applied to mobile storage SOC (system on chip) chip |
| US20140244204A1 (en) * | 2013-02-28 | 2014-08-28 | Advantest Corporation | Tester with acceleration for packet building within a fpga block |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110134099A (en) * | 2018-02-08 | 2019-08-16 | 中车株洲电力机车研究所有限公司 | A kind of test macro and method controlling software |
| CN108763676A (en) * | 2018-05-15 | 2018-11-06 | 天津芯海创科技有限公司 | Driving source and function verification method |
| CN108763743A (en) * | 2018-05-28 | 2018-11-06 | 天津芯海创科技有限公司 | Verification platform, method and electronic equipment |
| CN108829592A (en) * | 2018-06-01 | 2018-11-16 | 天津芯海创科技有限公司 | The quickly verification method of access register and list item, device and verifying equipment |
| CN108829592B (en) * | 2018-06-01 | 2021-11-05 | 天津芯海创科技有限公司 | Method and device for verifying quick access register and table entry and verification equipment |
| CN109381856A (en) * | 2018-09-12 | 2019-02-26 | 深圳闪电鸟网络科技有限公司 | Device, method, electronic equipment and the storage medium that game host is controlled |
| CN111355634A (en) * | 2020-02-20 | 2020-06-30 | 北京华力创通科技股份有限公司 | Network interface testing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107341083B (en) | 2020-08-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107341083A (en) | A kind of verification method of interface controller and checking system | |
| US20160140006A1 (en) | Testbench builder, system, device and method having agent loopback functionality | |
| CN112579381A (en) | UVM-based UART bus UVM verification system and method | |
| US8504344B2 (en) | Interface between a verification environment and a hardware acceleration engine | |
| JPWO2011001462A1 (en) | Test equipment | |
| Khalilzad et al. | FPGA implementation of real-time Ethernet communication using RMII interface | |
| CN109726800B (en) | Operation method, device and related product | |
| US20230261961A1 (en) | System and method for simulation and testing of multiple virtual ecus | |
| WO2015131697A1 (en) | Method and apparatus for multiplex-frame random data verification | |
| Priyanka et al. | Design of uart using verilog and verifying using uvm | |
| Wiecha et al. | Architecture and design of a Bluetooth low energy controller | |
| JP7337503B2 (en) | test equipment | |
| Mahale et al. | Architecture Analysis and Verification of I3C Protocol | |
| US8149721B2 (en) | Test apparatus and test method | |
| CN101276305B (en) | Automatic test system and method | |
| JP2015011363A (en) | Cooperation verification device and cooperation verification method | |
| CN110908846A (en) | SPI bus verification method | |
| JPH02219151A (en) | Computer input/output system and its channel diagnostics | |
| Dhar et al. | Coverage driven verification of I2C protocol using System Verilog | |
| Prasad et al. | Development of VIP for AMBA AXI-4.0 Protocol | |
| RU2809047C1 (en) | Method for providing asynchronous interaction of equipment when testing input-output devices | |
| Baker | UVM Based Verification of 10 Gigabit Ethernet Transmit | |
| CN115150343B (en) | Exchange chip verification platform device and method based on UVM | |
| CN114564432B (en) | Novel high-speed data SATA interface verification module and method based on FPGA | |
| US20230169226A1 (en) | Method and system for interfacing a testbench to circuit simulation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |