CN107329338B - Array substrate and manufacturing method thereof, display panel and display device - Google Patents
Array substrate and manufacturing method thereof, display panel and display device Download PDFInfo
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- CN107329338B CN107329338B CN201710687887.XA CN201710687887A CN107329338B CN 107329338 B CN107329338 B CN 107329338B CN 201710687887 A CN201710687887 A CN 201710687887A CN 107329338 B CN107329338 B CN 107329338B
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- 239000004020 conductor Substances 0.000 claims description 5
- 239000011810 insulating material Substances 0.000 claims description 4
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical group [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 3
- 230000003068 static effect Effects 0.000 abstract description 28
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- 229910052751 metal Inorganic materials 0.000 description 7
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- 238000002161 passivation Methods 0.000 description 7
- 239000002390 adhesive tape Substances 0.000 description 6
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- 239000004973 liquid crystal related substance Substances 0.000 description 6
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136277—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/133345—Insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/136295—Materials; Compositions; Manufacture processes
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Abstract
The invention discloses an array substrate and a manufacturing method thereof, a display panel and a display device, relates to the technical field of display and aims to reduce the influence of external static electricity on a four-side frameless display panel. The array substrate comprises a substrate, wherein the substrate comprises a frame forming area; the surface of the substrate base plate is provided with a first conducting layer, a first insulating layer is formed on the surface of the first conducting layer, a second conducting layer electrically connected with the ground wire lead is formed on the surface of the first insulating layer corresponding to the frame forming area, and the first conducting layer is electrically connected with the second conducting layer through a third conducting layer. The manufacturing method of the array substrate is used for manufacturing the array substrate provided by the technical scheme. The display panel provided by the invention is used in a display device.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a manufacturing method of the array substrate, a display panel and a display device.
Background
The liquid crystal display is an ultra-thin display device, which not only has low energy consumption, but also has good picture quality, and is widely popular with users. The display panel of the conventional liquid crystal display is generally designed with an anti-static structure to reduce the influence of external static electricity on the liquid crystal display. At present, a common display panel generally includes an array substrate and a color filter substrate which are paired together, and the following two setting modes are provided according to the distance between the array substrate and the display surface, as follows:
the first setting mode is as follows: the array substrate is far away from the display surface, and the color film substrate is close to the display surface, which is commonly found in a display panel with a frame; in order to prevent external static from affecting a display panel, in a modularized stage of manufacturing a liquid crystal display, one end of a conductive adhesive tape is attached to a color film substrate, the other end of the conductive adhesive tape is attached to the position of a silver adhesive point, and the conductive adhesive tape is ensured to be connected with a ground wire lead of the silver adhesive point to form an anti-static structure, so that static accumulated on the color film substrate and an array substrate is released into the ground wire lead by the conductive adhesive tape.
The second setting mode is as follows: the color film substrate is far away from the display surface, the array substrate is close to the display surface, and the structure is often found in a display panel without frames on four sides; however, in the modularized stage of the display panel with such an arrangement, the functional film layer of the array substrate faces downward, and it is difficult to attach the conductive tape according to the first arrangement, which makes the possible ratio of the display panel with four borderless exposed to external static larger, resulting in a reduction in the service life of the display panel with four borderless.
Disclosure of Invention
The invention aims to provide an array substrate, a manufacturing method thereof, a display panel and a display device, so as to reduce the influence of external static electricity on a four-side frameless display panel and prolong the service life of the four-side frameless display panel.
In order to achieve the above purpose, the invention provides the following technical scheme:
an array substrate comprises a substrate base plate, wherein the substrate base plate comprises a frame forming area; the surface of the substrate base plate is provided with a first conducting layer, a first insulating layer is formed on the surface of the first conducting layer, a second conducting layer electrically connected with a ground wire lead is formed on the surface of the first insulating layer corresponding to the frame forming area, and the first conducting layer is electrically connected with the second conducting layer through a third conducting layer.
Compared with the prior art, in the array substrate provided by the invention, the first conducting layer is formed on the surface of the substrate, the first insulating layer is formed on the surface of the first conducting layer, the second conducting layer electrically connected with the ground lead is formed on the surface of the first insulating layer corresponding to the frame forming area, and the first conducting layer and the second conducting layer are electrically connected through the third conducting layer, that is, the first conducting layer is indirectly connected with the ground lead through the third conducting layer and the second conducting layer. At this time, if the array substrate provided by the present invention is applied to a display panel with a structure similar to a four-sided borderless display panel, the first conductive layer of the array substrate is closest to the display surface of the display panel, this makes external static electricity, which is first accumulated in the first conductive layer when it affects the display panel, the first conductive layer is indirectly connected with the ground lead, therefore, the array substrate provided by the invention is applied to the display panel with the structure similar to the four-side frameless display panel, the first conductive layer can lead external static electricity into the ground wire through the ground wire lead wire when the display panel is influenced by the external static electricity without pasting a conductive adhesive tape, therefore, the influence of external static electricity on the display panel with the structure similar to that of the four-side frameless display panel is reduced, and the service life of the display panel with the structure similar to that of the four-side frameless display panel is prolonged.
The invention also provides a manufacturing method of the array substrate, which comprises the following steps:
providing a substrate base plate; the substrate base plate comprises a frame forming area;
a first conductive layer is formed on the surface of the substrate base plate;
forming a first insulating layer on the surface of the first conductive layer;
forming a second conducting layer on the surface of the first insulating layer corresponding to the frame forming area, so that the second conducting layer is connected with the ground wire lead;
forming a third conductive layer over the second conductive layer such that the first conductive layer and the second conductive layer are electrically connected through the third conductive layer.
Compared with the prior art, the manufacturing method of the array substrate provided by the invention has the same beneficial effects as the array substrate provided by the technical scheme, and the details are not repeated herein.
The invention also provides a display panel which comprises the array substrate provided by the technical scheme.
Compared with the prior art, the beneficial effects of the display panel provided by the invention are the same as those of the array substrate provided by the technical scheme, and are not repeated herein.
The invention also provides a display device which comprises the display panel provided by the technical scheme.
Compared with the prior art, the beneficial effects of the display device provided by the invention are the same as those of the display panel provided by the technical scheme, and are not repeated herein.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a manufacturing method of an array substrate according to an embodiment of the present invention;
fig. 3 is a first flowchart of a method for manufacturing an array substrate according to an embodiment of the present invention;
fig. 4 is a second flowchart of a method for manufacturing an array substrate according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
reference numerals:
1-array substrate, 10-substrate;
11-a first conductive layer, 12-a first insulating layer;
120-an insulating layer via, 13-a second conductive layer;
14-isolation layer, 141-isolation layer first via;
142-an isolation layer second via, 15-a third conductive layer;
2-color film substrate, 3-anisotropic conductive adhesive;
AA-display area, BM-non-display area.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1 and 5, an array substrate 1 according to an embodiment of the present invention includes a substrate 10, where the substrate 10 includes a frame forming region, and the frame forming region corresponds to a non-display region BM of the array substrate 1; a first conductive layer 11 is disposed on the surface of the substrate base plate 10, a first insulating layer 12 is formed on the surface of the first conductive layer 11, a second conductive layer 13 electrically connected to the ground lead is formed on the surface of the first insulating layer 12 corresponding to the frame forming region, and the first conductive layer 11 and the second conductive layer 13 are electrically connected through a third conductive layer 15.
The following describes in detail a manufacturing process of an array substrate according to an embodiment of the present invention with reference to fig. 1 to 3.
Step S100: providing a substrate 10; the substrate base plate 10 includes a frame forming region BM; forming a first conductive layer 11 on a surface of a base substrate 10;
step S200: forming a first insulating layer 12 on the surface of the first conductive layer 11;
step S300: forming a second conductive layer 13 on the surface of the first insulating layer 12 corresponding to the frame forming region, so that the second conductive layer 13 is connected with the ground lead;
step S500: a third conductive layer 15 is formed over the second conductive layer 13 so that the first conductive layer 11 and the second conductive layer 13 are electrically connected through the third conductive layer 15.
As shown in fig. 5, when the array substrate 1 provided in the embodiment of the present invention is applied to a display panel, the array substrate 1 and the color filter substrate 2 are paired together, the array substrate 1 is close to a display surface, and the color filter substrate 2 is far from the display surface, that is, a surface of the substrate 10 of the array substrate, which is far from the first conductive layer 11, is used as a light emitting surface of the display panel, that is, a display surface of the display panel. In fig. 5, the liquid crystal layer between the array substrate 1 and the color filter substrate 2 is omitted, but does not mean that the liquid crystal layer does not exist.
When an external static electricity test or use is performed, external static electricity is firstly accumulated in the first conductive layer 11, the first conductive layer 11 and the second conductive layer 13 are electrically connected through the third conductive layer 15, and the second conductive layer 13 is connected with a ground lead, so that the external static electricity accumulated in the first conductive layer 11 can be discharged into the ground through the third conductive layer 15 and the second conductive layer 13, and the influence of the external static electricity on the display panel is reduced.
Based on the structure of the array substrate and the external static electricity prevention process provided in the above embodiments, a first conductive layer 11 is formed on the surface of the substrate 10, a first insulating layer 12 is formed on the surface of the first conductive layer 11, a second conductive layer 13 electrically connected to the ground lead is formed on the surface of the first insulating layer 12 corresponding to the frame forming region, and the first conductive layer 11 and the second conductive layer 13 are electrically connected through a third conductive layer 15, that is, the first conductive layer 11 is indirectly connected to the ground lead through the third conductive layer 15 and the second conductive layer 13. At this time, if the array substrate 1 provided by the embodiment of the present invention is applied to a display panel with a structure similar to a four-sided borderless display panel (the array substrate 1 is close to the display surface, and the color filter substrate 2 is far from the display surface), the first conductive layer 11 of the array substrate 1 is closest to the display surface of the display panel, so that when external static electricity affects the display panel, the external static electricity is firstly accumulated in the first conductive layer 11, and the first conductive layer 11 is indirectly connected to the ground wire lead, therefore, the array substrate provided by the present invention is applied to a display panel with a structure similar to a four-sided borderless display panel, and when the display panel is affected by the external static electricity, the first conductive layer 11 can introduce the external static electricity into the ground wire through the ground wire lead without attaching a conductive tape, thereby reducing the influence of the external static electricity on the display panel with a structure similar to a four-sided borderless display panel, the service life of the display panel with the structure similar to that of the four-side frameless display panel is prolonged.
In view of the randomness of the occurrence of external static electricity, the above-mentioned embodiment provides an array substrate in which the first conductive layer 11 and the first insulating layer 12 cover the entire surface of the base substrate 10 in the orthographic projection of the base substrate 10, so that the first conductive layer 11 can be introduced into the ground line regardless of the occurrence of external static electricity at any position of the display surface of the display panel; the orthographic projection of the substrate 10 by the first insulating layer 12 covers the entire surface of the substrate 10, so that the thin film transistors in the display area AA of the array substrate 1 can be prevented from contacting the first conductive layer 11, thereby causing a short circuit. In order not to affect the display image of the display panel, the first conductive layer 11 is made of a transparent conductive material, typically an ito material, and the first insulating layer 12 is made of a transparent insulating material to ensure passing through the display area AA of the array substrate 1.
As shown in fig. 1, the substrate base plate 10 further includes a display forming area corresponding to the display area AA of the array base plate 1; at this time, a thin film transistor, which may be a top gate thin film transistor or a bottom gate thin film transistor, is formed on the surface of the first insulating layer 12 corresponding to the display formation region.
In order to simplify the manufacturing process of the array substrate, taking the bottom-gate thin film transistor as an example, the gate layer of the thin film transistor and the second conductive layer 13 are limited to be disposed in the same layer, so that the gate layer of the thin film transistor and the second conductive layer 13 can be formed simultaneously by using a single patterning process, thereby simplifying the manufacturing process of the array substrate.
Specifically, when the gate layer of the thin film transistor and the second conductive layer 13 are disposed on the same layer, the gate layer of the thin film transistor and the second conductive layer 13 are made of the same material, that is, when the gate layer of the thin film transistor and the second conductive layer 13 are formed simultaneously in a single patterning process, a metal film is sputtered on the surface of the first insulating layer 12, and then the metal layer is etched by using a mask, followed by development, so that the gate layer of the thin film transistor and the second conductive layer 13 can be completed.
Further, as shown in fig. 1, an isolation layer 14 covering a frame forming region corresponding to the first insulating layer 12 is formed on the surface of the second conductive layer 13 in the above embodiment; as shown in fig. 2, the isolation layer 14 defines an isolation layer first via 141 and an isolation layer second via 142, and the first insulation layer defines an insulation layer via 120 communicated with the isolation layer second via 142; the isolation layer first via 141 is located in the orthographic projection of the second conductive layer 13 on the substrate 10; the orthographic projections of the isolating layer second via 142 and the insulating layer via 120 on the substrate base plate 10 are both positioned in the orthographic projection of the first conducting layer 11 on the substrate base plate; the third conductive layer 15 covers the surface of the isolation layer 14, the third conductive layer 15 is electrically connected with the first conductive layer 11 through the isolation layer first via hole 141, and the third conductive layer 15 is electrically connected with the first conductive layer 11 sequentially through the isolation layer second via hole 142 and the insulation layer via hole 120. In order to conveniently form the isolation layer second via hole 142 and the insulation layer via hole 120, the insulation layer via hole 120 may be formed on the first insulation layer 12 when the isolation layer second via hole 142 is formed on the isolation layer 14 in a one-time etching process, and the isolation layer second via hole 142 and the insulation layer via hole 120 formed in the one-time etching process are not only communicated with each other, but also coincide with each other in the orthographic projection of the substrate 10, so as to ensure that the material of the third conductive layer can smoothly contact with the first conductive layer 11 through the isolation layer second via hole 142 and the insulation layer via hole 120 when the third conductive layer 15 is formed.
As shown in fig. 1 and 5, it is considered that a metal layer connected to a ground lead is generally disposed in the non-display area BM of the conventional array substrate 1, and silver paste is dispensed on the metal layer to realize signal connection between the array substrate 1 and the color filter substrate 2. Therefore, the frame forming area of the substrate base plate 10 is divided into a silver paste point area and a non-silver paste point area, the silver paste point area refers to an area of the substrate base plate 10 corresponding to the position of the silver paste point, and the non-silver paste point area refers to an area of the substrate base plate 10 corresponding to the position of the non-silver paste point.
Since the metal layer in the conventional array substrate is connected to the ground lead, the metal layer in the conventional art may be used as the second conductive layer 13. At this time, the orthographic projection of the second conductive layer 13 on the substrate base plate 10 should be located in the silver paste dot region of the substrate base plate 10; correspondingly, when the first via hole 141 of the isolation layer is manufactured, in order to enable the third conductive layer 15 to be electrically connected with the second conductive layer 13 through the first via hole 141 of the isolation layer, it should be ensured that the first via hole 141 of the isolation layer is located in the silver paste point region of the substrate 10 in the orthographic projection of the substrate 10, of course, the first via hole 141 of the isolation layer may also be a via hole originally provided on the isolation layer 14 when being used for silver paste point, so that it is not necessary to specially provide a via hole corresponding to the second conductive layer 13 on the isolation layer. As for the orthographic projection of the isolation layer second via 142 and the insulation layer via 120 on the substrate base plate 10, whether they are located in the silver paste dot region or the non-silver paste dot region of the substrate base plate is determined according to the actual situation.
Whereas, in view of the display area AA of the display panel being used for image display, in order to reduce the influence of the via on image display, the isolation layer second via 142 and the insulating layer via 120 may be defined in the non-silver adhesive dot region of the frame forming area of the substrate base plate 10 in the orthographic projection of the substrate base plate 10. It should be noted that the distance between the isolation layer first via 141 and the isolation layer second via 142 is not too long, which would make the resistance too large to introduce external static electricity into the ground line.
Specifically, on the premise that the orthographic projection of the isolation layer second via 142 on the substrate 10 is staggered from the orthographic projection of the second conductive layer 13 on the substrate 10, the distance between the outer edge of the orthographic projection of the isolation layer second via 142 on the substrate 10 and the outer edge of the orthographic projection of the second conductive layer 13 on the substrate 10 is reduced as much as possible.
Considering that the surface of the gate layer of the thin film transistor is also provided with a gate insulating layer, a semiconductor layer and a source drain electrode, and the gate insulating layer and the semiconductor layer are not involved in signal transmission, the isolation layer 14 is defined as a second insulating layer and a semiconductor layer which are arranged in a stacked manner, and considering that the material of the active layer is also a semiconductor material, the active layer and the semiconductor layer can also be defined to be arranged in the same layer to form the semiconductor layers of the active layer and the isolation layer in the same patterning process; and/or the presence of a gas in the gas,
the insulating layer of the thin film transistor can be arranged on the same layer with the second insulating layer, so that the second insulating layer is formed together when the insulating layer of the thin film transistor is formed. It is contemplated that the insulating layer of the thin film transistor generally includes a gate insulating layer and a passivation layer, which allows the second insulating layer to be divided into a first sub-layer and a second sub-layer. At this time, when the second insulating layer is formed, two steps are required, namely, when the gate insulating layer is deposited, the first sub-layer of the second insulating layer can be formed at the same time; the second sub-layer of the second insulating layer may be formed simultaneously when depositing the passivation layer. Since the gate insulating layer and the passivation layer further include an active layer and source and drain electrodes therebetween, a semiconductor layer formed simultaneously with the active layer in the same patterning process should be further included between the first sub-layer forming the second insulating layer and the second sub-layer forming the second insulating layer.
It is to be noted that, for the ADS display panel, a pixel electrode is generally formed on a surface of the thin film transistor, and at this time, the pixel electrode and the third conductive layer 15 are defined to be disposed in the same layer and connected into a whole, and a material of the pixel electrode is the same as a material of the third conductive layer 15, so that the third conductive layer 15 can be formed together when the pixel electrode is formed, thereby simplifying a manufacturing process of the array substrate.
For the HADS display panel, a common electrode is generally formed on the surface of the thin film transistor; at this time, the common electrode and the third conductive layer 15 may be defined to be disposed at the same layer and be connected into a whole, and the material of the common electrode is the same as that of the third conductive layer 15, so that the third conductive layer 15 may be formed together when the common electrode is formed, thereby simplifying the manufacturing process of the array substrate.
In addition, the common electrode and the pixel electrode are both generally made of an indium tin oxide material, and if the third conductive layer 15 is to be formed together with the common electrode or the pixel electrode, the material of the third conductive layer 15 should also be an indium tin oxide material.
The embodiment of the invention also provides a manufacturing method of the array substrate, which is shown in fig. 2 and 3 and comprises the following specific steps:
step S100: providing a substrate 10; the substrate base plate 10 includes a frame forming region; forming a first conductive layer 11 on a surface of a base substrate 10;
step S200: forming a first insulating layer 12 on the surface of the first conductive layer 11;
step S300: forming a second conductive layer 13 on the surface of the first insulating layer corresponding to the frame forming region, so that the second conductive layer 13 is connected with the ground lead;
step S500: a third conductive layer 15 is formed over the second conductive layer 13 so that the first conductive layer 11 and the second conductive layer 13 are electrically connected through the third conductive layer 15.
Compared with the prior art, the manufacturing method of the array substrate provided by the embodiment of the invention has the same beneficial effects as the array substrate provided by the embodiment, and the details are not repeated herein.
It is understood that in the manufacturing method of the array substrate provided in the above embodiment, the substrate further includes a display forming region corresponding to the display region AA of the display panel, the display region AA of the display panel is generally formed with thin film transistors arranged in an array, and in order to further improve the resistance of the array substrate to external static electricity, the first conductive layer 11 and the first insulating layer 12 cover the entire surface of the substrate 10 in the orthographic projection of the substrate 10, the first conductive layer 11 is a light-transmitting conductive material, and is generally an indium tin oxide material, and the first insulating layer 12 is a light-transmitting insulating material, so as to ensure that the first conductive layer 11 and the second insulating layer 12 do not affect image display.
Considering that the conventional array substrate is generally manufactured by using a 4mask process or a 5mask process, in the array substrate provided by the embodiment of the present invention, the first conductive layer 11 and the first insulating layer 12 need to cover the surface of the substrate 10, and therefore, before starting the 4mask process or the 5mask process, the first conductive layer 11 and the first insulating layer 12 are formed.
Further, after forming the first conductive layer 11 on the surface of the base substrate 10 and forming the first insulating layer 12 on the surface of the first conductive layer 11, the method for manufacturing the array substrate further includes:
forming a thin film transistor on a surface of the first insulating layer 12 corresponding to the display formation region; the thin film transistor may be a top gate thin film transistor or a bottom gate thin film transistor.
The following description will be made by taking a bottom-gate tft as an example to simplify the fabrication process of the array substrate.
First, when a gate layer of the thin film transistor is manufactured, it may be considered that the second conductive layer 13 is formed in one patterning process; that is, a metal layer is sputtered on the surface of the first insulating layer, and then the gate layer and the second conductive layer 13 are formed by a patterning process.
Secondly, when the gate insulating layer, the active layer and the passivation layer of the thin film transistor are manufactured, the gate insulating layer and the passivation layer are generally deposited on the whole layer, and the active layer also needs to be patterned. In order to avoid unnecessary material waste, when the gate insulating layer, the active layer and the passivation layer of the thin film transistor are manufactured, the method for manufacturing the array substrate provided by the above embodiment further includes step S400: forming an isolation layer 14 on the surface of the second conductive layer 13, so that the isolation layer 14 covers the frame forming region corresponding to the first insulating layer 12; the isolation layer comprises a semiconductor layer and a second insulating layer which are arranged in a stacked mode; the active layer and the semiconductor layer of the thin film transistor are formed by one-time composition process, and the second insulating layer is deposited together with the insulating layer of the thin film transistor. Considering that the insulating layer of the thin film transistor is divided into the gate insulating layer and the passivation layer, the second insulating layer should be formed in two parts, and the specific forming process is described with reference to the corresponding parts.
As shown in fig. 4, after the isolation layer 14 is formed on the surface of the second conductive layer 13, the step of forming the third conductive layer 15 above the second conductive layer 13 specifically includes the following steps:
step S510: forming an isolation layer first via 141 in the isolation layer 14;
step S520: an isolation layer second through hole 142 is formed in the isolation layer 14, and an isolation layer through hole 120 communicated with the isolation layer second through hole 142 is formed in the first insulation layer 12;
step S530: a third conductive layer 15 is formed on the surface of the isolation layer 14, such that the third conductive layer 15 is electrically connected to the second conductive layer 13 through the isolation layer first via 141, and the third conductive layer 15 is electrically connected to the first conductive layer 11 through the isolation layer second via 142 and the insulation layer via 120 in this order.
After the thin film transistor is formed on the surface of the first insulating layer corresponding to the display formation region, the method for manufacturing the array substrate further includes:
a pixel electrode or a common electrode formed together with the third conductive layer 15 is formed on the surface of the thin film transistor.
Since the pixel electrode or the common electrode is generally sputtered in a whole layer, when the pixel electrode or the common electrode is sputtered in a whole layer on the surface of the thin film transistor, the third conductive layer 15 is substantially formed on the surface of the isolation layer 14, that is, the pixel electrode or the common electrode and the third conductive layer 15 are formed in one forming process. The specific forming process may be sputtering or other processes.
As shown in fig. 5, an embodiment of the present invention further provides a display panel, including the array substrate 1 provided in the foregoing technical solution.
Compared with the prior art, the beneficial effects of the display panel provided by the embodiment of the invention are the same as those of the array substrate provided by the technical scheme, and are not repeated herein.
It can be understood that, in the display panel, in addition to the array substrate 1, the display panel further includes a color filter substrate 2 paired with the array substrate 1, and a light-transmitting conductive electrode is further formed on a surface of the color filter substrate 2 opposite to the array substrate 1, where the light-transmitting conductive electrode may be indium tin oxide or other transparent conductive materials. At this time, the side of the array substrate 1 is connected with the side of the color filter substrate 2 through the anisotropic conductive adhesive, so that the first conductive layer 11 of the array substrate 1 is connected with the light-transmitting conductive electrode in the color filter substrate 2 through the conductive ions in the anisotropic conductive adhesive 3, and a part of static electricity generated inside the color filter substrate is released to the ground line through the first conductive layer 11, thereby improving the static electricity lead-out rate.
In addition, the first conductive layer 11 of the array substrate 1 is connected to the transparent conductive electrode in the color filter substrate 2 through the conductive ions in the anisotropic conductive adhesive 3, and the first conductive layer 11 is electrically connected to the second conductive layer 13 through the third conductive layer 15, so that the transparent conductive electrode of the color filter substrate 2 is connected to the second conductive layer 13 through the first conductive layer 11, and thus, the display panel provided by the embodiment of the invention can release the static electricity generated inside the color filter substrate to the ground wire only by connecting the side surface of the array substrate 1 to the side surface of the color filter substrate 2 through the anisotropic conductive adhesive 3, and the static electricity generated inside the color filter substrate does not need to be released to the ground wire through the silver paste and the conductive adhesive tape pasted on the array substrate 1.
The embodiment of the invention also provides a display device which comprises the display panel provided by the technical scheme.
Compared with the prior art, the beneficial effects of the display device provided by the embodiment of the invention are the same as those of the array substrate provided by the technical scheme, and are not repeated herein.
The display device provided in the above embodiments may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, or a navigator.
In the foregoing description of embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (9)
1. An array substrate comprises a substrate base plate, wherein the substrate base plate comprises a frame forming area; the ground wire lead wire structure is characterized in that a first conducting layer is arranged on the surface of the substrate base plate, a first insulating layer is formed on the surface of the first conducting layer, a second conducting layer electrically connected with the ground wire lead wire is formed on the surface of the first insulating layer corresponding to a frame forming area, and an isolating layer covering the first insulating layer corresponding to the frame forming area is formed on the surface of the second conducting layer;
the isolation layer is provided with an isolation layer first via hole and an isolation layer second via hole;
the first insulating layer is provided with an insulating layer through hole;
the third conducting layer covers the surface of the isolation layer, is electrically connected with the second conducting layer through the first through hole of the isolation layer, and is electrically connected with the first conducting layer through the second through hole of the isolation layer and the through hole of the insulation layer;
the orthographic projection of the first conducting layer and the first insulating layer on the substrate base plate covers the surface of the substrate base plate, the first conducting layer is made of a light-transmitting conducting material, and the first insulating layer is made of a light-transmitting insulating material;
the surface of the substrate base plate of the array base plate, which is deviated from the first conducting layer, is used as a light emergent surface of the display panel.
2. The array substrate of claim 1, wherein the substrate further comprises a display formation region, and a thin film transistor is formed on the surface of the first insulating layer corresponding to the display formation region; the grid layer of the thin film transistor and the second conducting layer are arranged on the same layer; and/or the presence of a gas in the gas,
the array substrate further comprises a pixel electrode, and the third conducting layer and the pixel electrode are arranged on the same layer, and/or;
the array substrate further comprises a common electrode, and the third conducting layer and the common electrode are arranged on the same layer.
3. The array substrate of claim 2, wherein the first insulating layer defines an insulating layer via that communicates with the isolation layer second via;
the orthographic projections of the isolating layer second through hole and the insulating layer through hole on the substrate base plate are both positioned in the orthographic projection of the first conducting layer on the substrate base plate;
the third conducting layer is electrically connected with the first conducting layer sequentially through the isolating layer second through hole and the insulating layer through hole.
4. The array substrate of claim 3, wherein the frame forming region comprises a silver paste dot region and a non-silver paste dot region, wherein an orthographic projection of the isolation layer first via hole on the substrate is located in the silver paste dot region, and orthographic projections of the isolation layer second via hole and the insulation layer via hole are located in the non-silver paste dot region;
the isolation layer comprises a semiconductor layer and a second insulating layer which are arranged in a stacked mode; wherein,
the active layer and the semiconductor layer of the thin film transistor are arranged on the same layer; and/or the presence of a gas in the gas,
the insulating layer of the thin film transistor and the second insulating layer are arranged on the same layer.
5. A method for fabricating the array substrate according to any one of claims 1 to 4, comprising:
providing a substrate base plate; the substrate base plate comprises a frame forming area; forming a first conductive layer on the surface of the substrate base plate;
forming a first insulating layer on the surface of the first conductive layer;
forming a second conducting layer on the surface of the first insulating layer corresponding to the frame forming area, so that the second conducting layer is connected with the ground wire lead;
forming a third conductive layer over the second conductive layer such that the first conductive layer and the second conductive layer are electrically connected through the third conductive layer.
6. The method for manufacturing the array substrate according to claim 5, wherein the orthographic projection of the first conductive layer and the first insulating layer on the substrate covers the surface of the substrate, the first conductive layer is made of a light-transmitting conductive material, and the first insulating layer is made of a light-transmitting insulating material; the substrate base plate further comprises a display forming area, and after the first insulating layer is formed on the surface of the first conducting layer, the manufacturing method of the array base plate further comprises the following steps:
forming a thin film transistor on the surface of the first insulating layer corresponding to the display forming region; a grid layer of the thin film transistor and the second conducting layer are formed in a one-time composition process;
after the thin film transistor is formed on the surface of the first insulating layer corresponding to the display forming region, the manufacturing method of the array substrate further includes:
forming a pixel electrode on the surface of the thin film transistor, wherein the pixel electrode and the third conductive layer are formed in one forming process; or,
and forming a common electrode on the surface of the thin film transistor, wherein the common electrode and the third conductive layer are formed in one forming process.
7. The method for manufacturing an array substrate according to claim 6, wherein after the second conductive layer is formed on the surface of the first insulating layer corresponding to the frame forming region and before the third conductive layer is formed over the second conductive layer, the method further comprises:
forming an isolation layer on the surface of the second conductive layer, so that the isolation layer covers the frame forming area corresponding to the first insulation layer; the isolation layer comprises a semiconductor layer and a second insulating layer which are arranged in a stacked mode; the active layer and the semiconductor layer of the thin film transistor are formed through a one-time composition process;
the forming a third conductive layer over the second conductive layer comprises:
forming an isolation layer first via hole in the isolation layer;
the isolation layer is also provided with an isolation layer second through hole, and the first insulation layer is provided with an insulation layer through hole communicated with the isolation layer second through hole;
and forming a third conducting layer on the surface of the isolation layer, so that the third conducting layer is electrically connected with the second conducting layer through the first via hole of the isolation layer, and the third conducting layer is electrically connected with the first conducting layer through the second via hole of the isolation layer and the via hole of the insulation layer in sequence.
8. A display panel comprising the array substrate according to any one of claims 1 to 4.
9. A display device characterized by comprising the display panel according to claim 8.
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| CN108550580B (en) * | 2018-04-27 | 2019-10-11 | 武汉华星光电技术有限公司 | Tft array substrate |
| CN109709731B (en) * | 2019-02-25 | 2022-07-22 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN110045531B (en) * | 2019-04-18 | 2023-02-28 | 云谷（固安）科技有限公司 | Array substrate and display panel |
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| CN202548490U (en) * | 2012-03-07 | 2012-11-21 | 东莞通华液晶有限公司 | Antistatic liquid crystal display structure |
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| CN105607366B (en) * | 2016-01-05 | 2019-03-05 | 京东方科技集团股份有限公司 | Anti-static device and its manufacturing method, substrate |
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| JPH10161155A (en) * | 1996-12-04 | 1998-06-19 | Hitachi Ltd | Liquid crystal display device |
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