CN107316659B - Memory power-down time period positioning method and system power-down protection method - Google Patents
Memory power-down time period positioning method and system power-down protection method Download PDFInfo
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- CN107316659B CN107316659B CN201710508617.8A CN201710508617A CN107316659B CN 107316659 B CN107316659 B CN 107316659B CN 201710508617 A CN201710508617 A CN 201710508617A CN 107316659 B CN107316659 B CN 107316659B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
Abstract
The invention discloses a method for positioning a power-down time period of a memory, which comprises the following steps: taking a first time period as a step length, carrying out gradual power failure test on an instruction process, and positioning a programming time period programmed in a memory in the instruction process; and gradually carrying out gradual power failure test in the programming time period to locate the power failure time period of the memory, wherein in each locating, the power failure test step length adopted by the next gradual power failure test is smaller than the power failure test step length adopted by the last gradual power failure test, and the next gradual power failure test is carried out in the power failure time period located by the last gradual power failure test. The instruction process is successively positioned, the test step time period of the power failure test is sequentially reduced in each positioning, the power failure time period in the programming process of the memory is successively positioned, and the accurate positioning of the power failure time period of the memory can be realized. The invention also discloses a system power-down protection method adopting the memory power-down time period positioning method.
Description
Technical Field
The invention relates to the technical field of power failure tests, in particular to a method for positioning a power failure time period of a memory. The invention also relates to a system power-down protection method.
Background
In the prior art, in the positioning test of the power failure time period of a memory in a system, the power failure test is carried out on the whole instruction process, if the test time step is set to be too small, the consumed time of the whole power failure test is too long, and if the test time step is set to be larger, the hit rate of the power failure time period of the memory is reduced.
Therefore, how to realize the fast and accurate positioning of the power-down time period of the memory and overcome the defects of the prior art becomes a technical problem to be solved by the technical personnel in the field.
Disclosure of Invention
The invention aims to provide a method for positioning a power-down time period of a memory, which can realize accurate positioning of the power-down time period of the memory. The invention also provides a system power-down protection method.
In order to achieve the purpose, the invention provides the following technical scheme:
a method for positioning a power-down time period of a memory comprises the following steps:
taking a first time period as a step length, carrying out gradual power failure test on an instruction process, and positioning a programming time period programmed in a memory in the instruction process;
and gradually carrying out gradual power failure test in the programming time period to locate the power failure time period of the memory, wherein in each locating, the power failure test step length adopted by the next gradual power failure test is smaller than the power failure test step length adopted by the last gradual power failure test, and the next gradual power failure test is carried out in the power failure time period located by the last gradual power failure test.
Optionally, the step-by-step power-down test is performed on the instruction process by using the first time period as a step size, and locating the programming time period programmed in the memory in the instruction process includes:
gradually reading the value in the memory storage area in the instruction process, and determining the time period of the value in the memory storage area as the modified value and the time period of other values as the programming time period, wherein the other values are values different from the unmodified value and the modified value.
Optionally, performing the gradual power-down test includes:
the card is powered on, a reading instruction which is sent by the memory and used for reading the value in the memory area of the memory is received, and the card is powered off after a preset time period;
and powering on the card again, and reading the value in the memory storage area.
Optionally, after the reading of the value in the memory storage area, the method further includes:
determining whether the read value is an unmodified value, a modified value, or other value, the other value being a value that is distinct from the unmodified and modified values;
if the read value is an unmodified value, indicating that the power-down time point does not reach the programming process of the memory;
if the read value is a modified value, indicating that the power-down time point is after the programming process of the memory;
if the read value is other value, it indicates that the power-down time point is in the programming process of the memory.
Optionally, the performing the gradual power-down test successively in the programming time period, and locating the power-down time period of the memory includes:
taking a second time period as a step length, performing gradual power failure test in the programming time period, and positioning time periods with values in the storage area of the memory as other values, wherein the other values are values different from unmodified values and modified values;
taking a third time period as a step length, and performing gradual power failure test in the time period in which the value in the memory storage area is positioned as other values to position a power failure time period;
the second time period is less than the first time period, and the third time period is less than the second time period.
A system power-down protection method comprises the following steps:
when the system platform is identified to have power failure, triggering power failure protection to start and recording;
writing the old data into the backup area;
writing new data into the target area;
marking the completion of power failure protection after the completion of power failure protection;
by adopting the positioning method for the power-down time period of the memory, the power-down time period is positioned in the processes of starting the marking process of power-down protection, backing up old data, writing in new data and finishing the marking process of power-down protection in sequence.
Optionally, the power-down time period is located in a power-down protection starting marking process, an old data backup process, a new data writing process and a power-down protection completion marking process before the data rollback mechanism is started.
According to the technical scheme, the method for positioning the power-down time period of the memory comprises the steps of firstly taking a first time period as a step length, carrying out gradual power-down test on an instruction process, positioning a programming time period programmed in the memory in the instruction process, then carrying out gradual power-down test in the positioned programming time period, wherein in each positioning, the power-down test step length adopted by the next gradual power-down test is smaller than the power-down test step length adopted by the last gradual power-down test, and the next gradual power-down test is carried out in the power-down time period positioned by the last gradual power-down test. The method for positioning the power-down time period of the memory carries out successive positioning on the instruction process, and reduces the test step time period of the power-down test in each positioning in sequence so as to successively position the power-down time period in the programming process of the memory, thereby realizing the accurate positioning of the power-down time period of the memory.
The system power failure protection method provided by the invention triggers the start of power failure protection and records when recognizing that the system platform has power failure, and writes old data into a backup area; and then writing the new data into the target area, and marking the completion of the power failure protection after the completion of the power failure protection. The positioning test of the power failure time periods is carried out on each process in sequence by adopting a memory power failure time period positioning method, so that the accurate positioning of the power failure time periods in each process of the system can be realized.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a flowchart of a method for locating a memory power-down time period according to an embodiment of the present invention;
fig. 2 is a flowchart of a system power-down protection method according to an embodiment of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, a method for locating a memory in a power-down time period according to an embodiment of the present invention includes:
s10: and taking the first time period as a step length, carrying out gradual power failure test on the instruction process, and positioning the programming time period programmed in the memory in the instruction process.
In the step, a first time period is taken as a step size, the value in the memory storage area in the instruction process is read step by step, the time period in which the value in the memory storage area is the modified value and the time periods in which the value is other values are determined as the programming time period, and the other values are values different from the unmodified value and the modified value.
In the transaction process of the card and the system memory, if a programming process of the memory exists, the programming process is that the memory is erased and then written, and correspondingly, the storage duration time of the value in the memory storage area comprises the following steps: initial value phase, programmed value phase, other value phases.
Initial value stage: the card receives the instruction and the application performs logic processing. The values in the memory region are not modified during this phase.
A programming value phase: the application modification data is completed, and the card responds to the data, and the value in the memory area is modified in the process of the stage.
Other value phases: the method comprises an erasing process and a programming process.
Therefore, in this step, the values in the memory storage area are read, and it is determined whether the read values are unmodified values, modified values, or other values to locate the programming process.
In this step, the process of performing the gradual power-down test includes: the following process is repeated with the first time period as a step size:
s100: the card is powered on, a reading instruction which is sent by the memory and used for reading the value in the memory area of the memory is received, and the card is powered off after a first time period;
s101: and powering on the card again, and reading the value in the memory storage area.
Further comprising step S102: it is determined whether the read value is an unmodified value, a modified value, or other value, other values referring to values that are distinct from the unmodified and modified values.
And determining the time period with the value of the memory storage area as the modified value and the time periods with the values of the memory storage area as the other values as the programming time period through the gradual power-down test process.
For example, if the first time period is 20ms, the following processes are sequentially performed:
and powering on the card, receiving a reading instruction, and powering off the card after 20 ms.
And electrifying the card, reading the value in the storage area, and obtaining an unmodified value as a result.
And powering on the card, receiving a reading instruction, and powering off the card after 40 ms.
And electrifying the card, reading the value in the storage area, and obtaining an unmodified value as a result.
......
And powering on the card, receiving a reading instruction, and powering off the card after 140 ms.
And electrifying the card, reading the value in the storage area, and obtaining the result as other values.
And powering on the card, receiving a reading instruction, and powering off the card after 160 ms.
And electrifying the card, reading the value in the storage area, and obtaining a result which is a modified value.
The programming time period for obtaining the card is between 120ms and 160 ms.
S11: and gradually carrying out gradual power failure test in the programming time period to locate the power failure time period of the memory, wherein in each locating, the power failure test step length adopted by the next gradual power failure test is smaller than the power failure test step length adopted by the last gradual power failure test, and the next gradual power failure test is carried out in the power failure time period located by the last gradual power failure test.
Wherein, the process of performing the gradual power-down test in the positioned time period each time comprises the following steps: the following process is repeatedly carried out by taking a preset time period as a step length:
s110: and powering on the card, receiving a reading instruction which is sent by the memory and used for reading the value in the memory area of the memory, and powering off the card after a preset time period.
And adopting the corresponding preset time period as the step length when the gradual power failure test is carried out in the positioned time period each time.
S111: and powering on the card again, and reading the value in the memory storage area.
S112: it is determined whether the read value is an unmodified value, a modified value, or other value, other values referring to values that are distinct from the unmodified and modified values.
If the read value is an unmodified value, indicating that the power-down time point does not reach the programming process of the memory; if the read value is a modified value, indicating that the power-down time point is after the programming process of the memory; if the read value is other value, it indicates that the power-down time point is in the programming process of the memory.
The method is used for carrying out gradual power failure test in each positioned time period.
In one embodiment, the step includes:
s110: and taking a second time period as a step length, carrying out gradual power failure test in the programming time period, and positioning the time period with the value in the storage area of the memory as other values, wherein the other values are values different from the unmodified value and the modified value, and the second time period is smaller than the first time period.
For example, the time precision is reduced, the second time period is 2ms as a step size, and the located time period range of 120ms to 160ms is subjected to gradual power-down test. The specific test procedure can refer to the above method description procedure, locating the programming time period between 138ms-142 ms.
S111: and taking a third time period as a step length, and carrying out gradual power failure test in the time period in which the value in the memory storage area is positioned as other values, and positioning the power failure time period, wherein the third time period is smaller than the second time period.
For example, the time precision is reduced, the third time period is taken as 500us as a step size, the located 138ms-142ms time period range is subjected to step-by-step power-down test, and the programming time period obtained by the same method is between 139ms and 141 ms.
Further, using the lowest level of time precision, such as 10us as a step size, a step-by-step power-down test is performed within a time period range of 139ms-141ms, and a power-down time point is located.
Therefore, the method for positioning the power-down time period of the memory carries out successive positioning on the instruction process, and sequentially reduces the test step time period of the power-down test in each positioning to successively position the power-down time period in the programming process of the memory, so that the accurate positioning of the power-down time period of the memory can be realized.
Referring to fig. 2, an embodiment of the present invention further provides a system power down protection method, including the steps of:
s20: when the system platform is identified to have power failure, triggering power failure protection to start and recording;
s21: writing the old data into the backup area;
s22: writing new data into the target area;
s23: marking the completion of power failure protection after the completion of power failure protection;
s24: by adopting the method for positioning the power-down time period of the memory, the power-down time period is positioned in the processes of starting the marking process of power-down protection, backing up old data, writing in new data and finishing the marking process of power-down protection in sequence.
It can be seen that in the system power-down protection method of the embodiment, when the system platform is identified to have power-down, the power-down protection is triggered to start and record, and old data is written into the backup area; and then writing the new data into the target area, and marking the completion of the power failure protection after the completion of the power failure protection. The positioning test of the power failure time periods is carried out on each process in sequence by adopting a memory power failure time period positioning method, so that the accurate positioning of the power failure time periods in each process of the system can be realized.
Further, in the method of the embodiment, the power failure time period is located in the power failure protection starting marking process, the old data backup process, the new data writing process and the power failure protection finishing marking process before the data rollback mechanism is started.
And a data rollback process exists correspondingly in the power failure protection process of the system. The data in the storage area can be restored to an initial value or a programming value, the positioning of the power failure time period of each process is carried out before the data rollback mechanism is started, and therefore the situation that the data in the storage area is read when the positioning of the power failure time period is carried out, the data are restored, and the accurate positioning cannot be carried out is avoided.
The method for positioning the power-down time period of the memory and the power-down protection method of the system provided by the invention are described in detail above. The principles and embodiments of the present invention are explained herein using specific examples, which are presented only to assist in understanding the method and its core concepts. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
Claims (5)
1. A method for positioning a power-down time period of a memory is characterized by comprising the following steps:
taking a first time period as a step length, carrying out gradual power failure test on an instruction process, and positioning a programming time period programmed in a memory in the instruction process;
gradually carrying out gradual power-down test in the programming time period to locate the power-down time period of the memory, wherein in each locating, the power-down test step length adopted by the next gradual power-down test is smaller than the power-down test step length adopted by the last gradual power-down test, and the next gradual power-down test is carried out in the power-down time period located by the last gradual power-down test;
the step-by-step power-down test comprises the following steps:
the card is powered on, a reading instruction which is sent by the memory and used for reading the value in the memory area of the memory is received, and the card is powered off after a preset time period;
the card is electrified again, and the value in the memory storage area is read;
after the reading of the value into the memory storage area, further comprising:
determining whether the read value is an unmodified value, a modified value, or other value, the other value being a value that is distinct from the unmodified and modified values;
if the read value is an unmodified value, indicating that the power-down time point does not reach the programming process of the memory;
if the read value is a modified value, indicating that the power-down time point is after the programming process of the memory;
if the read value is other value, it indicates that the power-down time point is in the programming process of the memory.
2. The memory power-down time period positioning method according to claim 1, wherein the step-by-step power-down test is performed on an instruction process with the first time period as a step, and the positioning of the programming time period programmed in the memory in the instruction process includes:
gradually reading the value in the memory storage area in the instruction process, and determining the time period of the value in the memory storage area as the modified value and the time period of other values as the programming time period, wherein the other values are values different from the unmodified value and the modified value.
3. The memory power-down time period locating method according to any one of claims 1-2, wherein the step-by-step power-down test is performed successively in the programming time period, and locating the power-down time period of the memory includes:
taking a second time period as a step length, performing gradual power failure test in the programming time period, and positioning time periods with values in the storage area of the memory as other values, wherein the other values are values different from unmodified values and modified values;
taking a third time period as a step length, and performing gradual power failure test in the time period in which the value in the memory storage area is positioned as other values to position a power failure time period;
the second time period is less than the first time period, and the third time period is less than the second time period.
4. A system power-down protection method is characterized by comprising the following steps:
when power failure of the system platform is identified, triggering power failure protection to start and recording;
writing the old data into the backup area;
writing new data into the target area;
marking the completion of power failure protection after the completion of power failure protection;
the method for locating the power-down time period of the memory according to any one of claims 1 to 3 is adopted to locate the power-down time period in the processes of starting the power-down protection marking, backing up old data, writing in new data and completing the power-down protection marking in sequence.
5. The system power-fail protection method of claim 4, wherein the power-fail time period positioning is performed on the power-fail protection start marking process, the old data backup process, the new data writing process and the power-fail protection completion marking process before the data rollback mechanism is enabled.
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| CN109257185B (en) * | 2018-11-21 | 2021-01-26 | 新华三技术有限公司 | Network equipment, service card, logic device and notification information transmission method |
| CN109347685B (en) * | 2018-11-21 | 2021-01-26 | 新华三技术有限公司 | Network equipment, logic device and notification information transmission method |
| CN109524049B (en) * | 2018-11-26 | 2021-04-20 | 深圳忆联信息系统有限公司 | SSD abnormal power failure test method and device, computer equipment and storage medium |
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| CN102495264B (en) * | 2011-11-30 | 2013-12-18 | 甘肃电力科学研究院 | Voltage dip duration detection method based on information entropy |
| CN103531234B (en) * | 2012-07-06 | 2017-02-08 | 河南思维自动化设备股份有限公司 | Power-down protection method in write operation process of NandFlash memory |
| US9892798B2 (en) * | 2012-09-11 | 2018-02-13 | Seagate Technology Llc | Data protection for unexpected power loss |
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