CN107315369B - Intelligent co-processing device for BMC (baseboard management controller) chip - Google Patents
Intelligent co-processing device for BMC (baseboard management controller) chip Download PDFInfo
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- CN107315369B CN107315369B CN201710567604.8A CN201710567604A CN107315369B CN 107315369 B CN107315369 B CN 107315369B CN 201710567604 A CN201710567604 A CN 201710567604A CN 107315369 B CN107315369 B CN 107315369B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0428—Safety, monitoring
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0421—Multiprocessor system
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/048—Monitoring; Safety
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/22—Pc multi processor system
- G05B2219/2214—Multicontrollers, multimicrocomputers, multiprocessing
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/24—Pc safety
- G05B2219/24125—Watchdog, check at timed intervals
Abstract
The invention discloses a BMC chip intelligent co-processing device and a BMC chip intelligent co-processing method, wherein the BMC chip intelligent co-processing device comprises: the system comprises an ARM processor, a communication module, a co-processing module connected with the ARM processor, a server mainboard connected with the ARM processor and the co-processing module respectively, and a management platform connected with the co-processing module through the communication module. According to the invention, after the internal processor of the BMC chip fails, the transmission of videos and control is maintained, an alarm is sent to the management platform, the working state of the server is transmitted in real time, the operation of the server is monitored, and meanwhile, the alarm level is determined to be sent according to the time of a failure interval, and whether the server is closed or not is determined, so that no accident occurs to the server.
Description
Technical Field
the invention relates to the field of BMC (baseboard management controller) chips, in particular to an intelligent co-processing device and a processing method of a BMC chip.
background
with the higher requirement of the client on the stability of the server, the requirement on the management of the server mainboard is more and more strict. The server mainboard adopts a BMC chip for management, and the BMC chip can realize monitoring and control of system operation, thereby realizing better maintenance of the system. In practical application of the server, the BMC chip may be interfered by various factors, such as electromagnetic radiation, unstable voltage, and the like, and may cause a program of the BMC chip to run away. When the BMC chip fails, the operation and monitoring of the server are out of control, and the whole server has a risk of working abnormity. Meanwhile, the BMC chip cannot send alarm information even if the BMC chip fails, and even if a client finds a problem, the client needs to consume manpower to perform field maintenance, so that great resource waste is brought.
disclosure of Invention
In order to solve the above problems, the present invention provides an intelligent co-processing device and a processing method for a BMC chip, which can maintain the transmission of video and control after a processor in the BMC chip fails, send an alarm to a management platform, transmit the working state of a server in real time, and determine whether to shut down the server according to a configuration policy.
the technical scheme of the invention is as follows: a BMC chip intelligent co-processing device comprises: the system comprises an ARM processor, a communication module, a co-processing module connected with the ARM processor, a server mainboard connected with the ARM processor and the co-processing module respectively, and a management platform connected with the co-processing module through the communication module;
the co-processing module comprises:
Watchdog submodule: carrying out failure detection on the ARM processor, resetting the ARM processor, and sending failure information and resetting information of the ARM processor to the co-processing control submodule;
The coprocessing control submodule: a mainboard information receiving port and a mainboard control signal sending port are arranged; when the ARM processor normally operates, the interactive information sent by the ARM processor is forwarded to the management platform through the communication module, the mainboard control signal sent by the ARM processor is forwarded to the server mainboard through the mainboard control signal sending port, and the control information received through the communication module is sent to the ARM processor; when the ARM processor failure information is received, the mainboard information received by the mainboard information receiving port is sent to the management platform by the communication module, the mainboard control signal sending port sends a mainboard control signal to the server mainboard, and the communication module sends alarm information to the management platform.
Further, the co-processing control sub-module comprises:
An alarm receiving unit: receiving failure information of the ARM processor sent by the watching gate module;
an alarm determination unit: judging the alarm level according to the failure information of the ARM processor;
An alarm transmission unit: and sending out the alarm information in a message form.
Further, the alarm information message sent by the alarm sending unit includes the following information: alarm type, purpose number, equipment request number, current ARM processor failure time, last ARM processor failure time, 24-hour failure times, historical failure times, overflow mark and ECC check data.
Furthermore, the mainboard information receiving port is a video information receiving port, and the mainboard control signal sending port is a mainboard power supply control signal sending port.
further, the interactive information sent by the ARM processor includes video information.
further, the communication module is a network interface.
Furthermore, the co-processing module further comprises a data encapsulation and analysis submodule, and the data encapsulation and analysis submodule is used for encapsulating or analyzing the transmission data between the ARM processor and the co-processing control submodule.
An intelligent co-processing method of a BMC chip comprises an ARM processor, a co-processing module and a server mainboard;
Further comprising the steps of:
S1: the auxiliary processing module forwards the interactive information and the mainboard control signal sent by the ARM processor and judges whether the ARM processor fails or not;
S2: if the ARM processor is not invalid, the step S1 is repeated, and if the ARM processor is invalid, the co-processing module takes over the interaction information and the mainboard control signal, sends out an alarm message, and restarts the ARM processor.
Further, the step S2 in which the co-processing module takes over the interaction information means that the co-processing module receives and sends the motherboard information, and sends a motherboard power control signal to the server motherboard.
Further, the step S2 of sending out the alarm information specifically includes the following steps:
S2.1: judging whether the failure interval is smaller than a preset threshold value of the shortest interval or not;
S2.2: if the failure interval is smaller than the shortest interval preset threshold, sending a three-level alarm and closing the server; otherwise, judging whether the failure interval is smaller than a preset threshold value of the middle-level interval or not;
S2.3: if the failure interval is smaller than a preset threshold value of the middle-level interval, a second-level alarm is sent out; otherwise, judging whether the failure interval is smaller than the longest interval preset threshold value;
s2.4: and if the failure interval is smaller than the maximum time preset threshold, a primary alarm is sent out.
According to the intelligent co-processing device and the processing method for the BMC chip, provided by the invention, after the internal processor of the BMC chip fails, the transmission of videos and control is maintained, an alarm is sent to a management platform, the working state of a server is transmitted in real time, and the function of monitoring the operation of the server is achieved. Meanwhile, the device has the function of recording the failure interval of the BMC chip processor, and determines to send the alarm level according to the time of the failure interval and determines whether to close the server or not, so that the server is ensured not to have accidents.
Drawings
FIG. 1 is a schematic diagram of an apparatus according to an embodiment of the present invention.
FIG. 2 is a schematic flow chart of a method according to an embodiment of the present invention.
In the figure, the system comprises a 1-ARM processor, a 2-coprocessing module, a 21-watchdog submodule, a 22-data encapsulation and analysis submodule, a 23-coprocessing control submodule, a 3-server mainboard, a 4-communication module and a 5-management platform.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings by way of specific examples, which are illustrative of the present invention and are not limited to the following embodiments.
As shown in fig. 1, the intelligent co-processing device for BMC chip provided by the present invention includes: ARM treater 1, communication module 4, coprocessing module 2, server mainboard 3, management platform 5. The auxiliary processing module 2 is connected with the ARM processor 1, the server mainboard 3 is respectively connected with the ARM processor 1 and the auxiliary processing module 2, and the management platform 5 is connected with the auxiliary processor through the communication module 4.
Wherein the co-processing module 2 comprises: a watchdog sub-module 21 and a co-processing control sub-module 23.
Watchdog submodule 21: and carrying out failure detection on the ARM processor 1, resetting the ARM processor 1, and sending failure information and resetting information of the ARM processor 1 to the co-processing control submodule 23.
The co-processing control sub-module 23: a mainboard information receiving port and a mainboard control signal sending port are arranged; when the ARM processor 1 normally operates, the interactive information sent by the ARM processor 1 is forwarded to the management platform 5 through the communication module 4, the mainboard control signal sent by the ARM processor 1 is forwarded to the server mainboard 3 through the mainboard control signal sending port, and the control information received through the communication module 4 is sent to the ARM processor 1; when the failure information of the ARM processor 1 is received, the mainboard information received by the mainboard information receiving port is sent to the management platform 5 by the communication module 4, the mainboard control signal sending port sends a mainboard control signal to the server mainboard 3, and the communication module 4 sends alarm information to the management platform 5.
In this embodiment, the communication module 4 may adopt a network interface, the motherboard information receiving port is a video information receiving port, the motherboard control signal sending port is a motherboard power supply control signal sending port, and the interactive information sent by the ARM processor 1 includes video information. The server motherboard 3 sends out video information (VGA signals), converts the video information into digital signals through a digital-to-analog conversion circuit, and sends the digital signals to the ARM processor 1 or the co-processing control submodule 23.
The co-processing module 2 further comprises a data encapsulation and analysis submodule 22, and the data encapsulation and analysis submodule 22 is used for encapsulating or analyzing the transmission data between the ARM processor 1 and the co-processing control submodule 23.
When the ARM processor 1 normally runs, the co-processing module 2 forwards information sent by the ARM processor 1 to the management platform 5 or the server mainboard 3; during the failure period of the ARM processor 1, the co-processing module 2 takes over the monitoring of the server mainboard 3, namely receives video information sent by the server mainboard 3, directly sends the video information to the management platform 5 through a network, and sends a mainboard power supply control signal to the server mainboard 3, so that the function of monitoring the operation of the server is achieved. When the ARM processor 1 is reset and started, the control right is transferred to the ARM processor 1.
After receiving the failure information of the ARM processor 1, the co-processing control submodule 23 also judges the alarm level according to the internal configuration strategy thereof, so as to realize the alarm function and enable the administrator to find the fault in time. The co-processing control sub-module 23 is configured with:
an alarm receiving unit: receiving failure information of the ARM processor 1 sent by the watching gate module;
an alarm determination unit: judging the alarm level according to the failure information of the ARM processor 1;
an alarm transmission unit: and sending out the alarm information in a message form.
The co-processing control sub-module 23 judges the alarm level according to the failure interval time and decides whether to shut down the server.
When the failure interval is smaller than the shortest interval preset threshold (can be set to be 1 hour), sending out a three-level alarm and closing the server; when the failure interval is smaller than a preset threshold value (which can be set to be 12 hours) of the middle interval, a secondary alarm is sent out; when the failure interval is less than the longest interval preset threshold (which may be set to 24 hours), a three-level alarm is issued.
The alarm information message sent by the alarm sending unit comprises the following information: alarm type, purpose number, equipment request number, current ARM processor failure time, last ARM processor failure time, 24-hour failure times, historical failure times, overflow mark and ECC check data. The management platform 5 receives the message information and can monitor the failure state of the server in real time.
as shown in fig. 2, the intelligent co-processing method for the BMC chip provided in this embodiment specifically includes the following steps:
S1: the co-processing module 2 forwards the interaction information and the mainboard control signal sent by the ARM processor 1 and judges whether the ARM processor 1 is invalid;
s2: if the ARM processor 1 does not fail, repeating the step S1, and if the ARM processor 1 fails, taking over the interaction information and the motherboard control signal by the co-processing module 2, and sending an alarm information, and restarting the ARM processor 1.
in step S2, the co-processing module 2 takes over the interactive information means that the co-processing module 2 receives the motherboard information and sends it out, and sends out a motherboard power control signal to the server motherboard 3.
The step S2 of sending out the alarm information specifically includes the following steps:
s2.1: judging whether the failure interval is smaller than a preset threshold value of the shortest interval or not;
s2.2: if the failure interval is smaller than the shortest interval preset threshold, sending a three-level alarm and closing the server; otherwise, judging whether the failure interval is smaller than a preset threshold value of the middle-level interval or not;
S2.3: if the failure interval is smaller than a preset threshold value of the middle-level interval, a second-level alarm is sent out; otherwise, judging whether the failure interval is smaller than the longest interval preset threshold value;
s2.4: and if the failure interval is smaller than the maximum time preset threshold, a primary alarm is sent out.
The above disclosure is only for the preferred embodiments of the present invention, but the present invention is not limited thereto, and any non-inventive changes that can be made by those skilled in the art and several modifications and amendments made without departing from the principle of the present invention shall fall within the protection scope of the present invention.
Claims (7)
1. An intelligent co-processing device for a BMC chip is characterized by comprising: the system comprises an ARM processor, a communication module, a co-processing module connected with the ARM processor, a server mainboard connected with the ARM processor and the co-processing module respectively, and a management platform connected with the co-processing module through the communication module;
The co-processing module comprises:
Watchdog submodule: carrying out failure detection on the ARM processor, resetting the ARM processor, and sending failure information and resetting information of the ARM processor to the co-processing control submodule;
The coprocessing control submodule: a mainboard information receiving port and a mainboard control signal sending port are arranged; when the ARM processor normally operates, the interactive information sent by the ARM processor is forwarded to the management platform through the communication module, the mainboard control signal sent by the ARM processor is forwarded to the server mainboard through the mainboard control signal sending port, and the control information received through the communication module is sent to the ARM processor; when the ARM processor failure information is received, the mainboard information received by the mainboard information receiving port is sent to the management platform by the communication module, the mainboard control signal sending port sends a mainboard control signal to the server mainboard, and the communication module sends alarm information to the management platform.
2. The BMC chip intelligent co-processing device of claim 1, wherein said co-processing control sub-module comprises:
an alarm receiving unit: receiving failure information of the ARM processor sent by the watching gate module;
an alarm determination unit: judging the alarm level according to the failure information of the ARM processor;
an alarm transmission unit: and sending out the alarm information in a message form.
3. The intelligent co-processing device for the BMC chip of claim 2, wherein the alarm message sent by the alarm sending unit includes the following information: alarm type, purpose number, equipment request number, current ARM processor failure time, last ARM processor failure time, 24-hour failure times, historical failure times, overflow mark and ECC check data.
4. The intelligent co-processing device for the BMC chip according to claim 1, 2 or 3, wherein the motherboard information receiving port is a video information receiving port, and the motherboard control signal issuing port is a motherboard power control signal issuing port.
5. the BMC chip intelligent co-processing device of claim 4, wherein the interactive information sent by the ARM processor comprises video information.
6. the BMC chip intelligent co-processing device of claim 1, 2 or 3, wherein the communication module is a network interface.
7. the intelligent co-processing device for the BMC chip of claim 1, 2 or 3, wherein the co-processing module further comprises a data encapsulation parsing sub-module, the data encapsulation parsing sub-module is configured to encapsulate or parse the transmission data between the ARM processor and the co-processing control sub-module.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103324495A (en) * | 2012-03-23 | 2013-09-25 | 鸿富锦精密工业（深圳）有限公司 | Method and system for data center server boot management |
| CN103577298A (en) * | 2012-07-31 | 2014-02-12 | 鸿富锦精密工业（深圳）有限公司 | Baseboard management controller monitoring system and method |
| CN104317677A (en) * | 2014-09-29 | 2015-01-28 | 浪潮电子信息产业股份有限公司 | Brickland-based redundant monitoring management system and method |
| CN104503932A (en) * | 2015-01-07 | 2015-04-08 | 加弘科技咨询(上海)有限公司 | Method and system for judging master baseboard management controller of multi-mainboard server |
| CN104598329A (en) * | 2015-02-12 | 2015-05-06 | 浪潮电子信息产业股份有限公司 | Automatic BMC (baseboard management controller) fault solution method based on RMC (rack server management center) management |
| CN105117317A (en) * | 2015-08-17 | 2015-12-02 | 浪潮(北京)电子信息产业有限公司 | Method and device for monitoring server performance |
| CN105278644A (en) * | 2015-09-24 | 2016-01-27 | 浪潮电子信息产业股份有限公司 | Method for rotating fan of server at full-speed after BMC (Baseboard Management Controller) fails |
| CN106814834A (en) * | 2017-01-22 | 2017-06-09 | 济南浪潮高新科技投资发展有限公司 | A kind of server heat dissipation control method and system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070234123A1 (en) * | 2006-03-31 | 2007-10-04 | Inventec Corporation | Method for detecting switching failure |
-
2017
- 2017-07-12 CN CN201710567604.8A patent/CN107315369B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103324495A (en) * | 2012-03-23 | 2013-09-25 | 鸿富锦精密工业（深圳）有限公司 | Method and system for data center server boot management |
| CN103577298A (en) * | 2012-07-31 | 2014-02-12 | 鸿富锦精密工业（深圳）有限公司 | Baseboard management controller monitoring system and method |
| CN104317677A (en) * | 2014-09-29 | 2015-01-28 | 浪潮电子信息产业股份有限公司 | Brickland-based redundant monitoring management system and method |
| CN104503932A (en) * | 2015-01-07 | 2015-04-08 | 加弘科技咨询(上海)有限公司 | Method and system for judging master baseboard management controller of multi-mainboard server |
| CN104598329A (en) * | 2015-02-12 | 2015-05-06 | 浪潮电子信息产业股份有限公司 | Automatic BMC (baseboard management controller) fault solution method based on RMC (rack server management center) management |
| CN105117317A (en) * | 2015-08-17 | 2015-12-02 | 浪潮(北京)电子信息产业有限公司 | Method and device for monitoring server performance |
| CN105278644A (en) * | 2015-09-24 | 2016-01-27 | 浪潮电子信息产业股份有限公司 | Method for rotating fan of server at full-speed after BMC (Baseboard Management Controller) fails |
| CN106814834A (en) * | 2017-01-22 | 2017-06-09 | 济南浪潮高新科技投资发展有限公司 | A kind of server heat dissipation control method and system |
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Effective date of registration: 20191113 Address after: 215100 No. 1 Guanpu Road, Guoxiang Street, Wuzhong Economic Development Zone, Suzhou City, Jiangsu Province Applicant after: Suzhou Wave Intelligent Technology Co., Ltd. Address before: 450000 Henan province Zheng Dong New District of Zhengzhou City Xinyi Road No. 278 16 floor room 1601 Applicant before: Zhengzhou Yunhai Information Technology Co. Ltd. |
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