CN107305778B - Memory circuit and precharge method of memory circuit - Google Patents
Memory circuit and precharge method of memory circuit Download PDFInfo
- Publication number
- CN107305778B CN107305778B CN201610239879.4A CN201610239879A CN107305778B CN 107305778 B CN107305778 B CN 107305778B CN 201610239879 A CN201610239879 A CN 201610239879A CN 107305778 B CN107305778 B CN 107305778B
- Authority
- CN
- China
- Prior art keywords
- data line
- memory circuit
- bank
- switch element
- sense amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Read Only Memory (AREA)
Abstract
The invention provides a storage circuit and a pre-charging method of the storage circuit, wherein the storage circuit comprises a first storage bank, a second storage bank and a third storage bank, wherein the first storage bank is connected with a first sense amplifier through a first data line; a second storage bank connected to a second sense amplifier through a second data line; one end of the first switch element is connected with the first data line, and the other end of the first switch element is connected with the second data line; and a control circuit, connected to the control end of the first switch element, for controlling the on and off of the first switch element. The pre-charging method comprises the steps of arranging a first switch element, wherein one end of the first switch element is connected with the first data line, and the other end of the first switch element is connected with the second data line; when the first storage bank executes the pre-charge action of reading or writing and the second storage bank is operated in an idle state, the switch element is conducted.
Description
Technical Field
The present invention relates to a memory circuit, and more particularly, to a circuit and method for precharging a memory circuit during reading and writing.
Background
The requirement of the memory circuit for operation speed is getting higher nowadays, and among the time consumed by various actions inside the memory circuit, the time of the memory circuit for pre-charging after reading or writing is an important design parameter. In general, when a memory circuit performs a read or write operation, it is necessary to pre-charge a data line used for the read or write operation to a high voltage level.
In some cases, if the precharge operation is not performed correctly, the read data may be incorrect when the next read operation is performed; or when the memory circuit is processing continuous reading operation, the voltage level of the used data line is lower and lower because the precharging operation is not executed correctly, which causes the malfunction of the sensing amplifier of the memory circuit connected with the data line.
Disclosure of Invention
Accordingly, the present invention provides a memory circuit and a precharge method thereof to enhance the performance of the precharge circuit of the memory circuit and to prevent the precharge operation from being incorrectly performed.
According to an embodiment of the present invention, a memory circuit is provided, which includes a first memory bank (memorybank) connected to a first sense amplifier through a first data line; a second storage bank connected to a second sense amplifier through a second data line; one end of the first switch element is connected with the first data line, and the other end of the first switch element is connected with the second data line; and a control circuit connected to the control terminal of the first switch element for controlling the on/off of the first switch element, wherein when the storage circuit performs a read or write pre-charge operation on the first storage bank and the second storage bank is in an idle state, the control circuit turns on the first switch element.
According to another embodiment of the present invention, a method for precharging a memory circuit is provided, wherein a first bank of the memory circuit is connected to a first sense amplifier through a first data line, and a second bank of the memory circuit is connected to a second sense amplifier through a second data line, the method includes providing a first switching element, one end of the first switching element is connected to the first data line, and the other end of the first switching element is connected to the second data line; and turning on the first switch element when the first storage bank performs a read or write precharge operation and the second storage bank is in an idle state.
The invention has the advantages that when the storage bank is operated in an idle state and the storage bank is to execute the action of pre-charging, the control circuit not only conducts the switch element to execute the action of pre-charging, but also provides an additional pre-charging path, thereby providing a faster pre-charging speed than the prior art, ensuring the correct execution of pre-charging and reducing the possibility of incorrect read data.
Drawings
Fig. 1A is a schematic diagram of a memory circuit block according to an embodiment of the invention.
FIG. 1B is a diagram of a circuit block of a memory according to an embodiment of the invention.
Fig. 2A is a schematic diagram of a memory circuit block according to an embodiment of the invention.
FIG. 2B is a timing diagram illustrating the precharge of the memory circuit according to one embodiment of the present invention.
Reference numerals:
100A, 100B, 200 memory circuit
101. 102, 201, 202 repository
1011. 1012, 2011, 2013, 2012 and 2014 data lines
103B shared sense amplifier
1031. 1032, 2031, 2032 sense amplifier
104. 204 control circuit
110-130, 210-260 switching element
T set time
t1 time point
Vdd voltage source
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 1A is a schematic diagram of a memory circuit 100A according to an embodiment of the invention. The memory circuit 100A includes a memory bank (memory bank) 101; a repository 102; a sense amplifier 1031 connected to the repository 101 via a data line 1011; a sense amplifier 1032 connected to the storage bank 102 via a data line 1012; a switch element 110, one end of the switch element 110 is connected to the data line 1011, and the other end of the switch element 110 is connected to the data line 1012; a switch device 120, wherein one end of the switch device 120 is connected to the data line 1011, and the other end of the switch device 120 is connected to a voltage source Vdd; a switching element 130, one end of the switching element 130 is connected to the data line 1012, and the other end of the switching element 130 is connected to the voltage source Vdd; and a control circuit 104, respectively connected to the control terminals of the switching elements 110, 120, and 130, and respectively controlling the switching elements 110, 120, and 130 to be turned on and off.
Generally, when a memory circuit performs a read or write operation on a bank, a precharge operation is performed first after the read or write operation is completed, and then the next read or write operation is performed. According to the pre-charging operation of the conventional memory circuit, after the memory circuit 100A completes one read or write operation on the bank 101 through the data line 1011, the control circuit 104 only turns on the switch device 120, so that the data line 1011 is pre-charged to a high voltage level (e.g., approximately equal to the voltage level of the voltage source Vdd) by the voltage source Vdd before the next read or write operation. In addition, according to the operation configuration of the conventional memory circuit, when a bank of the memory circuit is operated in an idle state, the data line of the bank connected to a sense amplifier is charged to be maintained at the high voltage level, for example, when the bank 101 of the memory circuit 100A is operated in an idle state, the switching element 120 is operated in a conducting state, and the potential of the data line 1011 is maintained at the high voltage level.
In one embodiment of the present invention, when the bank 102 is in the idle state and the bank 101 is to perform the pre-charging operation, the control circuit 104 may further turn on the switching element 110 to provide an additional pre-charging path in addition to turning on the switching element 120 to perform the pre-charging operation, thereby providing a faster pre-charging speed than the conventional art. More specifically, when the bank 102 is in an idle state and the bank 101 completes a read or write operation, the control circuit 104 turns on the switch device 120 to precharge the data line 1011 via the voltage source Vdd, and after a predetermined time, the control circuit 104 turns on the switch device 110 to precharge the data line 1011 via the voltage source Vdd and the data line 1012 maintained at the high voltage level, thereby improving the precharge capability and speed of the memory circuit 100A.
In another embodiment of the present invention, when the bank 102 is in the idle state and the bank 101 completes one read or write operation, the control circuit 104 may turn on the switch device 110 first, so that the data line 1011 is precharged through the data line 1012 maintained at the high voltage level, and turn on the switch device 120 after a predetermined time, so that the data line 1011 is precharged through the data line 1012 and the voltage source Vdd at the same time. At this time, since the voltage between the data line 1011 and the data line 1012 maintained at the high level is larger, the precharging speed of the memory circuit 100A can be further increased compared to the previous embodiment.
In one embodiment, the sense amplifiers 1031, 1032 may be integrated into a common sense amplifier, such as the common sense amplifier 103B of the memory circuit 100B shown in fig. 1B. In one embodiment, when the bank 102 is in an idle state and the bank 101 is to perform the pre-charging operation, the control circuit 104 turns on the switch element 120 for a predetermined time and then turns on the switch element 110. In another embodiment, when the bank 102 is in an idle state and the bank 101 is going to perform the pre-charging operation, the control circuit 104 turns on the switch element 110 for a predetermined time and then turns on the switch element 120. In other embodiments, when the bank 102 is in an idle state and the bank 101 is to perform the pre-charging operation, the control circuit 104 turns on the switch elements 110 and 120 at the same time.
In one embodiment, the precharge path of the banks 101, 102 may be added simultaneously due to the setting of the switching element 110. Therefore, by providing one switching element 110 with the same precharge capability, the element size of the two switching elements 120 and 130 (switching elements conventionally used for the precharge operation of the banks 101 and 102) can be reduced at the same time, and the overall circuit size of the memory circuit can be reduced. In another embodiment, the switching element 110 is provided to increase the precharge speed of the memory circuit and reduce the overall circuit size of the memory circuit.
Fig. 2A is a schematic diagram of a memory circuit 200 according to an embodiment of the invention. The memory circuit 200 includes a repository 201; a repository 202; a sense amplifier 2031 connected to the repository 201 via data lines 2011, 2013; a sense amplifier 2032 connected to the storage bank 202 via data lines 2012 and 2014; a switching element 210, one end of the switching element 210 is connected to the data line 2011, and the other end of the switching element 210 is connected to the data line 2012; one end of the switching element 220 is connected to the data line 2013, and the other end of the switching element 220 is connected to the data line 2014; a switch element 230, wherein one end of the switch element 230 is connected to the data line 2011, and the other end of the switch element 230 is connected to a voltage source Vdd; a switching element 240, one end of the switching element 240 is connected to the data line 2012, and the other end of the switching element 240 is connected to the voltage source Vdd; a switch element 250, one end of the switch element 250 is connected to the data line 2013, and the other end of the switch element 250 is connected to the voltage source Vdd; a switch element 260, one end of the switch element 260 is connected to the data line 2014, and the other end of the switch element 260 is connected to the voltage source Vdd; and a control circuit 204, which is respectively connected to the control terminals (gates) of the switching elements 210, 220, 230, 240, 250, 260, and respectively controls the switching elements 210, 220, 230, 240, 250, 260 to be turned on and off. In this embodiment, the data line 2013 is the inverse data of the data transmitted by the transmission data line 2011, and the data line 2014 is the inverse data of the data transmitted by the transmission data line 2012. In this embodiment, the switching elements 210, 220, 230, 240, 250, 260 are P-type field effect transistors.
In this embodiment, the bank 202 is operated in an idle state, so the switching elements 240 and 260 are turned on and the potentials of the data lines 2012 and 2014 are maintained at a high voltage level (e.g., approximately equal to the voltage level of the voltage source Vdd). When the bank 201 is going to perform the above-mentioned pre-charging operation, the control circuit 204 turns on the switching elements 230 and 250 to make the data lines 2011 and 2013 perform the pre-charging operation via the voltage source Vdd, respectively, and after a predetermined time, the control circuit 204 turns on the switching elements 210 and 220 to make the data line 2011 perform the pre-charging operation via the data line 2012 and the voltage source Vdd at the same time; the data line 2013 is precharged via the data line 2014 and the voltage source Vdd, thereby improving the precharge capability of the memory circuit 200 and increasing the precharge speed of the memory circuit 200.
In another embodiment, when the bank 201 is going to perform the above-mentioned precharging operation, the control circuit 204 turns on the switching elements 210 and 220 to precharge the data lines 2011 and 2013 through the data lines 2012 and 2014, respectively, and after a predetermined time, the control circuit 204 turns on the switching elements 230 and 250 to precharge the data line 2011 through the data line 2012 and the voltage source Vdd at the same time; the data line 2013 is precharged via the data line 2014 and the voltage source Vdd. At this time, since the voltage between the data lines 2011 and 2013 and the data lines 2012 and 2014 maintained at the high level is larger, the precharging speed of the memory circuit 200 can be further increased compared to the previous embodiment. In addition, in other embodiments of the present invention, the controller may also turn on the switching elements 210, 220, 230, and 250 at the same time, so that the data line 2011 directly and simultaneously performs the pre-charging operation through the data line 2012 and the voltage source Vdd; the data line 2013 is precharged directly and simultaneously through the data line 2014 and the voltage source Vdd.
FIG. 2B is a timing diagram illustrating the precharge of the memory circuit 200 when reading from or writing to the bank 201 according to one embodiment of the present invention. Referring to FIG. 2A, in this embodiment, the storage bank 202 is operated in an idle state, so that the switching elements 240 and 260 are turned on and the potentials of the data lines 2012 and 2014 are maintained at a high voltage level (not shown, in this embodiment, equal to the voltage level of the voltage source Vdd); the bank 201 has just performed the write operation, and the voltage on the data line 2011 is at a low voltage level (0V), and the voltage on the data line 2013 transmitting the inverted data on the data line 2011 is at the high voltage level. When the bank 201 performs the above-mentioned precharge operation at time T1, the control circuit 204 first pulls down the gate voltages of the switching elements 210 and 220 to turn on the switching elements 210 and 220 to precharge the data lines 2011 and 2013 through the data lines 2012 and 2014, respectively, and after a predetermined time T, the control circuit 204 pulls down the gate voltages of the switching elements 230 and 250 to turn on the switching elements 230 and 250 to precharge the data lines 2011 and 2013 through the data lines 2012 and 2014 and the voltage source Vdd, respectively.
In one embodiment, the sense amplifiers 2031, 2032 may be integrated into a common sense amplifier. In one embodiment, the bank 202 is operated in an idle state, so that the switching elements 240 and 260 are turned on and the potentials of the data lines 2012 and 2014 are maintained at the high voltage level, when the bank 201 is to perform the pre-charge operation, the control circuit 204 turns on the switching elements 230 and 250 for a predetermined time and then turns on the switching elements 210 and 220. In another embodiment, when the bank 202 is in an idle state and the bank 201 is to perform the pre-charging operation, the control circuit 204 may first turn on the switch elements 210 and 220 for a predetermined time and then turn on the switch elements 230 and 250. In other embodiments, when the bank 202 is in an idle state and the bank 201 is to perform the pre-charging operation, the control circuit 104 turns on the switch elements 210, 220, 230, 250 at the same time.
In one embodiment, the memory circuits 100A, 100B, and 200 may be a dynamic random access memory circuit, a static random access memory circuit, a flash memory circuit, or a resistance random access memory circuit, but the invention is not limited thereto. In one embodiment, the switching devices 110 to 130, 210 to 260 may be P-type or N-type field effect transistor devices, but the invention is not limited thereto.
The invention has the advantages that when the storage bank is operated in an idle state and the storage bank is to execute the action of pre-charging, the control circuit not only conducts the switch element to execute the action of pre-charging, but also provides an additional pre-charging path, thereby providing a faster pre-charging speed than the prior art, ensuring the correct execution of pre-charging and reducing the possibility of incorrect read data.
Although the present invention has been described with reference to particular embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A memory circuit, comprising:
a first storage bank connected to a first sense amplifier through a first data line;
a second storage bank connected to a second sense amplifier through a second data line;
one end of the first switch element is connected with the first data line, and the other end of the first switch element is connected with the second data line; and
and a control circuit connected to the control terminal of the first switch element for controlling the on/off of the first switch element, wherein when the memory circuit performs a read or write precharge operation on the first bank and the second bank is in an idle state, the control circuit turns on the first switch element.
2. The memory circuit of claim 1, further comprising:
a third data line connecting the first storage bank and the first sense amplifier;
a fourth data line connecting the second storage bank and the second sense amplifier; and
one end of the second switch element is connected with the third data line, and the other end of the second switch element is connected with the fourth data line;
the third data line transmits inverted data of the data transmitted by the first data line, and the fourth data line transmits inverted data of the data transmitted by the second data line;
the control circuit is connected with the control end of the second switch element and controls the second switch element to be switched on and off.
3. The memory circuit of claim 2, further comprising:
one end of the third switching element is connected with the first data line, and the other end of the third switching element is connected with a voltage source;
one end of the fourth switching element is connected with the second data line, and the other end of the fourth switching element is connected with the voltage source;
one end of the fifth switching element is connected with the third data line, and the other end of the fifth switching element is connected with the voltage source; and
one end of the sixth switching element is connected with the fourth data line, and the other end of the sixth switching element is connected with the voltage source;
the control circuit is respectively connected with the control ends of the third, fourth, fifth and sixth switch elements, and the control circuit can respectively control the on and off of the first, second, third, fourth, fifth and sixth switch elements.
4. The memory circuit of claim 3, wherein the control circuit turns on the fourth and sixth switching elements when the second bank operates in an idle state;
when the storage circuit performs a read or write precharge operation on the first storage bank and the second storage bank is in an idle state, the control circuit respectively turns on the first, second, third and fifth switch elements.
5. The memory circuit of claim 4, wherein the control circuit turns on the first, second, third and fifth switch elements in a sequence that turns on the first and second switch elements first and then turns on the third and fifth switch elements when the memory circuit performs a read or write precharge operation on the first bank and the second bank is in an idle state.
6. The memory circuit of claim 1, wherein the memory circuit is a dynamic random access memory circuit, a static random access memory circuit, a flash memory circuit, or a resistive random access memory circuit.
7. The memory circuit of claim 1, wherein the first sense amplifier and the second sense amplifier are integrated into a common sense amplifier.
8. A method of precharging a memory circuit, wherein a first bank of the memory circuit is connected to a first sense amplifier through a first data line, and a second bank of the memory circuit is connected to a second sense amplifier through a second data line, the method comprising:
arranging a first switch element, wherein one end of the first switch element is connected with the first data line, and the other end of the first switch element is connected with the second data line; and
when the first storage bank executes the pre-charge action of reading or writing and the second storage bank is operated in an idle state, the switch element is conducted.
9. The method of precharging a memory circuit as recited in claim 8, further comprising:
the switching element is turned on while the first bank begins to perform a read or write precharge operation.
10. The method of claim 8, wherein the first sense amplifier and the second sense amplifier are integrated into a common sense amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610239879.4A CN107305778B (en) | 2016-04-18 | 2016-04-18 | Memory circuit and precharge method of memory circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610239879.4A CN107305778B (en) | 2016-04-18 | 2016-04-18 | Memory circuit and precharge method of memory circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107305778A CN107305778A (en) | 2017-10-31 |
| CN107305778B true CN107305778B (en) | 2020-05-01 |
Family
ID=60152656
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610239879.4A Active CN107305778B (en) | 2016-04-18 | 2016-04-18 | Memory circuit and precharge method of memory circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107305778B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101253570A (en) * | 2005-09-01 | 2008-08-27 | 飞思卡尔半导体公司 | Memory with robust data reading and method for reading data |
| CN104160453A (en) * | 2012-03-27 | 2014-11-19 | 苹果公司 | Memory with redundant sense amplifier |
| CN104616692A (en) * | 2013-11-05 | 2015-05-13 | 旺宏电子股份有限公司 | Integrated circuit of memory, and operating method thereof |
| CN204680377U (en) * | 2015-04-01 | 2015-09-30 | 山东华芯半导体有限公司 | A kind of RRAM sense amplifier |
| CN105469827A (en) * | 2014-09-25 | 2016-04-06 | 旺宏电子股份有限公司 | Sensing method for flash memory and memory element thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101666941B1 (en) * | 2010-07-06 | 2016-10-17 | 삼성전자주식회사 | Non-volatile memory device, method of operating the same, and semiconductor system having the same |
| US9552251B2 (en) * | 2014-04-22 | 2017-01-24 | Sandisk Technologies Llc | Neighboring word line program disturb countermeasure for charge-trapping memory |
-
2016
- 2016-04-18 CN CN201610239879.4A patent/CN107305778B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101253570A (en) * | 2005-09-01 | 2008-08-27 | 飞思卡尔半导体公司 | Memory with robust data reading and method for reading data |
| CN104160453A (en) * | 2012-03-27 | 2014-11-19 | 苹果公司 | Memory with redundant sense amplifier |
| CN104616692A (en) * | 2013-11-05 | 2015-05-13 | 旺宏电子股份有限公司 | Integrated circuit of memory, and operating method thereof |
| CN105469827A (en) * | 2014-09-25 | 2016-04-06 | 旺宏电子股份有限公司 | Sensing method for flash memory and memory element thereof |
| CN204680377U (en) * | 2015-04-01 | 2015-09-30 | 山东华芯半导体有限公司 | A kind of RRAM sense amplifier |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107305778A (en) | 2017-10-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9466357B2 (en) | Circuit for mitigating write disturbance of dual-port SRAM | |
| US10503421B2 (en) | Configurable memory storage system | |
| US9685208B2 (en) | Assist circuit for memory | |
| US8598912B2 (en) | Transistor voltage threshold mismatch compensated sense amplifiers and methods for precharging sense amplifiers | |
| US20150255148A1 (en) | Bit line write assist for static random access memory architectures | |
| US10714153B2 (en) | Reversed bias compensation for sense amplifier operation | |
| US11238908B2 (en) | Memory circuit and method of operating same | |
| US20130028007A1 (en) | Sense amplifier | |
| US7539064B2 (en) | Precharge circuit of semiconductor memory apparatus | |
| US9013914B2 (en) | Semiconductor memory device and method for controlling semiconductor memory device | |
| CN107305778B (en) | Memory circuit and precharge method of memory circuit | |
| JP2015056199A (en) | Nonvolatile semiconductor storage device and data transfer method | |
| CN111902872B (en) | Self-termination write circuit and method | |
| TWI582789B (en) | Memory circuit and the pre-charge method thereof | |
| US9076501B2 (en) | Apparatuses and methods for reducing current leakage in a memory | |
| US9812189B2 (en) | Read and write apparatus and method for a dual port memory | |
| CN105590647B (en) | Non-volatile static random access memory circuit | |
| US10803949B2 (en) | Master slave level shift latch for word line decoder memory architecture | |
| US10699761B2 (en) | Word line decoder memory architecture | |
| US10153036B2 (en) | Method for autocorrective writing to a multiport static random access memory device, and corresponding device | |
| US10141070B2 (en) | Semiconductor device | |
| JP2011159332A (en) | Semiconductor memory device | |
| KR20060088679A (en) | Device for controlling the activation period of a word line of a volatile memory circuit and the method therefor | |
| US9607669B2 (en) | Semiconductor memory device including precharge circuit | |
| US9378807B2 (en) | Non-volatile static random access memory circuits |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |