CN107302021B - Groove type transistor and manufacturing method thereof - Google Patents

Groove type transistor and manufacturing method thereof Download PDF

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CN107302021B
CN107302021B CN201710487846.6A CN201710487846A CN107302021B CN 107302021 B CN107302021 B CN 107302021B CN 201710487846 A CN201710487846 A CN 201710487846A CN 107302021 B CN107302021 B CN 107302021B
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gate electrode
substrate
trench
electrode
drain
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CN107302021A (en
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康晓旭
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Shanghai IC R&D Center Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Abstract

The invention discloses an optimized groove type transistor and a manufacturing method thereof, strip-shaped grooves are formed on the surface of a substrate, a channel layer is formed by utilizing the side wall and the bottom of the groove, and forming a first gate electrode dielectric layer on the inner wall of the trench, and forming a second gate electrode dielectric layer on the surface of the substrate, filling a gate electrode material in the trench to form a first gate electrode, and forming a ring-shaped source and a drain surrounding the two sides and the bottom of the trench at the two ends of the trench, forming a second gate electrode on the substrate covering the trench, the second gate electrode being formed on the substrate to serve as a conductive terminal of the first gate electrode, by also sharing the source, drain and channel layers in the substrate with the first gate electrode, two parallel transistors are formed, thereby enhancing the performance of the transistor while avoiding the complex non-planar processes involved in FINFET fabrication, and thus facilitating the simplification of process integration and cost reduction.

Description

Groove type transistor and manufacturing method thereof
Technical Field
The present invention relates to the field of semiconductor integrated circuit manufacturing technology, and more particularly, to a trench transistor and a method for manufacturing the same.
Background
The semiconductor Integrated Circuit (IC) industry has experienced rapid growth. In the development of ICs, functional density (i.e., the number of interconnected devices per chip area) is typically increased, while geometry size (i.e., the smallest device or interconnect line that can be fabricated using a fabrication process) is reduced. Improvements in IC performance have been achieved primarily by the ever shrinking dimensions of integrated circuit devices to increase their speed. This scaled down process has the advantage of improving production efficiency and reducing associated costs. At the same time, this scaling down process also increases the complexity of handling and manufacturing the ICs.
In the process of seeking higher device density, higher performance, and lower cost, as integrated circuit processes continue to evolve into nanotechnology process nodes, some manufacturers have begun considering how to transition from planar CMOS transistors to three-dimensional fin field effect transistor (FinFET) device structures in order to overcome short channel effects and increase drive current density per unit area. A FinFET device is a multi-gate MOS device that has a very outstanding short channel control and high drive current due to more gate control area, narrower channel depletion region. Compared with a planar transistor, the FinFET device can better control carriers in an active region and provide larger driving current compared with a traditional MOS structure, so that the device performance is improved. Also, the FinFET device reduces short channel effects due to improved control over the channel.
However, FinFET devices require bulk fabrication above the substrate and form a uniform structure; because the non-planar process in the FinFET device manufacturing is difficult to be compatible with the existing CMOS planar process, the forming process of the FinFET device is very complex and high in cost, and the rapid development of the FinFET device to low-cost and high-efficiency production is restricted.
Therefore, there is a need for a new transistor structure that enhances transistor performance while avoiding the complex non-planar processes involved in the fabrication of FinFET devices.
Disclosure of Invention
The present invention is directed to overcome the above-mentioned drawbacks of the prior art, and provides a trench transistor and a method for fabricating the same, which can enhance the performance of the transistor and facilitate the simplification of the process integration and the cost reduction.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a trench transistor, comprising:
the gate electrode structure comprises a strip-shaped groove horizontally formed on the surface of a substrate, wherein a gate electrode material is filled in the groove to form a first gate electrode;
a channel layer formed along the sidewall and bottom of the trench in the substrate;
the substrate is respectively positioned at two ends of the groove and forms a source electrode and a drain electrode around the strip-shaped two sides and the bottom of the groove outside the channel layer;
a second gate electrode on the substrate to completely cover the trench, the second gate electrode being connected to the top surface of the first gate electrode through a bottom surface thereof;
and the second gate electrode and the first gate electrode form two parallel transistors by sharing a source electrode, a drain electrode and a channel layer which are positioned in the substrate, and the second gate electrode simultaneously also serves as a conductive leading-out terminal of the first gate electrode.
Preferably, a first gate electrode dielectric layer is arranged on the inner wall of the trench between the first gate electrode and the channel layer, and a second gate electrode dielectric layer is arranged between the second gate electrode and the surface of the substrate.
Preferably, the width of the second gate electrode is greater than the width of the trench.
Preferably, the channel layer extends along the surface of the substrate under the second gate electrode to form a turn.
Preferably, the source and the drain respectively surround one end of the trench.
Preferably, the upper surfaces of the source electrode and the drain electrode are provided with source electrode and drain electrode conducting leads.
A manufacturing method of the trench transistor comprises the following steps:
providing a substrate, and forming a strip-shaped groove in the horizontal direction on the surface of the substrate;
forming a channel layer in the substrate by using the side wall and the bottom of the groove;
forming a first gate electrode dielectric layer on the inner wall of the groove, and forming a second gate electrode dielectric layer on the surface of the substrate;
filling a gate electrode material in the groove to form a first gate electrode;
forming a source electrode and a drain electrode on the outer sides of the channel layers at two ends of the groove respectively, and enabling the source electrode and the drain electrode to surround the two strip-shaped sides and the bottom of the groove respectively;
and forming a second gate electrode on the substrate, wherein the second gate electrode completely covers the groove and is connected with the first gate electrode.
Preferably, the method further comprises the following steps: and a source electrode and a drain electrode are formed on the upper surfaces of the source electrode and the drain electrode and are led out in a conducting manner.
Preferably, when the channel layer is formed, the channel layer is extended along the surface of the substrate at a position below the second gate electrode to form a turn.
Preferably, when the source electrode and the drain electrode are formed, the source electrode and the drain electrode are respectively extended toward an end surface of one end of the trench where the source electrode and the drain electrode are located so as to surround the end portion of the trench.
According to the technical scheme, the strip-shaped groove is formed on the surface of the substrate, the channel layer is formed by utilizing the side wall and the bottom of the groove, the first gate electrode dielectric layer is formed on the inner wall of the groove, the second gate electrode dielectric layer is formed on the surface of the substrate, the first gate electrode is formed by filling the gate electrode material in the groove, the annular source and the annular drain which surround the strip-shaped two sides and the bottom of the groove are formed at the two ends of the groove respectively, the second gate electrode which covers the groove is formed on the substrate, and the second gate electrode is used as a conductive leading-out end of the first gate electrode, and meanwhile, the source, the drain and the channel layer which are positioned in the substrate are shared with the. The invention improves the traditional mode of forming the gate electrode on the substrate into the mode of respectively forming the gate electrode on the substrate and in the substrate, and can be completely compatible with a planar CMOS process, thereby not only enhancing the performance of the transistor, but also avoiding the complex non-planar process in the FINFET manufacture, and being easier for simplifying the process integration and reducing the cost.
Drawings
Fig. 1-2 are schematic views of a trench transistor structure according to a preferred embodiment of the invention;
FIG. 3 is a perspective view of a trench structure;
FIG. 4 is a cross-sectional view of a trench and gate electrode structure;
fig. 5 is a cross-sectional view of a source (drain) and its conductive lead-out structure.
Detailed Description
The invention forms a strip-shaped groove on the surface of a substrate, forms a channel layer by utilizing the side wall and the bottom of the groove, forms a first gate electrode dielectric layer on the inner wall of the groove, forms a second gate electrode dielectric layer on the surface of the substrate, fills a gate electrode material in the groove to form a first gate electrode, forms an annular source and a drain which surround the strip-shaped two sides and the bottom of the groove at the two ends of the groove respectively, forms a second gate electrode covering the groove on the substrate, and forms two transistors which are connected in parallel by sharing the source, the drain and the channel layer with the first gate electrode while the second gate electrode is used as a conductive leading-out end of the first gate electrode.
The invention improves the traditional mode of forming the gate electrode on the substrate into the mode of respectively forming the gate electrode (the second gate electrode and the first gate electrode) on the substrate and in the substrate, and can be completely compatible with a planar CMOS process, thereby not only enhancing the performance of the transistor, but also avoiding the complex non-planar process in the FINFET manufacture, and being easier to simplify the process integration and reduce the cost.
The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.
In the following detailed description of the embodiments of the present invention, in order to clearly illustrate the structure of the present invention and to facilitate explanation, the structure shown in the drawings is not drawn to a general scale and is partially enlarged, deformed and simplified, so that the present invention should not be construed as limited thereto.
In the following description of the present invention, please refer to fig. 1-2, and fig. 1-2 are schematic views of a trench transistor structure according to a preferred embodiment of the present invention. As shown in fig. 1-2, a trench transistor of the present invention includes: the structure comprises a first gate electrode 3 formed in a substrate groove, a source electrode 1 and a drain electrode 4 positioned at two ends of the first gate electrode, a second gate electrode 7 positioned above the first gate electrode, a source electrode conductive lead-out 2 positioned on the surface of the source electrode, a drain electrode conductive lead-out 5 positioned on the surface of the drain electrode and the like.
Referring to fig. 3 and 4, fig. 3 is a perspective view of a trench structure, and fig. 4 is a cross-sectional view of a trench and gate electrode structure; please refer to fig. 1-2 in combination. As shown in fig. 3, the substrate 8 may be a conventional silicon substrate or other suitable substrate; on the substrate 8, a strip-shaped trench 9 is horizontally provided from the substrate surface downward, and the trench 9 may have a sidewall in a vertical or near vertical direction. As shown in fig. 4, the trench in fig. 3 is filled with a gate electrode material, such as polysilicon or metal, to form a first gate electrode 3 of polysilicon or metal.
Please continue to refer to fig. 4 in conjunction with fig. 1. In the substrate 8, a channel layer 10 is formed from the substrate surface along the side wall of the trench 9 and the bottom of the trench; the channel layer 10 surrounds the entire strip-shaped trench 9. A first gate electrode dielectric layer 6, which may be, for example, an oxide dielectric layer, a high-k dielectric layer, or other dielectric layer, is provided at the inner wall of the trench 9 between the first gate electrode 3 and the channel layer 10, i.e., along the inner wall surface of the trench 9. And a second gate electrode dielectric layer 6 'is also arranged on the surface of the substrate, and the second gate electrode dielectric layer 6' and the first gate electrode dielectric layer 6 can be intersected at the port part of the groove 9.
Referring to fig. 5, fig. 5 is a cross-sectional view of a source (drain) and its conductive lead-out structure; please refer to fig. 1-2 in combination. As shown in fig. 5, the source 1 and the drain 4 are respectively disposed in the substrate 8 at two ends of the trench 9 (i.e., two ends of the first gate electrode 3); the source electrode 1 and the drain electrode 4 are arranged around the two strip-shaped sides and the bottom of the trench 9 outside the channel layer 10, and form the annular source electrode 1 and the annular drain electrode 4.
Compared with the conventional channel layer and the source electrode and drain electrode structure, the channel layer distributed along the side wall of the groove and the bottom of the groove and the annular source electrode and drain electrode structure surrounding the groove are formed, so that the bottom space of the groove can be fully utilized, and the performance of the device is improved.
Please continue to refer to fig. 4 in conjunction with fig. 2. A second gate electrode 7 is also provided on the substrate 8; the second gate electrode 7 completely covers the underlying trench 9, and thus the width of the second gate electrode 7 is larger than the width of the trench 9. The length of the second gate electrode 7 is equal to the length of the trench 9, and extends to a part above the source 1 and the drain 4 at two ends of the trench.
The second gate electrode 7 is electrically connected by its bottom surface in contact with the top surface of the first gate electrode 3. A second gate electrode dielectric layer 6' is provided between the second gate electrode 7 and the surface of the substrate 8.
Please refer to fig. 4. The channel layer 10 extends along the surface of the substrate below the second gate electrode 7 to form a turn, so that the turn 10' is located below the second gate electrode 7. This enhances the control effect of the second gate electrode.
Please refer to fig. 1-2. And a source electrode conductive lead-out 2 is arranged on the upper surface of the source electrode 1, and a drain electrode conductive lead-out 5 is arranged on the upper surface of the drain electrode 4. The source electrode 1 and the drain electrode 4 may respectively surround one end of the trench 9. Thus, only one source and drain conductive lead- out 2, 5 need be provided on the upper surface of the source 1 and drain 4, respectively.
Or, the form shown in fig. 5 may be adopted, and a source electrode conductive lead and a drain electrode conductive lead are respectively arranged at the surface positions of the source electrode and the drain electrode on the two sides of the trench, that is, each source electrode 1 is provided with two source electrode conductive leads 2 ', 2 ", and each drain electrode 4 is provided with two drain electrode conductive leads 5', 5"; when the device is used, the two source electrode conductive leads 2 'and 2' are connected, and the two drain electrode conductive leads 5 'and 5' are connected.
Thus, a first gate electrode in the substrate, a source electrode and a drain electrode at two ends of the first gate electrode, and channel layers at two sides and the bottom of a groove between the source electrode and the drain electrode form a groove type transistor; meanwhile, another transistor is constituted by the second gate electrode on the substrate and the source, drain, and channel layers. That is, the second gate electrode and the first gate electrode form two transistors connected in parallel by sharing a source, a drain, and a channel layer in a substrate. The second gate electrode also serves as a conductive leading-out terminal of the first gate electrode; so that both transistors can be controlled simultaneously by controlling the second gate electrode.
By adopting the two parallel transistors, not only the area is fully utilized, but also the driving current can be multiplied.
A method for manufacturing the trench transistor according to the present invention will be described in detail below with reference to the following detailed description and the accompanying drawings.
The manufacturing method of the trench transistor comprises the following steps:
a substrate 8 is provided, which may be, for example, a silicon substrate or other suitable substrate. First, CMOS lithography and etching processes may be used on the substrate 8 to form a horizontal stripe-shaped trench 9 on the surface of the substrate 8, as shown in fig. 3. Wherein, the deeper the trench, the smaller the relative transistor occupation area, the higher the density of the formed devices, and the smaller the size of the final chip.
Then, an ion implantation process may be employed to form channel layers 10, 10' in the substrate 8 using the trench sidewalls and trench bottom. When the channel layer at the side wall of the groove is formed, ion implantation can be carried out on the side wall of the groove in a mode of inclining a certain angle; and ion implantation is also carried out at the position of the substrate surface corresponding to the second gate electrode, so that the channel layer extends along the substrate surface at the position below the second gate electrode to form a turning part 10'. As shown in fig. 3 and 4.
Next, gate electrode dielectric layers 6 and 6' may be formed on the inner wall surfaces of the trench and the substrate surface by a thermal oxidation or thin film deposition process. The gate electrode dielectric layer formed on the inner wall of the groove is used as a first gate electrode dielectric layer 6, and the gate electrode dielectric layer formed on the surface of the substrate is used as a second gate electrode dielectric layer 6'. Openings are formed on the second gate electrode dielectric layer 6' at appropriate positions of the source electrode 1 and the drain electrode 4, and the openings are used for manufacturing source electrode and drain electrode conduction leading-out. Then, the trench may be filled with a gate electrode material, such as polysilicon or metal, and planarized using CMOS conventional processes to form the first gate electrode 3, as shown in fig. 4.
Next, an ion implantation process may be used to form the source 1 and the drain 4 at two ends of the trench 9, so that the source 1 and the drain 4 are formed outside the channel layer 10, and the source 1 and the drain 4 surround two sides and the bottom of the trench 9, respectively, as shown in fig. 5.
The source electrode 1 and the drain electrode 4 may also extend toward the end surface of the end of the trench 9 where the source electrode and the drain electrode are located, respectively, so as to surround the end of the trench, as shown in fig. 1 and 2.
Before the source electrode and the drain electrode are implanted, an implantation barrier layer can be formed on the surface of the channel layer in advance. For example, a "sidewall" structure covering the plane of the channel layer may be formed in the source and drain implantation regions, or a mask may be set to avoid the influence on the channel when the source and drain implantation is performed.
Next, a layer of electrode material, such as polysilicon or metal, may be formed on the surface of the substrate 8, and patterned to form the second gate electrode 7 on the substrate, so that the second gate electrode 7 completely covers the trench 9 below and forms a connection with the first gate electrode 3, as shown in fig. 2 and 4. Meanwhile, by using the patterned electrode material, source and drain conductive leads 2(2 ', 2 "), 5(5 ', 5") are formed at the opening positions of the second gate electrode dielectric layer 6 ' on the upper surfaces of the source electrode 1 and the drain electrode 4, as shown in fig. 1 (fig. 5).
The above description is only for the preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all the equivalent structural changes made by using the contents of the description and the drawings of the present invention should be included in the scope of the present invention.

Claims (10)

1. A trench transistor, comprising:
the gate electrode structure comprises a strip-shaped groove horizontally formed on the surface of a substrate, wherein a gate electrode material is filled in the groove to form a first gate electrode;
a channel layer formed along the sidewall and bottom of the trench in the substrate;
a source electrode and a drain electrode in the substrate are respectively positioned on the outer sides of the channel layers at two ends of the groove and respectively surround two sides and the bottom of the strip-shaped groove;
a second gate electrode on the substrate to completely cover the trench, the second gate electrode being connected to the top surface of the first gate electrode through a bottom surface thereof;
and the second gate electrode and the first gate electrode form two parallel transistors by sharing a source electrode, a drain electrode and a channel layer which are positioned in the substrate, and the second gate electrode simultaneously also serves as a conductive leading-out terminal of the first gate electrode.
2. The trench transistor of claim 1 wherein a first gate electrode dielectric layer is disposed on the trench inner wall between the first gate electrode and the channel layer, and a second gate electrode dielectric layer is disposed between the second gate electrode and the substrate surface.
3. The trench transistor of claim 1 wherein the width of the second gate electrode is greater than the width of the trench.
4. The trench transistor of claim 1 wherein the channel layer forms a turn extending along a surface of the substrate below the second gate electrode.
5. The trench transistor of claim 1 wherein the source and drain each surround one of the ends of the trench.
6. The trench transistor of claim 1 wherein the source and drain conductive leads are provided on upper surfaces of the source and drain.
7. A method of manufacturing a trench transistor according to claim 2, comprising the steps of:
providing a substrate, and forming a strip-shaped groove in the horizontal direction on the surface of the substrate;
forming a channel layer in the substrate by using the side wall and the bottom of the groove;
forming a first gate electrode dielectric layer on the inner wall of the groove, and forming a second gate electrode dielectric layer on the surface of the substrate;
filling a gate electrode material in the groove to form a first gate electrode;
forming a source electrode and a drain electrode on the outer sides of the channel layers at two ends of the groove respectively, and enabling the source electrode and the drain electrode to surround the two strip-shaped sides and the bottom of the groove respectively;
and forming a second gate electrode on the substrate, wherein the second gate electrode completely covers the groove and is connected with the first gate electrode.
8. The method of manufacturing a trench transistor according to claim 7, further comprising: and a source electrode and a drain electrode are formed on the upper surfaces of the source electrode and the drain electrode and are led out in a conducting manner.
9. The method of claim 7 wherein the channel layer is formed by extending the channel layer along the surface of the substrate at a location below the second gate electrode to form a turn.
10. The method of claim 7, wherein the source and drain electrodes are formed so as to extend toward end faces of the trench on which the source and drain electrodes are located, respectively, to surround the end portions of the trench.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5583361A (en) * 1991-03-18 1996-12-10 Canon Kabushiki Kaisha Semiconductor device
US6127226A (en) * 1997-12-22 2000-10-03 Taiwan Semiconductor Manufacturing Company Method for forming vertical channel flash memory cell using P/N junction isolation
US6285054B1 (en) * 1998-03-30 2001-09-04 Advanced Micro Devices, Inc. Trenched gate non-volatile semiconductor device with the source/drain regions spaced from the trench by sidewall dopings
CN103681863A (en) * 2012-09-17 2014-03-26 三星电子株式会社 Semiconductor device and method of fabricating the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5583361A (en) * 1991-03-18 1996-12-10 Canon Kabushiki Kaisha Semiconductor device
US6127226A (en) * 1997-12-22 2000-10-03 Taiwan Semiconductor Manufacturing Company Method for forming vertical channel flash memory cell using P/N junction isolation
US6285054B1 (en) * 1998-03-30 2001-09-04 Advanced Micro Devices, Inc. Trenched gate non-volatile semiconductor device with the source/drain regions spaced from the trench by sidewall dopings
CN103681863A (en) * 2012-09-17 2014-03-26 三星电子株式会社 Semiconductor device and method of fabricating the same

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