CN107301952A - Grid field plate and source electrode and the Alignment Method of drain electrode in a kind of Planar power device - Google Patents
Grid field plate and source electrode and the Alignment Method of drain electrode in a kind of Planar power device Download PDFInfo
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- CN107301952A CN107301952A CN201710406570.4A CN201710406570A CN107301952A CN 107301952 A CN107301952 A CN 107301952A CN 201710406570 A CN201710406570 A CN 201710406570A CN 107301952 A CN107301952 A CN 107301952A
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- Prior art keywords
- grid
- drain
- gate
- source
- insulating barrier
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- 238000000034 method Methods 0.000 title claims abstract description 23
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 56
- 230000004888 barrier function Effects 0.000 claims abstract description 37
- 239000002184 metal Substances 0.000 claims abstract description 32
- 229910052751 metal Inorganic materials 0.000 claims abstract description 32
- 239000012212 insulator Substances 0.000 claims abstract description 18
- 238000001259 photo etching Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000011248 coating agent Substances 0.000 claims abstract description 8
- 238000000576 coating method Methods 0.000 claims abstract description 8
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 abstract description 2
- 238000005530 etching Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66515—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned selective metal deposition simultaneously on the gate and on source or drain
Abstract
The present invention relates to grid field plate in a kind of Planar power device and source electrode and the Alignment Method of drain electrode, it is included on substrate and forms insulating barrier, coating negative photoresist carries out photoetching development, forms the first grid/source/drain region；The first grid/source/drain region bottom insulation layer is etched to form gate/source/drain trenches；Coat positive photoresist and carry out photoetching development, positive photoresist filling is formed in gate trench, first grid polar region；Source/drain metal layer is formed in source/drain groove；Remove the filling of positive negative photoresist；In device upper surface formation gate insulator；Negative photoresist is coated on gate insulator and carries out photoetching development, second gate polar region is formed on negative photoresist, above gate trench；In gate trench, second gate gate metal layer is formed in polar region；Remove coating negative photoresist.The present invention eliminates the misalignment between grid and source/drain；Improve the allowance of device；Improve the yield of diameter wafers device.
Description
Technical field
The present invention relates to grid field plate in a kind of Planar power device and source electrode and the Alignment Method of drain electrode.
Background technology
In planar power switching device, grid is used for Schottky contacts or metal-insulator semiconductor (MIS) MIS is contacted, source electrode
Then be used for Ohmic contact with drain electrode, in the devices grid, source electrode and drain electrode be formed on fixed position, i.e. grid and source electrode,
Need to form alignment between drain electrode, existing method is when forming grid, source electrode and drain electrode using needs and source/drain mask version
Progress is directed at single gate mask version, however, according to the ability of phototool, this conventional method would always result in grid and
Misalignment between source/drain, or do not reach the requirement of alignment.
The content of the invention
It is an object of the invention to provide grid field plate in a kind of Planar power device and source electrode and the Alignment Method of drain electrode.
To reach above-mentioned purpose, the technical solution adopted by the present invention is：
Grid field plate and source electrode and the Alignment Method of drain electrode, including step in a kind of Planar power device：
（1）, insulating barrier is formed on substrate, coat negative photoresist on the insulating barrier, pass through grid, source electrode and drain electrode
Mask plate carries out photoetching development to the negative photoresist, formed on the negative photoresist first grid polar region, source area with
And drain region；
（2）, insulating barrier described in the first grid polar region, source area and drain region bottom is etched to be formed gate trench,
Source electrode groove and drain trenches；
（3）, device upper surface coat positive photoresist, by grid field plate mask plate to the positive photoresist carry out photoetching
Development, forms positive photoresist filling in the gate trench, first grid polar region；
（4）, in the source electrode groove, drain trenches formed source metal, drain metal layer；
（5）, removal step（1）、（3）The negative photoresist and the positive photoresist filling of middle coating；
（6）, device upper surface formation gate insulator；
（7）, on the gate insulator coat negative photoresist, the negative photoresist is entered by grid field plate mask plate
Row photoetching development, forms second gate polar region, and the second grid on the negative photoresist, above the gate trench
The width in area is more than the width of the gate trench；
（8）, in the gate trench, second gate form gate metal layer in polar region；
（9）, removal step（6）The middle coating negative photoresist.
Preferably, exist（1）In, the insulating barrier includes forming the first insulating barrier over the substrate, formed described
The second insulating barrier on first insulating barrier, negative photoresist is coated on second insulating barrier.
It is further preferred that the thickness of first insulating barrier is 0-25nm；The thickness of second insulating barrier is 25-
200nm。
It is further preferred that first insulating barrier, the second insulating barrier are oxide insulating layer or insulating nitride layer.
Preferably, exist（2）In, to insulator layer etch described in the first grid polar region, source area, drain region bottom to described
Substrate.
Preferably, exist（2）In, it is described to be etched to wet etching or dry etching.
Preferably, exist（6）In, the gate insulator is silicon nitride dielectric layer or oxide insulating layer.
Preferably, exist（6）In, the thickness of the gate insulator is 0-20nm.
Preferably, exist（7）In, the height of the second gate polar region formation gate metal layer is 50-250nm.
Preferably, exist（4）、（8）In removed by liftoff techniques, and the source metal, drain metal layer and
Gate metal layer is made annealing treatment.
Because above-mentioned technical proposal is used, the present invention has following advantages and effect compared with prior art：
1st, the misalignment between grid and source/drain is effectively eliminated；
2nd, the allowance of small geometry device is improved；
3rd, the yield of diameter wafers device is effectively improved.
Brief description of the drawings
The step of accompanying drawing 1-10 is the present embodiment is schemed.
Wherein：1st, substrate；20th, the first insulating barrier；21st, the second insulating barrier；2a, gate trench；2b, source electrode groove；2c, leakage
Pole groove；30th, negative photoresist；30a, first grid polar region；30b, source area；30c, drain region；31st, negative photoresist；31a、
Second gate polar region；4th, positive photoresist is filled；5th, metal level；5b, source metal；5c, drain metal layer；6th, gate insulator
Layer；7th, metal level；7a, gate metal layer.
Embodiment
Below in conjunction with the accompanying drawings and case study on implementation the invention will be further described：
Grid field plate and source electrode and the Alignment Method of drain electrode, specifically include following steps in a kind of Planar power device：
（1）, form insulating barrier on substrate 1, insulating barrier is specially：Form the first insulating barrier 20 on substrate 1, formed the
The second insulating barrier 21 on one insulating barrier 20, the thickness of the first insulating barrier 20 is 0-25nm, and the thickness of the second insulating barrier 21 is 25-
200nm, the first insulating barrier 20, the second insulating barrier 21 can use oxide insulating layer or insulating nitride layer, as shown in Figure 1；
（2）, on the second insulating barrier 21 coat negative photoresist 30, pass through grid, source electrode and drain electrode mask plate（Gate/
Source/Drain mask）Photoetching development is carried out to negative photoresist 30, first grid polar region is formed on negative photoresist 30
30a, source area 30b and drain region 30c, as shown in Figure 2；
（3）, first grid polar region 30a, source area 30b and drain region 30c bottom insulation layers are etched to form gate trench
2a, source electrode groove 2b and drain trenches 2c, and to oxide etch to substrate 1, wet method can be passed through using etching mode
Etching（wet etch）, dry etching（dry etch）, as shown in Figure 3；
（4）, positive photoresist is coated on device, pass through grid field plate mask plate（Gate field plate mask）Align
Property photoresist carry out photoetching development, in gate trench 2a, first grid polar region 30a formed positive photoresist filling 4, due to use
Grid field plate mask plate, positive photoresist is filled except being filled in inside and outside gate trench 2a, first grid polar region 30a, in the first grid
Also to be formed on the negative photoresist 30 of polar region 30a both sides, as shown in Figure 4；
（5）, source metal 5b, drain metal layer 5c are formed in source electrode groove 2b, drain trenches 2c, except in source electrode groove
Outside 2b, drain trenches 2c formation ohmic metal layer, also formed simultaneously in whole negative photoresist 30, positive photoresist filling 4
Metal level 5, as shown in Figure 5；
（6）, remove negative photoresist 30, the metal level 5 in positive photoresist filling 4, the mode of removal can pass through liftoff
Technique, removal step（2）、（4）Negative photoresist 30 and the positive photoresist filling 4 of middle coating, as shown in fig. 6, and to source electrode
Metal level 5b, drain metal layer 5c are made annealing treatment；
（7）, in device upper surface formation gate insulator 6, the thickness of gate insulator 6 is 0-20nm, and gate insulator 6 can be with
Using silicon nitride dielectric layer or oxide insulating layer, as shown in Figure 7；
（8）, on gate insulator 6 coat negative photoresist 31, pass through grid field plate mask plate（Gate field plate
mask）Photoetching development is carried out to negative photoresist 31,2a is square into second gate polar region on negative photoresist 31, on gate trench
31a, and second gate polar region 31a width of the width more than gate trench 2a, as shown in Figure 8；
（9）, gate metal layer 7a is formed in gate trench 2a, second gate polar region 31a, form grid on second gate polar region 31a
The height of metal level 7 is 50-250nm, as shown in Figure 9；Except forming grid gold in gate trench 2a, second gate polar region 31a
Belong to layer 7a, also form metal level 7 simultaneously on negative photoresist 31；
（10）, the metal level 7 that removes on negative photoresist 31, the mode of removal can pass through liftoff techniques, removal step
（8）Middle coating negative photoresist 31, forms product as shown in Figure 10.
The above embodiments merely illustrate the technical concept and features of the present invention, and its object is to allow person skilled in the art
Scholar can understand present disclosure and implement according to this, and it is not intended to limit the scope of the present invention.It is all according to the present invention
The equivalent change or modification that Spirit Essence is made, should all be included within the scope of the present invention.
Claims (10)
1. grid field plate and source electrode and the Alignment Method of drain electrode in a kind of Planar power device, it is characterised in that：Including step：
（1）, insulating barrier is formed on substrate, coat negative photoresist on the insulating barrier, pass through grid, source electrode and drain electrode
Mask plate carries out photoetching development to the negative photoresist, formed on the negative photoresist first grid polar region, source area with
And drain region；
（2）, insulating barrier described in the first grid polar region, source area and drain region bottom is etched to be formed gate trench,
Source electrode groove and drain trenches；
（3）, device upper surface coat positive photoresist, by grid field plate mask plate to the positive photoresist carry out photoetching
Development, forms positive photoresist filling in the gate trench, first grid polar region；
（4）, in the source electrode groove, drain trenches formed source metal, drain metal layer；
（5）, removal step（1）、（3）The negative photoresist and the positive photoresist filling of middle coating；
（6）, device upper surface formation gate insulator；
（7）, on the gate insulator coat negative photoresist, the negative photoresist is entered by grid field plate mask plate
Row photoetching development, forms second gate polar region, and the second grid on the negative photoresist, above the gate trench
The width in area is more than the width of the gate trench；
（8）, in the gate trench, second gate form gate metal layer in polar region；
（9）, removal step（6）The middle coating negative photoresist.
2. grid field plate and source electrode and the Alignment Method of drain electrode in a kind of Planar power device according to claim 1,
It is characterized in that：（1）In, the insulating barrier includes forming the first insulating barrier over the substrate, formed described first
The second insulating barrier on insulating barrier, negative photoresist is coated on second insulating barrier.
3. grid field plate and source electrode and the Alignment Method of drain electrode in a kind of Planar power device according to claim 2,
It is characterized in that：The thickness of first insulating barrier is 0-25nm；The thickness of second insulating barrier is 25-200nm.
4. grid field plate and source electrode and the Alignment Method of drain electrode in a kind of Planar power device according to claim 2,
It is characterized in that：First insulating barrier, the second insulating barrier are oxide insulating layer or insulating nitride layer.
5. grid field plate and source electrode and the Alignment Method of drain electrode in a kind of Planar power device according to claim 1,
It is characterized in that：（2）In, to insulator layer etch described in the first grid polar region, source area, drain region bottom to the lining
Bottom.
6. grid field plate and source electrode and the Alignment Method of drain electrode in a kind of Planar power device according to claim 1,
It is characterized in that：（2）In, it is described to be etched to wet etching or dry etching.
7. grid field plate and source electrode and the Alignment Method of drain electrode in a kind of Planar power device according to claim 1,
It is characterized in that：（6）In, the gate insulator is silicon nitride dielectric layer or oxide insulating layer.
8. grid field plate and source electrode and the Alignment Method of drain electrode in a kind of Planar power device according to claim 1,
It is characterized in that：（6）In, the thickness of the gate insulator is 0-20nm.
9. grid field plate and source electrode and the Alignment Method of drain electrode in a kind of Planar power device according to claim 1,
It is characterized in that：（7）In, the height of the second gate polar region formation gate metal layer is 50-250nm.
10. grid field plate and source electrode and the Alignment Method of drain electrode in a kind of Planar power device according to claim 1,
It is characterized in that：（4）、（8）In removed by liftoff techniques, and the source metal, drain metal layer and grid
Metal level is made annealing treatment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710406570.4A CN107301952B (en) | 2017-06-02 | 2017-06-02 | Self-alignment method for grid field plate, source electrode and drain electrode in planar power device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710406570.4A CN107301952B (en) | 2017-06-02 | 2017-06-02 | Self-alignment method for grid field plate, source electrode and drain electrode in planar power device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107301952A true CN107301952A (en) | 2017-10-27 |
| CN107301952B CN107301952B (en) | 2019-12-27 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710406570.4A Active CN107301952B (en) | 2017-06-02 | 2017-06-02 | Self-alignment method for grid field plate, source electrode and drain electrode in planar power device |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5356824A (en) * | 1992-02-26 | 1994-10-18 | France Telecom Establissement Autonome De Droit Public | Process for the production of a thin film transistor having a double gate and an optical mask |
| CN1189699A (en) * | 1997-01-27 | 1998-08-05 | 三菱电机株式会社 | Field-effect transistor and its mfg. method |
| TW508828B (en) * | 1999-08-24 | 2002-11-01 | Koninkl Philips Electronics Nv | Thin-film transistors and method for producing the same |
| US9337105B1 (en) * | 2014-12-03 | 2016-05-10 | Samsung Electronics Co., Ltd. | Methods for fabricating semiconductor devices with wet etching |
-
2017
- 2017-06-02 CN CN201710406570.4A patent/CN107301952B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5356824A (en) * | 1992-02-26 | 1994-10-18 | France Telecom Establissement Autonome De Droit Public | Process for the production of a thin film transistor having a double gate and an optical mask |
| CN1189699A (en) * | 1997-01-27 | 1998-08-05 | 三菱电机株式会社 | Field-effect transistor and its mfg. method |
| TW508828B (en) * | 1999-08-24 | 2002-11-01 | Koninkl Philips Electronics Nv | Thin-film transistors and method for producing the same |
| US9337105B1 (en) * | 2014-12-03 | 2016-05-10 | Samsung Electronics Co., Ltd. | Methods for fabricating semiconductor devices with wet etching |
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| Publication number | Publication date |
|---|---|
| CN107301952B (en) | 2019-12-27 |
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