CN103855034A - Method for manufacturing MOS grid device - Google Patents
Method for manufacturing MOS grid device Download PDFInfo
- Publication number
- CN103855034A CN103855034A CN201410074718.5A CN201410074718A CN103855034A CN 103855034 A CN103855034 A CN 103855034A CN 201410074718 A CN201410074718 A CN 201410074718A CN 103855034 A CN103855034 A CN 103855034A
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- Prior art keywords
- layer
- grid
- etching
- source region
- side wall
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- 238000000034 method Methods 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 230000004888 barrier function Effects 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 19
- 238000001259 photo etching Methods 0.000 claims abstract description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 16
- 239000002131 composite material Substances 0.000 claims description 9
- 239000000126 substance Substances 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000002210 silicon-based material Substances 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 abstract description 11
- 230000007547 defect Effects 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract 1
- 238000002955 isolation Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000002950 deficient Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
The invention discloses a method for manufacturing an MOS grid device. The method includes the following steps that a grid medium layer, a grid layer, a grid heightening layer and an etching retaining layer are sequentially formed on the surface of a semiconductor substrate; the photoetching technology is used for forming a grid graph structure; a body zone is formed; a source zone is formed by photoetching through the filling technology; a side wall layer is deposited; comprehensive etching is carried out on the side wall layer and a relative-width side wall is formed; the etching technology is adopted and autoregistration etching is carried out on the relative-width side wall to form a grid hole forming zone and a source zone hole forming zone; a front face metal layer is deposited; a front face electrode leading-out terminal is formed through photoetching in an etching mode. Compared with a traditional photomask registration technology, the requirement for photoetching precision is lowered. Meanwhile, the evenness and uniformity of the relative-width side wall are ensured, and therefore defects caused by the mask technology and the limitation on the current density are reduced, device density can be improved, and therefore the integration degree is improved. In addition, the additional etching barrier layer can also lower the precision requirement for the etching technology and the difficulty of the etching technology is lowered.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit method of manufacturing technology, particularly relate to a kind of manufacture method of mos gate utmost point device.
Background technology
Mos gate utmost point device is well known in the art, and these devices comprise power MOSFETS, mos gate thyristor, igbt (IGBT), gate turn-off device etc.
The manufacture method of existing mos gate utmost point devices generally comprises many plate-making mask film steps with strict mask alignment step, each strict mask alignment step has increased manufacturing time and expense, and provide may originating of device defects, and due to the restriction of masking process ability, current density can not be accomplished larger.As shown in Figure 1, be the mos gate utmost point device architecture figure that existing method forms.The manufacture method of existing mos gate utmost point device comprises the steps:
Step 1, provide semi-conductive substrate as silicon substrate 101, form successively gate dielectric layer if gate oxide 102, grid layer are as polysilicon gate 103 on described Semiconductor substrate 101 surfaces.
Step 2, adopt chemical wet etching work to form gate patterns structure, described gate dielectric layer 102, the described grid layer 103 of grid after by etching is formed by stacking.
Step 3, utilize described grid in the described Semiconductor substrate of each described grid outside, to form the tagma 104 of YouP-district composition for autoregistration mask.
Step 6, employing photoetching process form the formation region of mask pattern definition aperture area, oxide-isolation layer 106 is carried out to etching and form aperture area.
Step 7, at the positive deposit front metal layer 107 of described Semiconductor substrate, described front metal layer 107 is filled described aperture area and extends to oxide-isolation layer 106 surfaces of outside, aperture area completely.Described front metal layer 107 forms by aperture area and tagma 104 and source region 105 and contact, also by aperture area, 103 formation contact described front metal layer 107 with grid layer.
Step 9, employing chemical wet etching technique are carried out etching to described front metal layer 107 and are formed front electrode leading-out terminal.
As from the foregoing, in existing method, the photoetching process of aperture area is higher to alignment request, the photoetching process in source region also higher to alignment request, can make so the high number of steps of lithography alignment requirement more, manufacture difficulty and expense are increased, and may originating of device defects be provided, and due to the restriction of masking process ability, current density can not be accomplished larger.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of manufacture method of mos gate utmost point device, thereby can reduce alignment procedures number and reduce manufacture difficulty and cost, can reduce the defect brought due to mask alignment technique and the restriction to current density, improve integrated level thereby can improve device density.
For solving the problems of the technologies described above, the manufacture method of mos gate utmost point device provided by the invention comprises step:
Step 1, provide semi-conductive substrate, form successively gate dielectric layer, grid layer, grid at described semiconductor substrate surface and increase layer and etching barrier layer.
Step 2, employing chemical wet etching technique form gate patterns structure, described gate dielectric layer, described grid layer, the described grid of grid after by etching increases layer and described etching barrier layer is formed by stacking, and the described etching barrier layer between each described grid, described grid increase layer, described grid layer and described gate dielectric layer and be removed and expose described semiconductor substrate surface.
Step 3, the tagma that utilizes described grid to form for forming YouP-district in the described Semiconductor substrate of autoregistration mask between each described grid.
Step 6, adopt comprehensive etching technics described side wall layer is carried out to etching and form wide side wall in the side of each described grid, between adjacent described gate side two are described to exposing and by two between the adjacent described gate side described aperture area that wide side wall autoregistration defined to described source region and described tagma, expose on the described etching barrier layer surface of described grid on the surface, described tagma between described source region and described source region between wide side wall.
Step 7, at the positive deposit front metal layer of described Semiconductor substrate, described front metal layer is filled the aperture area in described source region and described tagma extend to the described etching barrier layer surface of described grid.
Step 8, employing chemical wet etching technique are carried out etching to described front metal layer and are formed front electrode leading-out terminal.
Further improvement is, the described gate dielectric layer in step 1 is oxide layer, and described grid layer is polysilicon layer, and described grid increases layer for oxide layer.
Further improving is that the composition material of described side wall layer is silica or silicon nitride; The composition material of described etching barrier layer is different with the composition material of described side wall layer and all different dielectric layers of silicon materials.
Further improve and be, the comprehensive etching technics in step 6 is etching technics in the same way comprehensively.
Further improve and be, after having formed the aperture area in described source region and described tagma in step 6, also be included in the step that P+ injection is carried out in the bottom of this aperture area, this P+ injection region and the described front metal layer being filled in the aperture area in described source region and described tagma form ohmic contact.
Further improving is that described mos gate utmost point device comprises power MOSFET, mos gate thyristor, igbt, gate turn-off device.
The present invention is by forming wide side wall in the side of grid, and by two between the adjacent gate side aperture area that autoregistration between wide side wall defined to source region and tagma, in corresponding prior art, need to adopt photo etched mask technique to form the method for aperture area, source region, the present invention can reduce the requirement of lithography alignment precision, reduces due to the restriction of mask size to current density; Increase etching barrier layer simultaneously and can ensure uniformity and the consistency to wide side wall, thereby reduce etching technics difficulty, reduce defective workmanship etc., in addition, the present invention defines aperture area by self-registered technology, can reduce the area of device, thereby thereby can improve device density and improve integrated level;
Brief description of the drawings
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the mos gate utmost point device architecture figure that existing method forms;
Fig. 2 is the mos gate utmost point device architecture figure that embodiment of the present invention method forms.
Embodiment
As shown in Figure 2, be the mos gate utmost point device architecture figure that embodiment of the present invention method forms.Embodiment of the present invention mos gate utmost point device comprises power MOSFET, mos gate thyristor, and igbt, gate turn-off device, the manufacture method of embodiment of the present invention mos gate utmost point device comprises step:
Step 1, provide semi-conductive substrate 1, form successively gate dielectric layer 2, grid layer 3, grid on described Semiconductor substrate 1 surface and increase layer 4 and etching barrier layer 5.Be preferably, described Semiconductor substrate 1 is silicon substrate, and described gate dielectric layer 2 is oxide layer, and described grid layer 3 is polysilicon layer, and described grid increases layer 4 for oxide layer.
Step 2, employing chemical wet etching technique form gate patterns structure, described gate dielectric layer 2, described grid layer 3, the described grid of grid after by etching increases layer 4 and described etching barrier layer 5 is formed by stacking, and the described etching barrier layer 5 between each described grid, described grid increase layer 4, described grid layer 3 and described gate dielectric layer 2 and be removed and expose described Semiconductor substrate 1 surface.
Step 3, the tagma 6 that utilizes described grid to form for forming YouP-district in the described Semiconductor substrate 1 of autoregistration mask between each described grid.
Step 6, adopt comprehensive etching technics described side wall layer is carried out to etching and form in the side of each described grid wide side wall 8, between adjacent described gate side two are described to exposing and by two between the adjacent described gate side described aperture area 9 that wide side wall 8 autoregistrations defined to described source region 7 and described tagma 6, expose on described etching barrier layer 5 surfaces of described grid on 6 surfaces, described tagma between described source region 7 and described source region 7 between wide side wall 8.Be preferably, comprehensively etching technics is etching technics in the same way comprehensively.
Be preferably, also comprise that adopting photoetching process to form mask pattern defines the formation region of grid aperture area, etch away the described etching barrier layer 5 in formation region of described grid aperture area and grid and increase layer 4 and expose grid layer 3 and form described grid aperture area.
Be preferably, after the aperture area 9 that forms described source region 7 and described tagma 6, be also included in the step of carrying out P+ injection of 9 bottoms, aperture area in described source region 7 and described tagma 6, this P+ injection region forms ohmic contact with the described front metal layer 10 being filled in the aperture area 9 in described source region 7 and described tagma 6.
Step 7, at the positive deposit front metal layer 10 of described Semiconductor substrate, described front metal layer 10 is filled the aperture area 9 in described source region 7 and described tagma 6 extend to described etching barrier layer 5 surfaces of described grid; Described front metal layer 10 is also filled described grid aperture area and is formed and contact with described grid.
Step 8, employing chemical wet etching technique are carried out etching to described front metal layer 10 and are formed front electrode leading-out terminal.
By specific embodiment, the present invention is had been described in detail above, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (6)
1. a manufacture method for mos gate utmost point device, is characterized in that, comprises step:
Step 1, provide semi-conductive substrate, form successively gate dielectric layer, grid layer, grid at described semiconductor substrate surface and increase layer and etching barrier layer;
Step 2, employing chemical wet etching technique form gate patterns structure, described gate dielectric layer, described grid layer, the described grid of grid after by etching increases layer and described etching barrier layer is formed by stacking, and the described etching barrier layer between each described grid, described grid increase layer, described grid layer and described gate dielectric layer and be removed and expose described semiconductor substrate surface;
Step 3, the tagma that utilizes described grid to form for forming YouP-district in the described Semiconductor substrate of autoregistration mask between each described grid;
Step 4, employing photoetching process formation mask pattern define the formation region in source region, in the formation region in described source region, carry out N+ and inject the described source region that forms YouN+ district composition, described source region is arranged in the subregion in described tagma, one side in described source region and described grid autoregistration, the opposite side in described source region is defined by mask pattern, and the region between two adjacent described source regions keeps the doping condition in described tagma;
Step 5, at the positive deposit side wall layer of the described Semiconductor substrate that is being formed with described source region;
Step 6, adopt comprehensive etching technics described side wall layer is carried out to etching and form wide side wall in the side of each described grid, between adjacent described gate side two are described to exposing and by two between the adjacent described gate side described aperture area that wide side wall autoregistration defined to described source region and described tagma, expose on the described etching barrier layer surface of described grid on the surface, described tagma between described source region and described source region between wide side wall;
Step 7, at the positive deposit front metal layer of described Semiconductor substrate, described front metal layer is filled the aperture area in described source region and described tagma extend to the described etching barrier layer surface of described grid;
Step 8, employing chemical wet etching technique are carried out etching to described front metal layer and are formed front electrode leading-out terminal.
2. the method for claim 1, is characterized in that: the described gate dielectric layer in step 1 is oxide layer, and described grid layer is polysilicon layer, and described grid increases layer for oxide layer.
3. the method for claim 1, is characterized in that: the composition material of described side wall layer is silica or silicon nitride; The composition material of described etching barrier layer is different with the composition material of described side wall layer and all different dielectric layers of silicon materials.
4. the method for claim 1, is characterized in that: the comprehensive etching technics in step 6 is etching technics in the same way comprehensively.
5. the method for claim 1, it is characterized in that: after having formed the aperture area in described source region and described tagma in step 6, also be included in the step that P+ injection is carried out in the bottom of this aperture area, this P+ injection region and the described front metal layer being filled in the aperture area in described source region and described tagma form ohmic contact.
6. the method for claim 1, is characterized in that: described mos gate utmost point device comprises power MOSFET, mos gate thyristor, igbt, gate turn-off device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410074718.5A CN103855034A (en) | 2014-03-03 | 2014-03-03 | Method for manufacturing MOS grid device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410074718.5A CN103855034A (en) | 2014-03-03 | 2014-03-03 | Method for manufacturing MOS grid device |
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| CN103855034A true CN103855034A (en) | 2014-06-11 |
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| CN201410074718.5A Pending CN103855034A (en) | 2014-03-03 | 2014-03-03 | Method for manufacturing MOS grid device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109309121A (en) * | 2017-07-26 | 2019-02-05 | 比亚迪股份有限公司 | Semiconductor power device and preparation method thereof |
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| US20120139034A1 (en) * | 2005-04-27 | 2012-06-07 | Stmicroelectronics S.R.L. | Process For Manufacturing A MOS Device With Intercell Ion Implant |
| CN102544100A (en) * | 2010-12-14 | 2012-07-04 | 万国半导体股份有限公司 | Self aligned trench MOSFET with integrated diode |
| CN102738215A (en) * | 2011-08-18 | 2012-10-17 | 成都芯源系统有限公司 | Lateral double-diffused metal oxide semiconductor field effect transistor and manufacturing method thereof |
| US20130082335A1 (en) * | 2011-09-30 | 2013-04-04 | Micrel, Inc. | Extended Drain Lateral DMOS Transistor with Reduced Gate Charge and Self-Aligned Extended Drain |
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2014
- 2014-03-03 CN CN201410074718.5A patent/CN103855034A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US6992353B1 (en) * | 2004-11-01 | 2006-01-31 | Silicon-Based Technology Corp. | Self-aligned source structure of planar DMOS power transistor and its manufacturing methods |
| US6965146B1 (en) * | 2004-11-29 | 2005-11-15 | Silicon-Based Technology Corp. | Self-aligned planar DMOS transistor structure and its manufacturing methods |
| US20120139034A1 (en) * | 2005-04-27 | 2012-06-07 | Stmicroelectronics S.R.L. | Process For Manufacturing A MOS Device With Intercell Ion Implant |
| CN101459132A (en) * | 2007-12-10 | 2009-06-17 | 上海华虹Nec电子有限公司 | Manufacturing process for high voltage planar power MOS device |
| CN101964355A (en) * | 2009-09-11 | 2011-02-02 | 成都芯源系统有限公司 | Power device with self-aligned silicide contacts and method of making the same |
| CN102544100A (en) * | 2010-12-14 | 2012-07-04 | 万国半导体股份有限公司 | Self aligned trench MOSFET with integrated diode |
| CN102738215A (en) * | 2011-08-18 | 2012-10-17 | 成都芯源系统有限公司 | Lateral double-diffused metal oxide semiconductor field effect transistor and manufacturing method thereof |
| US20130082335A1 (en) * | 2011-09-30 | 2013-04-04 | Micrel, Inc. | Extended Drain Lateral DMOS Transistor with Reduced Gate Charge and Self-Aligned Extended Drain |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109309121A (en) * | 2017-07-26 | 2019-02-05 | 比亚迪股份有限公司 | Semiconductor power device and preparation method thereof |
| CN109309121B (en) * | 2017-07-26 | 2022-09-16 | 比亚迪半导体股份有限公司 | Semiconductor power device and preparation method thereof |
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Application publication date: 20140611 |