CN107301941B - Apparatus for processing plasma and its operating method - Google Patents
Apparatus for processing plasma and its operating method Download PDFInfo
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- CN107301941B CN107301941B CN201610232603.3A CN201610232603A CN107301941B CN 107301941 B CN107301941 B CN 107301941B CN 201610232603 A CN201610232603 A CN 201610232603A CN 107301941 B CN107301941 B CN 107301941B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32458—Vessel
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32715—Workpiece holder
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/321—Radio frequency generated discharge the radio frequency energy being inductively coupled to the plasma
- H01J37/3211—Antennas, e.g. particular shapes of coils
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/32174—Circuits specially adapted for controlling the RF discharge
- H01J37/32183—Matching circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32458—Vessel
- H01J37/32477—Vessel characterised by the means for protecting vessels or internal parts, e.g. coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32798—Further details of plasma apparatus not provided for in groups H01J37/3244 - H01J37/32788; special provisions for cleaning or maintenance of the apparatus
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32798—Further details of plasma apparatus not provided for in groups H01J37/3244 - H01J37/32788; special provisions for cleaning or maintenance of the apparatus
- H01J37/32816—Pressure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32798—Further details of plasma apparatus not provided for in groups H01J37/3244 - H01J37/32788; special provisions for cleaning or maintenance of the apparatus
- H01J37/32816—Pressure
- H01J37/32834—Exhausting
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66818—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the channel being thinned after patterning, e.g. sacrificial oxidation on fin
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The present invention provides a kind of semiconductor manufacturing facility and its operating methods.The semiconductor manufacturing facility includes reaction chamber, supporting element and lining.Reaction chamber is used for plasma process, and has locular wall.The fixed wafer of supporting element is in reaction chamber.Lining surrounds supporting element, and has top side and bottom side, and top side is removably hung on the locular wall, and bottom side then has multiple gas passages to allow plasma particle to pass through lining.
Description
Technical field
The related apparatus for processing plasma of the present invention and its operating method.
Background technique
Plasma is generally used in manufacturing process being also used for losing with deposition materials layer when semiconductor integrated circuit manufactures
Carve the material on wafer.
In deposition or etching operation, plasma is formed in the chamber of equipment.Different condition in chamber will affect
The quality of semiconductor devices in manufacture.
Summary of the invention
The object of the present invention is to provide the semiconductors that a kind of semiconductor manufacturing facility and a kind of operation have matching network
The method of manufacturing equipment.
One embodiment of the invention discloses a kind of semiconductor manufacturing facility comprising reaction chamber, supporting element and lining.Reaction
Room is configured for plasma process, and has locular wall.Supporting element is configured to fixed wafer in reaction chamber.Lining quilt
It is configured to around the supporting element, and there is top side and bottom side.Top side is removably hung on locular wall, and bottom side then have it is multiple
Gas passage is to allow plasma particle to pass through lining.
Above-mentioned semiconductor manufacturing facility further comprise positioned at reaction chamber bottom pump and be coupled to the exhaust pipe of pump,
And exhaust pipe is straight tube.
In above-mentioned semiconductor manufacturing facility, multiple gas passages include the bottom opening of the bottom surface positioned at the bottom side.
In above-mentioned semiconductor manufacturing facility, bottom opening is cylindrical or taper.
In above-mentioned semiconductor manufacturing facility, lining further comprises the side extended between top side and bottom side, and
Positioned at the turning of side and bottom side junction.
In above-mentioned semiconductor manufacturing facility, multiple gas passages include the corner openings positioned at turning.
In above-mentioned semiconductor manufacturing facility, it is inclined channel that corner openings, which have the bottom surface relative to bottom side,.
Another embodiment of the present invention discloses a kind of semiconductor manufacturing facility, has for making plasma under nominal pressure
The reaction chamber of build-up of luminance, semiconductor manufacturing facility include RF power supply and matching network.RF power supply is configured to generate radiofrequency signal, and
It powers in the first output end and second output terminal.The power that matching network is configured to be exported RF power supply is coupled to reaction chamber,
And make reaction chamber build-up of luminance plasma under the pressure lower than the nominal pressure.Matching network includes the first circuit and the second electricity
Road.First circuit because should be in radiofrequency signal to adjust voltage class, and has the first inductance device to export the electricity adjusted
Grade is pressed, and the first inductance device and a condenser network are series between first output end and reference voltage grade.Second electricity
There is the second inductance device to light plasma to provide scheduled voltage class on road, and the second inductance device is coupled directly to
Between the second output terminal and the reference voltage grade.
In above-mentioned semiconductor manufacturing facility, the voltage of the electric current maximum point of the first inductance device and the second inductance device is most
It is symmetrical with the center line for generating the reaction chamber of plasma a little louder.
In above-mentioned semiconductor manufacturing facility, the scheduled voltage class of second circuit is higher than what first circuit was adjusted
Voltage class.
In above-mentioned semiconductor manufacturing facility, the first inductance device or the second inductance device have planar coil or helix
The antenna of loop-shaped.
In above-mentioned semiconductor manufacturing facility, the second inductance device is compared with the first inductance device close to the anti-of generation plasma
Answer the center line of room.
In above-mentioned semiconductor manufacturing facility, the first inductance device and second inductance device 255 are concentrically surrounding in this
Heart line.
Above-mentioned semiconductor manufacturing facility further comprises shielding part, surrounds semiconductor manufacturing facility and matching network.
A kind of method that another embodiment of the present invention discloses semiconductor manufacturing facility of the operation with matching network, the party
Method includes: to apply radiofrequency signal to matching network；In response in the RF signal, established by matching network for generating plasma
RF energy, the matching network have first node and inductance device, and inductance device have be coupled to the first of first node
Terminal and the second terminal for being directly coupled to reference voltage grade, and there is the second section between first terminal and second terminal
Point；Predetermined voltage class is provided in second node；Plasma is lighted under the predetermined voltage class；And adjust pair net
Network, to realize the impedance matching between RF signal and inductance device.
Aforesaid operations have in the method for the semiconductor manufacturing facility of matching network, provide predetermined voltage in second node
Operation includes increasing the reactance of matching network.
Aforesaid operations have in the method for the semiconductor manufacturing facility of matching network, and predetermined voltage is approximately higher than 1000 volts.
Aforesaid operations have in the method for the semiconductor manufacturing facility of matching network, provide predetermined voltage in second node
Operation includes most of RF signal of the reflection from inductance device.
Aforesaid operations have in the method for the semiconductor manufacturing facility of matching network, and matching network includes another inductance dress
It sets, there is the terminal for being couple to the reference voltage grade by capacitive means.
It further comprises utilizing shielding part closing half that aforesaid operations, which have the method for the semiconductor manufacturing facility of matching network,
Conductor manufacturing equipment.
The embodiment of the present invention discloses a kind of semiconductor devices comprising the firstth area and the secondth area.Firstth area has multiple
Device is arranged with the first device density.Secondth area is spaced with the firstth area, and there are multiple devices to be arranged with the second device density,
And the second device density is less than the first device density, and in the secondth area the predetermined depth of multiple device with it is multiple in the firstth area
The predetermined depth of device is identical.Wherein, the depth of multiple device and the depth of multiple device in the secondth area in the firstth area
Difference is 6%~8% relative to the predetermined depth.
In above-mentioned semiconductor devices, the depth of the depth of multiple device and multiple device in the secondth area in the firstth area
Mean difference relative to the predetermined depth be 7%.
In above-mentioned semiconductor devices, multiple device in the predetermined side inclination angle Yu the secondth area of multiple device in the firstth area
The predetermined side inclination angle of part is identical, and in the firstth area in the side inclination angle Yu the secondth area of multiple device multiple device side
The difference at inclination angle is 4%~7% relative to predetermined side inclination angle.
In above-mentioned semiconductor devices, multiple device in the side inclination angle Yu the secondth area of multiple device in the firstth area
The mean difference at side inclination angle is 6% relative to predetermined side inclination angle.
In above-mentioned semiconductor devices, the difference phase at the upper side inclination angle with downside inclination angle of multiple device in the firstth area
It is 4%~7% for predetermined side inclination angle.
In above-mentioned semiconductor devices, the mean difference at the upper side inclination angle Yu downside inclination angle of multiple device in the firstth area
Out-phase is 5.5% for predetermined side inclination angle.
There is the method for the semiconductor manufacturing facility of matching network using semiconductor manufacturing facility of the invention and operation,
Higher accuracy and repeatability can be provided in wafer-process, moreover it is possible to reduce in the high density integrated circuit on wafer
The various effects of wafer quality may be changed.For example, reduce that high density may cause such as current leakage, non-uniform etch, figure
The quality problems of case load effect or micro loading effect.
Those skilled in the art should be appreciated that using relatively slight based on the concept and specific embodiment being disclosed below
It changes places and is modified or designed other structures or technique, to realize purpose same as the present invention.Those skilled in the art are also
It should be appreciated that this kind of equivalent construction and the spirit and scope of the present invention that claims are proposed can not be detached from.
Detailed description of the invention
Attached drawing refering to accompanying and the feature it is clearly understood that of the invention is detailed description below.It is hereby stated that each
A feature does not press the standard convention scale of industry.In fact, the size of each feature may in order to clearly discuss
Arbitrarily increase or reduce.
Figure 1A is the plan view of semiconductor devices according to some embodiments of the invention；
Figure 1B is the section of the semiconductor devices of AA' line interception according to some embodiments of the invention shown in Figure 1A
Figure；
Fig. 2A is the plan view of semiconductor devices according to some embodiments of the invention；
Fig. 2 B is the section of the semiconductor devices of the interception of the BB' line shown in Fig. 2A according to some embodiments of the invention
Figure；
Fig. 3 to 5 is the sectional view of semiconductor devices according to some embodiments of the invention；
Fig. 6 is the sectional view of equipment according to some embodiments of the invention；
Fig. 7 is the sectional view of lining according to some embodiments of the invention；
Fig. 8 is the sectional view of lining according to some embodiments of the invention；
Fig. 9 is the block diagram of matching network according to some embodiments of the invention；
Figure 10 is the flow chart of operation device, method according to some embodiments of the invention；
Figure 11 is the schematic diagram of matching impedance according to some embodiments of the invention.
Specific embodiment
Following disclosure provides many different embodiment or examples, different characteristic for carrying out the present invention.It retouches as follows
The specific example of component and configuration is stated, to simplify this exposure.Certainly, they are only example, are not intended to and limit this hair
It is bright.For example, forming fisrt feature in being described below on second feature or in second feature may include being formed directly to connect
The fisrt feature of touching and the embodiment of second feature, can also be included between fisrt feature and second feature can be formed it is additional
Feature is so that the embodiment that fisrt feature and second feature can be not directly contacted with.In addition, this is disclosed in each example
Appended drawing reference and/or letter are reused in the hope of simple and clear, itself do not indicate described in each embodiment and/or match
Relationship between setting.
In addition, spatial relation term, such as " under ", " lower section ", " following ", " on ", " top " etc., be used herein to letter
Change and describes a unit shown in the drawings and feature to the relationship of another unit or feature.In addition to the direction described in attached drawing,
Spatial relation term is intended to the different directions of the device comprising using or operating.Equipment can orient (rotation 90 in other ways
Spend or in other directions), and spatial relationship description used herein can be similarly explained accordingly.
With semiconductor technology generation upon generation of, transistor size reduces and the density of the semiconductor devices on wafer increases, and leads
Cause needs higher accuracy and repeatability in wafer-process.In high density integrated circuit on wafer, various effects
The quality of wafer may be changed.For example, high density may cause such as current leakage, non-uniform etch, pattern load effect or micro-
The quality problems of load effect.
Etching process is the usual procedure in modern integrated circuits (IC) production.There are different etching technique and method can be with
It uses, including plasma etching.During etching process, keep uniformity especially important.Required for uniformity refers to for example
The uniformity of the etching of the critical dimension of depth, and the uniformity across wafer with the etching of wafer to wafer.In microcosmic point,
Etch-rate and profile depend on characteristic size and character separation.The problem of microscopic uniformity, can be divided into several classes, including pattern
Rely on etching effect, commonly referred to as pattern load effect.Pattern load effect includes macro load effect or micro loading effect.More
Specifically, micro-loading refers to the dependence of the etch-rate on the character separation for identical size characteristic, and have in wafer
When having local, high-density region, caused by reactant depletion.
From the perspective of term, critical dimension only refers to the size (such as width) of the feature in related direction.For example,
In the plan view 100 of semiconductor devices shown in figure 1A, the feature corresponding to transistor 141 includes grid structure 14, drain region 15
With source region 17.In some embodiments, transistor 141 is p-type metal oxide semiconductor (p-type metal-oxide-
Semiconductor, PMOS) field effect transistor, n-type metal oxide semiconductor (n-type metal-oxide-
Semiconductor, NMOS) field effect transistor or complementary metal oxide semiconductor (complementary metal-
oxide-semiconductor,CMOS).There is different length or width there may be multiple, to be short, some are long for some
Transistor 141.
Referring to Figure 1A, circuit includes transistor 141, conductive material 10 and semiconductor substrate 1.Transistor 141 has length
L and width W, including two grid structures 14, centre have source region 17, and drain region 15,151 is in 17 two sides of source region.Length L is
From 15 side of drain region to the length of 151 side of drain region.Width W is from a surface of drain region 15 to same drain region 15
The width on another surface.In some embodiments, the drain region 15 is separated with length L142 and the conductive material 10.
Drain region 15 can also be separated with length L141 and other conductive materials 10.
Source region 17 is separated with length L17 and conductive material 10.One conductive material 10 is between another conductive material 10
Distance is L10.According to the design of circuit, length L141, L142, L10 and L17 can not be identical.
Referring to Figure 1B, the sectional view 110 of the circuit is along the hatching AA' interception for passing through source region 17 and conductive material 10.
Sectional view 110 is aligned with conductive material 10.Sectional view 110 includes semiconductor substrate 1, conductive material 10 and middle layer 11.In
Interbed 11 is between semiconductor substrate 1 and conductive material 10.Conductive material 10 is on semiconductor substrate 1.Semiconductor substrate packet
Include groove 20.Groove 20 can be between source region 17 and conductive material 10.Groove 20 has from 17 top of source region to conductive material
The length L17 at 10 tops.The bottom of groove 20 has length L20.In some embodiments, length L20 is smaller than length L17.
Groove 21 is between conductive material.The distance between 10 top of 10 top of conductive material and another conductive material is long
Spend L10.Groove 21 includes the side S in conjunction with a bottom surface B with groove 21.Bottom surface B has length L21.One
In a little embodiments, side S is taper, so that length L21 ratio L10 length is small.In some embodiments, conductive material 10 has height
Spend H3.Middle layer 11 has height H2.It in some embodiments, is substantially the same for each conductive material height H3.
There is part 105 on the part 107 of semiconductor substrate 1.Part 105 has side.The side has from semiconductor substrate 1
Height H1 of the bottom surface B to top surface T cross measure.In some embodiments, different grooves has different or similar
Size.For example, length L20 can be greater than, it is equal to or less than length L21.
In fig. 2, the plan view 200 of circuit is similar to shown in Figure 1A.In fig. 2b, 210 edge of sectional view of the circuit
It is intercepted across the hatching BB' of drain region 15 and another drain region 15.Sectional view 210 is aligned with conductive material 10.In some realities
Apply in example, due to micro loading effect, different grooves have different depth so that the bottom surface of different groove than higher each other or
It is lower.
For example, length L22 is the length from a drain region 15 to another adjacent drain area 15.Conductive material 10 is draining
On the top in area 15.Conductive material 10 and middle layer 11 are substantially vertical, so that length L22 is from the top of conductive material 10
It is substantially constant to the bottom of middle layer 11.Groove 23 is between drain region 15.Groove 23 has bottom surface B23.Bottom surface table
Face B23 has length L23.Groove 23 is taper, so that length L23 ratio L22 length is small.Bottom surface B23 with height H4 with
The top surface T of semiconductor substrate 1 is separated.Bottom surface B23 than groove 21 bottom surface B rise from D5.Height H4 compares portion
105 height H1 is divided to differ distance D5.
The process gas pressure of chamber interior during one factor of micro loading effect is corona treatment.In Fig. 3,
Groove 25 is compared with groove 27, due to micro loading effect.Groove 25 is more shallow than groove 27.Groove 25 has smaller open on top of this
Mouth P25.Groove 27 has larger open P27 at the top of it.
Groove 25 has length L251 at the top of smaller opening P25, has length L25 in the top surface of groove 25.It is recessed
Slot 25 is taper, so that length L251 is greater than length L25.Groove 25 has at the top of smaller opening P25 to 25 bottom table of groove
The height H25 in face.
Groove 27 has length L271 at the top of larger open P27, has length L27 in the bottom surface of groove 27.It is recessed
Slot 27 is taper, so that length L271 is greater than length L27.Groove 27 has at the top of larger open P27 to 27 bottom table of groove
The height H27 in face.
Length L251 is smaller than length L271.A height H25 length L57 smaller than height H27.In some embodiments, recessed
Slot 25 is bigger than the taper of groove 27, so that the ratio between length L251 and L25 is greater than between length L271 and length 27
Ratio.It is small that smaller opening P25 compares big opening P27.
Plasma particle 30 removes the part of semiconductor substrate 1 under smaller opening P25 or larger open P27, with
It is respectively formed groove 25 or 27.Some plasma particles 30 are impinging one another before reaching opening.Collision occur it is described compared with
On small opening P25 or larger open P27.Plasma particle 30 converges to incident path 33 before collision.After collision, etc.
Gas ions particle 30 scatters along deflection path 34.For the incident path 33 with horizontal component, corresponding deflection path 34 can also
To have horizontal component in the opposite direction.For the collision on smaller opening P25, plasma particle 30 is more likely to meeting
Smaller opening P25 is missed, and is more likely to fall in other regions outside smaller opening.For touching on larger open P27
It hits, plasma particle 30 is less likely that larger open P27 can be missed, thus may not too much fall in outside larger open P27
Other regions.For the collision on larger open P27, plasma particle 30 is still possibly into larger open P27 and more
It is easy to enter groove 27 by larger open P27 and be etched.
For using plasma particle 30 with etched recesses 25 or groove 27, undergo the plasma particle 30 of collision into
Enter larger open P27 ratio and enter smaller opening P25 to be easier.For smaller opening P25, larger open P27 allows more
30 etched recesses 27 of plasma particle collided.Due to capableing of the plasma particle 30 of etched recesses 27 collided
Than the plasma particle more than 30 of etched recesses 25 collided, therefore groove 27 is deeper than groove 25.It is this to different openings
One of the reason of non-uniform etch of size is micro loading effect.
For the corona treatment with higher collision rate, the micro loading effect is become readily apparent from, so that groove
More uneven and depth of groove variation increases.The collision rate of plasma particle 30 is averaged with plasma particle 30
Free path is related.Longer average path is related to less collision.In corona treatment, most of plasma grains
The low collision rate of son 30 means that most of plasma particles 30 move to wafer straight down.Make include horizontal component side
It is reduced to collision, to allow more plasma particles 30 to be etched into smaller opening P25.Increase plasma particle
30 mean free path is to reduce micro loading effect.It is that increase plasma particle 30 is flat by reducing process gas pressure
A kind of method of equal free path.
In Fig. 4, different corona treatments 331 and 332 etches semiconductor substrate 1, has different results.For
Micro loading effect, it is more more obvious than corona treatment 332 by corona treatment 331.For being imitated with more micro-loading
The corona treatment 331 answered, the lesser depth of groove of slot opening reduce.For the plasma with more micro loading effect
Body processing 332, the lesser depth of groove of slot opening is held substantially constant.Slot opening can be the critical dimension of groove.
Critical dimension can be width W25, W27 or W28, and width W28 is greater than width W27, and width W27 is greater than width W25.
Groove 117 under corona treatment 331 has width W28, W27 and W25.Groove 117 is respectively provided with depth
D4, D7 and D8, depth D4 are greater than in depth D7, and depth D7 is greater than depth D8.
Groove 115 under corona treatment 332 has width W28, W27 and W25.Groove 115 has substantially permanent
Fixed depth D4.The size no matter being open, groove 115 equably have depth D4.
In Fig. 5, groove 117 includes similar to the micro loading effect in Fig. 4.Groove 117 is filled with insulating materials, such as
It will be for the dielectric material of isolation structure 18.Groove 117 has the bending part 181 of transversely side S117.Dislocation 19 is from bending part
181 extend to semiconductor substrate 1.Dislocation 19 transversely side S117 close to bending part 181.Interface 111 is placed on semiconductor-based
Between plate 1 and middle layer 11.
In Fig. 5, micro loading effect causes leakage current to some extent.
In some embodiments, for the isolation structure 18 with shorter depth D8, electric charge carrier 40 is easier from one
A part 105 moves to another part 105.For example, in some embodiments, part 105 is drain region adjacent in Fig. 2
15.Electric charge carrier 40 passes through 18 lower section of isolation structure, and leaks into another drain region from a drain region.
In some embodiments, electric charge carrier 40 is leaked by interface 111.Charge carriers in yet other embodiments,
Son 40 passes through 19 leakage of dislocation.
Reducing process gas pressure will increase mean free path, increases the mean free path and reduces plasma grain
The collision rate of son 30, micro loading effect can be reduced by reducing collision rate, and reducing micro loading effect can be reduced in semiconductor devices
Leakage current problem.
Fig. 6 shows semiconductor manufacturing facility 500.Semiconductor manufacturing facility 500 includes plasma-reaction-chamber 59, plasma
Precursor reactant room 59 includes lining 57, and lining 57 is for constraining plasma.The presence of lining 57 can change the distribution of electric field, will
The plasma substantially on constrain in the region R inside the lining 57 and increase plasma density.Lining 57 can be with
For preventing the other parts of plasma etching plasma-reaction-chamber 59, such as locular wall 55, to protect the plasma
Reaction chamber 59, to keep plasma-reaction-chamber 59 against damages.Lining 57 can be cleaned and/or be replaced.Lining 57 can be reinforced
The uniformity of process gas pressure.The uniformity of the process gas pressure corresponds to the mean free path of gas particle 321
Uniformity.
Region R is on the wafer 70 in plasma-reaction-chamber 59.Wafer 70 includes semiconductor substrate 1.Be subjected to etc. from
Uniform process gas pressure is kept on the semiconductor substrate 1 of daughter processing, may consequently contribute on semiconductor substrate 1 make each device
Part crystal grain generates uniform critical dimension.Pressure in classicalpiston reaction chamber 59 passes through while introducing process gas and pumping
Empty plasma-reaction-chamber 59 is controlled.There is no any restrictions to the flow of process gases in plasma-reaction-chamber 59,
Then process gas pressure can be from close to the relatively high pressure that air supply opening 38 exports to the pressure relatively low close to exhaust outlet 71
Form a gradient.57 part of lining limitation flow of process gases reduces the barometric gradient inside the lining 57.Reduce institute
The uniformity of the gas pressure can be promoted by stating barometric gradient.
Lining 57, which can constrain process gas, makes its small volume, to reduce the gas supply flow and process gas from air supply opening 38
The consumed flow of body.
Lining 57 has various features.Lining 57 has the side 83 extended on wafer 70.In order to realize process gas
The high homogeneity of pressure and plasma density, lining 57 are preferably symmetrical.Process gas pressure and plasma density
Uniformity reduce the micro loading effect across chip 70.In some embodiments, lining 57 is symmetrical for wafer 70,
And avoid the opening in side 83.
Fig. 6 is the diagrammatic cross-section of semiconductor manufacturing facility 500, and the semiconductor manufacturing facility 500 includes plasma
Reaction chamber 59, lining 57, locular wall 55 and dielectric window 39 (such as planar dielectric window with uniform thickness).Electricity
Induction device 35 is placed on dielectric window 39.The inductance device 35 can be the spiral winding of plane multi-turn, non-planar
Multi-turn coil, or there is other shapes of antenna, pass through suitable RF using radio frequency (radio frequency, RF) power supply 201
Impedance matching circuit 200 is powered, and RF energy is inductively coupled to plasma reaction by the suitable RF impedance matching circuit 200
Room 59 is to generate plasma (for example, high-density plasma).Match circuit 200 can also be matching network, for RF electricity
Impedance matching between source 201 and inductance device 35.The match circuit 200 can be distributed along the coil in inductance device 35
Power is to establish the RF energy for generating plasma.Air supply opening 38 is connected to gas source 37, the gas source 37 supply into
Enter the process gas of plasma-reaction-chamber 59.
It is the wafer 70 with semiconductor substrate 1 being processed immediately below dielectric window 39.The semiconductor substrate 1
It is supported on substrate support 58, the substrate support 58 includes the lower electrode that can be biased by RF.The lower electrode is by another
RF power supply 47 carries out RF biasing.RF power supply 47 is different from RF power supply 201.Under RF power supply 47 is coupled to by impedance matching circuit 45
Electrode.
It is a moveable symmetrical lining 57 around substrate support 58.Lining 57 is removably hung in locular wall
55.The lining 57 has bottom side 82 in homogeneous thickness, and the bottom side 82 has multiple gas passages.Lining 57 relative to etc.
Gas ions reaction chamber 59 is symmetrical.Lining 57 is the form of annulus, and the center of the annulus is substantially in plasma-reaction-chamber 59
Center line 501 at.Lining 57 surrounds the substrate support 58.The center of substrate support 58 also substantially centered line
At 501.Bottom side 82 can also be the horizontal component being in close proximity on substrate support 58.Substrate support 58 supports wafer 70
And it is substantially orthogonal to locular wall 55.In some embodiments, bottom side 82 is substantially with the substrate support 58 in same level.Base
Plate support 58 is referred to as supporting element.The supporting element is disposed adjacent to the interposition of the plasma-reaction-chamber 59
It sets.In some embodiments, the supporting element extends from locular wall 55, and contacts with the locular wall 55.
Side 83 is a continuous cylinder outer wall in homogeneous thickness, is extended axially upward from the periphery of bottom side 82.Side
83 is substantially parallel with the locular wall 55.Side 83 and 55 distance of locular wall, one length L9.The side is close to turning 84, turning
84 are combined with the side 83 and the bottom side 82.Corner openings 81 are disposed close to the position at the turning 84.Side 83 exists
Extend on the substrate support 58.Substrate support 58 is height H7 at a distance from dielectric window 39.Bottom side 82 has
Such as the gas passage of bottom opening 80.Turning 84 is also with the gas passage of such as corner openings 81.Such as bottom opening 80
Or the gas passage of corner openings 81 allows gas particle 321 or plasma particle to pass through the lining 57.In some implementations
In example, substrate support 58 is lower than, and is equal to or higher than bottom side 82.
Lining 57 has top side 88.Top side 88 has the protruding portion for hanging buckle in locular wall 55.Top side 88 and dielectric window
The distance of mouth 39 is height H8.Bottom side 82 is height H5 at a distance from dielectric window 39.
Plasma reactor chamber 59 further includes the pump 73 for being placed on its bottom.Pump 73 can be symmetrical turbine pump,
It is symmetrically arranged relative to center line 501.Pump 73 can be the turbine pump for increasing gas discharge rate, so that plasma reaction
Low pressure is generated inside room 59.In some embodiments, pump 73, which can reduce pressure, makes pressure below about 1 millitorr.Pump 73 is by symmetrically
It is placed at the center of plasma-reaction-chamber 59, to help 59 inside of plasma-reaction-chamber uniformly to reduce pressure.This increases
Uniformity close to wafer 70 for the gas pressure of corona treatment.
Pump 73 is coupled to exhaust outlet 71 by exhaust pipe 72.Exhaust pipe 72 is the straight tube of no any steering.Exhaust pipe 72
It is arranged in parallel with the center line 501 of semiconductor manufacturing facility 500.In some embodiments, exhaust outlet 71, exhaust pipe 72, or pump
73 are symmetrically arranged relative to center line 501.
Shielding part 79 surrounds semiconductor manufacturing facility 500 and match circuit 200 and 45.Shielding part 79 is prevented from outside
Electric or magnetic field interference shielding part 79 inside electric field, magnetic field or any circuit.Shielding part 79 help to stablize by induced electricity or
The plasma that magnetic field generates.Shielding part 79 includes upper shielding part 75 and lower shielding part 77, with complete during corona treatment
Totally-enclosed semiconductor manufacturing facility 500.
In fig. 7 it is shown that the sectional view of lining 57.Lining 57 has top side 88, side 83 and bottom side 82.Top side 88 exists
On the top of side 83 in a ring.Turning 84 is ring-type in the bottom of side 83.Ring of the corner openings 81 around turning 84 is distributed.
Bottom side 82 is ring structure, and bottom opening 80 is distributed around the entire ring structure.The ring structure has for the substrate around Fig. 6
The hole 822 of supporting element 58.Substrate support 58 can symmetrically fit in the center in hole 822.In some embodiments, bottom side 82 is
Horizontal side, it is substantially orthogonal with side 83.In some other embodiment, bottom side 82 tilts an angle from side 83, fits
Pass through gas passage in the gas particle 321 of such as plasma.
In Fig. 7, top side 88 includes upper surface T88 and bottom surface B88.Bottom surface B88 is removably placed in Fig. 6
On locular wall 55, so that bottom surface B88 is contacted with the top of locular wall 55.Top side 88 has vertical from upper surface T88 to bottom surface B88
The thickness TH88 of measurement.Top side 88 protrudes a length L88 from side 83.Top side 88 has the planar rings around side 83.
Side 83 is columnar structured under top side 88.Side 83, which has from inner surface S831 to outer surface S832 level, to be surveyed
The thickness TH83 of amount.Side 83 has the H10 of the 82 upper surface T82 from upper surface T88 to bottom side.Height H10 is also from upper table
Face T88 is approximatively measured to turning 84.Side 83 it is columnar structured with the diameter surrounded by inner surface S831 be D83
Circle.
Bottom side 82 includes upper surface T82 and bottom surface B82.Thickness TH82 is vertically surveyed from upper surface T82 to bottom surface B82
Amount.Turning 84 combines between the inner surface S831 of upper surface T82 and side 83.Bottom side 82 at the center of lining 57 have pair
Claim the hole 822 of arrangement.
Hole 822 is diametrically the cylinder that D82 and its height are substantially equal to thickness TH82.Length L82 is from turning 84 to hole
822 upper measurements in the horizontal direction.Bottom side 82 has the bottom opening 80 for being scattered in 822 surrounding of hole.Bottom opening 80 is diametrically
D80 and its height are substantially equal to the cylinder of thickness TH82.Diameter D82 ratio D80 diameter is much bigger.Bottom opening 80 is to each other
Distance about length L80.Bottom opening 80 allows gas particle 321 to pass through lining 57.In some embodiments, bottom opening
80 have conical by its shape, so that the top surface and bottom surface of bottom opening 80 be not identical.For example, the bottom surface of bottom opening 80
It is smaller than top surface.
Corner openings 81 are arranged at turning 84.Corner openings 81 have side surface S84.Side surface S84 has along interior table
The height H81 that face S831 is directly measured from turning 84 to 81 highest point of corner openings.Side surface S84 and bottom side 82 are not parallel.Bottom side
82 be horizontal component.In some embodiments, side surface S84 is perpendicular to horizontal component.Side surface S84 is parallel with side 83.Side
Surface S84 is coplanar with inner surface S831.Corner openings 81 have bottom surface B84.Bottom surface B84 has along upper surface T82 from turning
The length L81 being measured in parallel closest to 822 deepest point of hole is arrived at angle 84.Distance between corner openings 80 is approximately length
L811。
Corner openings 81 include the upper surface 812 in side 83.Upper surface 812 has the highest point from inner surface S831
The thickness TH81 of relatively low spot measurement at the S832 of outer surface.In some embodiments, lower point is located at bottom surface B82.Turning
Opening 81 is with the lower surface 814 in bottom side 82.Lower surface 814 is from the highest point positioned at upper surface T82 to positioned at bottom surface B82
Relatively low spot.In some embodiments, lower point is located at outer surface S832.Lower surface 814 bottom surface B82 is deviateed with angle M81.
In some embodiments, upper surface 812 is roughly parallel to lower surface 814.In some other embodiments, upper surface 812 is under
Surface 814 is not parallel, so that upper surface 812 is with the angle deviating bottom surface B82 different from angle M81.Corner openings 81 have
Relative to the inclined channel bottom surface B82 of bottom side 82, so that gas particle 321 is moved towards the direction close to turning 84 to pass through
Lining 57.This can be prevented towards the gas particle 321 close to the movement of 84 direction of turning from inner surface S831 or close to the upper of angle 84
Surface T82 deflection.
In fig. 8 it is shown that some possible paths that gas particle 321 passes through in lining 570.It is turned in addition to not close
The silicon angle opening 81 at angle 84, lining 570 is similar to the lining 57 in Fig. 7.Lining 57 has the bottom opening 80 positioned at bottom side 82.
In situation 571, gas particle 321 is moved along incident path 33 to side 83.Gas particle 321 is anti-from side 83
Bullet is simultaneously moved along deflection path 34.Deflection path 34 is directed toward bottom side 82 and passes through bottom opening 80.
In situation 572, gas particle 321 is moved along incident path 33 to side 83.Gas particle 321 is from 83 He of side
It rebounds and is moved along deflection path 34 in bottom side 82.Deflection path 34 is directed toward the region on hole 822, which is placed with wafer
70.Deflection path 34 includes the horizontal component 341 of vertical portion 342 and oblique wafer 70 upward.Deflection path 34 has can
It can cause the collision with the other gas particles 322 moved downward to wafer 70.Gas particle 322, which has, is directed toward region 78 almost
Vertical direction.Presumptive area on wafer 70 of the covering of region 78 to be etched by gas particle 322.Such collision is similar to
Collision in Fig. 3, and the mean free path of gas particle 322 in lining 570 can be reduced.For example, if do not collided, gas
Body particle 322 can move the distance that one section is height H10 from top side 88 to wafer 70.However, the collision can be shortened gas
The distance that particle 322 moves.Gas particle 322 collides at the P4 of approximated position with gas particle 321.Position P4 is lower than top side 88
One height H11.Difference in height of the distance that the movement of gas particle 322 is shortened between height H10 and height H11.Gas particle
The shortening of 322 move distances reduces the mean free path of gas particle 322.Horizontal component 341 can make gas particle 322
Deviate from region 78.The collision reduces the micro loading effect on wafer 70.
Situation 573 is similar to situation 572, first beats in addition to gas particle 321 and then beats in bottom side 82 in side 83.In situation
In 573, gas particle 321 is moved along incident path 33 to bottom side 82.Gas particle 321 rebounds then from bottom side 82 from close to angle
84 side deflection.Deflection path 34 is directed toward the region on wafer 70 on region 78.Deflection path 34 includes upward vertical
Part 342 and the horizontal component 341 for being directed toward wafer 70.Deflection path 34 be easy to cause and along almost downward vertical direction direction crystalline substance
The collision of the gas particle of 70 movement of circle.
Situation 574 is similar to situation 573 or situation 572, the difference is that gas particle 321 beat than situation 573 or
Closer to the position at angle 84 in situation 572.It beats in the gas particle 321 close to 84 position of turning from bottom side 82 and/or close to turning
The side 83 at angle 84 deflects.By deflecting from bottom side 82, gas particle 321 obtains the vertical portion that downwardly top side 88 moves
342.By deflecting from side 83, gas particle 321 obtains the horizontal component 341 towards 83 oblique movement of side.Deflection path 34
It can cause the collision with other gas particles and change its direction, shorten its mean free path.
Corner openings 81 in Fig. 7 eliminate the gas close to turning 84 by allowing gas particle 321 by turning 84
The deflection of particle 321.The deflection of major part and bottom side 82 and/or side 83 is eliminated, which leads to the collision in lining 57.
Specifically, cause gas particle oblique movement with the collision of side 83 so that the gas particle collided be easy to miss it is scheduled
Etch areas, such as region 78, especially when the size in region 78 is smaller.The collision for causing horizontal component 341 is oblique touches
It hits.Gas particle, as the plasma particle 30 in Fig. 3 is more likely undergone oblique with respect to the larger open P27 in Fig. 3
It collides and misses smaller opening P25.For smaller opening P25, a small amount of horizontal component 341 can be knocked out from smaller opening P25
Gas particle.For larger open P27, a small amount of horizontal component 341 can change the direction of gas particle, but still allow gas
Particle falls into larger open P27.Oblique collision can be by knocking out from smaller opening P25 than knocking out more from larger open P27
Gas particle cause micro loading effect.
The method of another kind increase gas particle mean free path is the pressure by reducing the gas particle.So
And when the pressure reduction of the gas particle, the voltage for lighting the plasma from the gas particle increases.For
Raising voltage, the second inductance device 255 are directly grounded, as shown in Figure 9.
Fig. 9 is the schematic diagram of impedance matching network 211.Impedance matching network 211 is by RF power supply 201 in response in radio frequency
(RF) power and modify impedance.Impedance matching network 211 includes the first circuit 220 and second circuit 212.Impedance matching network
211 can be the combination similar to match circuit 200 and inductance device 35 in Fig. 6.
First circuit 220 includes 222 the first inductance device of ﹑ 250 of circuit and condenser network 232.First circuit 220 in response in
Radio frequency (RF) signal from RF power supply 201 adjusts the first output end for being located at circuit 222, i.e., the voltage etc. at node 251
Grade.First inductance device 250 exports the voltage class adjusted.Node 251 is between circuit 222 and the first inductance device 250
Coupling.First inductance device 250 has the Second terminal at node 252.Node 252 is in the first inductance device 250 and capacitor
It is coupled between circuit 232.Node 252 is coupled to reference voltage grade 270 by condenser network 232.The reference voltage grade
270 can be null ground voltage.First inductance device 250 includes inductance.The placement of first inductance device 250 is similar to
Inductance device 35 in Fig. 6.Second inductance device 255 of the first inductance device 250 or second circuit 212 have loop construction with
Establish the electric field of access areas R or magnetic field in RF energy, such as Fig. 6.First inductance device 250 or the second inductance device 255 can
To be the antenna with planar coil or helical coil shape.Condenser network 232 has the reactance of such as capacitor or inductor
Component.Condenser network 232 has more much bigger than the second capacitor between node 258 and the reference voltage grade 270 first
Capacitor.The current or voltage of node 251 or node 252 variation depend on the first inductance device 250 reactance (reactance) and
The reactance of condenser network 232.In some embodiments, circuit 222 is analogous to the match circuit 200 in Fig. 6.
Second circuit 212 includes circuit 222 and the second inductance device 255.Second circuit 212 provides predetermined at point 551
Voltage class.During plasma igniting, the scheduled voltage class of the second circuit 212 is higher than described first
The voltage class of circuit 220 adjusted.Second circuit 212 provides scheduled voltage class to light plasma.Plasma
Body igniting can be carried out by using different gas.Every kind of gas has different minimum ignition voltages.For example, nitrogen (N2) tool
There are the ignition voltage of about 250V, oxygen (O2) ignition voltage with about 440V.However, relatively low in millitorr magnitude pressure
Region, due to low collision rate, plasma igniting is relatively difficult.As a result, the voltage of hot spot is higher, for example, about 800V
To 1000V.In some embodiments, scheduled voltage is higher than about 1000 volts.
Second inductance device 255 includes first terminal 259, is coupled to the second output terminal of circuit 222, i.e. node 257,
And second terminal 258, it is directly coupled to reference voltage grade 270.
The RF power supply 201 can be through the power supply of circuit 222 to the first inductance device 250 or the second inductance device 255
Power supply.In some embodiments, the first inductance device 250 or the second inductance device 255 are twined around the axis for being parallel to center line 501
Around the i.e. plane perpendicular to dielectric window 39 in Fig. 6.In some embodiments, pass through the first inductance device 250 or the second electricity
The RF electric current of induction device 255 generates the RF electromagnetic field below dielectric window 39, in the Zone R domain of plasma-reaction-chamber 59,
To couple plasma for RF power, to increase the density of Fig. 6 plasma.
The circuit 222 can have more than two reactance components (reactive element).Inductor, capacitor,
Or the combination of inductor and capacitor can be used as more than two reactance components and use.The capacitor or inductor can be with
Parallel way or series system are connected to power supply.Described two above reactance components can have fixed or variable capacitor or electricity
Sense.Described two above reactance components be it is variable, to adjust the phase or size of applied voltage and current.
After the phase and size of the voltage applied are changed by the reactance component in circuit 222, distributed Voltage
It is applied to the first inductance device 250 or the second inductance device 255.In some embodiments, circuit 222 can have with parallel connection
Mode or series system are connected to the capacitor of node 251 or node 257.Circuit 222 can be in response in the RF from RF power supply
Signal adjusts the first inductance device 250 and/or distributed Voltage or electric current in the second inductance device 255.Circuit 222 can be with
Voltage or electric current between concept transfer 251 and node 252, between node 259 and node 258 or node 251 and node 259
Difference.
For the first inductance device 250 or the second inductance device 255 by the winding of spiral loop-shaped, by such helix
The circular electric current mode that circle provides produces peripheral plasma, which can cause in Fig. 6 in wafer in turn
The axial heterogeneity of etch-rate at 70.In other words, the field E (E-field) generated by planar coil antenna induction is logical
It is often angular (azimuthal) to generate angular plasma.
Some coupling lines for being used to construct the planar coil antenna such as the first inductance device 250 or the second inductance device 255
Length has particular electrical length at the certain radio frequency usually operated.In some embodiments, first from such as node 251 is whole
End proceeds forward to the voltage and current wave of such as second terminal of node 252, can reflect partially or completely in second terminal
Back.The superposition of forward and reflection wave, which will lead to, generates standing wave (that is, along the period of coil length voltage and current on coil
Property variation).
For the coil that such as the second inductance device 255 is grounded in node 258, electric current is in maximum value, voltage in node 258
It is zero in node 258.Along coil to node 259, voltage increases and electric current decreases up to the point of arrival 551, and electrical length is at point 551
90 degree, the voltage is in maximum value and the electric current is in minimum value.In some embodiments, voltage can be neighbouring other
Reach maximum at position, such as node 259.According to the electrical length of the second inductance device 255, point 551 can be located at node 259 and section
Any position between point 258.Point 551 is referred to alternatively as hot spot, and maximum voltage is located at the hot spot along the second inductance device 255
Place.By the way that node 258 to be directly grounded, maximum voltage is higher than filling the distributed Voltage in 250 in the first inductance.
For the coil of such as the first inductance device 250, in some embodiments, the electricity in node 252 and condenser network 232
Hold coupling, so that electric current is similar in node 251 and node 252 in coil, and increases to maximum value among the coil.Electricity
Pressure then reaches maximum at two-end-point, such as node 251 and node 252, and reduces among the coil to minimum value.?
In some embodiments, the maximum voltage at node 251 and node 252 is than the maximum voltage at the point 551 of the second inductance device 255
It is small.
Voltage changes on the direction along coil length.For example, point 551 is in maximum electricity in the second inductance device 255
Press position.The voltage of the either side of point 551 all declines.Therefore, compared to node 259, node 258 or the first inductance device
255, the energy coupling for lighting plasma is higher in point 551, and corresponding plasma is easier to be formed at point 551.Phase
High voltage can be realized by shortening the second inductance device 255 to ground connection, so that electric discharge can be easily in environment under low pressure
Middle progress, the low pressure are usually less than 1 millitorr.
It for improving the system of inductive coupling uniformity include position and the electricity for controlling the antenna in a kind of antenna system
Flow distribution, to improve the uniformity of plasma.
According to some exemplary embodiments, two or more spiral coils dispose the dielectric window in Fig. 6
On 39.The combination of the spiral winding of each coil or plane or planar coil and vertical stacking.The condenser network 232
Determine the position of current or voltage maximum value or minimum value in the first inductance device 250, and the reactance component in circuit 222 can be with
Change the overall impedance of each circuit such as the first circuit 220 or second circuit 212, therefore, the electricity in these multiple coils
The ratio of stream size can be adjusted.The position of maximum current in size and each coil by adjusting the electric current, etc.
The uniformity of plasma density and plasma can control.
In some embodiments, the electrical length of the coil can influence the uniformity of voltage or electric current along the coil.
For example, in some embodiments, the second inductance device 255 has the length shorter than the first inductance device 250.In some embodiments
In, voltage or electric current in the second inductance device 255 can than in the first inductance device 250 more evenly.
In some embodiments, the first inductance device 250 and the second inductance device 255 are two multiturns or single-turn circular coil.
Second inductance device 255 is closer to center line 501, and the first inductance device 250 is far from center line 501 and closer Fig. 6
In outer boundary 351.In some embodiments, the first inductance device 250 and the second inductance device 255 are concentrically surrounding center
Line 501.First inductance device 250 and the second inductance device 255 are symmetrical relative to center line 501.In Fig. 9, RF signal passes through
Node 251 and node 259 are sent to the first inductance device 250 and the second inductance device 255 simultaneously respectively.First inductance device
250 and second the opposite end of inductance device 255 terminated to condenser network 232 and reference voltage grade 270 respectively.It is described two
Coil effectively generates the plasma of more progressive annulars.In some embodiments, the first inductance device 250 and the second inductance
Electric current in device 255 relative to the center line 501 in Fig. 6 in the same direction.It is coupled to the plasma from the coil
Energy in the electromagnetic field of body scatters on the R of region, and generates the plasma of single flat, annular.First inductance is filled
Set 250 and the second unbalanced electric current between inductance device 255, the ring field of electromagnetic field can near center line 501 or
Outer boundary 351 is stronger.For example, plasma density can be in external edge by increasing the electric current in the first inductance device 250
Boundary 351 nearby increases, or by increasing the electric current in the second inductance device 255, plasma density can be in center line 501
Nearby increase.
Each coil is provided with the reactance component in circuit 222, to obtain along the more symmetrical electric current of the coil point
Cloth.For example, the adjustable reactance component of people, so that current maxima (and pure resistance impedance point) appears in the first electricity
Maximum point 550 in induction device 250.Maximum point 550 can be at the midpoint of the electrical length since node 251 or node 252.Institute
Electric current is stated in 550 highest of maximum point, nominally and it is reduced when the mode of either side sine is far from the maximum point 550.People
The capacitor of adjustable capacitance current 232, the maximum current near maximum point 550 to realize the first inductance device 250.It is tied
Fruit be coupled to plasma power it is higher below maximum point 550, and corresponding plasma density is higher.Some
In embodiment, maximum current described in the second inductance device 255 can be near node 258.In first inductance device 250 most
A little bigger 550 position is adjustable, so that the position of maximum point 550 and the hot spot is right relative to the center line 501 in Fig. 6
Claim.Maximum point 550 can be in the opposite side of the point 551 along same radial axis.Therefore, in node 258 in the second inductance device 255
Higher power coupling counteracts the influence of high-density plasma by the maximum point 550 of the first inductance device 250, to produce
Raw angular plasma more evenly.As the substitution for the reactance for adjusting circuit 222 or condenser network 232, the first inductance device
250 azimuth position can physically be rotated relative to the azimuth position of the second inductance device 255, so that electric first inductance
Current maxima in device 250 and the second inductance device 255 occurs mutual opposite side on the center line 501 in Fig. 6.
The matching network 211 may be implemented between the RF power supply 201 and the first inductance device 250 and/or the RF
Impedance matching between power supply 201 and second inductance device 255.
Matching network 211 changes the impedance of the first inductance device 250 and/or the second inductance device 255, to match such as RF
The characteristic resistance output impedance of the power supply of power supply 201.In some embodiments, the characteristic impedance is about 50 ohm (ohm).It adjusts
The reactance component in economize on electricity road 222, so that the reflection power at the output 202 of RF power supply 201 minimizes.Matching network
211 are adjusted to the smallest reflection power.
In fig. 10 it is shown that the method 400 of operation semiconductor manufacturing facility 500.Figure 10 is shown in operation diagram 6
Semiconductor manufacturing facility 500 operating process.It operates (or step) 410 and applies pair net of radio frequency (RF) signal into Fig. 9
Network 211.The exemplary embodiment of some operations 410 is shown in operation 410 in Figure 11.Operation (or step) 415 provides
Predetermined voltage class at the hot spot of point 551 in such as Fig. 9.Some operations 415 are shown in operation 415 in Figure 11
Exemplary embodiment.Operation (or step) 420 lights plasma under predetermined voltage class.Show in operation 420 in Figure 11
Some exemplary embodiments of operation 420 are gone out.It operates (or step) 425 and adjusts the matching network 211 described in realization
Impedance matching between inductance device 250 or 255 described in RF signal and Fig. 9.Operation 425 is shown in the operation 425 of Figure 11
Some exemplary embodiments.It operates (or step) 430 and realizes the impedance matching.It is shown in operation 430 in Figure 11
Some exemplary embodiments of operation 430.
In Figure 11, the chart 401 for generating plasma includes operation (or step) 410,415,420,425 and 430.Often
A operation, which all represents, is generating a stage in plasma process.Plasma generates in various semiconductor fabrication process
It is useful, such as plasmaassisted etches and deposition.Plasma is by the electric field ionization and generation of free electron low
It calms the anger and generates in body, the free electron, which passes through, ionizes single gas point through Single Electron-gas molecule collision momentum transfer
Son.The electronics usually accelerates in the electric field, and typical electric field is rf electric field.
In some embodiments, during plasma generates, the upper semiconductor manufacturing facility 500 is by 79 envelope of shielding part
It closes, to prevent the interference from external electromagnetic field.The plasma lower than predetermined pressure pressure condition under wait from
Daughter reaction chamber 59 generates.In some embodiments, predetermined pressure is set to about 2 millitorrs (millitorrs), with reduction etc.
Micro loading effect during gas ions processing.
In act 410, such as the radio frequency source of RF power supply 201, for providing oscillating current or voltage to the such as first electricity
The antenna system of induction device 250 or the second inductance device 255, the process usually pass through the radio frequency matching network 211 in Fig. 9 into
Row.Oscillating current is resonated by antenna system, induces the angular electric field in Fig. 6 plasma reaction chamber 59.At the same time,
Process gas introduces the plasma-reaction-chamber 59 through air supply opening 38, and the electric field ionization process gas induced is to generate Fig. 6
Plasma in plasma reaction chamber 59.The plasma then strikes on wafer 70, and the wafer 70 is with all
(such as etching) wafer 70 is handled as the mode of the electrostatic chuck of substrate support 58 is fixed, and by required mode.
In Figure 11, during operation 410, the impedance in matching network 211 in Fig. 9 is mainly almost without resistance
Reactance.This occurs when RF power supply 201 starts to supply electrical power to matching network 211.RF signal passes through the matching network 211
RF energy is established, for generating in response in the plasma of the RF signal.The RF energy is believed by matching network 211 from RF
Number coupling.The matching network 211 in Fig. 9 has first node 257 and the second inductance device 255, the second inductance dress
Setting 255 has 259 first terminal of such as node for being coupled to first node 257.Such as the second terminal of node 258 then direct coupling
Close reference voltage grade 270.Such as put 551 second node be such as first terminal of node 259 and as node 258 second
Hot spot between terminal.In some embodiments, matching network 211 includes another inductance device, for example, having such as node
First inductance device 250 of 252 terminal, the node 252 are coupled to by the capacitive means in condenser network 232 with reference to electricity
Press grade 270.
In act 410, in some embodiments, reactance is capacitive, as shown in the chart 401 in Figure 11.It is described
Impedance is located on the point of unit circle, the unit circle instruction RF power supply 201 and such as the first inductance device 250 and/or the second electricity
Short circuit between the load of induction device 255.
In act 410, the voltage is mostly from the load reflection.For example, being transmitted to the institute of the first inductance device 250
Voltage is stated to reflect towards RF power supply 201.Ratio between the reflected voltage and the incident voltage is the big of reflection coefficient
It is small.The size of the reflection coefficient is unified, and the almost all of power from RF power supply 201 during operation 410
It is reflected.It is formed during operation 410 almost without plasma.
In operation 415, the impedance of matching network 211 still mainly has low-resistance reactance in Fig. 9.In some realities
It applies in example, the reactance component in circuit 222 is adjusted so that the capacity reactance increases in matching network 211.Increase institute
Reactance is stated to increase the voltage in the first inductance device 250 or the second inductance device 255.During operation 415, the impedance is still
Short circuit so on the point of unit circle, between the unit circle instruction RF power supply 201 and the load.It is nearly all to come from RF
The power of power supply 201 is reflected.
It during operation 415, puts 551 voltage or electric current starts to increase, to reach maximum voltage, such as the second inductance dress
Set the scheduled maximum voltage of institute in 255.The RF energy of plasma-reaction-chamber 59 is also increasing, and is used for plasma point to reach
The ceiling capacity of fire.In some embodiments, according to the variation of capacitor in circuit 222 or condenser network 232, in 251 He of node
Voltage at node 252 is also increasing, to reach another maximum voltage in the first inductance device 250.In some embodiments
In, the maximum voltage in the second inductance device 255 is than high in the first inductance device 250.During operation 415 still almost
There is no plasma to be formed below point 551.
During operation 415, in some embodiments, the electric current at point 551 is decreased in the second inductance device 255 most
Small value.The electric current increases from point 551 to such as terminal of node 259 or node 258.
During operation 420, the impedance of matching network 211 is still mainly with the reactance of low-resistance value in Fig. 9.It is described
Capacitive reactance about in chart 401 normalized impedance 0.5 near reach maximum value.
During operation 420, in some embodiments, the voltage at point 551 reaches the maximum in the second inductance device 255
Voltage.In some embodiments, maximum voltage is the predetermined voltage being arranged at such as second node of point 551.The predetermined electricity
Pressure approximation is more than 1000 volts (volt).In some embodiments, the voltage at node 251 and node 252 also reaches
Maximum voltage in one inductance device 250.When in maximum voltage, plasma igniting occurs in the R of region, in point 551
Close beneath.The plasma is ignited under scheduled voltage class.In some embodiments, plasma igniting also can
The point close beneath in such as node 251 or node 252 occurs, and the maximum voltage in the first inductance device 250 appears in node
251 or node 252 at.
During operation 420, the electric current at point 551 increases from point 551 to the either side of point 551, and close to node 259
Or the either side of node 258 reaches current maxima.The plasma density of second inductance device, 255 lower section is also from by near point
The region of 551 lower sections increases to other regions under node 259 and/or node 258.In some embodiments, the first inductance
Electric current in device 250 also reaches maximum current value in certain predetermined positions, so that the density of the plasma is substantially
Uniformly, and the position of each maximum current value is symmetrically arranged relative to the center line 501 in Fig. 6.
During operation 425, the impedance of matching network 211 is regulated so that reactance and resistance are changed in Fig. 9.It is described
Capacitive reactance can automatically change from the maximum value about at 0.5 to the impedance matching point in chart 401.The impedance can
To be changed during operation 425 in various ways.The impedance final reaches at 401 center of chart, there the coil
Impedance, such as the first inductance device 250 and/or the second inductance device 255 impedance be equal to the RF power supply characteristic impedance.
From operation 420 to operation 430, the normalized impedance of the resistance changes between about 0 to about 1, the normalized impedance
It is shown in chart 401.The normalized impedance of the reactance changes between about 0.5 to about 1.
During operation 425, in some embodiments, the voltage in the first inductance device 250 or the second inductance device 255
Changed according to the adjusting of impedance described in matching network 211.After plasma ignition, which can be reduced to any electricity
Lower voltage in induction device 255 or 250.In some embodiments, the voltage at point 551 can be reduced to for plasma
Under the maximum voltage of igniting.
In operation 425, the electric current in the first inductance device 250 or the second inductance device 255 is also according to matching network
The adjusting of 211 middle impedances and change.In some embodiments, operation 425 is the uniformity in order to realize the electric current, so that edge
The difference of the size of current of the first inductance device 250 or the second inductance device 255 reduce.First inductance device 250 and second
Size of current in inductance device 255 is symmetrical relative to the center line 501 in Fig. 6.The plasma density is relative to described
The size of electric current is formed.Most of plasma is formed during operation 425.
During operation 430, the impedance of matching network 211 and the impedance of the RF power supply match in Fig. 9.The impedance
The normalized impedance of reactance reach 0, the normalized impedance is shown in chart 401.The normalized impedance of the resistance reaches
To 1.
During operation 430, the voltage is transmitted to the load mostly.For example, being transmitted to the voltage quilt of node 251
Reach the first inductance device 250.The size of the reflection coefficient is almost 0 during operation 430, nearly all to come from RF power supply
201 power is all transmitted.In some embodiments, down to after certain grade, which can for example lose for the voltage drop
A period of time is maintained during the corona treatment at quarter.Most of plasmas are formed during operation 430.
In operation 430, the electric current in the first inductance device 250 or the second inductance device 255 is kept, so that plasma
Volume density keeps substantially uniform within the regular period during the plasma processing operation.
Using the matching network 211 and operation device, method of the embodiment of the present invention, the process gas originally for being passed through can be made
React and under a nominal pressure build-up of luminance plasma reaction chamber 59, obtain in being passed through under identical process gas, make etc. from
Daughter build-up of luminance under lower pressure, to reduce the micro loading effect during corona treatment.Nominal pressure means reaction chamber
59 under conditions of without matching network 211 of the present invention, usually make the pressure of plasma glow start, for example, 3 millitorrs.In some realities
It applies in example, reaction chamber 59 cooperates matching network 211 that can make plasma build-up of luminance under lower pressure, for example, 2 millitorrs.Only originally
The pressure value or range being not limited to the above embodiments is invented, such as under the process gas of difference, above-mentioned nominal pressure is had
Institute is different, therefore above-mentioned lower build-up of luminance pressure is also different therewith.
As shown in table 1 below in semiconductor crystal wafer, made semiconductor devices is in its first Qu Yu according to the present invention
The measured data in 2nd area.Firstth area is spaced with the secondth area, and the device density in the firstth area is greater than the device density in the secondth area,
That is, first area be compact district (R1) and second is area rarefaction (R2).In table 1, depth D1 and D2 means the bottom table of groove
The distance of the top surface of face and semiconductor substrate, even if groove will insert such as insulating materials in follow-up process.Some
In embodiment, the predetermined value of depth D1 and D2 are 2700 angstroms.Also, side inclination angle SWA1 means that the upper side wall of groove (is located at example
As Fig. 5 bending part 181 and middle layer 11 between) angle with the bottom surface of semiconductor substrate, and side inclination angle SWA2 system
Refer to the bottom of lower wall (between the bending part 181 and the bottom surface of groove of such as Fig. 5) and semiconductor substrate of groove
The angle on surface.In the ideal case, side inclination angle SWA1 and SWA2 is close to 90 °.In addition, because in the R2 of rarefaction without obvious curved
Folding part 181, so side inclination angle SWA can treat as the upper side wall of groove.
Table 1
It can be found by table 1 because of micro loading effect, depth D2 of the depth D1 less than rarefaction R2 of compact district R1, and compact district
The side inclination angle SWA1 of R1 is then greater than the side inclination angle SWA of rarefaction R2.
It is analyzed for it for the data based on table 1 as shown in table 2 below.
Table 2
As shown in Table 2 because of micro loading effect, the minimum difference value of the depth D2 of the depth D1 and rarefaction R2 of compact district R1
For(wafer number 6), and maximum different value is(wafer number 8), relative to depth predetermined value
For, there is 4.96% and 10.67% error respectively.In addition, the depth D2 of the depth D1 and rarefaction R2 of compact district R1 is flat
Equal difference value isIt is relative to depth predetermined valueFor, error 7.1%.In some embodiments,
The difference of the depth D2 of the depth D1 and rarefaction R2 of compact district R1 are about 5% to 11% for depth predetermined value, compared with
Good person is 6%~8%, and mean error is about 7%.Therefore, close caused by the present invention has been effectively improved because of micro loading effect
The depth difference of Ji Qu and rarefaction.
Because of micro loading effect, the minimum difference of the side inclination angle SWA of the side inclination angle SWA1 and rarefaction R2 of compact district R1
Value is 3 ° (wafer number 3), and maximum different value is 6.5 ° (wafer number 11), for 90 ° of inclination angle predetermined value, point
There is not 3.33% and 7.22% error.In addition, the side inclination angle SWA of the side inclination angle SWA1 and rarefaction R2 of compact district R1 it
Average difference values are 5.31 °, for 90 ° of inclination angle predetermined value, error 5.9%.In some embodiments, compact district
The difference of the side inclination angle SWA of the side inclination angle SWA1 and rarefaction R2 of R1 for the predetermined value of inclination angle be about 3% to
7.5%, preferably it is 4%~7%, and mean error is about 6%.Therefore, the present invention has been effectively improved because of micro loading effect institute
The side inclination angle difference of caused compact district and rarefaction.
Because of the difference of aperture opening ratio (aspect ratio), the minimum difference value of the side inclination angle SWA1 and SWA2 of compact district R1
For 2 ° (wafer numbers 7), and maximum different value is 7.5 ° (wafer number 6), for 90 ° of inclination angle predetermined value, is distinguished
There is 2.22% and 8.33% error.In addition, the average difference values of the side inclination angle SWA1 and SWA2 of compact district R1 are 4.94 °,
It is for 90 ° of inclination angle predetermined value, error 5.49%.In some embodiments, the side inclination angle SWA1 of compact district R1
Difference with SWA2 is about 2% to 8.5% for the predetermined value of inclination angle, preferably and it is 4%~7%, and mean error is about
It is 5.5%.Therefore, the compact district side inclination angle difference caused by the present invention has been effectively improved the difference because of aperture opening ratio.
Some embodiments of the present invention provide a kind of semiconductor manufacturing facility.The semiconductor manufacturing facility includes configuration
At the chamber for plasma process.The chamber includes wall, and the supporting element for fixing wafer.The supporting element essence
On perpendicular to the wall.Stress liner configuration is at removably hanging on the wall.The lining includes substantially parallel to the wall
Side, and the horizontal side in conjunction in the side of corner.The horizontal side has the first opening.Second opening is put
It sets in the position close to the turning.
Some embodiments of the present invention provide a kind of semiconductor manufacturing facility.The semiconductor manufacturing facility includes being matched
It is set to the matching network established for generating plasma rf RF energy.The matching network have the first circuit, in response to
Voltage class is adjusted in radio frequency rf signal.First circuit has first node and the first inductance device, is adjusted with exporting
The voltage class crossed.Second circuit has the second inductance device.Second inductance device includes being coupled to the first node
First terminal and be directly coupled to the second terminal of reference voltage grade.The second circuit is in the first terminal and institute
The second node stated between second terminal provides predetermined voltage class.
Some embodiments of the present invention provide a kind of method of semiconductor manufacturing facility of the operation with matching network.Institute
The method of stating includes: that radio frequency rf signal is transmitted to the matching network；In response in the RF signal, built by the matching network
The RF energy for generating plasma is found, the matching network has first node and inductance device, the first inductance dress
It sets to have and is coupled to the first terminal of the first node and is directly coupled to the second terminal of reference voltage grade, Yi Ji
Second node between the first terminal and the second terminal；Predetermined voltage is provided in the second node；In predetermined electricity
Plasma is lighted under pressure grade；And the matching network is adjusted to realize between the RF signal and the inductance device
Impedance matching.
Foregoing has outlined the feature of several embodiments so that those skilled in the art be better understood it is of the invention each
Aspect.Those skilled in the art should be understood that they can be by the present invention as basis, for designing or modifying for executing phase
With the other processes and structure of purpose and/or the same benefits for obtaining the embodiment introduced herein.Those skilled in the art can also
Recognize construction equivalent in this way without departing from spirit and scope of the invention, and do not depart from spirit of the invention and
In the case where protection scope, they can do various changes, substitutions and modifications herein.
Claims (18)
1. a kind of semiconductor manufacturing facility characterized by comprising
Reaction chamber is configured for plasma process, and the reaction chamber has locular wall；
Supporting element is configured to fixed wafer in the reaction chamber；And
Lining is configured to around the supporting element, and the lining includes
Top side is removably hung on the locular wall；
Bottom side has multiple gas passages to allow plasma particle to pass through the lining；
Extend the side between the top side and the bottom side；And
Right angle corner positioned at the side and the bottom side junction, wherein multiple gas passage includes being located at the right angle corner
Corner openings.
2. equipment as described in claim 1, which is characterized in that further comprise the pump positioned at the reaction chamber bottom and coupling
To the exhaust pipe of the pump, and the exhaust pipe is straight tube.
3. equipment as described in claim 1, which is characterized in that multiple gas passage includes the bottom surface positioned at the bottom side
Bottom opening.
4. equipment as claimed in claim 3, which is characterized in that the bottom opening is cylindrical or taper.
5. equipment as described in claim 1, which is characterized in that it is to incline that the corner openings, which have the bottom surface relative to the bottom side,
Oblique channel.
6. a kind of semiconductor manufacturing facility, including for making the reaction chamber of plasma glow start under nominal pressure, which is characterized in that
Include:
RF power supply is configured to generate radiofrequency signal, and powers in the first output end and second output terminal；And
Matching network, the power for being configured to be exported RF power supply are coupled to reaction chamber, and make reaction chamber lower than the mark
Claim build-up of luminance plasma under the pressure of pressure, which includes:
First circuit, in response to, to adjust voltage class, which has the first inductance device to export in radiofrequency signal
The voltage class adjusted, and first inductance device and a condenser network are series at first output end and reference voltage etc.
Between grade；
Second circuit has the second inductance device to provide scheduled voltage class to light plasma, second inductance
Device is coupled directly between the second output terminal and the reference voltage grade；And
The lining of reaction chamber locular wall is removably hung over, which includes
Top side；
Bottom side has multiple gas passages to allow plasma particle to pass through the lining；
Extend the side between the top side and the bottom side；And
Right angle corner positioned at the side and the bottom side junction, wherein multiple gas passage includes being located at the right angle corner
Corner openings.
7. equipment as claimed in claim 6, which is characterized in that the electric current maximum point of first inductance device and the second inductance fill
The voltage maximum point set is symmetrical with the center line for generating the reaction chamber of plasma.
8. equipment as claimed in claim 6, which is characterized in that the scheduled voltage class of the second circuit be higher than this first
The voltage class that circuit was adjusted.
9. equipment as claimed in claim 6, which is characterized in that first inductance device or the second inductance device have planar line
The antenna of circle or helical coil shape.
10. equipment as claimed in claim 6, which is characterized in that second inductance device is compared with the first inductance device close to generation
The center line of the reaction chamber of plasma.
11. equipment as claimed in claim 10, which is characterized in that first inductance device and second inductance device 255 are same
Heart surrounds the center line.
12. equipment as claimed in claim 6, which is characterized in that further comprise shielding part, surround the semiconductors manufacture and set
The standby and matching network.
13. a kind of semiconductor devices manufactured with semiconductor manufacturing facility as claimed in claim 6 characterized by comprising
There are multiple devices to be arranged with the first device density in the firstth area；And
Secondth area is spaced with the firstth area, and there are multiple devices to be arranged with the second device density, and the second device density is less than the
One device density, and the predetermined depth of multiple device is identical as the predetermined depth of multiple device in the firstth area in the secondth area,
Wherein, the depth of multiple device and the difference of the depth of multiple device in the secondth area are predetermined relative to this in the firstth area
Depth is 6%~8%.
14. semiconductor devices as claimed in claim 13, which is characterized in that the depth of multiple device and second in the firstth area
The mean difference of the depth of multiple device is 7% relative to the predetermined depth in area.
15. semiconductor devices as claimed in claim 13, wherein the predetermined side inclination angle of multiple device and the in the firstth area
The predetermined side inclination angle of multiple device is identical in 2nd area, which is characterized in that in the firstth area the side inclination angle of multiple device with
The difference at the side inclination angle of multiple device is 4%~7% relative to predetermined side inclination angle in secondth area.
16. semiconductor devices as claimed in claim 15, which is characterized in that in the firstth area the side inclination angle of multiple device with
The mean difference at the side inclination angle of multiple device is 6% relative to predetermined side inclination angle in secondth area.
17. semiconductor devices as claimed in claim 15, which is characterized in that in the firstth area the upper side inclination angle of multiple device
It relative to predetermined side inclination angle is 4%~7% with the difference at downside inclination angle.
18. semiconductor devices as claimed in claim 17, which is characterized in that in the firstth area the upper side inclination angle of multiple device
It relative to predetermined side inclination angle is 5.5% with the mean difference at downside inclination angle.
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| CN201610232603.3A CN107301941B (en) | 2016-04-14 | 2016-04-14 | Apparatus for processing plasma and its operating method |
| US15/162,992 US9899194B2 (en) | 2016-04-14 | 2016-05-24 | Apparatus for plasma treatment and method of operating the apparatus |
| TW106121764A TWI656559B (en) | 2016-04-14 | 2016-06-03 | Operation method for plasma treatment apparatus |
| TW105117531A TWI595530B (en) | 2016-04-14 | 2016-06-03 | Apparatus for plasma treatment and operation method thereof |
| US15/866,878 US10170285B2 (en) | 2016-04-14 | 2018-01-10 | Method of operating semiconductor manufacturing apparatus and semiconductor devices |
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| TWI581910B (en) * | 2016-02-01 | 2017-05-11 | Yi-He Liao | Dust-proof ratchet wrench construction (2) |
| TWI581911B (en) * | 2016-02-01 | 2017-05-11 | Yi-He Liao | Dustproof ratchet wrench structure (a) |
| KR20220032608A (en) * | 2019-07-15 | 2022-03-15 | 어플라이드 머티어리얼스, 인코포레이티드 | Large Area High Density Plasma Processing Chamber for Flat Panel Displays |
| CN110223904A (en) * | 2019-07-19 | 2019-09-10 | 江苏鲁汶仪器有限公司 | A kind of plasma process system with Faraday shield device |
| CN111725106B (en) * | 2020-06-22 | 2023-09-08 | 北京北方华创微电子装备有限公司 | Semiconductor process equipment and process chamber thereof |
| CN114242554B (en) * | 2021-12-20 | 2024-01-05 | 北京北方华创微电子装备有限公司 | Semiconductor process equipment and impedance compensation method in radio frequency loop |
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Also Published As
| Publication number | Publication date |
|---|---|
| US10170285B2 (en) | 2019-01-01 |
| TW201802862A (en) | 2018-01-16 |
| US20180158656A1 (en) | 2018-06-07 |
| TW201737289A (en) | 2017-10-16 |
| US20170301523A1 (en) | 2017-10-19 |
| US9899194B2 (en) | 2018-02-20 |
| TWI595530B (en) | 2017-08-11 |
| TWI656559B (en) | 2019-04-11 |
| CN107301941A (en) | 2017-10-27 |
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