CN107301868A - Audio decoding system and audio-frequency decoding method - Google Patents
Audio decoding system and audio-frequency decoding method Download PDFInfo
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- CN107301868A CN107301868A CN201710488307.4A CN201710488307A CN107301868A CN 107301868 A CN107301868 A CN 107301868A CN 201710488307 A CN201710488307 A CN 201710488307A CN 107301868 A CN107301868 A CN 107301868A
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- G10L19/00—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis
- G10L19/04—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis using predictive techniques
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Abstract
The invention provides a kind of audio decoding system and audio-frequency decoding method, voice data to be decoded is sent to second processor by data buffer zone and handled by first processor, and the first processor controls the audio decoder of the second processor by the interactive unit, realizes that audio decoder improves decoding efficiency and system real time jointly by two processors；Interaction between two processors is realized by interactive unit, the transmission of voice data to be decoded is realized by data buffer zone, it is ensured that two processors realize the reliability of audio decoder jointly.
Description
Technical field
The present invention relates to audio signal processing technique field, more particularly to a kind of audio decoding system and audio-frequency decoding method.
Background technology
With developing rapidly for microelectric technique and multimedia technology, embedded product is widely used in family, yard
The multiple fields such as institute, public place of entertainment, the demand to audio broadcast decoder in embedded system is also constantly being lifted.But it is due to
Embedded system kernel is small, the features such as limited system resources, so there is performance bottleneck, system always to high quality audio decoding
Decoding is likely to occur in operation and is taken causes the other tasks of system to handle in time or causes solution due to handling other tasks
The problem of code can not be completed in time, the real-time and Consumer's Experience of extreme influence system.
The content of the invention
It is an object of the invention to provide a kind of audio decoding system and audio-frequency decoding method, to solve to deposit in the prior art
Decoding is likely to occur in system operation and is taken causes the other tasks of system to handle in time or due to handling other tasks
Cause the problem of decoding can not be completed in time.
Based on above-mentioned purpose, the present invention provides a kind of audio decoding system, and the audio decoding system includes：First processing
Device, second processor, interactive unit and data buffer zone；Wherein,
Voice data to be decoded is sent to the second processing by the first processor by the data buffer zone
Device is handled, and the first processor controls the audio decoder of the second processor by the interactive unit.
Optionally, in described audio decoding system, the interactive unit includes the first interactive unit and the second interaction
Unit；Wherein, first interactive unit is used to realize the interaction between the first processor and the second processor；Institute
State the memory address mappings that the second interactive unit is used to store the second processor operation.
Optionally, in described audio decoding system, the first processor is stored by second interactive unit
The memory address mappings start the second processor.
Optionally, in described audio decoding system, the first processor is additionally operable to reset the second processor.
Optionally, in described audio decoding system, first interactive unit includes interrupt control register, described
Interrupt control register is used for Transmission signal, and the first processor and the second processor pass through the interrupt signal
Interact.
Optionally, in described audio decoding system, the interrupt control register includes first and interrupts control deposit
Device and the second interrupt control register, first interrupt control register be used to transmitting the first processor be sent to it is described
The interrupt signal of second processor, second interrupt control register, which is used to transmitting the second processor, is sent to described the
The interrupt signal of one processor.
Optionally, in described audio decoding system, first interrupt control register and described second interrupts control
Register processed is 32 interrupt control registers.
Optionally, in described audio decoding system, first interactive unit also includes mailbox registers, the letter
Case register includes data register and mutual exclusion lock, and the data register is used to store the first processor and described second
The order of processor interaction, the mutual exclusion lock is used to latch the data register.
Optionally, in described audio decoding system, the mutual exclusion lock includes for latching the data register：When
When the first processor sends control command, the first processor inquires about mutual exclusion lock；The first processor obtains idle
Mutual exclusion lock, and by the idle mutual exclusion lock labeled as busy；The corresponding data of mutual exclusion lock from the first processor to acquisition
Control command is write in register；The first processor produces interrupt signal according to the mutual exclusion lock of the acquisition；Described first
Processor discharges the mutual exclusion lock of the acquisition.
Optionally, in described audio decoding system, the mutual exclusion lock also includes for latching the data register：
When the second processor receives control command, the second processor receives interrupt signal；The second processor according to
The interrupt signal obtains mutual exclusion lock；The second processor is read in corresponding data register according to the mutual exclusion lock of acquisition
Control command；The second processor writes commands in return into the data register；The second processor, which is set, interrupts
Signal；The mutual exclusion lock that the second processor release is obtained.
Optionally, in described audio decoding system, the mutual exclusion lock also includes for latching the data register：
When the first processor receives commands in return, the first processor receives interrupt signal；The first processor according to
The interrupt signal obtains mutual exclusion lock；The first processor reads the reply in corresponding data box according to the mutual exclusion lock of acquisition
Order；The mutual exclusion lock that the first processor release is obtained.
Optionally, in described audio decoding system, the quantity of the data register is 32 groups, the mutual exclusion
The quantity of lock is 32 groups, wherein, mutual exclusion lock is corresponded described in data register described in 32 groups and 32 groups.
Optionally, in described audio decoding system, the first processor is sent to the life of the second processor
Order includes DMA interruptions.
Optionally, in described audio decoding system, the first processor is described by sending control command control
The audio decoder of second processor, the control command is including playing, exiting, suspending, fast forward and fast reverse.
Optionally, in described audio decoding system, the data buffer zone is used to deposit voice data to be decoded
With decoded voice data.
Optionally, in described audio decoding system, the data buffer zone includes input data buffering area and output
Data buffer zone, wherein, the input data buffering area is used to deposit voice data to be decoded, the data output buffer area
Audio-frequency information for depositing decoded voice data and decoded voice data.
Optionally, in described audio decoding system, the input data buffering area enters line number by the first write pointer
According to write-in, digital independent is carried out by the first read pointer；The data output buffer area carries out data by the second write pointer and write
Enter, digital independent is carried out by the second read pointer.
Optionally, in described audio decoding system, the second processor is carried out to be decoded using chain type dma mode
Voice data input and decoded voice data output.
Optionally, in described audio decoding system, the first processor and/or the second processor are additionally operable to
Audio post processing, the processing of audio transcoding, recording processing and/or playback process are carried out to decoded voice data.
Optionally, in described audio decoding system, the first processor is additionally operable to decoded voice data
Write peripheral hardware storage medium.
Optionally, in described audio decoding system, the first processor is RISC, and the second processor is
DSP。
The present invention also provides a kind of audio-frequency decoding method, and the audio-frequency decoding method includes：First processor will be to be decoded
Voice data second processor be sent to by data buffer zone handled；And the first processor passes through interactive unit
Control the audio decoder of the second processor.
Optionally, in described audio-frequency decoding method, first processor delays voice data to be decoded by data
Rush area and be sent to that second processor is handled and the first processor controls the second processor by interactive unit
Audio decoder is carried out simultaneously；Or voice data to be decoded is sent to second processing by first processor by data buffer zone
Device is handled to be carried out before the first processor controls the audio decoder of the second processor by interactive unit；Or
Voice data to be decoded is sent to second processor by data buffer zone and handled described by person's first processor
One processor controls to carry out after the audio decoder of the second processor by interactive unit.
Optionally, in described audio-frequency decoding method, the first processor controls described second by interactive unit
The audio decoder of processor includes：
The first processor sends control command to the interactive unit, and the first processor is by sending control life
Order control audio decoder；
The second processor receives control command from the interactive unit, and handles to be decoded according to the control command
Voice data.
Optionally, in described audio-frequency decoding method, the first processor sends control life to the interactive unit
Order includes：
The first processor inquires about mutual exclusion lock；
The first processor obtains idle mutual exclusion lock, and by the idle mutual exclusion lock labeled as busy；
The first processor writes control command into the corresponding data register of mutual exclusion lock of acquisition；
The first processor produces interrupt signal according to the mutual exclusion lock of the acquisition；
The first processor discharges the mutual exclusion lock of the acquisition.
Optionally, in described audio-frequency decoding method, the second processor receives control life from the interactive unit
Order, and included according to control command processing voice data to be decoded：
The second processor receives interrupt signal；
The second processor obtains mutual exclusion lock according to the interrupt signal；
The second processor reads the control command in corresponding data register according to the mutual exclusion lock of acquisition；
The second processor writes commands in return into the data register；
The second processor sets interrupt signal；
The mutual exclusion lock that the second processor release is obtained.
Optionally, in described audio-frequency decoding method, the second processor reads correspondence according to the mutual exclusion lock of acquisition
Data register in control command after, the second processor from the interactive unit receive control command, and according to
The control command, which handles voice data to be decoded, also to be included：
The second processor reads the voice data to be decoded of input data buffering area；
The voice data to be decoded that the second processor decoding is read；
The second processor writes decoded voice data and decoded voice data to data output buffer area
Audio-frequency information.
Optionally, in described audio-frequency decoding method, the second processor reads correspondence according to the mutual exclusion lock of acquisition
Data register in control command after, the second processor from the interactive unit receive control command, and according to
The control command, which handles voice data to be decoded, also to be included：
The second processor carries out the input of voice data to be decoded using chain type dma mode；
The voice data to be decoded of the second processor decoding input；
The second processor carries out the output of decoded voice data using chain type dma mode.
Optionally, in described audio-frequency decoding method, the second processor receives control life from the interactive unit
Order, and after handling voice data to be decoded according to the control command, the first processor passes through interactive unit control
The audio decoder of the second processor also includes：
The first processor receives commands in return from the interactive unit.
Optionally, in described audio-frequency decoding method, the first processor is received back to from the interactive unit and reported on completion of a task
Order includes：
The first processor receives interrupt signal；
The first processor obtains mutual exclusion lock according to the interrupt signal；
The first processor reads the commands in return in corresponding data register according to the mutual exclusion lock of acquisition；
The mutual exclusion lock that the first processor release is obtained.
Optionally, in described audio-frequency decoding method, the first processor is received back to from the interactive unit and reported on completion of a task
After order, the audio-frequency decoding method also includes：
The first processor reads the decoded voice data in data output buffer area.
Optionally, in described audio-frequency decoding method, the first processor reads the solution in data output buffer area
After the voice data of code, the audio-frequency decoding method also includes：
The first processor and/or the second processor carry out audio post processing, sound to decoded voice data
The processing of frequency transcoding, recording processing and/or playback process.
Optionally, in described audio-frequency decoding method, the first processor reads the solution in data output buffer area
After the voice data of code, the audio-frequency decoding method also includes：
Decoded voice data is write peripheral hardware storage medium by the first processor.
Optionally, in described audio-frequency decoding method, described is controlled by interactive unit in the first processor
Before the audio decoder of two processors, the audio-frequency decoding method also includes：
The memory address mappings that the first processor is stored by the second interactive unit start the second processor.
In the audio decoding system that provides of the present invention and audio-frequency decoding method, first processor is by audio number to be decoded
Handled according to second processor is sent to by data buffer zone, and the first processor passes through the interactive unit control
The audio decoder of the second processor is made, realizes that audio decoder improves decoding efficiency and system jointly by two processors
Real-time；Interaction between two processors is realized by interactive unit, audio number to be decoded is realized by data buffer zone
According to transmission, it is ensured that two processors realize the reliability of audio decoder jointly.
Brief description of the drawings
Fig. 1 is the mount structure schematic diagram of the audio decoding system of the embodiment of the present invention；
Fig. 2 is the schematic flow sheet of the audio-frequency decoding method of the embodiment of the present invention；
Fig. 3 be the embodiment of the present invention audio-frequency decoding method in control command interact schematic flow sheet.
Embodiment
Below in conjunction with the drawings and specific embodiments audio decoding system proposed by the present invention and audio-frequency decoding method are made into
One step is described in detail.According to following explanation and claims, advantages and features of the invention will become apparent from.It should be noted that,
Accompanying drawing uses very simplified form and uses non-accurately ratio, only of the invention conveniently, lucidly to aid in illustrating
The purpose of embodiment.Particularly, each accompanying drawing needs the emphasis shown different, often all employs different ratios.
Fig. 1 is refer to, it is the mount structure schematic diagram of the audio decoding system of the embodiment of the present invention.As shown in figure 1, shown
Audio decoding system 1 includes：First processor 10, second processor 11, interactive unit 12 and data buffer zone 13；Wherein, institute
State first processor 10 voice data to be decoded be sent into the second processor 11 by the data buffer zone 13
Row processing, and the first processor 10 controls the audio decoder of the second processor 11 by the interactive unit 12.
In the embodiment of the present application, audio decoding process is mainly controlled by the first processor 10；Pass through the second processor
11 processing voice data to be decoded, so as to realize that audio decoder improves decoding efficiency and system jointly by two processors
Real-time.Further, the first processor 10 controls audio decoding process, the control command by sending control command
Including playing, exiting, suspend, the order of the control audio decoder operation such as fast forward and fast reverse audio.In the embodiment of the present application, institute
First processor 10 is stated for RISC (Reduced Instruction Set Computing, Reduced Instruction Set Computer), it is described
Second processor 11 is DSP (Digital Signal Processing, Digital Signal Processing).
Specifically, the interactive unit 12 includes the first interactive unit 120 and the second interactive unit 121；Wherein, described
One interactive unit 120 is used to realize the interaction between the first processor 10 and the second processor 11；Described second hands over
Mutual unit 121 is used to store the memory address mappings that the second processor 11 is run.
In the embodiment of the present application, the first processor 10 is additionally operable to control the operation of the second processor 11.Tool
Body, the first processor 10 starts the second processor 11 according to the memory address mappings.Mainly include：Described
One processor 10 according to the memory address mappings by the firmware program of the second processor 11 with copying corresponding internal memory to
Location；The first processor 10 sets the state of the second processor 11 to start, and now the second processor 11 starts
Normal operation.In the embodiment of the present application, the operation of the second processor 11 is controlled by the first processor 10, thus may be used
Preferably to adapt to the system operation of different complexities.
In addition, the first processor 10 is additionally operable to reset the second processor 11.Specifically, when the second processing
When occurring fatal error in the running of device 11, the first processor 10 can be according to resetting the memory address mappings
Second processor 11, i.e., described first processor 10 restarts the second processor 11 according to the memory address mappings,
Thus avoid occur system delay machine the problem of, it is ensured that the reliability of system operation.
In the embodiment of the present application, the communication between the first processor 10 and the second processor 11 is by interrupting
Signal is controlled.Specifically, first interactive unit 120 includes interrupt control register, the interrupt control register is used for
Transmission signal, the first processor 10 and the second processor 11 are interacted by the interrupt signal.Enter one
Step, the interrupt control register is included in the first interrupt control register and the second interrupt control register, described first
The interrupt signal that disconnected control register is sent to the second processor 11 for transmitting the first processor 10 (transmits institute
State the interrupt signal of the generation of first processor 10), second interrupt control register is used to transmit the second processor 11
It is sent to the interrupt signal (transmitting the interrupt signal that the second processor 11 is produced) of the first processor 10.It is preferred that
, first interrupt control register and second interrupt control register are 32 interrupt control registers.
Further, first interactive unit 120 also includes mailbox registers, and the mailbox registers are posted including data
Storage and mutual exclusion lock, the data register are used to store the life that the first processor 10 and the second processor 11 are interacted
Order, the mutual exclusion lock is used to latch the data register.It is preferred that, the quantity of the data register is 32 groups, institute
The quantity for stating mutual exclusion lock is 32 groups, wherein, mutual exclusion lock described in data register described in 32 groups and 32 groups is one by one
Correspondence.In the embodiment of the present application, the data register is latched by the mutual exclusion lock, so as to prevent the first processor
10 and the second processor 11 simultaneously access same data register, it is to avoid occur data access conflict.
Specifically, when the first processor 10 sends control command, the first processor 10 inquires about mutual exclusion lock；Institute
State first processor 10 and obtain idle mutual exclusion lock, and by the idle mutual exclusion lock labeled as busy；The first processor 10
Control command is write into the corresponding data register of the mutual exclusion lock of acquisition；The first processor 10 is according to the mutual of the acquisition
Reprimand lock produces interrupt signal；The first processor 10 discharges the mutual exclusion lock of the acquisition.
When the second processor 11 receives control command, the second processor 11 receives interrupt signal；Described
Two processors 11 obtain mutual exclusion lock according to the interrupt signal；The second processor 11 reads correspondence according to the mutual exclusion lock of acquisition
Data register in control command；The second processor 11 writes commands in return into the data register；It is described
Second processor 11 sets interrupt signal；The mutual exclusion lock that the release of second processor 11 is obtained.
When the first processor 10 receives commands in return, the first processor 10 receives interrupt signal；Described
One processor 10 obtains mutual exclusion lock according to the interrupt signal；The first processor 10 reads correspondence according to the mutual exclusion lock of acquisition
Data box in commands in return；The mutual exclusion lock that the release of first processor 10 is obtained.
Further, the first processor 10 be sent to the second processor 11 order include DMA interrupt.At this
Apply in embodiment, the second processor 11 is DSP, and traditional DSP can not receive DMA interruptions, herein by described first
Reason device 10 sends DMA interruptions, so as to solve in the way of order after DMA interruptions are detected to the second processor 11
Traditional DSP can not receive the problem of DMA is interrupted.
Further, the first processor 10 to first interactive unit 120 by sending control command, described the
Two processors 11 receive control command from first interactive unit 120, so as to control the audio solution of the second processor 11
Code, the control command is including playing, exiting, suspending, fast forward and fast reverse.
In the embodiment of the present application, the data buffer zone 13 is used to deposit voice data and decoded sound to be decoded
Frequency evidence.Specifically, the data buffer zone includes input data buffering area 130 and data output buffer area 131, wherein, institute
Stating input data buffering area 130 is used to deposit voice data to be decoded, and the data output buffer area 131, which is used to deposit, have been solved
The voice data of code.Further, the data output buffer area 131 is additionally operable to deposit the audio letter of decoded voice data
Breath.The audio-frequency information specifically may include the information such as sound channel, sample rate or audio format, consequently facilitating the first processor
10 use when further handling decoded voice data.
In the embodiment of the present application, the input data buffering area carries out data write-in by the first write pointer, by the
One read pointer carries out digital independent；The data output buffer area carries out data write-in by the second write pointer, is read by second
Pointer carries out digital independent.I.e. the write-in of data is realized from the reading of data by different pointers, thereby may be ensured that described
The write-in of data and the reliability read, and can easily find out that the input data buffering area and the output data are slow
Rush the data volume stored in area.
Further, the second processor 11 it is also possible to use chain type dma mode and carry out the defeated of voice data to be decoded
Enter the output with decoded voice data.So that the second processor 11 has the input of more channels to be decoded
Voice data and the decoded voice data of output；Meanwhile, also with higher data input and output speed.
In the embodiment of the present application, the first processor 10 and/or the second processor 11 can be additionally used in having solved
The voice data of code carries out audio post processing.Wherein, the audio post processing includes carrying out one for decoded voice data
A little post processings for improving audio quality, for example, noise reduction, equilibrium etc..Further, the first processor 10 and/or described
Two processors 11 can also be used to carry out decoded voice data the processing of audio transcoding, recording processing and/or playback process；Institute
First processor 10 is stated to be additionally operable to decoded voice data writing peripheral hardware storage medium or sound-box device, it is follow-up to carry out
Preservation, broadcasting etc..
Accordingly, the present embodiment also provides a kind of audio-frequency decoding method.Specifically, Fig. 2 and Fig. 3 are refer to, wherein, Fig. 2
For the schematic flow sheet of the audio-frequency decoding method of the embodiment of the present invention, Fig. 3 is control in the audio-frequency decoding method of the embodiment of the present invention
The schematic flow sheet of command interaction processed.As shown in Figures 2 and 3, the audio-frequency decoding method includes：
Step one：Voice data to be decoded is sent to second processor by first processor 10 by data buffer zone 13
11 are handled；And
Step 2：The first processor 10 controls the audio decoder of the second processor 11 by interactive unit 12.
In the embodiment of the present application, between the step one and the step 2 order is simultaneously not construed as limiting, i.e. at first
Voice data to be decoded is sent to second processor 11 by data buffer zone 13 and handled and described first by reason device 10
Processor 10 controls the audio decoder of the second processor 11 to carry out simultaneously by interactive unit 12；Or first processor 10
Voice data to be decoded is sent into second processor 11 by data buffer zone 13 to be handled in the first processor
10 control to carry out before the audio decoder of the second processor 11 by interactive unit 12；Or first processor 10 will be waited to solve
The voice data of code is sent to second processor 11 and handled by data buffer zone 13 to be passed through in the first processor 10
Interactive unit 12 controls to carry out after the audio decoder of the second processor 11.
Specifically, the first processor 10 controls the audio decoder bag of the second processor 11 by interactive unit 12
Include：The first processor 10 sends control command to the interactive unit 12, and the first processor 10 is by sending control
Order control audio decoder；The second processor 11 receives control command from the interactive unit 12, and according to the control
Command process voice data to be decoded.In the embodiment of the present application, the first processor 10 and the second processor 11
Realized by interactive unit 12 before interacting and realizing jointly audio decoder, i.e., before above-mentioned steps two are performed, the audio
Coding/decoding method also includes：The first processor 10 is according to the interactive unit 12 (being second interactive unit 121 herein)
The memory address mappings that the second processor 11 of storage is run start the second processor 11.
Wherein, the first processor 10 sends control command to the interactive unit 12 and included：
The first processor 10 inquires about (interactive unit 12) mutual exclusion lock；
The first processor 10 obtains (described interactive unit 12) idle mutual exclusion lock, and by the idle mutual exclusion lock mark
It is designated as busy (mutual exclusion lock can be labeled as 1 herein)；
The first processor 10 writes control command into the corresponding data register of mutual exclusion lock of acquisition；
The first processor 10 produces interrupt signal according to the mutual exclusion lock of the acquisition and (is properly termed as the first interruption herein
Signal)；
The first processor 10 discharges the mutual exclusion lock (mutual exclusion lock can be labeled as into 0 herein) of the acquisition.
Further, the second processor 11 receives control command from the interactive unit 12, and according to the control
Command process voice data to be decoded includes：
The second processor 11 receives interrupt signal (receiving the first interrupt signal herein)；
The second processor 11 obtains mutual exclusion lock according to the interrupt signal (being the first interrupt signal herein) and (herein may be used
By the mutual exclusion lock labeled as 1)；
The second processor 11 reads the control command in corresponding data register according to the mutual exclusion lock of acquisition；
The second processor 11 writes commands in return into the data register；
The second processor 11 sets interrupt signal (being properly termed as the second interrupt signal herein)；
The mutual exclusion lock (mutual exclusion lock can be labeled as 0 herein) that the release of second processor 11 is obtained.
Accordingly, the control that the second processor 11 is read according to the mutual exclusion lock of acquisition in corresponding data register is ordered
After order, the second processor 11 receives control command from the interactive unit 12, and is treated according to control command processing
The voice data of decoding also includes：The second processor 11 reads the voice data to be decoded of input data buffering area；Institute
State the voice data to be decoded that the decoding of second processor 11 is read；The second processor 11 writes to data output buffer area
Decoded voice data.Further, the second processor 11 also writes decoded audio to data output buffer area
The audio-frequency information of data.Wherein, the second processor 11, which have read, updates the first read pointer after voice data to be decoded
Aud_rdptr, the second processor 11 updates second after writing decoded voice data to data output buffer area
Write pointer pcm_wrptr.
In the other embodiment of the application, the second processor 11 reads corresponding data according to the mutual exclusion lock of acquisition
After control command in register, the second processor 11 receives control command from the interactive unit 12, and according to institute
Control command processing voice data to be decoded is stated to may also include：The second processor 11 is treated using chain type dma mode
The input of the voice data of decoding；The voice data to be decoded of the decoding of second processor 11 input；The second processing
Device 11 carries out the output of decoded voice data using chain type dma mode.I.e. described second processor 11 can also be by other
Mode carries out the input of voice data to be decoded and the output of decoded voice data.
Further, the second processor 11 receives control command from the interactive unit 12, and according to the control
After command process voice data to be decoded, the first processor 10 controls the second processor by interactive unit 12
11 audio decoder also includes：The first processor 10 receives commands in return from the interactive unit 12.First processing
Device 10 receives commands in return from the interactive unit 12 to be included：
The first processor 10 receives interrupt signal (i.e. the second interrupt signal)；
The first processor 10 obtains mutual exclusion lock according to the interrupt signal；
The first processor 10 reads the commands in return in corresponding data register according to the mutual exclusion lock of acquisition；
The mutual exclusion lock that the release of first processor 10 is obtained.
The first processor 10 is received from the interactive unit 12 after commands in return, and the audio-frequency decoding method is also wrapped
Include：The first processor 10 reads the decoded voice data in data output buffer area.Wherein, the first processor 10
The second read pointer pcm_rdptr is updated after the decoded voice data for reading data output buffer area.
In the embodiment of the present application, the first processor 10 reads the decoded voice data in data output buffer area
Afterwards, the audio-frequency decoding method may also include：The first processor 10 and/or the second processor 11 are to decoded
Voice data carries out audio post processing, the processing of audio transcoding, recording processing and/or playback process；Or the first processor
Decoded voice data is write peripheral hardware storage medium etc. by 10.
As fully visible, in audio decoding system provided in an embodiment of the present invention and audio-frequency decoding method, first processor
Voice data to be decoded is sent into second processor by data buffer zone to be handled, and the first processor is logical
The audio decoder that the interactive unit controls the second processor is crossed, realizes that audio decoder is lifted jointly by two processors
Decoding efficiency and system real time；Interaction between two processors is realized by interactive unit, it is real by data buffer zone
The transmission of existing voice data to be decoded, it is ensured that two processors realize the reliability of audio decoder jointly.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Scope.
Claims (34)
1. a kind of audio decoding system, it is characterised in that the audio decoding system includes：First processor, second processor,
Interactive unit and data buffer zone；Wherein,
Voice data to be decoded is sent to the second processor by the data buffer zone and entered by the first processor
Row processing, and the first processor controls the audio decoder of the second processor by the interactive unit.
2. audio decoding system as claimed in claim 1, it is characterised in that the interactive unit include the first interactive unit and
Second interactive unit；Wherein, first interactive unit is used to realize between the first processor and the second processor
Interaction；Second interactive unit is used for the memory address mappings for storing the second processor operation.
3. audio decoding system as claimed in claim 2, it is characterised in that the first processor is interacted by described second
The memory address mappings of unit storage start the second processor.
4. audio decoding system as claimed in claim 2, it is characterised in that the first processor is additionally operable to reset described the
Two processors.
5. audio decoding system as claimed in claim 2, it is characterised in that first interactive unit includes interruption control and posted
Storage, the interrupt control register is used for Transmission signal, and the first processor and the second processor pass through institute
Interrupt signal is stated to interact.
6. audio decoding system as claimed in claim 5, it is characterised in that the interrupt control register, which includes first, to interrupt
Control register and the second interrupt control register, first interrupt control register are used to transmit the first processor hair
The interrupt signal of the second processor is given, second interrupt control register is used to transmit the second processor transmission
Interrupt signal to the first processor.
7. audio decoding system as claimed in claim 6, it is characterised in that first interrupt control register and described
Two interrupt control registers are 32 interrupt control registers.
8. audio decoding system as claimed in claim 5, it is characterised in that first interactive unit also includes mailbox and deposited
Device, the mailbox registers include data register and mutual exclusion lock, and the data register is used to store the first processor
The order interacted with the second processor, the mutual exclusion lock is used to latch the data register.
9. audio decoding system as claimed in claim 8, it is characterised in that the mutual exclusion lock is used to latch the data register
Device includes：When the first processor sends control command, the first processor inquires about mutual exclusion lock；The first processor
Idle mutual exclusion lock is obtained, and by the idle mutual exclusion lock labeled as busy；Mutual exclusion lock pair from the first processor to acquisition
Control command is write in the data register answered；The first processor produces interrupt signal according to the mutual exclusion lock of the acquisition；
The first processor discharges the mutual exclusion lock of the acquisition.
10. audio decoding system as claimed in claim 9, it is characterised in that the mutual exclusion lock is posted for latching the data
Storage also includes：When the second processor receives control command, the second processor receives interrupt signal；Described second
Processor obtains mutual exclusion lock according to the interrupt signal；The second processor reads corresponding data according to the mutual exclusion lock of acquisition
Control command in register；The second processor writes commands in return into the data register；The second processing
Device sets interrupt signal；The mutual exclusion lock that the second processor release is obtained.
11. audio decoding system as claimed in claim 10, it is characterised in that the mutual exclusion lock is posted for latching the data
Storage also includes：When the first processor receives commands in return, the first processor receives interrupt signal；Described first
Processor obtains mutual exclusion lock according to the interrupt signal；The first processor reads corresponding data according to the mutual exclusion lock of acquisition
Commands in return in case；The mutual exclusion lock that the first processor release is obtained.
12. audio decoding system as claimed in claim 8, it is characterised in that the quantity of the data register is 32
Group, the quantity of the mutual exclusion lock is 32 groups, wherein, mutual exclusion lock described in data register described in 32 groups and 32 groups
Correspond.
13. audio decoding system as claimed in claim 8, it is characterised in that the first processor is sent to described second
The order of processor is interrupted including DMA.
14. audio decoding system as claimed in claim 8, it is characterised in that the first processor is by sending control life
The audio decoder of the order control second processor, the control command is including playing, exiting, suspending, fast forward and fast reverse.
15. audio decoding system as claimed in claim 1, it is characterised in that the data buffer zone is used to deposit to be decoded
Voice data and decoded voice data.
16. audio decoding system as claimed in claim 15, it is characterised in that the data buffer zone is slow including input data
Area and data output buffer area are rushed, wherein, the input data buffering area is used to deposit voice data to be decoded, the output
Data buffer zone is used for the audio-frequency information for depositing decoded voice data and decoded voice data.
17. audio decoding system as claimed in claim 16, it is characterised in that the input data buffering area is write by first
Pointer carries out data write-in, and digital independent is carried out by the first read pointer；The data output buffer area passes through the second write pointer
Data write-in is carried out, digital independent is carried out by the second read pointer.
18. audio decoding system as claimed in claim 1, it is characterised in that the second processor uses chain type dma mode
Carry out the input of voice data to be decoded and the output of decoded voice data.
19. audio decoding system as claimed in claim 1, it is characterised in that at the first processor and/or described second
Reason device is additionally operable to carry out decoded voice data at audio post processing, the processing of audio transcoding, recording processing and/or broadcasting
Reason.
20. audio decoding system as claimed in claim 1, it is characterised in that the first processor is additionally operable to have decoded
Voice data write-in peripheral hardware storage medium.
21. the audio decoding system as any one of claim 1~20, it is characterised in that the first processor is
RISC, the second processor is DSP.
22. a kind of audio-frequency decoding method, it is characterised in that the audio-frequency decoding method includes：First processor will be to be decoded
Voice data is sent to second processor by data buffer zone and handled；And the first processor passes through interactive unit control
Make the audio decoder of the second processor.
23. audio-frequency decoding method as claimed in claim 22, it is characterised in that first processor is by voice data to be decoded
It is sent to that second processor is handled and the first processor by interactive unit controls described by data buffer zone
The audio decoder of two processors is carried out simultaneously；Or first processor transmits voice data to be decoded by data buffer zone
The audio decoder for controlling the second processor by interactive unit in the first processor is handled to second processor
Carry out before；Or voice data to be decoded is sent at second processor by first processor by data buffer zone
Reason is carried out after the first processor controls the audio decoder of the second processor by interactive unit.
24. audio-frequency decoding method as claimed in claim 23, it is characterised in that the first processor passes through interactive unit control
Making the audio decoder of the second processor includes：
The first processor sends control command to the interactive unit, and the first processor is by sending control command control
Audio decoder processed；
The second processor receives control command from the interactive unit, and according to control command processing sound to be decoded
Frequency evidence.
25. audio-frequency decoding method as claimed in claim 24, it is characterised in that the first processor is to the interactive unit
Sending control command includes：
The first processor inquires about mutual exclusion lock；
The first processor obtains idle mutual exclusion lock, and by the idle mutual exclusion lock labeled as busy；
The first processor writes control command into the corresponding data register of mutual exclusion lock of acquisition；
The first processor produces interrupt signal according to the mutual exclusion lock of the acquisition；
The first processor discharges the mutual exclusion lock of the acquisition.
26. audio-frequency decoding method as claimed in claim 25, it is characterised in that the second processor is from the interactive unit
Receiving control command, and handle voice data to be decoded according to the control command includes：
The second processor receives interrupt signal；
The second processor obtains mutual exclusion lock according to the interrupt signal；
The second processor reads the control command in corresponding data register according to the mutual exclusion lock of acquisition；
The second processor writes commands in return into the data register；
The second processor sets interrupt signal；
The mutual exclusion lock that the second processor release is obtained.
27. audio-frequency decoding method as claimed in claim 26, it is characterised in that the second processor is according to the mutual exclusion of acquisition
Lock is read after the control command in corresponding data register, and the second processor receives control life from the interactive unit
Order, and also included according to control command processing voice data to be decoded：
The second processor reads the voice data to be decoded of input data buffering area；
The voice data to be decoded that the second processor decoding is read；
The second processor writes the sound of decoded voice data and decoded voice data to data output buffer area
Frequency information.
28. audio-frequency decoding method as claimed in claim 26, it is characterised in that the second processor is according to the mutual exclusion of acquisition
Lock is read after the control command in corresponding data register, and the second processor receives control life from the interactive unit
Order, and also included according to control command processing voice data to be decoded：
The second processor carries out the input of voice data to be decoded using chain type dma mode；
The voice data to be decoded of the second processor decoding input；
The second processor carries out the output of decoded voice data using chain type dma mode.
29. audio-frequency decoding method as claimed in claim 27, it is characterised in that the second processor is from the interactive unit
Receive control command, and after handling voice data to be decoded according to the control command, the first processor, which passes through, to be handed over
Mutual unit controls the audio decoder of the second processor also to include：
The first processor receives commands in return from the interactive unit.
30. audio-frequency decoding method as claimed in claim 29, it is characterised in that the first processor is from the interactive unit
Receiving commands in return includes：
The first processor receives interrupt signal；
The first processor obtains mutual exclusion lock according to the interrupt signal；
The first processor reads the commands in return in corresponding data register according to the mutual exclusion lock of acquisition；
The mutual exclusion lock that the first processor release is obtained.
31. audio-frequency decoding method as claimed in claim 30, it is characterised in that the first processor is from the interactive unit
Receive after commands in return, the audio-frequency decoding method also includes：
The first processor reads the decoded voice data in data output buffer area.
32. audio-frequency decoding method as claimed in claim 31, it is characterised in that the first processor reads output data and delayed
After the decoded voice data for rushing area, the audio-frequency decoding method also includes：
The first processor and/or the second processor carry out audio post processing, audio conversion to decoded voice data
Code processing, recording processing and/or playback process.
33. audio-frequency decoding method as claimed in claim 31, it is characterised in that the first processor reads output data and delayed
After the decoded voice data for rushing area, the audio-frequency decoding method also includes：
Decoded voice data is write peripheral hardware storage medium by the first processor.
34. the audio-frequency decoding method as any one of claim 22~33, it is characterised in that in the first processor
Before the audio decoder that the second processor is controlled by interactive unit, the audio-frequency decoding method also includes：
The memory address mappings that the first processor is stored by the second interactive unit start the second processor.
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