CN107291660A - A kind of device for realizing Fast Fourier Transform (FFT) - Google Patents
A kind of device for realizing Fast Fourier Transform (FFT) Download PDFInfo
- Publication number
- CN107291660A CN107291660A CN201710453249.1A CN201710453249A CN107291660A CN 107291660 A CN107291660 A CN 107291660A CN 201710453249 A CN201710453249 A CN 201710453249A CN 107291660 A CN107291660 A CN 107291660A
- Authority
- CN
- China
- Prior art keywords
- dish
- shaped
- address
- module
- computing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
- G06F17/141—Discrete Fourier transforms
- G06F17/142—Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Data Mining & Analysis (AREA)
- Theoretical Computer Science (AREA)
- Discrete Mathematics (AREA)
- Algebra (AREA)
- Databases & Information Systems (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
Abstract
The invention provides a kind of device for realizing Fast Fourier Transform (FFT), including：Logarithm variator, data input/output register, dish-shaped engine, control module, twiddle factor module, calculating address module and antilogarithm variator, logarithm variator connects data input/output register, the dish-shaped engine of data input/output register connection, dish-shaped engine difference link control module, twiddle factor module, calculating address module, antilogarithm variator connection data input/output register.By the above-mentioned means, resource overhead can be effectively reduced, arithmetic speed is improved, multiplier is also saved.
Description
Technical field
The present invention relates to digital signal processing technique field, more particularly to a kind of device for realizing Fast Fourier Transform (FFT).
Background technology
Fast Fourier Transform (FFT) FFT is a kind of discrete Fourier transform DFT fast algorithm, and it is one and utilizes computing
Periodically, the data of time domain can be transformed to frequency domain by reducing operand, usual FFT, and same reason IFFT can be by frequency domain
Data variation be applied to time domain, so for communication, medical treatment, aviation etc. and obtained extensive utilization, the FFT formula of standard
It is the process that iterates of a data.
Wherein,
The operand of positive anti-change is all identical, and data are all sequence of complex numbers, calculates X (k) value, it is necessary to which n times are multiple
Number multiplication and N-1 complex addition, X (k) has N number of point, described to need N*N complex multiplication and N* (N-1) addition altogether.Plural number
Computing is really what is completed with real arithmetic, can be derived：
It is considered that once-through operation is exactly once dish-shaped computing, wherein once dish-shaped computing is 4 multiplication and 3 sub-additions.
It can be seen that, conventional FFT computings need substantial amounts of memory, multiplier and add (subtracting) musical instruments used in a Buddhist or Taoist mass, more digits and point
Number more operation time and resource overhead.
If in order to increase precision or increase points, it is necessary to increase by 2NTable look-up device (N be data bits width).Such as
Single precision will 232Depth of tabling look-up, its resource overhead is very big, if using 4 ground dish (reducing operation time) fortune
Calculate, then also need to corresponding 2 times of resources of tabling look-up, in the FPGA that resource is nervous, either the plug-in DDR modules of DSP or ARM etc. be all
Need the substantial amounts of RAM of resource.
Therefore, there is the big technical problem of resource overhead in the existing device for realizing Fast Fourier Transform (FFT).
The content of the invention
The invention provides a kind of device for realizing Fast Fourier Transform (FFT), it can be solved while processing speed is not influenceed
Certainly the problem of resource occupation.
In order to solve the above technical problems, one aspect of the present invention is：One kind is provided and realizes fast Fourier
The device of conversion, including：Logarithm variator, data input/output register, dish-shaped engine, control module, twiddle factor module,
Calculate address module and antilogarithm variator；
Logarithm variator is used to becoming pending data into the logarithm numeric field data for turning to plural number by tabling look-up；
Data input/output register is used to store the logarithm numeric field data and content of tabling look-up of plural number；
Control module is used to, according to temporal decimation order or frequency domain extraction order, send address instruction to calculating address mould
Block；
Calculate address module be used for according to the address instruction calculate currently with plural number log-domain data address and rotation
Factor address；
Dish-shaped engine is used for according to the plural log-domain data address and twiddle factor address provided to calculating address, from
Data input/output register search corresponding plural logarithm numeric field data with from the corresponding rotation of twiddle factor module searches because
Son, and the plural logarithmic data and twiddle factor are subjected to dish-shaped computing, the dish-shaped computing include 3 table lookup operations and
4 add operations；
The operation result that antilogarithm variator is used to complete dish-shaped engine after the dish-shaped computing of preset times passes through change of tabling look-up
Conventional complex field is changed to, the computing of Fast Fourier Transform (FFT) is completed..
Preferably, the control module is additionally operable to calculate the number of times of dish-shaped computing, if the number of times of dish-shaped computing be not up to it is pre-
If complete number of times, again according to temporal decimation order or frequency domain extraction order, address instruction is sent to address module is calculated, is made
Obtain dish-shaped engine and proceed dish-shaped computing.
Preferably, input/output register is additionally operable to after dish-shaped engine completes every time dish-shaped computing, stores each dish
The result that shape computing is completed.
Preferably, the length of the data input/output register is equal to the length of pending data.
The situation of prior art is different from, the beneficial effects of the invention are as follows：
Due to increasing logarithmic converter and antilogarithm on the basis of original device for realizing standard Fast Fourier Transform (FFT)
Pending data are changed into logarithm numeric field data by variator by plural number, when then by the computing of dish-shaped engine, can be by original
Have multiplying in computing and plus (subtracting) method computing be converted into simple plus the computing of (subtracting) method and table lookup operations, therefore, effectively
Resource overhead is reduced, arithmetic speed is improved, multiplier is saved.
Brief description of the drawings
Fig. 1 is the module diagram for the device that Fast Fourier Transform (FFT) is realized in the embodiment of the present invention；
Fig. 2 is log algorithm exporting change curve synoptic diagrams in the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
The embodiments of the invention provide a kind of device for realizing Fast Fourier Transform (FFT), as shown in figure 1, including logarithm change
Device 10, data input/output register 20, dish-shaped engine 30, control module 40, twiddle factor module 50, calculating address module 60
And antilogarithm variator 70.
Specifically, the connection of logarithm variator 10 data input/output register 20, the data input/output register 20 connects
Dish-shaped engine 30 is connect, the dish-shaped difference of engine 30 link control module 40, twiddle factor module 50, calculating address module 60 are opposed
The number connection data input/output register of variator 70.
In a particular embodiment, the logarithm variator 10 is used to pending data being transformed to plural number by tabling look-up
Logarithm numeric field data, the data input/output register 20 is used to store the logarithm numeric field data and content of tabling look-up of plural number,
Wherein, the length of the data input/output register 20 is corresponding with the length of pending device data.The control module 40 is used to press
According to temporal decimation or frequency domain extraction order, address instruction is sent to address module 60 is calculated, calculating address module 60 is used for basis
Address instruction calculates log-domain data address and twiddle factor address currently with plural number, and dish-shaped engine 30 is used for according to calculating
Plural log-domain data address and twiddle factor address that address module 60 is provided, are searched from data input/output register 20
Corresponding plural logarithm numeric field data and search corresponding twiddle factor from twiddle factor module 50, and by the log-domain number of plural number
Dish-shaped computing is carried out according to twiddle factor, the dish-shaped computing includes 3 table lookup operations and 4 add operations, finally, and antilogarithm becomes
The operation result that changing device 70 is used to complete dish-shaped engine after the dish-shaped computing of preset times is transformed to conventional complex field by tabling look-up,
Complete the computing of Fast Fourier Transform (FFT).
Specifically, pending data are mapped on the log-domain of plural number first, i.e.,：
Wherein,
Processing procedure so in dish-shaped engine 30 is just changed into tabling look-up and adds and (subtract) method to operate：
Wherein,It is a table lookup operation, LNS is the abbreviation of log-domain.
Therefore, it can obtain every time dish-shaped computing is 3 table lookup operations and 4 add operations, instead of original multiplication
Operation and add operation.Due to not using the multiplier of multiplication operation, therefore, resource overhead is reduced.
Wherein, the control module 40 calculates the number of times of the dish-shaped computing in the dish-shaped calculating process of engine 30, if dish fortune
When the number of times of calculation is not up to default completion number of times, again according to temporal decimation order or frequency domain extraction order, address instruction is sent
To calculating address module 60 so that dish-shaped engine 30 proceeds dish-shaped computing.Until the number of times of dish-shaped computing reach it is default complete
Into number of times.
The input/output register 20 is additionally operable to after dish-shaped engine 30 completes every time dish-shaped computing, and storage is dish-shaped every time
The result that computing is completed, is easy to output.
By using above-mentioned technical scheme, the computing done in dish-shaped engine 30 does not include the computing for having multiplier,
Only exist plus (subtracting) method computing, so, effectively reduce resource overhead, improve arithmetic speed, save multiplier.
In order to increase precision or increase points, it is necessary to increase by 2NTable look-up device (N be data bits width), such as single essence
Degree will 232Table look-up device depth, its resource overhead is very big, if using 4 dish-shaped engines (reduction computing) to carry out
Computing, then need corresponding 2 times of table look-up device resources, in the FPGA that resource is nervous, either the plug-in DDR modules of DSP or ARM etc.
It is required for the substantial amounts of RAM of resource.
" broken line algorithm " is used in the application, the storage resource expense of logarithm table look-up device is reduced, precision can not be influenceed
In the case of, the substantial amounts of resource for declining table look-up device is used on logarithm variator and antilogarithm variator, and the output of log algorithms becomes
Change makes to be that data precision change is not linear change, but a curvilinear motion, and data are bigger, and the change of log precision is smaller.
As shown in Figure 2, after Y-axis and X-axis become big, the change of Y-axis is not obvious enough, can be reduced from the algorithm corresponding
Digit changes so that broken line look-up table optimizes logarithmic table and antilogarithm table, it be not it is simple correspond into line translation but
Line translation, symbol invariant position, numerical part are entered by following formula：
Wherein A is a constant, and its modulation is changed by the change of data bit width, can be determined in emulation, typically
Situation can select the change that 3-8, u are data, it can be seen that LANumber of significant digit can be significantly smaller than 32bit and (be directed to 32
Single precision), if double precision saving resource is more.
For the logFFT modules of 16bit input, realized in FPGA system, following table be traditional FFT with it is new
The comparison of LOG-FFT resource occupation and processing speed：
As can be seen from the above table, the amended logFF of this algorithm is approximate to the demand of resource also more traditional FFT, still
Arithmetic speed is improved, multiplier is saved, while having avoided logFFT substantial amounts of RAM resource overheads.
The environment at full stretch with resource, a typical FPGA application environment, while greatly can be utilized using this algorithm
LogFFT execution cycle is improved greatly, and reduces RAM expenses and a slices (FPGA standard block, for difference
Device model be possible to be made up of 4-16 table look-up device).Comparatively FPGA slices expenses are small with the FFT of standard, and often
The logFFT of rule comparatively saves RAM, simultaneously as without multiplier, overall arithmetic speed improves 10%-30%
(being directed to different components).
By the above-mentioned means, the device for realizing Fast Fourier Transform (FFT) of the embodiment of the present invention, can effectively reduce resource
Expense, improves arithmetic speed.
Embodiments of the invention are the foregoing is only, are not intended to limit the scope of the invention, it is every to utilize this hair
Equivalent structure or equivalent flow conversion that bright specification and accompanying drawing content are made, or directly or indirectly it is used in other related skills
Art field, is included within the scope of the present invention.
Claims (4)
1. a kind of device for realizing Fast Fourier Transform (FFT), it is characterised in that including：Logarithm variator, data input output are posted
Storage, dish-shaped engine, control module, twiddle factor module, calculating address module and antilogarithm variator, logarithm variator connect
Connect data input/output register, the dish-shaped engine of data input/output register connection, dish-shaped engine difference link control module,
Twiddle factor module, calculating address module, antilogarithm variator connection data input/output register；
Logarithm variator is used to becoming pending data into the logarithm numeric field data for turning to plural number by tabling look-up；
Data input/output register is used to store the logarithm numeric field data and content of tabling look-up of plural number；
Control module is used to, according to temporal decimation order or frequency domain extraction order, send address instruction to calculating address module；
Calculating address module is used for the log-domain data address and twiddle factor according to address instruction calculating currently with plural number
Address；
Dish-shaped engine is used for according to calculating plural log-domain data address and the twiddle factor address that address is provided, from data
Input/output register search corresponding plural logarithm numeric field data with from the corresponding twiddle factor of twiddle factor module searches, and
The plural logarithm numeric field data and twiddle factor are subjected to dish-shaped computing, the dish-shaped computing includes 3 table lookup operations and 4
Add operation；
The operation result that antilogarithm variator is used to complete dish-shaped engine after the dish-shaped computing of preset times is transformed to by tabling look-up
Conventional complex field, completes the computing of Fast Fourier Transform (FFT).
2. the device according to claim 1 for realizing Fast Fourier Transform (FFT), it is characterised in that the control module is also used
It is again suitable according to temporal decimation if the number of times of dish-shaped computing is not up to default completion number of times in the number of times for calculating dish-shaped computing
Sequence or frequency domain extraction order, send address instruction to calculating address module so that dish-shaped engine proceeds dish-shaped computing.
3. the device according to claim 1 for realizing Fast Fourier Transform (FFT), it is characterised in that the input and output deposit
Device is additionally operable to after dish-shaped engine completes every time dish-shaped computing, the storage result that dish-shaped computing is completed every time.
4. the device according to claim 1 for realizing Fast Fourier Transform (FFT), it is characterised in that the data input output
The length of register is equal to the length of pending data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710453249.1A CN107291660A (en) | 2017-06-15 | 2017-06-15 | A kind of device for realizing Fast Fourier Transform (FFT) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710453249.1A CN107291660A (en) | 2017-06-15 | 2017-06-15 | A kind of device for realizing Fast Fourier Transform (FFT) |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107291660A true CN107291660A (en) | 2017-10-24 |
Family
ID=60096271
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710453249.1A Pending CN107291660A (en) | 2017-06-15 | 2017-06-15 | A kind of device for realizing Fast Fourier Transform (FFT) |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107291660A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS603789A (en) * | 1983-06-21 | 1985-01-10 | Victor Co Of Japan Ltd | Operating device of fast fourier transform |
| CN101551790A (en) * | 2008-04-03 | 2009-10-07 | 中兴通讯股份有限公司 | Realizing method and device of fast Fourier transform |
| CN103970718A (en) * | 2014-05-26 | 2014-08-06 | 苏州威士达信息科技有限公司 | Quick Fourier transformation implementation device and method |
-
2017
- 2017-06-15 CN CN201710453249.1A patent/CN107291660A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS603789A (en) * | 1983-06-21 | 1985-01-10 | Victor Co Of Japan Ltd | Operating device of fast fourier transform |
| CN101551790A (en) * | 2008-04-03 | 2009-10-07 | 中兴通讯股份有限公司 | Realizing method and device of fast Fourier transform |
| CN103970718A (en) * | 2014-05-26 | 2014-08-06 | 苏州威士达信息科技有限公司 | Quick Fourier transformation implementation device and method |
Non-Patent Citations (2)
| Title |
|---|
| 杨军 等: "一种高速实时浮点蝶形运算单元的设计与实现", 《仪器仪表学报》 * |
| 牟胜梅: "面向可重构系统的几个常用算法及其实现技术研究", 《中国博士学位论文全文数据库信息科技辑》 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103970718B (en) | Device and method is realized in a kind of fast Fourier transform | |
| CN105468335A (en) | Pipeline-level operation device, data processing method and network-on-chip chip | |
| CN106484658A (en) | The device and method of 65536 points of pulse compressions is realized based on FPGA | |
| CN109739470A (en) | A kind of computing system based on 2 type hyperbolic CORDIC arbitrary characteristics functions | |
| CN112231626A (en) | FFT processor | |
| CN101894096A (en) | FFT computing circuit structure applied to CMMB and DVB-H/T | |
| Tang et al. | CORDIC-based FFT real-time processing design and FPGA implementation | |
| CN114996638A (en) | Configurable fast Fourier transform circuit with sequential architecture | |
| CN114186183B (en) | Light FFT operation method and implementation device thereof | |
| Revanna et al. | A scalable FFT processor architecture for OFDM based communication systems | |
| CN102567254B (en) | The method that adopts dma controller to carry out data normalization processing | |
| CN104657334B (en) | A kind of base 2-4-8 mixed base butterfly of fast Fourier variation calculates device and its application | |
| CN109614073A (en) | Four-quadrant arctan function hardware circuit implementation | |
| CN102364456A (en) | 64-point fast Fourier transform (FFT) calculator | |
| CN112559954B (en) | FFT algorithm processing method and device based on software-defined reconfigurable processor | |
| CN106814990A (en) | The optimization method of cordic algorithm | |
| CN107291660A (en) | A kind of device for realizing Fast Fourier Transform (FFT) | |
| Kavitha et al. | An efficient FPGA architecture for reconfigurable FFT processor incorporating an integration of an improved CORDIC and Radix-2 r Algorithm | |
| CN110096672A (en) | Inexpensive pipeline-type fft processor implementation method based on FPGA | |
| US20220051354A1 (en) | Electric energy meter and metering device thereof | |
| Bansal et al. | Memory-efficient Radix-2 FFT processor using CORDIC algorithm | |
| CN112364589A (en) | Novel improved butterfly unit algorithm structure for FFT processor chip design | |
| CN108319804B (en) | 8192 point base 2 DIT ASIC design method for low resource call | |
| Ramesha et al. | A novel Architecture of FBMC Transmitter using Poly phase Filtering and its FPGA implementation | |
| CN109408027A (en) | Method and device based on the quick gauge index function of FPGA hardware equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20171024 |
|
| RJ01 | Rejection of invention patent application after publication |