CN112364589A - Novel improved butterfly unit algorithm structure for FFT processor chip design - Google Patents

Novel improved butterfly unit algorithm structure for FFT processor chip design Download PDF

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CN112364589A
CN112364589A CN202011251828.6A CN202011251828A CN112364589A CN 112364589 A CN112364589 A CN 112364589A CN 202011251828 A CN202011251828 A CN 202011251828A CN 112364589 A CN112364589 A CN 112364589A
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fft processor
butterfly unit
fft
processor chip
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于建
范浩阳
姚宇凤
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Hebei Normal University for Nationalities
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Abstract

The invention discloses a novel improved butterfly unit algorithm structure for designing an FFT (fast Fourier transform) processor chip, which comprises a module twiddle factor
Figure DDA0002771831390000011
And control logic r, adding specific module twiddle factor based on the original butterfly unit frame
Figure DDA0002771831390000012
And additional control logic "r" form a new improved butterfly unit architecture model, using popular radix-2 in the design of FFT processor chipkAlgorithms and SDF pipeline architecture. The novel improved butterfly unit algorithm structure for designing the FFT processor chip focuses on the improvement of the butterfly unit which forms the basic unit of the FFT processor, and reduces the FFT position by simplifying the complexity of the subsequent twiddle factorsHardware overhead and power consumption of the processor provide a new idea for designing the FFT processor with low power consumption and low hardware overhead under the background of a new information era, and have important theoretical significance and engineering application value.

Description

Novel improved butterfly unit algorithm structure for FFT processor chip design
Technical Field
The invention relates to the technical field of FFT (fast Fourier transform) processors, in particular to a novel improved butterfly unit algorithm structure for designing an FFT processor chip.
Background
The FFT processor is widely applied to the fields of spectrum analysis, image processing, voice recognition, biomedicine, radar, filtering, wireless and wired communication and the like. With the advent of the 5G era, various new services and application scenarios, such as car networking, virtual reality, online games, machine type communication, internet of things, and the like, are continuously emerging, and in response to the demands of the 5G era on the new services, new multi-carrier transmission technologies, such as filter bank multi-carrier, generalized frequency division multiplexing, general filtering multi-carrier, and the like, are developed. The FFT processor is the most important module in the multi-carrier transmission system, and the hardware cost and power consumption of the FFT processor affect the performance of the whole multi-carrier transmission system, so it is very important for the optimization design of the FFT processor.
In the past, the optimization design of the FFT processor is mostly optimized on an algorithm and an overall framework, and the research on the algorithm and the overall framework at present tends to be mature and is difficult to break through. Therefore, we propose a new and improved butterfly unit algorithm structure for FFT processor chip design.
Disclosure of Invention
The present invention provides a new and improved butterfly unit algorithm structure for designing FFT processor chip, so as to solve the problem of condition limitation existing in the current optimization design of FFT processor proposed by the above background art.
In order to achieve the purpose, the invention provides the following technical scheme:
novel improved butterfly unit algorithm structure for FFT processor chip design, including module twiddle factor
Figure BDA0002771831370000021
And control logic r, adding specific module twiddle factor based on the original butterfly unit frame
Figure BDA0002771831370000022
And additional control logic "r" formationA novel improved butterfly unit architecture model, using popular radix-2 in the design of FFT processor chipkAlgorithms and SDF pipeline architecture.
Preferably, the module twiddle factor
Figure BDA0002771831370000023
Is calculated by the formula
Figure BDA0002771831370000024
Wherein
Figure BDA0002771831370000025
N in (b) is determined according to the number of points of the designed FFT processor.
Preferably, the control logic "r" is used to control the input sequence to perform complex multiplication with W, "N" is the number of FFT points, "t" and "x" are basic butterfly operation control signals, and perform multiplication by "-j" and whether or not to perform butterfly operation, respectively, and in order to reduce the critical path, a pipeline register is added between the W complex multiplication module and the selector.
Preferably, for group-2kFor FFT processor with SDF pipeline structure, the control logic "r" of the new improved butterfly unit can pass through the formula
Figure BDA0002771831370000026
Find, where "C" represents the control clock of the FFT processor,
Figure BDA0002771831370000027
represents an exclusive-OR logic operation, ". represents an AND logic operation," k "represents a base-2kThe k value of the algorithm, "n" represents the highest bit value of the clock.
Preferably, the module twiddle factor
Figure BDA0002771831370000028
The values of (a) are repeated regularly.
Compared with the prior art, the invention has the beneficial effects that:
1. hardware resource consumption during design of the FFT processor is reduced;
2. simplifying the control logic for realizing the complex multiplication multiplier of the FFT processor;
3. for the design of FFT processor with the point number not exceeding 1024, CSD constant multiplier can be used for replacing the traditional complex multiplier, thereby achieving the purpose of minimizing the consumption of hardware resources.
In summary, the novel improved butterfly unit algorithm structure for designing the FFT processor chip provided by the invention focuses on the improvement of the butterfly unit which is the basic unit of the FFT processor, reduces the hardware overhead and power consumption of the FFT processor by simplifying the complexity of the subsequent twiddle factors, provides a new idea for designing the FFT processor with low power consumption and low hardware overhead in the context of a new information era, and has important theoretical significance and engineering application value.
Drawings
Fig. 1 is a schematic diagram of an original butterfly unit architecture (a), I-type butterfly unit (b), and II-type butterfly unit.
Fig. 2 is a schematic diagram of the new and improved butterfly unit architecture of the present invention (a), I-type improved butterfly unit (b), II-type improved butterfly unit.
FIG. 3 is a modified 64-point base-2 of the present invention5Algorithm SDFFFT pipeline architecture schematic.
FIG. 4 shows a 64-point radix-2 based on a new and improved butterfly unit of the present invention5And (4) an algorithm signal flow diagram.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiment is only one mechanical embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1-4, the present invention provides a technical solution: a novel improved butterfly unit algorithm structure for FFT processor chip design:
as shown in FIG. 1, for the original butterfly unit architecture, (a) is type I, (b) is type II, where xr (N) and xr (N + N/2) are real parts of the input complex sequence, xi (N) and xi (N + N/2) are imaginary parts of the input complex sequence, zr (N) and zr (N + N/2) are real parts of the output complex sequence, zi (N) and zi (N + N/2) are imaginary parts of the output complex sequence, and "t" and "c" are butterfly unit logic control terminals, which are associated with the control clock of the FFT processor.
As shown in FIG. 2, a specific module twiddle factor is added based on the original butterfly unit architecture
Figure BDA0002771831370000041
And additional control logic "r" form a new and improved butterfly unit architecture model, in which
Figure BDA0002771831370000042
N in (1) is determined according to the number of points of the designed FFT processor, for example, 1024 points of the designed FFT processor, then N is 1024, since
Figure BDA0002771831370000043
When the value of N is larger, the more,
Figure BDA0002771831370000044
the closer the real part of (1) is to 1, the closer the imaginary part is to 0, the more the real part is added on the basis of the original butterfly unit
Figure BDA0002771831370000045
The smaller the hardware resources occupied by the module, the better the effect of the improved butterfly unit designed by the invention on the optimization design of the long-point FFT processor chip.
Use of popular radix-2 in the design of FFT processor chipskAlgorithm and SDF pipeline architecture due to radix-2kThe algorithm has the butterfly structure which is as simple as the radix-2 algorithm, and simultaneously can reduce the complexity of twiddle factors, and the SDF pipeline structure is adopted because the implementation is simple, the execution speed is high, the resource utilization ratio is high, and the algorithm aims at the radix-2 algorithmkAlgorithm SDF pipeline architectureFor the FFT processor, the control logic "r" of the new and improved butterfly unit can be expressed by the formula
Figure BDA0002771831370000046
Find, where "C" represents the control clock of the FFT processor,
Figure BDA0002771831370000047
represents an exclusive-OR logic operation, ". represents an AND logic operation," k "represents a base-2kThe k value of the algorithm, "n" represents the highest bit value of the clock (e.g., the highest bit of the clock controlling the 64-point FFT processor operation is 5, i.e., C)5C4C3C2C1C0)。
As shown in FIG. 3, the following is a radical-25Algorithm implementation a 64-point SDF architecture FFT processor is an example of how an improved butterfly unit can be implemented to reduce the hardware resources consumed in the design of the FFT processor, and fig. 3 shows an improved 64-point radix-25An algorithm SDF FFT pipeline architecture diagram, wherein the MOD BFII part is an improved butterfly unit part,
Figure BDA0002771831370000051
representing a complex multiplication operation, BFI and BFII represent the original butterfly units of type I and type II, respectively.
FIG. 4 shows a 64-point radix-2 based on a new and improved butterfly unit5Algorithm signal flow diagram, as can be seen from fig. 4, the boxed part a is the part calculated by using the modified butterfly unit, and the twiddle factor of the boxed part B is the same as the original twiddle factor due to using the modified butterfly unit
Figure BDA0002771831370000052
Is converted into
Figure BDA0002771831370000053
The complexity is reduced to half, and meanwhile, the value of the twiddle factor shows regular repetition (0, 16, 8, 24, 4, 20, 12, 28, 2, 18, 10, 26, 6, 22, 14, 30 … …), the complexity of the control logic of the complex multiplier is greatly reduced, and the complexity is greatly reduced by using the methodAfter the butterfly unit is obviously improved, the hardware resource and the power consumption consumed by the FFT processor can be greatly reduced.
The invention uses Verilog HDL language to describe the design of hardware, develops based on QUARTUS PRIME platform, and the evaluation report of the development platform shows that when 64-point FFT processor is realized, the novel improved butterfly unit of the invention can reduce the hardware resource consumption by 25% and the power consumption by 18% compared with the previous research.
Although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that various changes in the embodiments and/or equivalent arrangements may be made therein without departing from the spirit and scope of the invention.

Claims (5)

1. Novel improved butterfly unit algorithm structure for FFT processor chip design, including module twiddle factor
Figure FDA0002771831360000011
And a control logic "r", characterized by: adding specific module twiddle factors on the basis of the original butterfly unit framework
Figure FDA0002771831360000012
And additional control logic "r" form a new improved butterfly unit architecture model, using popular radix-2 in the design of FFT processor chipkAlgorithms and SDF pipeline architecture.
2. The new and improved butterfly unit algorithm architecture for FFT processor chip design according to claim 1, wherein: the module twiddle factor
Figure FDA0002771831360000013
Is calculated by the formula
Figure FDA0002771831360000014
Wherein
Figure FDA0002771831360000015
N in (b) is determined according to the number of points of the designed FFT processor.
3. The new and improved butterfly unit algorithm architecture for FFT processor chip design according to claim 1, wherein: the control logic ' r ' is used for controlling the input sequence to carry out complex multiplication operation with W, ' N ' is the FFT point number, and't ' and ' x ' are basic butterfly operation control signals, and multiplication-j ' operation and butterfly operation are correspondingly carried out respectively, and in order to reduce a critical path, a pipeline type register is added between the W complex multiplication operation module and the selector.
4. The new and improved butterfly unit algorithm architecture for FFT processor chip design according to claim 1, wherein: to radical-2kFor FFT processor with SDF pipeline structure, the control logic "r" of the new improved butterfly unit can pass through the formula
Figure FDA0002771831360000016
Find, where "C" represents the control clock of the FFT processor,
Figure FDA0002771831360000017
represents an exclusive-OR logic operation, ". represents an AND logic operation," k "represents a base-2kThe k value of the algorithm, "n" represents the highest bit value of the clock.
5. The new and improved butterfly unit algorithm junction of claim 2 for FFT processor chip designConstruct, its characterized in that: the module twiddle factor
Figure FDA0002771831360000021
The values of (a) are repeated regularly.
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Cited By (1)

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CN113434811A (en) * 2021-06-29 2021-09-24 河北民族师范学院 Improved-2 ^6 algorithm and 2048-point FFT processor IP core used by FFT processor IP core

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US20050015420A1 (en) * 2003-07-18 2005-01-20 Gibb Sean G. Recoded radix-2 pipeline FFT processor
CN108021781A (en) * 2018-01-31 2018-05-11 中国电子科技集团公司第五十四研究所 The FFT IP core designs and optimization method of a kind of parameterisable
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