CN107276647B

CN107276647B - Loop gain control system and method

Info

Publication number: CN107276647B
Application number: CN201710551441.4A
Authority: CN
Inventors: 高永振; 黄鹏飞; 雷文明; 葛卫敏
Original assignee: Comba Network Systems Co Ltd
Current assignee: Comba Network Systems Co Ltd
Priority date: 2017-07-07
Filing date: 2017-07-07
Publication date: 2023-10-10
Anticipated expiration: 2037-07-07
Also published as: CN107276647A

Abstract

The embodiment of the invention provides a loop gain control system and a loop gain control method, which are used for carrying out gain control on downlink signals in a MIMO system, wherein the system comprises the following components: the FPGA is used for generating a Field Programmable Gate Array (FPGA), a feedback channel, a processor and M downlink channels, wherein M is a positive integer not less than 2; and the processor is used for controlling the gain of a loop formed by the FPGA, any one of the M downlink channels and the feedback channel, so as to realize the control of the gain of a downlink signal in the MIMO system.

Description

Loop gain control system and method

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a loop gain control system and method.

Background

Multiple-Input Multiple-Out-put (MIMO) technology is one of the core technologies of mobile communication, and MIMO systems have great advantages in terms of the rate and quality of the network. In the research process of the MIMO system, the phenomenon that the total power dynamic range of the downlink signal output by the existing MIMO system is critical or even exceeds the requirement of a 3gpp third generation partnership project (3rd Generation Partnership Project,3gpp) protocol is often found, so that the gain of the downlink signal of the MIMO system needs to be controlled. However, since the downlink signal of the MIMO system is output through a plurality of different output channels, gain control needs to be performed on each output channel separately, and the prior art cannot meet the requirement of the MIMO system for performing gain control on multiple output channels separately. In summary, the prior art has a technical problem that the gain of the downlink signal in the MIMO system cannot be controlled.

Disclosure of Invention

The embodiment of the invention provides a loop gain control system and a loop gain control method, which are used for solving the technical problem that the gain of a downlink signal in a MIMO system cannot be controlled in the prior art.

A first aspect of an embodiment of the present invention provides a loop gain control system, for gain control of downlink signals in a MIMO system, the system comprising: the FPGA is used for generating a Field Programmable Gate Array (FPGA), a feedback channel, a processor and M downlink channels, wherein M is a positive integer not less than 2;

the FPGA is used for: processing a baseband signal to form M paths of digital signals, respectively amplifying the M paths of digital signals in a gain mode, and respectively outputting the M paths of digital signals subjected to gain amplification to the M downlink channels;

a first downstream channel of the M downstream channels is for: receiving a first path of digital signals in the M paths of digital signals, performing digital-to-analog conversion and gain amplification on the first path of digital signals to form a first radio frequency signal, wherein the first radio frequency signal is used for transmitting downlink signals by an antenna, the first downlink channel is any downlink channel in the M downlink channels, and the first path of digital signals is any digital signal in the M paths of digital signals;

The feedback channel is used for: receiving the first radio frequency signal of the first downlink channel, performing analog-to-digital conversion on the first radio frequency signal to form a first feedback signal, and outputting the first feedback signal to the FPGA;

the FPGA is further configured to: determining the forward power of the first path of digital signals and the power of the first feedback signals, wherein the forward power of the first path of digital signals is the power of the first path of digital signals when the gain of the FPGA is not adjusted; transmitting the forward power of the first path of digital signal and the power of the first feedback signal to the processor;

the processor is configured to: determining gains of loops formed by the FPGA, the first downlink channel and the feedback channel according to the forward power of the first path of digital signals and the power of the first feedback signal, wherein the gains of the loops are used for representing gains of downlink signals output by the rear-end antenna of the first downlink channel in the MIMO system; and adjusting the gain of the loop when the gain of the loop exceeds a predetermined range.

According to the scheme, the feedback channel is led out from the output end of the downlink channel needing gain control and is connected with the FPGA, a loop is formed by the FPGA, the downlink channel needing gain control and the feedback channel, and the control of the gain of a downlink signal output by the rear-end antenna of the downlink channel in the MIMO system is realized through the detection and control of the gain of the loop, so that the requirement of a 3gpp third generation partnership project 3gpp protocol can be strictly met; meanwhile, the gain control of downlink signals output by different output channels of the MIMO system is realized through the gain control of different loops, so that the requirement of the MIMO system on the gain control of multiple output channels is met.

Optionally, the processor is configured to adjust the gain of the loop when the gain of the loop is out of a predetermined range, including: when the gain of the loop exceeds the preset range, adjusting the baseband gain of the FPGA for carrying out gain amplification on the first path of digital signals; and/or when the gain of the loop exceeds the preset range, adjusting the radio frequency gain of the first downlink channel for carrying out gain amplification on the first path of digital signal. Through the mode, the output ends of the M downlink channels are selectively conducted with the input ends of the feedback channels by the coupler, so that gain control is more convenient and faster to carry out on different loops respectively.

Optionally, the processor is configured to adjust the gain of the loop when the gain of the loop is out of a predetermined range, including: when the gain of the loop is larger than a first threshold value, reducing the baseband gain of the FPGA for carrying out gain amplification on the first path of digital signals; and/or when the gain of the loop is greater than a first threshold value, reducing the radio frequency gain of the first downlink channel for gain amplification of the first path of digital signal. By the method, when the gain of the first loop does not meet the preset range, the gain of the first loop can be adjusted, and further the control of the gain of the downlink signal output by the rear-end antenna of the first downlink channel in the MIMO system is realized.

Optionally, the processor is configured to adjust the gain of the loop when the gain of the loop is out of a predetermined range, including: when the gain of the loop is larger than the first threshold and smaller than a second threshold, reducing the baseband gain of the FPGA for carrying out gain amplification on the first path of digital signals, wherein the first threshold is smaller than the second threshold; and/or when the gain of the loop is greater than the second threshold, reducing the radio frequency gain of the first downlink channel for gain amplification of the first path of digital signal. By the method, when the gain of the first loop does not meet the preset range, the gain of the first loop can be adjusted, and further the control of the gain of the downlink signal output by the rear-end antenna of the first downlink channel in the MIMO system is realized.

Optionally, the system further comprises: a coupler for: and the output ends of the M downlink channels are selectively conducted with the input ends of the feedback channels. Through the mode, the output ends of the M downlink channels are selectively conducted with the input ends of the feedback channels by the coupler, so that gain control is more convenient and faster to carry out on different loops respectively.

Optionally, the processor is further configured to: when the gain of the loop accords with the preset range, the coupler is instructed to switch from conducting the output end of the first downlink channel with the input end of the feedback channel to conducting the output end of a second downlink channel in the M downlink channels with the input end of the feedback channel, wherein the second downlink channel is any downlink channel in the M downlink channels except the first downlink channel; the coupler is used for: and responding to the instruction of the processor, and switching from conducting the output end of the first downlink channel with the input end of the feedback channel to conducting the output end of the second downlink channel in the M downlink channels with the input end of the feedback channel. The output ends of the M downlink channels are selectively conducted with the input ends of the feedback channels by adopting the coupler, so that gain control is more convenient and faster for different loops.

Optionally, the system further comprises: a temperature sensor for: acquiring the temperature parameter of the first downlink channel, and sending the temperature parameter of the first downlink channel to the processor; the processor is further configured to: before the first downlink channel carries out gain amplification on the first path of digital signals, determining radio frequency gain parameters of the first downlink channel for carrying out gain amplification on the first path of digital signals according to temperature parameters of the first downlink channel, and sending the radio frequency gain parameters to the first downlink channel; the first downlink channel is configured to gain-amplify the first digital signal, and includes: and carrying out gain amplification on the first path of digital signals according to the radio frequency gain parameters sent by the processor. By the mode, when the downlink channel carries out gain adjustment on the received signal, the temperature gain compensation is carried out on the downlink channel, so that the MIMO system can output downlink signals with stable power under different temperature environments, and the stability of the MIMO system is improved.

Optionally, the system further comprises: a temperature sensor for: acquiring the temperature parameter of the first downlink channel and the temperature parameter of the feedback channel, and sending the temperature parameter of the first downlink channel and the temperature parameter of the feedback channel to the processor; the processor is configured to determine a gain of the loop according to the forward power of the first digital signal and the power of the first feedback signal, and includes: and determining the gain of the loop according to the forward power of the first path of digital signal, the power of the first feedback signal, the temperature parameter of the first downlink channel and the temperature parameter of the feedback channel. By the mode, the temperature gain compensation is carried out on the feedback channel, the gain of the loop can be determined more accurately, and the loop gain control is more accurate.

The second aspect of the embodiment of the invention provides a downlink channel gain control method, which is applied to a multiple-input multiple-output (MIMO) system, wherein the MIMO system comprises an FPGA, a feedback channel, a processor and M downlink channels, and M is a positive integer not less than 2; the method comprising the following steps: processing a baseband signal through the FPGA to form M paths of digital signals, respectively amplifying the gains of the M paths of digital signals, and respectively outputting the M paths of digital signals after the gains are amplified to the M downlink channels; receiving a first path of digital signals in the M paths of digital signals through a first downlink channel in the M downlink channels, performing digital-to-analog conversion and gain amplification on the first path of digital signals to form a first radio frequency signal, wherein the first radio frequency signal is used for transmitting downlink signals by an antenna, the first downlink channel is any downlink channel in the M downlink channels, and the first path of digital signals is any digital signal in the M paths of digital signals; receiving the first radio frequency signal of the first downlink channel through the feedback channel, performing analog-to-digital conversion on the first radio frequency signal to form a first feedback signal, and outputting the first feedback signal to the FPGA; determining the forward power of the first path of digital signals and the power of the first feedback signals through the FPGA, wherein the forward power of the first path of digital signals is the power of the first path of digital signals when the gain of the FPGA is not adjusted; transmitting the forward power of the first path of digital signal and the power of the first feedback signal to the processor; determining, by the processor, gains of loops formed by the FPGA, the first downlink channel, and the feedback channel according to the forward power of the first digital signal and the power of the first feedback signal, where the gains of the loops are used to characterize gains of downlink signals output by the rear-end antenna of the first downlink channel in the MIMO system; and adjusting the gain of the loop when the gain of the loop exceeds a predetermined range.

Optionally, the adjusting, by the processor, the gain of the loop when the gain of the loop exceeds the predetermined range includes: when the gain of the loop exceeds the preset range, the processor adjusts the baseband gain of the FPGA for carrying out gain amplification on the first path of digital signals; and/or when the gain of the loop exceeds the preset range, the processor adjusts the radio frequency gain of the first downlink channel for gain amplification of the first path of digital signal.

Optionally, the adjusting, by the processor, the gain of the loop when the gain of the loop exceeds the predetermined range includes: when the gain of the loop is larger than a first threshold value, reducing the baseband gain of the FPGA for carrying out gain amplification on the first path of digital signals; and/or reducing, by the processor, a radio frequency gain of the first downlink channel for gain amplification of the first path of digital signal when the gain of the loop is greater than a first threshold.

Optionally, the adjusting, by the processor, the gain of the loop when the gain of the loop exceeds the predetermined range includes: when the gain of the loop is larger than the first threshold and smaller than a second threshold, the processor reduces the baseband gain of the FPGA for carrying out gain amplification on the first path of digital signal, wherein the first threshold is smaller than the second threshold; and/or reducing, by the processor, a radio frequency gain of the first downlink channel for gain amplification of the first path of digital signal when the gain of the loop is greater than the second threshold.

Optionally, the system further comprises a coupler, and the method further comprises: and the output ends of the M downlink channels are alternatively conducted with the input ends of the feedback channels through the coupler.

Optionally, the method further comprises: when the gain of the loop accords with the preset range, the processor instructs the coupler to switch from conducting the output end of the first downlink channel with the input end of the feedback channel to conducting the output end of a second downlink channel in the M downlink channels with the input end of the feedback channel, wherein the second downlink channel is any downlink channel except the first downlink channel in the M downlink channels; and responding to the instruction of the processor through the coupler, and switching from conducting the output end of the first downlink channel with the input end of the feedback channel to conducting the output end of the second downlink channel in the M downlink channels with the input end of the feedback channel.

Optionally, the system further comprises a temperature sensor; prior to gain amplifying the first digital signal via the first downstream channel, the method further comprises the steps of: acquiring the temperature parameter of the first downlink channel through the temperature sensor, and sending the temperature parameter of the first downlink channel to the processor; determining, by the processor, a parameter of the first downlink channel for performing gain amplification on the first path of digital signal according to a temperature parameter of the first downlink channel, and sending the parameter to the first downlink channel; the gain amplifying the first path of digital signal through the first downlink channel includes: and carrying out gain amplification on the first path of digital signals through the first downlink channel according to the parameters sent by the processor.

Optionally, the system further comprises a temperature sensor; before determining, by the processor, the gain of the loop from the forward power of the first digital signal and the power of the first feedback signal, the method further comprises: acquiring the temperature parameters of the first downlink channel and the temperature parameters of the feedback channel through the temperature sensor, and sending the temperature parameters of the first downlink channel and the temperature parameters of the feedback channel to the processor; the determining, by the processor, the gain of the loop according to the forward power of the first digital signal and the power of the first feedback signal includes: and determining the gain of the loop by the processor according to the forward power of the first path of digital signal, the power of the first feedback signal, the temperature parameter of the first downlink channel and the temperature parameter of the feedback channel.

One or more technical solutions provided in the embodiments of the present invention at least have the following technical effects or advantages:

1. a feedback channel is led out from the output end of a downlink channel needing gain control and is connected with an FPGA, a loop is formed by the FPGA, the downlink channel needing gain control and the feedback channel, and the control of the gain of a downlink signal output by an antenna at the rear end of the downlink channel in a MIMO system is realized through the detection and control of the gain of the loop, so that the requirement of a 3gpp third generation partnership project 3gpp protocol can be strictly met; meanwhile, the gain control of downlink signals output by different output channels of the MIMO system is realized through the gain control of different loops, so that the requirement of the MIMO system on the gain control of multiple output channels is met.

2. The output ends of the M downlink channels are selectively conducted with the input ends of the feedback channels by adopting the coupler, so that gain control is more convenient and faster for different loops.

3. And temperature gain compensation is carried out on the downlink channel and the feedback channel, so that the MIMO system can output downlink signals with stable power under different temperature environments, and the stability of the MIMO system is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it will be apparent that the drawings in the following description are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a loop gain control system according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a first loop of a loop gain control system according to an embodiment of the present invention;

FIG. 3 is a graph showing the relationship between temperature and gain variation of the first downlink channel according to an embodiment of the present invention;

fig. 4 is a flowchart of a loop gain control method according to an embodiment of the invention.

Detailed Description

The following detailed description of the technical solutions of the embodiments of the present invention will be given by way of the accompanying drawings and the specific embodiments, and it should be understood that the detailed description of the technical solutions of the embodiments of the present invention and the specific features in the embodiments of the present invention are not limiting, and the embodiments of the present invention and the technical features in the embodiments of the present invention may be combined with each other without conflict.

Example 1

An embodiment of the present invention provides a loop gain control system, including: a Field-Programmable Gate Array (FPGA) chip, a feedback channel, a processor and M downstream channels, where M is a positive integer not less than 2.

In the embodiment of the invention, the downlink channel refers to a physical channel formed by all physical elements between a signal output end of an FPGA chip in a remote radio unit (Radio Remote Unit, RRU) and a signal input end of an antenna, for transmitting a signal sent to the antenna, and the feedback channel is a physical channel formed by all physical elements between the signal input end of the antenna and a feedback signal input end of the FPGA, for transmitting a signal fed back from the antenna.

Referring to fig. 1, the internal structure of the system is: the processor is respectively connected with the FPGA, the feedback channels and the M downlink channels; the first input end of the FPGA is connected with BUU equipment of the base station through an optical fiber; the M output ends of the FPGA are connected with the M input ends of the M downlink channels in a one-to-one correspondence manner; the input end of the feedback channel is connected and conducted with the output end of the downlink channel which needs to be subjected to gain control in the M downlink channels, and at any moment, only one downlink channel in the M downlink channels is conducted with the feedback channel; the output end of the feedback channel is connected with the second input end of the FPGA.

The FPGA is used for: receiving baseband signals sent by indoor baseband processing units (Building Base band Unite, BBU), processing the baseband signals to form M paths of digital signals, respectively amplifying baseband gains of the M paths of digital signals, and transmitting the M paths of digital signals after gain amplification to M downlink channels through M output ends of an FPGA and M input ends of the M downlink channels;

the M downstream channels are for: m paths of digital signals sent by the FPGA are received, digital-to-analog conversion and radio frequency gain amplification are respectively carried out on the M paths of digital signals to form M paths of radio frequency signals, the M paths of radio frequency signals are sent to the antenna, and the M paths of radio frequency signals are used for transmitting downlink signals by the antenna. The digital-to-analog conversion of the signal by the downlink channel can be completed through a digital-to-analog converter (Digital to Analog Converter, DAC), the gain amplification of the signal by the downlink channel can be completed through the cooperation of a digital-to-analog Attenuator (ATT) and a power amplifier, the radio frequency signal after the radio frequency gain amplification is output to an antenna by the power amplifier, and the downlink signal is formed through the antenna processing and is sent to a space.

Specifically, each of the M downstream channels is configured to receive a digital signal corresponding to the digital signal output at the output end of the FPGA, and perform digital-to-analog conversion and baseband gain amplification processing on the digital signal. For example, referring to fig. 1, the FPGA transmits a first digital signal after baseband gain amplification to a first downlink channel through a first output end thereof and an input end of the first downlink channel, and the first downlink channel sequentially performs digital-to-analog conversion and radio frequency gain amplification processing on the first digital signal after receiving the first digital signal, so as to form a first radio frequency signal, and transmits the first radio frequency signal to the antenna.

The feedback channel is used for: and receiving signals which are needed to be subjected to gain control and are output to the antenna by the downlink channels in the M downlink channels, performing analog-to-digital conversion processing on the signals to form feedback signals, and transmitting the feedback signals to the FPGA through the output end of the feedback channels and the second input end of the FPGA. Wherein the analog-to-digital conversion of the signal by the feedback channel can be done by an analog-to-digital converter (Analog to Digital Converter, ADC). The signal received by the feedback channel may be all signals to be output to the antenna by the downlink channel which needs to perform gain control, or may be part of signals to be output to the antenna by the downlink channel which needs to perform gain control.

The connection modes of the M downlink channels and the feedback channels comprise the following two modes:

1 st: only the output end of one downlink channel in the M downlink channels is connected and conducted with the input end of the feedback channel.

For example, assuming that the downlink channel requiring gain control is the first downlink channel of the M downlink channels, a coupler may be used to connect the first downlink channel with the feedback channel in a conductive manner. Specifically, the processor may be connected to the coupler, and the processor instructs the coupler to connect and conduct the input end of the feedback channel to the output end of the first downlink channel; the FPGA can also be connected with the coupler, and the FPGA indicates the coupler to connect and conduct the input end of the feedback channel with the output end of the first downlink channel; a control circuit may also be provided separately for the coupler, the control circuit instructing the coupler to connect and conduct the input of the feedback channel to the output of the first downstream channel. The embodiment of the invention does not particularly limit the main body of the control coupler.

2 nd: the input end of the feedback channel is connected with the output ends of the M downlink channels, but only the output end of one downlink channel in the M downlink channels is communicated with the input end of the feedback channel.

For example, as shown in fig. 1, assuming that the downlink channel requiring gain control is the first downlink channel of the M downlink channels, a coupler may be used to connect all the M output ends of the M downlink channels with the feedback channel, but only the output end of the first downlink channel is kept in conduction with the input end of the feedback channel, and the outputs of all the other downlink channels except the first downlink channel of the M downlink channels are interrupted with the output end of the feedback channel, in fig. 1, the arrow direction indicates the signal transmission direction.

Specifically, the processor may be connected to the coupler, and the processor instructs the coupler to conduct the input end of the feedback channel with the output end of the first downlink channel, and interrupt the input end of the feedback channel with the output ends of other downlink channels except the first downlink channel in the M downlink channels; the FPGA can also be connected with the coupler, the FPGA indicates the coupler to conduct the input end of the feedback channel with the output end of the first downlink channel, and the input end of the feedback channel is interrupted with the output ends of other downlink channels except the first downlink channel in the M downlink channels; a control circuit may be separately provided for the coupler, and the control circuit instructs the coupler to conduct the input end of the feedback channel with the output end of the first downlink channel, and interrupt the input end of the feedback channel with the output ends of other downlink channels except the first downlink channel among the M downlink channels. The embodiment of the invention does not particularly limit the main body of the control coupler.

The FPGA is also used to: determining the power (i.e. forward power) of a signal transmitted by a downlink channel which needs to be subjected to gain control when the signal is not subjected to FPGA gain adjustment, and the power (i.e. feedback power) of a feedback signal formed by performing analog-to-digital conversion through a feedback channel after the signal is sent to the feedback channel; and transmits the forward power and the feedback power to the processor.

Specifically, the FPGA records the forward power and the feedback power of the signal transmitted on the loop, and when determining the loop gain of a certain signal, the processor can read the forward power and the feedback power of the signal from the record, where the FPGA can perform power statistics on each frame of signal or perform power statistics on each two frames of signal, and the embodiment of the present invention is not limited specifically.

The processor is used for: determining the gain of a loop formed by a downlink channel, a feedback channel and an FPGA (field programmable gate array) which need to be subjected to gain control according to the received forward power and the feedback power, wherein the gain of the loop is used for representing the gain of a downlink signal output by a rear-end antenna of the downlink channel in the MIMO system; and adjusting the gain of the loop when the gain of the loop exceeds a predetermined range. The predetermined range is determined according to the requirements of the 3gpp protocol.

The processor may be implemented as a microprocessor (Advanced RISC Machines, ARM), a digital signal processor (Digital Signal Processing, DSP), a microcontroller ((Micro Controller Unit, MCU), etc., and the embodiments of the present invention are not limited in particular.

Next, in the embodiment of the present invention, taking a downlink channel that needs to be subjected to gain control as a first downlink channel of M downlink channels as an example, a process of performing gain control on a loop by a processor will be described in detail.

Referring to fig. 2, the FPGA, the first downlink channel, the coupler, and the feedback channel form a first loop, and it is assumed that a predetermined range of gain of the first loop is [ g4, g1], where g4 is a fourth threshold of gain of the first loop, g1 is a first threshold of gain of the first loop, and g4< g1. The processor determines that the actual gain of the current first loop is G=P2-P1 according to the forward power P1 and the feedback power P2 sent by the FPGA. The method for the processor to perform gain control on the first loop comprises the following steps: the processor judges the current actual gain of the first loop, and adjusts the gain parameter of the first loop when the actual gain does not meet the preset range until the first loop gain meets the preset range, wherein the specific adjustment method is as follows:

If G > G1, the processor controls to reduce the baseband gain of the FPGA for carrying out gain amplification on the first path of digital signals and/or reduce the radio frequency gain of the first downlink channel for carrying out gain amplification on the first path of digital signals; the radio frequency gain of the first downlink channel for performing gain amplification on the first path of digital signal specifically refers to: the first downlink channel carries out gain amplification on the radio frequency signal formed by the first path of digital signal after being processed by the digital-to-analog converter;

if G < G4, the processor controls to increase the baseband gain of the FPGA for gain amplification of the first path of digital signals and/or increase the radio frequency gain of the first downlink channel for gain amplification of the first path of digital signals;

if g4= < g= < G1, the processor stops the gain adjustment of the first loop, instructs the coupler to interrupt the feedback channel from the first downlink channel, turns on the feedback channel from the second downlink channel, and starts the gain control of the second loop formed by the FPGA, the second downlink channel, the coupler, and the feedback channel.

In the implementation process, when G > G1, the specific range of G can be further judged, and different adjustment modes are adopted. Specifically, the second threshold G2 and the third threshold G3 may be set on the basis of G > G1, where G1< G2< G3, and the adjustment manner of the loop gain by the processor includes, but is not limited to, the following three manners:

Firstly, when G1 is less than G2, reducing baseband gain of the FPGA for gain amplification of a first path of digital signal, wherein G2 is a second threshold value of gain of a first loop;

second, increasing the attenuation parameter of the digitally controlled attenuator ATT in the first downlink channel when G2< G3, wherein G3 is a third threshold of the gain of the first loop;

and thirdly, when G3 is smaller than G, closing the power amplification function of the power amplifier in the first downlink channel, and giving an over-power alarm to the first downlink channel.

In the implementation process, when G < G4, the specific range of G can be further judged, and different adjustment modes are adopted. Specifically, the fifth threshold G5 and the sixth threshold G6 may be set on the basis of G < G4, where G6< G5< G4, and the adjustment manner of the loop gain by the processor includes, but is not limited to, the following three manners:

firstly, when G5 is less than G < G4, increasing the baseband gain of the FPGA for gain amplification of the first path of digital signals, wherein G5 is a fifth threshold value of the gain of the first loop;

second, decreasing the attenuation parameter of the digitally controlled attenuator ATT in the first downlink channel when G6< G5, wherein G3 is a fifth threshold of the gain of the first loop;

third, when G < G6, stopping the power control of the processor on the first loop, and alarming the first downlink channel for too low power.

Wherein the specific parameter values of the second threshold g2 and the fifth threshold g5 are determined by the scaling gain g0 of the gain of the first loop and the step attenuation parameter X of the digitally controlled attenuator ATT: g5 =g0-X, g2=g0+x. The scaling gain g0 satisfies: g4< = g0< = g1.

In the scheme, the gain control system leads out a feedback channel from the output end of a downlink channel needing gain control and is connected with the FPGA, the downlink channel needing gain control and the feedback channel form a loop, and the gain of a downlink signal output by an antenna at the rear end of the downlink channel in the MIMO system is controlled by detecting and controlling the gain of the loop, so that the gain can strictly meet the requirement of a 3gpp third generation partnership project 3gpp protocol; meanwhile, the gain control of downlink signals output by different output channels of the MIMO system is realized through the gain control of different loops, so that the requirement of the MIMO system on the gain control of multiple output channels is met; moreover, the output ends of the M downlink channels are alternatively conducted with the input ends of the feedback channels by adopting the coupler, so that gain control is more convenient and faster for different loops.

In practical application, the temperature of the device during operation also affects the accuracy of gain adjustment of the device on signals, so that in order to enable the MIMO system to output downlink signals with stable power in different temperature environments, temperature gain compensation needs to be performed on a downlink channel. The temperature gain compensation of the downlink channel may be performed by performing gain adjustment on the received signal in the downlink channel, or may be performed when the processor regulates and controls the gain of the loop, which is not limited by the embodiment of the present invention.

(1) The specific implementation method for the processor to carry out gain adjustment on the received signal in the downlink channel and carry out temperature gain compensation on the downlink channel comprises the following steps:

optionally, the system may further include a temperature sensor, configured to obtain a temperature parameter of a downlink channel that needs to be subjected to gain control, and send the temperature parameter of the downlink channel to the processor; the processor is further configured to: before a downlink channel needing to perform gain control performs gain amplification on a digital signal received by the downlink channel, determining a radio frequency gain parameter of the downlink channel for performing gain amplification on the digital signal received by the downlink channel according to the temperature parameter of the downlink channel, and transmitting the radio frequency gain parameter to the downlink channel, so that the downlink channel performs gain amplification on the digital signal received by the downlink channel according to the radio frequency gain parameter transmitted by a processor.

Next, taking a downlink channel that needs to be gain controlled as a first downlink channel as an example, temperature gain compensation of the downlink channel will be described in detail:

specifically, the temperature sensor is configured to obtain a temperature parameter of the first downlink channel, and send the temperature parameter of the first downlink channel to the processor; the processor is further configured to: before the first downlink channel carries out gain amplification on the first path of digital signals, determining radio frequency gain parameters of the first downlink channel for carrying out gain amplification on the first path of digital signals according to temperature parameters of the first downlink channel, and sending the radio frequency gain parameters to the first downlink channel; the first downlink channel is used for gain amplifying the first path of digital signal, and comprises the following steps: and carrying out gain amplification on the first path of digital signals according to the radio frequency gain parameters sent by the processor.

In the implementation process, the influence of different temperatures on the gain of the downlink channel can be counted in advance to generate a downlink temperature compensation table. Before the first downlink channel carries out gain amplification on the first path of digital signals, the processor reads gain change delta C corresponding to the temperature parameter from a downlink temperature compensation table according to the temperature parameter of the first downlink channel, corrects the radio frequency gain parameter K0 of the first downlink channel for carrying out gain amplification on the first path of digital signals to obtain corrected radio frequency gain parameters K0-delta C, and sends the corrected radio frequency gain parameters K0-delta C to the first downlink channel; the first downlink channel carries out gain amplification on the first path of digital signals according to the corrected radio frequency gain parameters K0-delta C sent by the processor.

The manufacturing process of the downlink temperature compensation table is as follows: the method comprises the steps of keeping all configuration parameters of an FPGA and a first downlink channel unchanged, keeping power of a first path of digital signals output by the FPGA unchanged, carrying out temperature sampling on the first downlink channel at intervals of a certain temperature value, recording power of a first radio frequency signal of an antenna port at different temperature points, and determining sampling temperature intervals according to actual conditions. And obtaining the relative value of each temperature point relative to the reference temperature, obtaining the functional relation between the temperature and the gain change according to the relative value of each temperature point and each temperature point relative to the reference temperature, and generating a downlink temperature compensation table according to the functional relation.

For example, in an ambient temperature of-40 ℃ to +60 ℃, the processor instructs the temperature sensor to sample the temperature of the first downlink channel every 10 ℃ and keeps the power of the first path of digital signal output by the FPGA at the same value at all sampling points; the processor acquires the power of the first radio frequency signal of the antenna port at each sampling temperature, and obtains the relative value of the power of the first radio frequency signal at each temperature point relative to the power of the first radio frequency signal at the reference temperature; and the sampling temperature and the relative value are manufactured into a data table, and the function relation of the temperature to the gain change of the first downlink channel is obtained. Referring to fig. 3, the abscissa of the graph shows a temperature T, the ordinate shows a power C of the first rf signal, and Δc1 shows a relative value of the power of the first rf signal at the temperature T1 with respect to the power of the first rf signal at the reference temperature T0, that is, a gain change caused by the temperature T1 on the first downlink channel.

In the specific implementation process, in order to make the function relation between the temperature and the gain change of the downlink channel more reliable, a plurality of base station devices may be adopted to sample data, and then the average value of the data of the plurality of base station devices is used to calculate the function relation between the temperature and the gain change of the downlink channel.

According to the method, the received signal is subjected to gain adjustment in the downlink channel, and the temperature gain compensation is performed on the downlink channel, so that the MIMO system can output downlink signals with stable power in different temperature environments, and the stability of the MIMO system is improved.

Similarly, the temperature will also have a gain effect on the feedback channel, which needs to be temperature gain compensated in order to correct the gain variation of the loop gain caused by the temperature.

Optionally, the temperature sensor is further configured to obtain a temperature parameter of a feedback channel, and send the temperature parameter of the feedback channel to the processor; the processor is configured to determine, according to the received forward power and the received feedback power, a gain of a loop formed by a downlink channel, a feedback channel and the FPGA, where the gain is required to be controlled, and the processor includes: the gain of the loop is determined based on the forward power, the feedback power, and the temperature parameter of the feedback path.

Next, taking a downlink channel that needs to be gain controlled as a first downlink channel as an example, temperature gain compensation of the feedback channel will be described in detail:

the temperature sensor is used for acquiring the temperature parameters of the feedback channel and sending the temperature parameters of the feedback downlink channel to the processor; the processor is further configured to determine a gain of a first loop formed by the first downlink channel, the feedback channel, and the FPGA according to the received temperature parameter of the feedback downlink channel, the forward power of the first digital signal, and the power of the first feedback signal.

Specifically, the influence of different temperatures on the gain of the feedback channel can be counted in advance to generate a feedback temperature compensation table. When the processor determines the gain of the first loop, the gain change deltac 2 corresponding to the temperature parameter is read from the feedback temperature compensation table according to the temperature parameter of the feedback channel, and then the gain of the first loop is determined according to the forward power P3 of the received first path of digital signal and the power P4 of the first feedback signal, and the gain change deltac 2: g1 =p4-p3- Δc2.

The manufacturing process of the feedback temperature compensation table is as follows: the power of the first radio frequency signal output by the first downlink channel to the antenna is kept unchanged, the feedback channel is subjected to temperature sampling once at intervals of certain temperature values, the power of the first feedback signal output by the feedback channel is recorded at different temperature points, the sampling temperature interval is determined according to actual conditions, and the embodiment of the invention is not particularly limited. And obtaining the relative value of each temperature point relative to the reference temperature, obtaining the functional relation between the temperature and the gain change according to the relative value of each temperature point and each temperature point relative to the reference temperature, and generating a downlink temperature compensation table according to the functional relation. The specific embodiments may refer to the manufacturing process of the downlink temperature compensation table, and will not be described herein for example.

In order to make the function relation between the temperature and the gain change of the feedback channel more reliable, a plurality of base station devices can be adopted to sample data, and then the average value of the data of the plurality of base station devices is used to calculate the function relation between the temperature and the gain change of the feedback channel.

By the mode, the temperature gain compensation is carried out on the feedback channel, the gain of the loop can be determined more accurately, and the loop gain control is more accurate.

(2) The specific implementation method for temperature gain compensation of the downlink channel when the processor regulates and controls the gain of the loop comprises the following steps:

optionally, the system may further include a temperature sensor, configured to obtain a temperature parameter of a downlink channel and a temperature parameter of a feedback channel that need to be subjected to gain control, and send the temperature parameter of the downlink channel and the temperature parameter of the feedback channel to the processor; the processor is configured to determine, according to the received forward power and the received feedback power, a gain of a loop formed by a downlink channel, a feedback channel and the FPGA, where the gain is required to be controlled, and the processor includes: and determining the gain of the loop according to the forward power, the feedback power, the temperature parameter of the downlink channel needing gain control and the temperature parameter of the feedback channel.

Next, taking a downlink channel that needs to be gain controlled as a first downlink channel, temperature gain compensation of the downlink channel will be described in detail:

specifically, the influence of different temperatures on the gain of the feedback channel and the influence of different temperatures on the gain of the first downlink channel can be counted in advance, so as to generate a downlink temperature compensation table and a feedback temperature compensation table. The method for manufacturing the downlink temperature compensation table and the feedback temperature compensation table can refer to the specific implementation process for manufacturing the downlink temperature compensation table and the feedback temperature compensation table described in the foregoing mode (1), and will not be described herein.

The processor determines the gain of the first loop according to the received forward power P5, the first feedback signal power P6, the temperature parameter Δc3 of the first downlink channel and the temperature parameter Δc4 of the feedback channel of the first path of digital signal: g2 =p6-p5- Δc3- Δc4; the processor adjusts the gain of the first loop when the gain of the first loop does not meet the predetermined range; after the gain of the first loop is adjusted, the processor adjusts the radio frequency gain parameter of the first downlink channel for gain amplification of the first path of digital signal according to the temperature parameter delta C3 of the first downlink channel.

By the method, the temperature gain compensation is performed on the downlink channel when the gain of the loop is regulated and controlled, so that the gain of the loop can be more accurately determined, the downlink signals with stable power can be output by the MIMO system in different temperature environments, and the stability of the MIMO system is improved.

Example two

The second embodiment of the invention provides a downlink channel gain control method, which is applied to a multiple-input multiple-output (MIMO) system, wherein the MIMO system comprises an FPGA, a feedback channel, a processor and M downlink channels, and M is a positive integer not less than 2; referring to fig. 4, the method includes:

step 11, processing a baseband signal through the FPGA to form M paths of digital signals, respectively amplifying the gains of the M paths of digital signals, and respectively outputting the M paths of digital signals after the gains are amplified to the M downlink channels;

step 12, receiving a first path of digital signals in the M paths of digital signals through a first downlink channel in the M downlink channels, performing digital-to-analog conversion and gain amplification on the first path of digital signals to form a first radio frequency signal, wherein the first radio frequency signal is used by an antenna to transmit downlink signals, the first downlink channel is any downlink channel in the M downlink channels, and the first path of digital signals is any digital signal in the M paths of digital signals;

Step 13, receiving the first radio frequency signal of the first downlink channel through the feedback channel, performing analog-to-digital conversion on the first radio frequency signal to form a first feedback signal, and outputting the first feedback signal to the FPGA;

step 14, determining the forward power of the first path of digital signals and the power of the first feedback signals through the FPGA, wherein the forward power of the first path of digital signals is the power of the first path of digital signals when the gain of the FPGA is not adjusted; transmitting the forward power of the first path of digital signal and the power of the first feedback signal to the processor;

step 15, determining, by the processor, gains of a loop formed by the FPGA, the first downlink channel, and the feedback channel according to the forward power of the first digital signal and the power of the first feedback signal, where the gains of the loop are used to characterize the gains of downlink signals output by the back-end antenna of the downlink channel in the MIMO system; and adjusting the gain of the loop when the gain of the loop exceeds a predetermined range.

Optionally, adjusting, by the processor, the gain of the loop when the gain of the loop exceeds the predetermined range includes:

When the gain of the loop exceeds the preset range, the processor adjusts the baseband gain of the FPGA for carrying out gain amplification on the first path of digital signals; and/or

And when the gain of the loop exceeds the preset range, the processor adjusts the radio frequency gain of the first downlink channel for gain amplification of the first path of digital signal.

Optionally, the adjusting, by the processor, the gain of the loop when the gain of the loop exceeds the predetermined range includes:

when the gain of the loop is larger than a first threshold value, the processor increases the baseband gain of the FPGA for carrying out gain amplification on the first path of digital signals; and/or

And when the gain of the loop is larger than a first threshold value, reducing the radio frequency gain of the first downlink channel for gain amplification of the first path of digital signal by the processor.

when the gain of the loop is larger than the first threshold and smaller than a second threshold, the processor reduces the baseband gain of the FPGA for carrying out gain amplification on the first path of digital signal, wherein the first threshold is smaller than the second threshold; and/or

And when the gain of the loop is larger than the second threshold value, reducing the radio frequency gain of the first downlink channel for gain amplification of the first path of digital signal by the processor.

Optionally, the system further comprises a coupler, and the method further comprises:

and the output ends of the M downlink channels are alternatively conducted with the input ends of the feedback channels through the coupler.

Optionally, the method further comprises: when the gain of the loop accords with the preset range, the processor instructs the coupler to switch from conducting the output end of the first downlink channel with the input end of the feedback channel to conducting the output end of a second downlink channel in the M downlink channels with the input end of the feedback channel, wherein the second downlink channel is any downlink channel except the first downlink channel in the M downlink channels;

and responding to the instruction of the processor through the coupler, and switching from conducting the output end of the first downlink channel with the input end of the feedback channel to conducting the output end of the second downlink channel in the M downlink channels with the input end of the feedback channel.

Optionally, the system further comprises a temperature sensor; before gain amplifying the first digital signal via the first downlink channel, the method further includes:

acquiring the temperature parameter of the first downlink channel through the temperature sensor, and sending the temperature parameter of the first downlink channel to the processor;

determining, by the processor, a parameter of the first downlink channel for performing gain amplification on the first path of digital signal according to a temperature parameter of the first downlink channel, and sending the parameter to the first downlink channel;

the gain amplifying the first path of digital signal through the first downlink channel includes: and carrying out gain amplification on the first path of digital signals through the first downlink channel according to the parameters sent by the processor.

Optionally, the system further comprises a temperature sensor; before determining, by the processor, the gain of the loop from the forward power of the first digital signal and the power of the first feedback signal, the method further comprises:

acquiring the temperature parameters of the first downlink channel and the temperature parameters of the feedback channel through the temperature sensor, and sending the temperature parameters of the first downlink channel and the temperature parameters of the feedback channel to the processor;

The determining, by the processor, the gain of the loop according to the forward power of the first digital signal and the power of the first feedback signal includes: and determining the gain of the loop by the processor according to the forward power of the first path of digital signal, the power of the first feedback signal, the temperature parameter of the first downlink channel and the temperature parameter of the feedback channel.

It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the invention may take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present invention without departing from the spirit or scope of the embodiments of the invention. Thus, the embodiments of the present invention are intended to include such modifications and alterations insofar as they come within the scope of the embodiments of the invention as claimed and the equivalents thereof.

Claims

1. A loop gain control system for gain control of a downlink signal in a multiple-input-output, MIMO, system, the system comprising: a field programmable gate array FPGA, a feedback channel, a processor and M downlink channels, M is a positive integer not less than 2;

the processor is configured to: determining gains of loops formed by the FPGA, the first downlink channel and the feedback channel according to the forward power of the first path of digital signals and the power of the first feedback signal, wherein the gains of the loops are used for representing gains of downlink signals output by the rear-end antenna of the first downlink channel in the MIMO system; when the gain of the loop exceeds a preset range, adjusting the gain of the loop;

the system further comprises:

a temperature sensor for: acquiring the temperature parameter of the first downlink channel and the temperature parameter of the feedback channel, and sending the temperature parameter of the first downlink channel and the temperature parameter of the feedback channel to the processor;

The processor is configured to determine a gain of the loop according to the forward power of the first digital signal and the power of the first feedback signal, and includes: and determining the gain of the loop according to the forward power of the first path of digital signal, the power of the first feedback signal, the temperature parameter of the first downlink channel and the temperature parameter of the feedback channel.

2. The system of claim 1, wherein the processor is configured to adjust the gain of the loop when the gain of the loop is outside a predetermined range, comprising:

when the gain of the loop exceeds the preset range, adjusting the baseband gain of the FPGA for carrying out gain amplification on the first path of digital signals; and/or

And when the gain of the loop exceeds the preset range, adjusting the radio frequency gain of the first downlink channel for carrying out gain amplification on the first path of digital signal.

3. The system of claim 1, wherein the processor is configured to adjust the gain of the loop when the gain of the loop is outside a predetermined range, comprising:

when the gain of the loop is larger than a first threshold value, reducing the baseband gain of the FPGA for carrying out gain amplification on the first path of digital signals; and/or

And when the gain of the loop is larger than a first threshold value, reducing the radio frequency gain of the first downlink channel for carrying out gain amplification on the first path of digital signals.

4. The system of claim 3, wherein the processor is configured to adjust the gain of the loop when the gain of the loop is outside a predetermined range, comprising:

when the gain of the loop is larger than the first threshold and smaller than a second threshold, reducing the baseband gain of the FPGA for carrying out gain amplification on the first path of digital signals, wherein the first threshold is smaller than the second threshold; and/or

And when the gain of the loop is larger than the second threshold value, reducing the radio frequency gain of the first downlink channel for carrying out gain amplification on the first path of digital signals.

5. The system of any one of claims 1-4, wherein the system further comprises:

a coupler for: and the output ends of the M downlink channels are selectively conducted with the input ends of the feedback channels.

6. The system of claim 5, wherein the processor is further configured to: when the gain of the loop accords with the preset range, the coupler is instructed to switch from conducting the output end of the first downlink channel with the input end of the feedback channel to conducting the output end of a second downlink channel in the M downlink channels with the input end of the feedback channel, wherein the second downlink channel is any downlink channel in the M downlink channels except the first downlink channel;

The coupler is used for: and responding to the instruction of the processor, and switching from conducting the output end of the first downlink channel with the input end of the feedback channel to conducting the output end of the second downlink channel in the M downlink channels with the input end of the feedback channel.

7. The system of any one of claims 1-4, wherein the system further comprises:

a temperature sensor for: acquiring the temperature parameter of the first downlink channel, and sending the temperature parameter of the first downlink channel to the processor;

the processor is further configured to: before the first downlink channel carries out gain amplification on the first path of digital signals, determining radio frequency gain parameters of the first downlink channel for carrying out gain amplification on the first path of digital signals according to temperature parameters of the first downlink channel, and sending the radio frequency gain parameters to the first downlink channel;

the first downlink channel is configured to gain-amplify the first digital signal, and includes: and carrying out gain amplification on the first path of digital signals according to the radio frequency gain parameters sent by the processor.

8. The downlink channel gain control method is characterized by being applied to a multiple-input multiple-output (MIMO) system, wherein the MIMO system comprises an FPGA, a feedback channel, a processor and M downlink channels, and M is a positive integer not less than 2; the method comprises the following steps:

Processing a baseband signal through the FPGA to form M paths of digital signals, respectively amplifying the gains of the M paths of digital signals, and respectively outputting the M paths of digital signals after the gains are amplified to the M downlink channels;

receiving a first path of digital signals in the M paths of digital signals through a first downlink channel in the M downlink channels, performing digital-to-analog conversion and gain amplification on the first path of digital signals to form a first radio frequency signal, wherein the first radio frequency signal is used for transmitting downlink signals by an antenna, the first downlink channel is any downlink channel in the M downlink channels, and the first path of digital signals is any digital signal in the M paths of digital signals;

receiving the first radio frequency signal of the first downlink channel through the feedback channel, performing analog-to-digital conversion on the first radio frequency signal to form a first feedback signal, and outputting the first feedback signal to the FPGA;

determining the forward power of the first path of digital signals and the power of the first feedback signals through the FPGA, wherein the forward power of the first path of digital signals is the power of the first path of digital signals when the gain of the FPGA is not adjusted; transmitting the forward power of the first path of digital signal and the power of the first feedback signal to the processor;

Determining, by the processor, gains of loops formed by the FPGA, the first downlink channel, and the feedback channel according to the forward power of the first digital signal and the power of the first feedback signal, where the gains of the loops are used to characterize gains of downlink signals output by the rear-end antenna of the first downlink channel in the MIMO system; when the gain of the loop exceeds a preset range, adjusting the gain of the loop;

the system further comprises a temperature sensor; before determining, by the processor, the gain of the loop from the forward power of the first digital signal and the power of the first feedback signal, the method further comprises:

9. The method of claim 8, wherein said adjusting, by the processor, the gain of the loop when the gain of the loop is outside the predetermined range comprises:

10. The method of claim 8, wherein said adjusting, by the processor, the gain of the loop when the gain of the loop is outside the predetermined range comprises:

11. The method of claim 10, wherein said adjusting, by the processor, the gain of the loop when the gain of the loop is outside the predetermined range comprises:

12. The method of any of claims 8-11, wherein the system further comprises a coupler, the method further comprising:

13. The method as recited in claim 12, further comprising:

when the gain of the loop accords with the preset range, the processor instructs the coupler to switch from conducting the output end of the first downlink channel with the input end of the feedback channel to conducting the output end of a second downlink channel in the M downlink channels with the input end of the feedback channel, wherein the second downlink channel is any downlink channel except the first downlink channel in the M downlink channels;

14. The method of any one of claim 8 to 11, wherein the system further comprises a temperature sensor; before gain amplifying the first digital signal via the first downlink channel, the method further includes: