CN107276580B - Millimeter wave high-speed frequency divider - Google Patents
Millimeter wave high-speed frequency divider Download PDFInfo
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- CN107276580B CN107276580B CN201710416951.0A CN201710416951A CN107276580B CN 107276580 B CN107276580 B CN 107276580B CN 201710416951 A CN201710416951 A CN 201710416951A CN 107276580 B CN107276580 B CN 107276580B
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- flop
- millimeter wave
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/3562—Bistable circuits of the master-slave type
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/002—Pulse counters comprising counting chains; Frequency dividers comprising counting chains using semiconductor devices
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- Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention discloses a millimeter wave high-speed frequency divider, relates to the field of millimeter wave integrated circuits, and discloses a frequency divider module applied to a millimeter wave transceiver chip, which solves the technical problems of overlarge area and too narrow frequency dividing range of the conventional high-speed frequency divider. The millimeter wave high-speed frequency divider comprises four simple D triggers which are sequentially connected and connected into a ring. The millimeter wave high-speed oscillator does not use passive devices such as inductors and the like which occupy the area, and has the technical advantages of small area and large frequency division range.
Description
Technical Field
The invention relates to the field of millimeter wave integrated circuits, in particular to a millimeter wave high-speed frequency divider, which is a frequency divider module applied to a millimeter wave transceiver chip.
Background
Because the millimeter wave frequency band has higher available bandwidth and higher detection precision, the millimeter wave chip has wide application in various aspects such as wireless communication, radar, guidance, remote sensing technology, radio astronomy, electronic countermeasure and the like. In recent years, with the successive opening of millimeter wave frequency bands, millimeter wave chips have become hot spots. How to design a high-speed frequency divider with low power consumption, small area and large frequency dividing range is a topic worthy of research.
Currently, a common millimeter wave high-speed frequency divider is an injection locked frequency divider. In the injection locking frequency divider, an inductor and a capacitor passive device are adopted, self-resonance is carried out at the frequency division frequency, and a signal is injected at a common-mode end to realize the function of frequency division by two. Because of the adoption of passive devices of the inductor and the capacitor, the area of the circuit is large, and because of the high Q value characteristic of the inductor and the capacitor, the traditional circuit cannot realize a wider frequency division range.
Disclosure of Invention
The purpose of the invention is as follows: the invention aims to solve the defects in the prior art and provide a millimeter wave high-speed frequency divider with small area and large frequency dividing range.
The technical scheme is as follows: the millimeter wave high-speed frequency divider comprises a first D trigger, a second D trigger, a third D trigger and a fourth D trigger which are connected in sequence, wherein the output end of the first D trigger is connected with the input end of the second D trigger in series, the output end of the second D trigger is connected with the input end of the third D trigger in series, the output end of the third D trigger is connected with the input end of the fourth D trigger in series, and the output end of the fourth D trigger is connected with the input end of the first D trigger in series; the internal circuit structures of the first D flip-flop, the second D flip-flop, the third D flip-flop and the fourth D flip-flop comprise a signal injection part and a signal transmission part, and the first D flip-flop, the second D flip-flop, the third D flip-flop and the fourth D flip-flop are all connected with a clock signal clk and a clock signal clkb.
Further, the output end signals VOUTP and VOUTN of the fourth D flip-flop are not only connected to the input end of the first D flip-flop, but also serve as the output of the whole millimeter wave high-speed frequency divider to drive a post-stage circuit.
Further, the internal circuit structures of the first D flip-flop, the second D flip-flop, the third D flip-flop and the fourth D flip-flop are the same.
Further, the signal injection part consists of an NMOS transistor Mn1, a PMOS transistor Mp1 and a PMOS transistor Mp 2; the signal transmission part is composed of an NMOS transistor Mn2 and an NMOS transistor Mn 3.
Furthermore, the source end of the NMOS transistor Mn1 is connected to VSS, the drain end of the NMOS transistor Mn1 is connected to the source ends of the NMOS transistor Mn2 and the NMOS transistor Mn3, respectively, the drain end of the NMOS transistor Mn2 is connected to the drain end of the PMOS transistor Mp1, the drain end of the NMOS transistor Mn3 is connected to the drain end of the PMOS transistor Mp2, and the source ends of the PMOS transistor Mp1 and the PMOS transistor Mp2 are connected to VDD.
Furthermore, a clock signal is connected with the gate end of the NMOS tube Mn1 through clkin, and the clock signal is connected with the gate ends of the PMOS tube Mp1 and the PMOS tube Mp2 through clkin to realize an injection function; the input signal is connected with the gate end of the NMOS tube Mn2 through the INP, connected with the gate end of the NMOS tube Mn3 through the INN, and output through the drain ends OUTP and OUTN of the NMOS tube Mn2 and the NMOS tube Mn3, so that the data transmission function is realized.
Further, the clock signal clk is connected to a clkin port of the first D flip-flop, a clkin port of the second D flip-flop, a clkin port of the third D flip-flop, and a clkin port of the fourth D flip-flop, respectively; the clock signal clkb is connected with a clkin port of the first D trigger, a clkin port of the second D trigger, a clkin port of the third D trigger and a clkin port of the fourth D trigger respectively.
Has the advantages that: the millimeter wave high-speed oscillator disclosed by the invention does not use passive devices such as inductors and the like which occupy the area, and has the technical advantages of small area and large frequency division range.
Drawings
FIG. 1 is a system block diagram of a millimeter wave high speed frequency divider of the present invention;
fig. 2 is a circuit diagram of a simple D flip-flop of the present invention.
Detailed Description
The technical solution of the present invention will be further described in detail with reference to the following embodiments and the accompanying drawings.
A millimeter wave high-speed frequency divider as shown in fig. 1 and fig. 2, comprising a first D flip-flop, a second D flip-flop, a third D flip-flop and a fourth D flip-flop, which are connected in sequence, wherein an output end of the first D flip-flop is connected in series with an input end of the second D flip-flop, an output end of the second D flip-flop is connected in series with an input end of the third D flip-flop, an output end of the third D flip-flop is connected in series with an input end of the fourth D flip-flop, and an output end of the fourth D flip-flop is connected in series with an input end of the first D flip-flop; the internal circuit structures of the first D flip-flop, the second D flip-flop, the third D flip-flop and the fourth D flip-flop comprise a signal injection part and a signal transmission part, and the first D flip-flop, the second D flip-flop, the third D flip-flop and the fourth D flip-flop are all connected with a clock signal clk and a clock signal clkb.
As a further optimization of this embodiment:
preferably, the output end signals VOUTP and VOUTN of the fourth D flip-flop are not only connected to the input end of the first D flip-flop, but also used as the output of the whole millimeter wave high-speed frequency divider to drive the subsequent circuit.
Preferably, the first D flip-flop, the second D flip-flop, the third D flip-flop, and the fourth D flip-flop have the same internal circuit structure, and the specific internal circuit structure includes a signal injection part and a signal transmission part:
the signal injection part consists of an NMOS tube Mn1, a PMOS tube Mp1 and a PMOS tube Mp 2; the signal transmission part is composed of an NMOS transistor Mn2 and an NMOS transistor Mn 3.
The source end of the NMOS tube Mn1 is connected with VSS, the drain end of the NMOS tube Mn1 is connected with the source ends of the NMOS tube Mn2 and the NMOS tube Mn3 respectively, the drain end of the NMOS tube Mn2 is connected with the drain end of the PMOS tube Mp1, the drain end of the NMOS tube Mn3 is connected with the drain end of the PMOS tube Mp2, and the source ends of the PMOS tube Mp1 and the PMOS tube Mp2 are connected with VDD together.
The clock signal is connected with the gate end of the NMOS tube Mn1 through clkin, and the clock signal is connected with the gate ends of the PMOS tube Mp1 and the PMOS tube Mp2 through clkin to realize the injection function; the input signal is connected with the gate end of the NMOS tube Mn2 through the INP, connected with the gate end of the NMOS tube Mn3 through the INN, and output through the drain ends OUTP and OUTN of the NMOS tube Mn2 and the NMOS tube Mn3, so that the data transmission function is realized.
The clock signals clk and clkb are differential clock signals, which are specifically connected as follows:
the clock signal clk is respectively connected with a clkin port of the first D trigger, a clkin port of the second D trigger, a clkin port of the third D trigger and a clkin port of the fourth D trigger; the clock signal clkb is connected with a clkin port of the first D trigger, a clkin port of the second D trigger, a clkin port of the third D trigger and a clkin port of the fourth D trigger respectively.
The millimeter wave high-speed oscillator disclosed by the invention does not use passive devices such as inductors and the like which occupy the area, and has the technical advantages of small area and large frequency division range.
Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (3)
1. A millimeter wave high-speed frequency divider is characterized in that: the trigger comprises a first D trigger, a second D trigger, a third D trigger and a fourth D trigger which are connected in sequence, wherein the output end of the first D trigger is connected with the input end of the second D trigger in series, the output end of the second D trigger is connected with the input end of the third D trigger in series, the output end of the third D trigger is connected with the input end of the fourth D trigger in series, and the output end of the fourth D trigger is connected with the input end of the first D trigger in series; the internal circuit structures of the first D flip-flop, the second D flip-flop, the third D flip-flop and the fourth D flip-flop comprise a signal injection part and a signal transmission part, and the first D flip-flop, the second D flip-flop, the third D flip-flop and the fourth D flip-flop are connected with a clock signal clk and a clock signal clkb;
the signal injection part consists of an NMOS tube Mn1, a PMOS tube Mp1 and a PMOS tube Mp 2; the signal transmission part consists of an NMOS transistor Mn2 and an NMOS transistor Mn 3;
the source end of an NMOS tube Mn1 is connected with VSS, the drain end of an NMOS tube Mn1 is respectively connected with the source ends of an NMOS tube Mn2 and an NMOS tube Mn3, the drain end of the NMOS tube Mn2 is connected with the drain end of a PMOS tube Mp1, the drain end of an NMOS tube Mn3 is connected with the drain end of a PMOS tube Mp2, and the source ends of the PMOS tube Mp1 and the PMOS tube Mp2 are commonly connected with VDD;
the clock signal is connected with the gate end of the NMOS tube Mn1 through clkin, and the clock signal is connected with the gate ends of the PMOS tube Mp1 and the PMOS tube Mp2 through clkin to realize the injection function; the input signal is connected with the gate end of an NMOS (N-channel metal oxide semiconductor) tube Mn2 through INP (indium tin oxide) and the gate end of an NMOS tube Mn3 through INN (indium tin oxide), and is output through drain ends OUTP and OUTN of an NMOS tube Mn2 and an NMOS tube Mn3, so that a data transmission function is realized;
the clock signal clk is respectively connected with a clkin port of a first D trigger, a clkin port of a second D trigger, a clkin port of a third D trigger and a clkin port of a fourth D trigger; the clock signal clkb is connected with a clkin port of the first D trigger, a clkin port of the second D trigger, a clkin port of the third D trigger and a clkin port of the fourth D trigger respectively.
2. A millimeter wave high speed frequency divider according to claim 1, wherein: and the output end signals VOUTP and VOUTN of the fourth D trigger are not only connected with the input end of the first D trigger, but also used as the output of the whole millimeter wave high-speed frequency divider to drive a post-stage circuit.
3. A millimeter wave high speed frequency divider according to claim 1, wherein: the first D trigger, the second D trigger, the third D trigger and the fourth D trigger have the same internal circuit structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710416951.0A CN107276580B (en) | 2017-06-06 | 2017-06-06 | Millimeter wave high-speed frequency divider |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710416951.0A CN107276580B (en) | 2017-06-06 | 2017-06-06 | Millimeter wave high-speed frequency divider |
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| CN107276580A CN107276580A (en) | 2017-10-20 |
| CN107276580B true CN107276580B (en) | 2020-07-31 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0621806A (en) * | 1992-07-06 | 1994-01-28 | Nec Corp | Frequency divider circuit |
| SE506817C2 (en) * | 1996-06-20 | 1998-02-16 | Ericsson Telefon Ab L M | Serial-parallel and parallel-serial converters including frequency dividers |
| JP5372114B2 (en) * | 2011-11-10 | 2013-12-18 | 株式会社半導体理工学研究センター | Frequency divider circuit and PLL circuit |
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2017
- 2017-06-06 CN CN201710416951.0A patent/CN107276580B/en active Active
Non-Patent Citations (1)
| Title |
|---|
| 10～37 GHz CMOS四分频器的设计;沈炎俊， 冯军;《电子设计工程》;20091130;第79-80,83页 * |
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Inventor after: Tian Tong Inventor after: Yuan Shengyue Inventor after: Zhao Chen Inventor after: Ding Bowen Inventor after: Tao Li Inventor after: Cao Xuepo Inventor before: Tian Tong Inventor before: Yuan Shengyue Inventor before: Zhao Chen Inventor before: Ding Bowen Inventor before: Tao Li Inventor before: Cao Xuepo Inventor before: Shen Yedong |
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Denomination of invention: A millimeter wave high-speed frequency divider Effective date of registration: 20220729 Granted publication date: 20200731 Pledgee: China Construction Bank Corporation Nantong Economic and Technological Development Zone sub branch Pledgor: STORMICRO TECHNOLOGIES Co.,Ltd. Registration number: Y2022980011632 |