CN107275387A - A kind of power semiconductor terminal structure and preparation method thereof - Google Patents
A kind of power semiconductor terminal structure and preparation method thereof Download PDFInfo
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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Abstract
The present invention provides a kind of terminal structure of power semiconductor and preparation method thereof, including：Drift region, field oxide, the main interface of the second conductive type semiconductor, the first conductive type semiconductor heavy doping cut-off ring is lightly doped in cathodic metal electrode, the first conduction type heavily-doped semiconductor substrate, the first conductive type semiconductor；Drift region inside upper surface, which is lightly doped, in first conductive type semiconductor has provided with filled media in groove, groove, and beneath trenches are lightly doped RESURF layers provided with the second conductive type semiconductor；Second conductive type semiconductor of the invention is lightly doped RESURF layers and mutually exhausted with the first conductive type semiconductor lightly doped district above and below it, change parallel to the Electric Field Distribution on semiconductor surface direction, electric field is set to be rendered as approximate rectangular distribution, reduce terminal area under equal voltage conditions, improve chip area efficiency；And RESURF layers can be lightly doped by ion implanting the second conductive type semiconductor of formation again after digging groove, reduce technology difficulty.
Description
Technical field
The invention belongs to technical field of semiconductors, it is related to a kind of power semiconductor terminal structure and preparation method thereof.
Background technology
Power device blocks the ability of high pressure to be primarily limited to edge cellular PN junction voltage endurance capability.The PN junction meeting diffuseed to form
In diffusion window edge one cylinder knot of formation, and sphere knot is diffuseed to form at rectangle diffusion window corner, caused PN junction
Breakdown voltage be less than parallel plane junction voltage.Simultaneously as the influence of interface charge so that superficial semiconductor surface field leads to
Often it is higher than internal electric field so that the avalanche breakdown of chip occurs on surface.Knot terminal is exactly to reduce internal field, raising table
Face breakdown voltage and reliability, the special knot for making device actual breakdown voltage specially be designed closer to parallel plane knot ideal value
Structure.Knot terminal is typically distributed on the periphery of device active region in longitudinal conductive devices, is to be used to bear outer high pressure in active area
PN junction accessory structure.
At present, the power semiconductor made using planar technology, its junction termination structures is mainly in main knot edge
Some extended structures of (being often bending) setting, these extended structures play a part of the main knot outside broadening of depletion region, so that
The electric-field intensity in it is reduced, breakdown voltage, such as field plate (FP), field limiting ring (FLR), knot terminal extension (JTE), horizontal stroke is finally improved
To varying doping (VLD) etc..Realize high pressure-resistant, spatial area needed for such extended terminal is larger, and chip area efficiency is low,
It is unfavorable for reducing cost.
Therefore, the present invention changes semiconductor surface electric field and internal electric field by introducing one layer RESURF layers in termination environment
Distribution, so as to reduce terminal width, improves chip efficiency.Conventional RESURF layers are prepared by ion implanting, due to injection energy
The relation of amount, injection depth is frequently subjected to limitation, therefore differs and surely obtain optimal RESURF structures.
The content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to propose a kind of power semiconductor
RESURF structures and preparation method thereof, can be using the structure again by RESURF layers of ion implanting formation after digging groove
High breakdown voltage is obtained under less area, RESURF layers of technology difficulty is prepared while reducing.
For achieving the above object, technical solution of the present invention is as follows：
A kind of terminal structure of power semiconductor, includes successively from bottom to up：Cathodic metal electrode, cathodic metal electricity
First above the first conduction type heavily-doped semiconductor substrate, the first conduction type heavily-doped semiconductor substrate above pole is led
Drift region is lightly doped in electric type semiconductor；First conductive type semiconductor is lightly doped the upper surface of drift region and aoxidized for field
Layer；It is the main interface of the second conductive type semiconductor that upper left side inside drift region, which is lightly doped, in first conductive type semiconductor；Institute
The main interface upper surface of the second conductive type semiconductor is stated with anode metal electrodes current potential to connect；First conductive type semiconductor
Upper right side inside drift region is lightly doped, and there is the first conductive type semiconductor heavy doping to end ring；First conduction type is partly led
Drift region inside upper surface, which is lightly doped, in body has in groove, groove provided with filled media, the first conduction type half of beneath trenches
Conductor is lightly doped inside drift region and is lightly doped RESURF layers provided with the second conductive type semiconductor.
It is preferred that, the filled media in the groove is thick oxide layer.
It is preferred that, the filled media that the left and right sidewall of groove and bottom are provided with trench oxide layer, groove is many
Crystal silicon field plate.
It is preferred that, the left and right sidewall of the groove is provided with the filled media in trenched side-wall oxide layer, groove
For semi-insulating polysilicon layer, directly drift region phase is lightly doped with the first conductive type semiconductor in the semi-insulating polysilicon layer bottom
Contact, semi-insulating polysilicon layer top respectively with the metal electrode and first above the main interface of the second conductive type semiconductor
Metal electrode above conductive type semiconductor heavy doping cut-off ring is connected.
It is preferred that, the preparation method that the second conductive type semiconductor is lightly doped RESURF layers is：By etching work
Skill forms groove on the surface that drift region is lightly doped in the first conductive type semiconductor, then is formed in trench region by ion implanting
Second conductive type semiconductor is lightly doped RESURF layers.
It is preferred that, the first conduction type is N-type, and the second conduction type is p-type；Or first conduction type be P
Type, the second conduction type is N-type.
For achieving the above object, the present invention also provides a kind of preparation of the terminal structure of above-mentioned power semiconductor
Method, comprises the following steps：
(1), it is lightly doped in first conduction type heavily-doped semiconductor substrate the first conductive type semiconductor of Epitaxial growth
Drift region；
(2), drift region upper surface growth field oxide is lightly doped in the first conductive type semiconductor；
(3), photoetching active area, and boron ion injection is carried out, form the main interface of the second conductive type semiconductor；By picking
Enter process so that the main interface of the second conductive type semiconductor reaches certain junction depth；
(4), photoetching cut-off ring region, etches field oxide, and carries out phosphonium ion injection, forms the first conductive type semiconductor
Heavy doping ends ring；
(5), lithographic trenches region, etching forms groove；
(6), injected by the boron ion of high-energy and to form the second conductive type semiconductor and be lightly doped RESURF layers, then passed through
Energy and the relatively low phosphorus atoms injection of dosage, compensate the boron atom of injection, activated at foreign ion；
(7), dielectric layer deposited, fills groove, forms filled media layer, and etch away the oxide layer above device and filling
Dielectric layer；
(8), deposited oxide layer, forms field oxide；
(9), metal sputtering, and metal is anti-carved, form anode metal electrodes；Silicon chip back side is thinned, metallization forms cloudy
Pole metal electrode.
For achieving the above object, the present invention also provides a kind of preparation of the terminal structure of above-mentioned power semiconductor
Method, comprises the following steps：
(1), it is lightly doped in first conduction type heavily-doped semiconductor substrate the first conductive type semiconductor of Epitaxial growth
Drift region；
(2), drift region upper surface growth field oxide is lightly doped in the first conductive type semiconductor；
(3), photoetching active area, and boron ion injection is carried out, the main interface of the second conductive type semiconductor is formed, by picking
Enter process so that the main interface of the second conductive type semiconductor reaches certain junction depth；
(4), photoetching cut-off ring region, etches field oxide, and carries out phosphonium ion injection, forms the first conductive type semiconductor
Heavy doping ends ring；
(5), lithographic trenches region, etching forms groove；
(6), injected by the boron ion of high-energy and to form the second conductive type semiconductor and be lightly doped RESURF layers, then passed through
Energy and the relatively low phosphorus atoms injection of dosage, compensate the boron atom of injection, activated at foreign ion；
(7), deposited oxide layer, fills groove, forms thick oxide layer；
(8), metal sputtering, and metal is anti-carved, form anode metal electrodes；Silicon chip back side is thinned, metallization forms cloudy
Pole metal electrode.
For achieving the above object, the present invention also provides a kind of preparation of the terminal structure of above-mentioned power semiconductor
Method, comprises the following steps：
(1), it is lightly doped in first conduction type heavily-doped semiconductor substrate the first conductive type semiconductor of Epitaxial growth
Drift region；
(2), drift region upper surface growth field oxide is lightly doped in the first conductive type semiconductor；
(3), photoetching active area, and boron ion injection is carried out, the main interface of the second conductive type semiconductor is formed, by picking
Enter process so that the main interface of the second conductive type semiconductor reaches certain junction depth；
(4), photoetching cut-off ring region, etches field oxide, and carries out phosphonium ion injection, forms the first conductive type semiconductor
Heavy doping ends ring；
(5), lithographic trenches region, etching forms groove；
(6), injected by the boron ion of high-energy and to form the second conductive type semiconductor and be lightly doped RESURF layers, then passed through
Energy and the relatively low phosphorus atoms injection of dosage, compensate the boron atom of injection, activated at foreign ion；
(7) oxide layer, is grown, trench oxide layer is formed in the left and right sidewall of groove and bottom；
(8), dielectric layer deposited, fills groove, forms polysilicon field plate；
(9) oxide layer and polysilicon above device, are etched away；
(10), deposited oxide layer, forms field oxide；
(11), metal sputtering, and metal is anti-carved, form anode metal electrodes；Silicon chip back side is thinned, metallization forms cloudy
Pole metal electrode.
For achieving the above object, the present invention also provides a kind of preparation of the terminal structure of above-mentioned power semiconductor
Method, comprises the following steps：
(1), it is lightly doped in first conduction type heavily-doped semiconductor substrate the first conductive type semiconductor of Epitaxial growth
Drift region；
(2), drift region upper surface growth field oxide is lightly doped in the first conductive type semiconductor；
(3), photoetching active area, and boron ion injection is carried out, the main interface of the second conductive type semiconductor is formed, by picking
Enter process so that the main interface of the second conductive type semiconductor reaches certain junction depth；
(4), photoetching cut-off ring region, etches field oxide, and carries out phosphonium ion injection, forms the first conductive type semiconductor
Heavy doping ends ring；
(5), lithographic trenches region, etching forms groove；
(6), injected by the boron ion of high-energy and to form the second conductive type semiconductor and be lightly doped RESURF layers, then passed through
Energy and the relatively low phosphorus atoms injection of dosage, compensate the boron atom of injection, activated at foreign ion；
(7) oxide layer, is grown, groove-shaped oxide layer is formed；
(8), etching groove type bottom oxidization layer, forms trenched side-wall oxide layer；
(9) semi-insulating polysilicon, is deposited, groove is filled, semi-insulating polysilicon layer is formed；
(10) oxide layer and semi-insulating polysilicon above device, are etched away；
(11), deposited oxide layer, forms field oxide；
(12), metal sputtering, and metal is anti-carved, form anode metal electrodes and metal electrode；Silicon chip back side is thinned, gold
Categoryization forms cathodic metal electrode.
Beneficial effects of the present invention are：The second conductive type semiconductor beside the main interface of second conductive type semiconductor is light
RESURF layers of the first conduction type that drift region and lower section is lightly doped with the first conductive type semiconductor above it of doping are partly led
Body lightly doped district mutually exhausts, and forms space-charge region, changes parallel to the Electric Field Distribution on semiconductor surface direction, make electricity
Field is rendered as approximate rectangular distribution, the resistance to pressure energy of terminal is tried one's best and reaches the breakdown voltage of parallel plane knot, in equal voltage
Under the conditions of reduce terminal area, improve chip area efficiency, reduce production cost.And the invention is in the second conduction type half
RESURF layers of top, which are lightly doped, in conductor has groove, can partly be led by ion implanting the second conduction type of formation again after digging groove
Body is lightly doped RESURF layers, reduces the requirement to ion implantation energy, reduces technology difficulty.
Brief description of the drawings
Fig. 1 is a kind of power semiconductor terminal structure schematic diagram that the embodiment of the present invention 1 is provided；
Fig. 2-1 is a kind of power semiconductor terminal structure that is provided of the embodiment of the present invention 1 in negative electrode high voltage
Schematic diagram；
Fig. 2-2 is that a kind of power semiconductor terminal structure that the embodiment of the present invention 1 is provided divides along the electric field at AA'
Cloth schematic diagram；
Fig. 3-Figure 11 is that a kind of preparation flow for power semiconductor terminal structure that the embodiment of the present invention 1 is provided shows
It is intended to；
Figure 12 is a kind of power semiconductor terminal structure schematic diagram that the embodiment of the present invention 2 is provided；
Figure 13 is a kind of power semiconductor terminal structure schematic diagram that the embodiment of the present invention 3 is provided；
Figure 14 is a kind of power semiconductor terminal structure schematic diagram that the embodiment of the present invention 4 is provided.
Wherein, 1 is cathodic metal electrode, and 2 be the first conduction type heavily-doped semiconductor substrate, and 3 be the first conduction type
Drift region is lightly doped in semiconductor, and 4 be the main interface of the second conductive type semiconductor, and 5 be that the second conductive type semiconductor is lightly doped
RESURF layers, 6 be that the first conductive type semiconductor heavy doping ends ring, and 7 be anode metal electrodes, and 81 be field oxide, and 82 are
Thick oxide layer, 83 be trench oxide layer, and 84 be trenched side-wall oxide layer, and 9 be filled media, and 10 be polysilicon field plate, and 11 be half
Insulated polysilicon layer 12 is metal electrode, 13 be groove.
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Embodiment 1
As shown in figure 1, the present embodiment provides a kind of terminal structure of power semiconductor, include successively from bottom to up：
Cathodic metal electrode 1, the first conduction type heavily-doped semiconductor substrate 2, the first conduction type weight of the top of cathodic metal electrode 1
Drift region 3 is lightly doped in first conductive type semiconductor of the top of dope semiconductor substrates 2；First conductive type semiconductor is light
The upper surface of doped drift region 3 is field oxide 81；The inside upper left side of drift region 3 is lightly doped in first conductive type semiconductor
For the main interface 4 of the second conductive type semiconductor；The main upper surface of interface 4 of second conductive type semiconductor and anode metal electrodes
7 current potentials connect；The inside upper right side of drift region 3 is lightly doped with the first conductive type semiconductor in first conductive type semiconductor
Heavy doping ends ring 6；The inside upper surface of drift region 3, which is lightly doped, in first conductive type semiconductor has in groove 13, groove
Provided with filled media 9, the first conductive type semiconductor of the lower section of groove 13 is lightly doped the inside of drift region 3 and is provided with the second conduction type
RESURF layers 5 are lightly doped in semiconductor.
A kind of preparation method of the terminal structure of power semiconductor of the present embodiment, comprises the following steps：
(1), it is lightly doped in the first conductive type semiconductor of Epitaxial growth of the first conduction type heavily-doped semiconductor substrate 2
Drift region 3, as shown in Figure 3；
(2), the upper surface of drift region 3 growth field oxide 81 is lightly doped in the first conductive type semiconductor, as shown in Figure 4；
(3), photoetching active area, and boron ion injection is carried out, form the main interface 4 of the second conductive type semiconductor；Pass through heat
Progradation causes the main interface 4 of the second conductive type semiconductor to reach certain junction depth, as shown in Figure 5；
(4), photoetching cut-off ring region, etches field oxide 81, and carries out phosphonium ion injection, forms the first conduction type and partly leads
Body weight doping cut-off ring 6, as shown in Figure 6；
(5), lithographic trenches region, etching forms groove 13, as shown in Figure 7；
(6), injected by the boron ion of high-energy and to form the second conductive type semiconductor RESURF layers 5 are lightly doped, then led to
Cross energy and the relatively low phosphorus atoms of dosage inject, the boron atom of compensation injection, activated at foreign ion, as shown in Figure 8；
(7), dielectric layer deposited, fill groove 13, formed filled media layer 9, and etch away the oxide layer above device and
Filled media layer, as shown in Figure 9；
(8), deposited oxide layer, forms field oxide 81, as shown in Figure 10；
(9), metal sputtering, and metal is anti-carved, form anode metal electrodes 7；Silicon chip back side is thinned, metallization forms cloudy
Pole metal electrode 1, as shown in figure 11.
Illustrate the operation principle of the present invention with embodiment 1：
Below so that the first conductive type semiconductor is N-type semiconductor, the second conduction type is p-type as an example, illustrate embodiment
A kind of operation principle of the power device terminal structure provided.
In the present embodiment, when diode is in reverse blocking state, RESURF layers 5 and upper surface N is lightly doped in P-type semiconductor
Type is lightly doped drift region 3 and mutually exhausted, and forms space-charge region, the space-charge region is due to introducing longitudinal electric field component, no longer
One-dimensional Poisson's equation is met, two-dimentional Poisson's equation is met：
Wherein NDFor drift doping concentration, q is electronic charge, εsFor semiconductor permittivity.Because p-type is lightly doped
The introducing of RESURF layers 5 so that longitudinal electric field gradientNo longer it is 0, thus the change of semiconductor surface transverse electric field gradient
Slow, the electrical potential difference increase of unit length, peak surface electric field reduction, breakdown point is moved in vivo from surface, its surface field point
Cloth schematic diagram is as shown in Fig. 2-1 and 2-2.
Embodiment 2
As shown in figure 12, the present embodiment and embodiment 1 are essentially identical, and difference is：Filled media in the groove 13
For thick oxide layer 82.
A kind of preparation method of the terminal structure of power semiconductor of the present embodiment, comprises the following steps：
(1), it is lightly doped in the first conductive type semiconductor of Epitaxial growth of the first conduction type heavily-doped semiconductor substrate 2
Drift region 3；
(2), the upper surface of drift region 3 growth field oxide 81 is lightly doped in the first conductive type semiconductor；
(3), photoetching active area, and boron ion injection is carried out, the main interface 4 of the second conductive type semiconductor is formed, passes through heat
Progradation causes the main interface 4 of the second conductive type semiconductor to reach certain junction depth；
(4), photoetching cut-off ring region, etches field oxide 81, and carries out phosphonium ion injection, forms the first conduction type and partly leads
Body weight doping cut-off ring 6；
(5), lithographic trenches region, etching forms groove 13；
(6), injected by the boron ion of high-energy and to form the second conductive type semiconductor RESURF layers 5 are lightly doped, then led to
Energy and the relatively low phosphorus atoms injection of dosage are crossed, the boron atom of injection, activated at foreign ion is compensated；
(7), deposited oxide layer, fills groove 13, forms thick oxide layer 82；
(8), metal sputtering, and metal is anti-carved, form anode metal electrodes 7；Silicon chip back side is thinned, metallization forms cloudy
Pole metal electrode 1.
Embodiment 3
As shown in figure 13, the present embodiment and embodiment 1 are essentially identical, and difference is：The left and right sidewall of groove 13 and bottom
Provided with trench oxide layer 83, the filled media in groove 13 is polysilicon field plate 10.It is so light in the first conductive type semiconductor
Polysilicon field plate 10 is introduced in doped drift region 3, longitudinal electric field is produced, RESURF is lightly doped with the second conductive type semiconductor
The first conductive type semiconductor that layer 5 is pointed on RESURF layers 5 together is lightly doped drift region 3 and exhausted.The structure
Advantage is that RESURF effects can be improved further, and surface transverse electric field can further be improved.
A kind of preparation method of the terminal structure of power semiconductor of the present embodiment, comprises the following steps：
(1), it is lightly doped in the first conductive type semiconductor of Epitaxial growth of the first conduction type heavily-doped semiconductor substrate 2
Drift region 3；
(2), the upper surface of drift region 3 growth field oxide 81 is lightly doped in the first conductive type semiconductor；
(3), photoetching active area, and boron ion injection is carried out, the main interface 4 of the second conductive type semiconductor is formed, passes through heat
Progradation causes the main interface 4 of the second conductive type semiconductor to reach certain junction depth；
(4), photoetching cut-off ring region, etches field oxide 81, and carries out phosphonium ion injection, forms the first conduction type and partly leads
Body weight doping cut-off ring 6；
(5), lithographic trenches region, etching forms groove 13；
(6), injected by the boron ion of high-energy and to form the second conductive type semiconductor RESURF layers 5 are lightly doped, then led to
Energy and the relatively low phosphorus atoms injection of dosage are crossed, the boron atom of injection, activated at foreign ion is compensated；
(7) oxide layer, is grown, trench oxide layer 83 is formed in the left and right sidewall of groove 13 and bottom；
(8), dielectric layer deposited, fills groove 13, forms polysilicon field plate 10；
(9) oxide layer and polysilicon above device, are etched away；
(10), deposited oxide layer, forms field oxide 81；
(11), metal sputtering, and metal is anti-carved, form anode metal electrodes 7；Silicon chip back side is thinned, metallization is formed
Cathodic metal electrode 1.
Embodiment 4
As shown in figure 14, the present embodiment and embodiment 1 are essentially identical, and difference is：In the left and right sidewall of the groove 13
Provided with trenched side-wall oxide layer 84, the filled media in groove 13 is semi-insulating polysilicon layer 11, the semi-insulating polysilicon layer
11 bottoms are directly lightly doped drift region 3 with the first conductive type semiconductor and are in contact, 11 top of semi-insulating polysilicon layer
The conductive type semiconductor heavy doping of metal electrode 7 and first not with the top of the main interface of the second conductive type semiconductor 4 ends ring 6
The metal electrode 12 of top is connected.So it is lightly doped in the first conductive type semiconductor in drift region 3 and introduces SIPOS (half
Insulated polysilicon) 11, produce longitudinal electric field, RESURF layers 5 are lightly doped with the second conductive type semiconductor together be pointed to
The first conductive type semiconductor on RESURF layers 5 is lightly doped drift region 3 and exhausted.The advantage of the structure is RESURF effects
Fruit can further be improved, and surface transverse electric field can further be improved.And SIPOS applications can also reduce trap electricity in the terminal
The accumulation of lotus, it is to avoid terminal is pressure-resistant after long-term use degenerates, and improves device reliability.
During making devices, the semi-conducting material substituted for silicon such as carborundum, GaAs or germanium silicon are also can use.
A kind of preparation method of the terminal structure of power semiconductor of the present embodiment, comprises the following steps：
(1), it is lightly doped in the first conductive type semiconductor of Epitaxial growth of the first conduction type heavily-doped semiconductor substrate 2
Drift region 3；
(2), the upper surface of drift region 3 growth field oxide 81 is lightly doped in the first conductive type semiconductor；
(3), photoetching active area, and boron ion injection is carried out, the main interface 4 of the second conductive type semiconductor is formed, passes through heat
Progradation causes the main interface 4 of the second conductive type semiconductor to reach certain junction depth；
(4), photoetching cut-off ring region, etches field oxide 81, and carries out phosphonium ion injection, forms the first conduction type and partly leads
Body weight doping cut-off ring 6；
(5), lithographic trenches region, etching forms groove 13；
(6), injected by the boron ion of high-energy and to form the second conductive type semiconductor RESURF layers 5 are lightly doped, then led to
Energy and the relatively low phosphorus atoms injection of dosage are crossed, the boron atom of injection, activated at foreign ion is compensated；
(7) oxide layer, is grown, groove-shaped oxide layer is formed；
(8), etching groove type bottom oxidization layer, forms trenched side-wall oxide layer 84；
(9) semi-insulating polysilicon, is deposited, groove 13 is filled, semi-insulating polysilicon layer 11 is formed；
(10) oxide layer and semi-insulating polysilicon above device, are etched away；
(11), deposited oxide layer, forms field oxide 81；
(12), metal sputtering, and metal is anti-carved, form anode metal electrodes 7 and metal electrode 12；Silicon chip back side is subtracted
Thin, metallization forms cathodic metal electrode 1.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, all those of ordinary skill in the art without departing from disclosed spirit with being completed under technological thought
All equivalent modifications or change, should by the present invention claim be covered.
Claims (10)
1. a kind of terminal structure of power semiconductor, it is characterised in that include successively from bottom to up：Cathodic metal electrode
(1) the first conduction type heavily-doped semiconductor substrate (2), above cathodic metal electrode (1), the first conduction type heavy doping half
Drift region (3) is lightly doped in the first conductive type semiconductor above conductor substrate (2)；First conductive type semiconductor is gently mixed
The upper surface of miscellaneous drift region (3) is field oxide (81)；It is internal left that drift region (3) is lightly doped in first conductive type semiconductor
Top is the main interface of the second conductive type semiconductor (4)；The main interface of second conductive type semiconductor (4) upper surface and anode
Metal electrode (7) current potential connects；The internal upper right side in drift region (3), which is lightly doped, in first conductive type semiconductor has first to lead
Electric type semiconductor heavy doping cut-off ring (6)；Drift region (3) inside upper surface tool is lightly doped in first conductive type semiconductor
There is the first conductive type semiconductor being provided with groove (13), groove below filled media (9), groove (13) that drift region is lightly doped
(3) it is internal to be lightly doped RESURF layers (5) provided with the second conductive type semiconductor.
2. a kind of terminal structure of power semiconductor according to claim 1, it is characterised in that：The groove (13)
In filled media be thick oxide layer (82).
3. a kind of terminal structure of power semiconductor according to claim 1, it is characterised in that：A left side for groove (13)
The filled media that right side wall and bottom are provided with trench oxide layer (83), groove (13) is polysilicon field plate (10).
4. a kind of terminal structure of power semiconductor according to claim 1, it is characterised in that：The groove (13)
Left and right sidewall be provided with trenched side-wall oxide layer (84), the filled media in groove (13) is semi-insulating polysilicon layer (11),
Drift region (3) is directly lightly doped with the first conductive type semiconductor and is in contact for described semi-insulating polysilicon layer (11) bottom, described
At the top of semi-insulating polysilicon layer (11) respectively with the metal electrode (7) above the main interface of the second conductive type semiconductor (4) and the
Metal electrode (12) above one conductive type semiconductor heavy doping cut-off ring (6) is connected.
5. a kind of terminal structure of power semiconductor according to claim 1, it is characterised in that：Second conduction type
The preparation method that RESURF layers (5) are lightly doped in semiconductor is：Drift is lightly doped in the first conductive type semiconductor by etching technics
The surface for moving area (3) forms groove, then is lightly doped in trench region by ion implanting the second conductive type semiconductor of formation
RESURF layers (5).
6. a kind of terminal structure of power semiconductor according to claim 1 to 5 any one, it is characterised in that：
First conduction type is N-type, and the second conduction type is p-type；Or first conduction type be p-type, the second conduction type be N-type.
7. a kind of preparation method of the terminal structure of power semiconductor according to claim 1, it is characterised in that：Bag
Include following steps：
(1) drift, is lightly doped in first conduction type heavily-doped semiconductor substrate (2) first conductive type semiconductor of Epitaxial growth
Move area (3)；
(2), drift region (3) upper surface growth field oxide (81) is lightly doped in the first conductive type semiconductor；
(3), photoetching active area, and boron ion injection is carried out, formed the main interface of the second conductive type semiconductor (4)；By picking
Enter process so that the main interface of the second conductive type semiconductor (4) reaches certain junction depth；
(4), photoetching cut-off ring region, etching field oxide (81), and phosphonium ion injection is carried out, form the first conductive type semiconductor
Heavy doping cut-off ring (6)；
(5), lithographic trenches region, etching forms groove (13)；
(6), injected by the boron ion of high-energy and to form the second conductive type semiconductor RESURF layers (5) are lightly doped, then passed through
Energy and the relatively low phosphorus atoms injection of dosage, compensate the boron atom of injection, activated at foreign ion；
(7), dielectric layer deposited, filling groove (13), formed filled media layer (9), and etch away the oxide layer above device and
Filled media layer；
(8), deposited oxide layer, forms field oxide (81)；
(9), metal sputtering, and metal is anti-carved, form anode metal electrodes (7)；Silicon chip back side is thinned, metallization forms negative electrode
Metal electrode (1).
8. a kind of preparation method of the terminal structure of power semiconductor according to claim 2, it is characterised in that：Bag
Include following steps：
(1) drift, is lightly doped in first conduction type heavily-doped semiconductor substrate (2) first conductive type semiconductor of Epitaxial growth
Move area 3；
(2), drift region (3) upper surface growth field oxide (81) is lightly doped in the first conductive type semiconductor；
(3), photoetching active area, and boron ion injection is carried out, formed the main interface of the second conductive type semiconductor (4), by picking
Enter process so that the main interface of the second conductive type semiconductor (4) reaches certain junction depth；
(4), photoetching cut-off ring region, etching field oxide (81), and phosphonium ion injection is carried out, form the first conductive type semiconductor
Heavy doping cut-off ring (6)；
(5), lithographic trenches region, etching forms groove (13)；
(6), injected by the boron ion of high-energy and to form the second conductive type semiconductor RESURF layers (5) are lightly doped, then passed through
Energy and the relatively low phosphorus atoms injection of dosage, compensate the boron atom of injection, activated at foreign ion；
(7), deposited oxide layer, filling groove (13) forms thick oxide layer (82)；
(8), metal sputtering, and metal is anti-carved, form anode metal electrodes (7)；Silicon chip back side is thinned, metallization forms negative electrode
Metal electrode (1).
9. a kind of preparation method of the terminal structure of power semiconductor according to claim 3, it is characterised in that：Bag
Include following steps：
(1) drift, is lightly doped in first conduction type heavily-doped semiconductor substrate (2) first conductive type semiconductor of Epitaxial growth
Move area (3)；
(2), drift region (3) upper surface growth field oxide (81) is lightly doped in the first conductive type semiconductor；
(3), photoetching active area, and boron ion injection is carried out, formed the main interface of the second conductive type semiconductor (4), by picking
Enter process so that the main interface of the second conductive type semiconductor (4) reaches certain junction depth；
(4), photoetching cut-off ring region, etching field oxide (81), and phosphonium ion injection is carried out, form the first conductive type semiconductor
Heavy doping cut-off ring (6)；
(5), lithographic trenches region, etching forms groove (13)；
(6), injected by the boron ion of high-energy and to form the second conductive type semiconductor RESURF layers (5) are lightly doped, then passed through
Energy and the relatively low phosphorus atoms injection of dosage, compensate the boron atom of injection, activated at foreign ion；
(7) oxide layer, is grown, trench oxide layer (83) is formed in the left and right sidewall of groove (13) and bottom；
(8), dielectric layer deposited, filling groove (13) forms polysilicon field plate (10)；
(9) oxide layer and polysilicon above device, are etched away；
(10), deposited oxide layer, forms field oxide (81)；
(11), metal sputtering, and metal is anti-carved, form anode metal electrodes (7)；Silicon chip back side is thinned, metallization forms cloudy
Pole metal electrode (1).
10. a kind of preparation method of the terminal structure of power semiconductor according to claim 4, it is characterised in that：
Comprise the following steps：
(1) drift, is lightly doped in first conduction type heavily-doped semiconductor substrate (2) first conductive type semiconductor of Epitaxial growth
Move area (3)；
(2), drift region (3) upper surface growth field oxide (81) is lightly doped in the first conductive type semiconductor；
(3), photoetching active area, and boron ion injection is carried out, formed the main interface of the second conductive type semiconductor (4), by picking
Enter process so that the main interface of the second conductive type semiconductor (4) reaches certain junction depth；
(4), photoetching cut-off ring region, etching field oxide (81), and phosphonium ion injection is carried out, form the first conductive type semiconductor
Heavy doping cut-off ring (6)；
(5), lithographic trenches region, etching forms groove (13)；
(6), injected by the boron ion of high-energy and to form the second conductive type semiconductor RESURF layers (5) are lightly doped, then passed through
Energy and the relatively low phosphorus atoms injection of dosage, compensate the boron atom of injection, activated at foreign ion；
(7) oxide layer, is grown, groove-shaped oxide layer is formed；
(8), etching groove type bottom oxidization layer, forms trenched side-wall oxide layer (84)；
(9) semi-insulating polysilicon, is deposited, filling groove (13) forms semi-insulating polysilicon layer (11)；
(10) oxide layer and semi-insulating polysilicon above device, are etched away；
(11), deposited oxide layer, forms field oxide (81)；
(12), metal sputtering, and metal is anti-carved, form anode metal electrodes (7) and metal electrode (12)；Silicon chip back side is subtracted
Thin, metallization forms cathodic metal electrode (1).
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| CN109545842A (en) * | 2018-11-23 | 2019-03-29 | 中国电子科技集团公司第十三研究所 | Silicon carbide device terminal structure and preparation method thereof |
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