CN107275286B - A kind of manufacturing method of storage unit, storage unit and memory - Google Patents
A kind of manufacturing method of storage unit, storage unit and memory Download PDFInfo
- Publication number
- CN107275286B CN107275286B CN201710294055.1A CN201710294055A CN107275286B CN 107275286 B CN107275286 B CN 107275286B CN 201710294055 A CN201710294055 A CN 201710294055A CN 107275286 B CN107275286 B CN 107275286B
- Authority
- CN
- China
- Prior art keywords
- layer
- capacitance
- wordline
- work
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000003860 storage Methods 0.000 title claims abstract description 97
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 230000015654 memory Effects 0.000 title claims abstract description 20
- 239000010410 layer Substances 0.000 claims abstract description 636
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 238000000034 method Methods 0.000 claims abstract description 19
- 230000003252 repetitive effect Effects 0.000 claims abstract description 8
- 239000011241 protective layer Substances 0.000 claims abstract description 7
- 239000000463 material Substances 0.000 claims description 127
- 239000003990 capacitor Substances 0.000 claims description 64
- 229910052751 metal Inorganic materials 0.000 claims description 51
- 239000002184 metal Substances 0.000 claims description 51
- 238000000151 deposition Methods 0.000 claims description 29
- 238000005530 etching Methods 0.000 claims description 23
- 239000010936 titanium Substances 0.000 claims description 19
- 230000015572 biosynthetic process Effects 0.000 claims description 18
- 230000005611 electricity Effects 0.000 claims description 18
- 229910052719 titanium Inorganic materials 0.000 claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 230000006870 function Effects 0.000 claims description 13
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 12
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 12
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 230000009194 climbing Effects 0.000 claims description 10
- 230000008021 deposition Effects 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 229910019044 CoSix Inorganic materials 0.000 claims description 7
- 229910005889 NiSix Inorganic materials 0.000 claims description 7
- 229910008486 TiSix Inorganic materials 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- 229910052759 nickel Inorganic materials 0.000 claims description 7
- 229910052697 platinum Inorganic materials 0.000 claims description 7
- 229910052721 tungsten Inorganic materials 0.000 claims description 7
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 6
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 6
- 229910001925 ruthenium oxide Inorganic materials 0.000 claims description 6
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 claims description 6
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 6
- 229910018316 SbOx Inorganic materials 0.000 claims description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 229910017052 cobalt Inorganic materials 0.000 claims description 2
- 239000010941 cobalt Substances 0.000 claims description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 2
- ZARVOZCHNMQIBL-UHFFFAOYSA-N oxygen(2-) titanium(4+) zirconium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4] ZARVOZCHNMQIBL-UHFFFAOYSA-N 0.000 claims description 2
- 229910021332 silicide Inorganic materials 0.000 claims description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 150000001875 compounds Chemical class 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 8
- 230000010354 integration Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 11
- 229920005591 polysilicon Polymers 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 229910052681 coesite Inorganic materials 0.000 description 4
- 229910052906 cristobalite Inorganic materials 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 230000001276 controlling effect Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000000407 epitaxy Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910017107 AlOx Inorganic materials 0.000 description 2
- 241000209094 Oryza Species 0.000 description 2
- 235000007164 Oryza sativa Nutrition 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 235000009566 rice Nutrition 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000008961 swelling Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
Abstract
The present invention provides a kind of manufacturing method of storage unit, storage unit and memory, passes through substrate of the offer with wordline；Form gate electrode；Work-function layer, length direction and wordline are formed into first angle；Deposit active layer；Form side wall；Form drain electrode and bit line, bit line is with active layer extending direction into second angle, with wordline into third angle；Form the protective layer of bit line；Form multi-medium-layer；Multi-medium-layer is etched, forms stepped capacitance groove, and form capacitance and top electrode.The protuberance road area of transistor is distributed along the side of work-function layer and top surface in the present invention, is formed the transistor arrangement of vertical-channel, is effectively inhibited short-channel effect so that transistor can have superperformance in technique micro；Capacitance employs stepped groove and is prepared, and has two-layered medium layer, effectively increases the area of capacitance, and then improve capacitance；In addition, the repetitive unit area occupied in the storage unit can reach 4F2, there is high integration.
Description
Technical field
The present invention relates to a kind of manufacturing method of storage unit, storage unit and memories, have more particularly to one kind
Manufacturing method, storage unit and the memory of the storage unit of 4F2 cellar areas.
Background technology
Dynamic RAM (English：Dynamic Random Access Memory, referred to as：DRAM it is) a kind of extensive
Semiconductor memory applied to computer system.DRAM is made of multiple storage units, and each storage unit generally includes crystalline substance
Body pipe and capacitance；The grid of transistor is electrically connected with wordline, source electrode is electrically connected with bit line, drain electrode is electrically connected with capacitance, wordline
On word line voltage be capable of the opening and closing of controlling transistor, so as to which the data being stored in capacitance can be read by bit line
Data information is written in capacitance by information.
In order to prepare more storage units in compared with small area, the integrated level of DRAM is improved, it usually needs carry out
Technique micro；By the size for reducing transistor and/or capacitance so that storage unit has smaller area.Current usual one
The area of a storage unit is 2F × 3F=6F2, wherein F is " characteristic size " the i.e. size of wordline.
However, inventors discovered through research that, when carrying out technique micro, the performance of transistor and capacitance is with size
Reduction can also generate larger deterioration.For transistor, with becoming smaller for transistor size, short-channel effect is also increasingly
Significantly, i.e., the threshold voltage of transistor can become smaller with becoming smaller for transistor size, and word line voltage smaller so just can
Transistor is opened, so as to cause the mistake of read-write, short-channel effect is also possible to the punch-through failure for leading to transistor when serious.For
For capacitance, so that the quantity of electric charge for storage is reduced therewith, the reduction of the quantity of electric charge causes different data for the diminution of capacitor size
Signal difference corresponding to information (" 0 " and " 1 "), in this way, when carrying out data information reading, may lead to data information away from becoming smaller
Misread.
Therefore, device performance degradation caused by how overcoming above-mentioned technique micro, and then the integrated level of DRAM is improved, it is this
The technical issues of field technology personnel's urgent need to resolve.
Invention content
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of manufacturers of storage unit
Method, storage unit and memory, for solving the problems, such as that technique micro causes device performance degradation in the prior art, improves DRAM
Integrated level.
In order to achieve the above objects and other related objects, the present invention provides a kind of manufacturing method of storage unit, this method
Include the following steps：
Substrate is provided, and in formation is buried by first medium layer on the substrate the first wordline and the second wordline；
The first medium layer is etched based on the first litho pattern so that in forming the first gate groove in first wordline
And in forming the second gate groove in second wordline, and to form the in filling grid metal in first gate groove
One gate electrode and in second gate groove fill grid metal formed the second gate electrode；
Based on first litho pattern, in forming the first work-function layer in the first gate electrode and embossed in described
On one dielectric layer, and the first gate dielectric layer is formed in the embossed surface of first work-function layer；In on second gate electrode
It forms the second work-function layer and embossed on the first medium layer, and the is formed in the embossed surface of second work-function layer
Two gate dielectric layers, wherein, the angle between the length direction of first work-function layer and first wordline and described
Angle between the length direction of two work-function layers and second wordline into the first angle more than 0 degree and less than 90 degree,
The overlapping part of first work-function layer and the first wordline, the overlapping part pair with second work-function layer and the second wordline
Claim setting；
In depositing active layer on the first medium layer, the active layer includes climbing the of first work-function layer
One protuberance road area, is connected to the first protuberance road area and described at the second protuberance road area for climbing second work-function layer
Between the second protuberance road area and drain region of Cheng Guzhuan recess is connected to the first protuberance road area and is formed in the first medium
First source region of floor is connected to the second protuberance road area and the second source region being formed on the first medium floor；
Second dielectric layer is formed in the surface of the active layer；
Correspond to the lateral surface of first source region and second source region and the drain region in the second dielectric layer
On be respectively formed corresponding to the active layer side with center the first material the first side wall；
In the first side wall side, the edge of the second dielectric layer, Yi Jisuo corresponding to the active layer side
The edge for stating active layer forms the second side wall of the second material；
Based on the second litho pattern, etching removes first side for corresponding to active layer center on the drain region
Wall forms drain electrode groove, and in forming drain electrode in the drain electrode groove；
Form bit line in deposition on the drain electrode, the bit line is in electrical contact with drain electrode, the bit line with it is described active
Angle between the extending direction of layer is into second angle, angle between the bit line and first wordline and with described second
Angle between wordline is into third angle；
Protective layer is formed in the top of the bit line and side；
The first material of alternating deposit and the second material form multi-medium-layer with multi-layer structure successively；
Based on third litho pattern, the first material of autoregistration selective etch and the second material, corresponding to the active layer
First side wall of side is until the exposure active layer so that includes in formation in the first source region of the active layer multiple
First capacitance groove of step structure and in the second source region of the active layer formed include multiple step structures
Second capacitance groove；
In sequentially forming the first capacitance bottom crown, the first capacitor dielectric layer in the first capacitance groove, on the first capacitance
Pole plate forms the first capacitance；In sequentially formed in the second capacitance groove the second capacitance bottom crown, the second capacitor dielectric layer,
Second capacitance top crown forms the second capacitance；And
In forming top electrode on the first capacitance top crown and the second capacitance top crown.
Optionally, the step of, includes：
The first medium layer of the first material is formed in the substrate surface；
In deposition wordline metal layer on the first medium layer；
The wordline metal layer is etched, obtains first wordline and second wordline；
Depositing first material buries first wordline and second wordline.
Optionally, the portion bottom surface of the first gate electrode locally coincides with first wordline, the two gate electrode
Portion bottom surface coincide with second wordline；And the first gate electrode and the first wordline overlapping area are relative to institute
State first gate electrode floor space ratio and second gate electrode relative to the second wordline overlapping area and second gate
The ratio of electrode floor space is between 35% to 99.8%.
Optionally, during first side wall is formed with second side wall, including：
Based on the 4th litho pattern, etching forms the active layer and the edge of the second dielectric layer；
Depositing first material, in the corresponding second dielectric layer side of first source region, second source region corresponding
The corresponding second dielectric layer side in second medium layer side and the drain region forms first side wall of the first material；
Based on the 4th litho pattern, etching forms the edge of first side wall corresponding to the active layer side；
The dielectric layer of depositing second material forms the second side wall, and polish to expose in the side of first side wall
State the top surface of the first side wall.
Optionally, it before depositing second material, further includes：
Based on the 4th litho pattern, the first medium layer except the active layer overlay area is etched, makes etching
There are spacing for rear first medium layer top surface and the first medium layer top surface that does not etch.
Optionally, the spacing between the first work-function layer height or the second work-function layer height 1% to
98%.
Optionally, in the forming process of first capacitance and second capacitance, including：
In forming the first capacitance bottom crown in the first capacitance groove, in the second electricity of formation in the second capacitance groove
Pole plate is held, the first capacitance bottom crown and the first capacitance groove are conformal, the second capacitance bottom crown and the second capacitance ditch
Slot is conformal；
Etch the second material at the top of multi-medium-layer on the bit line, and the first material of exposure；
The first material that etching off exposes；
The first capacitor dielectric layer is formed, and in described the in the inner wall of the first capacitance bottom crown and the outer wall of exposure
The inner wall of two capacitance bottom crowns and the outer wall of exposure form the second capacitor dielectric layer；And
In the upper first capacitance top crown of formation on the first capacitor dielectric layer, and on the second capacitor dielectric layer
Form the second capacitance top crown.
Optionally, the first angle is between 25 degree to 35 degree, and the second angle is between 12 degree to 60 degree, the third
Angle is between 28 degree to 90 degree.
Optionally, the figure of any first work-function layer and the figure of second work-function layer include arc
Or rectangle.
The embodiment of the present invention also provides a kind of storage unit, and the storage unit includes at least：
The first medium layer of substrate and setting over the substrate；
First wordline and the second wordline, first wordline and second wordline be buried in the first medium layer,
And it is spaced from each other by the first medium layer；
First gate electrode and the second gate electrode, the first gate electrode pass through the first medium layer and are set to described the
It is overlapped in one wordline and with first word line portion, second gate electrode passes through the first medium layer and is set to described
It is overlapped in second wordline and with second word line portion；
First work-function layer and the second work-function layer are set to the top surface of the first gate electrode and embossed in described first
On dielectric layer, second work-function layer is set to the top surface of second gate electrode and embossed on the first medium layer,
The length of angle and second work-function layer between the length direction of first work-function layer and first wordline
Angle between direction and second wordline is into the first angle more than 0 degree and less than 90 degree, first work-function layer
With the overlapping part of the first wordline, it is symmetrical arranged with the overlapping part of second work-function layer and the second wordline；
First gate dielectric layer and the second gate dielectric layer, first gate dielectric layer are formed in the floating of first work-function layer
Prominent surface, second gate dielectric layer are formed in the embossed surface of second work-function layer；
Active layer is deposited on the first medium layer, and the active layer includes climbing first work-function layer
First protuberance road area, is connected to the first protuberance road area and institute at the second protuberance road area for climbing second work-function layer
State between the second protuberance road area and in the drain region of paddy shape recess, be connected to the first protuberance road area and be formed in described first and be situated between
The first source region on matter floor is connected to the second protuberance road area and the second source region being formed on the first medium floor；
Drain electrode and bit line are in electrical contact on the drain region and with the drain region；The bit line is in electrical contact with the drain electrode,
The extending direction of the bit line and the active layer into second angle, angle between the bit line and first wordline and with
The angle of second wordline is into third angle；
Second dielectric layer is at least covered on the active layer；And
First capacitance groove and the second capacitance groove, the first capacitance groove is set in first source region, described
Second capacitance groove is set in second source region.
Optionally, the storage unit further includes：
First capacitance bottom crown and the second capacitance bottom crown, the first capacitance bottom crown connect with the first source region electricity
It touching, the first capacitance bottom crown extends along the inner wall of the first capacitance groove to the direction far from the substrate, and described the
One capacitance bottom crown includes multiple step structures；The second capacitance bottom crown and second source region are in electrical contact, and described the
Two capacitance bottom crowns extend along the inner wall of the second capacitance groove to the direction far from the substrate, pole under second capacitance
Plate includes multiple step structures；
First capacitor dielectric layer and the second capacitor dielectric layer, the first capacitor dielectric layer are formed under first capacitance
The surface of pole plate exposure, the second capacitor dielectric layer are formed in the surface of the second capacitance bottom crown exposure；
First capacitance top crown and the second capacitance top crown, the first capacitance top crown are formed in first capacitance and are situated between
The surface of matter layer exposure, the second capacitance top crown are formed in the surface of the second capacitor dielectric layer exposure；And
The top electrode being in electrical contact with above-mentioned first capacitance top crown and the second capacitance top crown.
Optionally, the drain electrode includes the first metal layer and the second metal being deposited on the first metal layer
Layer, the first metal layer are in electrical contact with the drain region；
The top electrode includes first electrode layer and the second electrode lay being deposited in the first electrode layer, described
First electrode layer is in electrical contact with the first capacitance top crown and the second capacitance top crown.
Optionally, first wordline, second wordline, the bit line, the first electrode layer and second gold medal
The material for belonging to layer includes one or more groups of tungsten (W), titanium (Ti), nickel (Ni), aluminium (Al), platinum (Pt) and DOPOS doped polycrystalline silicon
It closes；The second electrode lay, the first metal layer, the first gate electrode and second gate electrode material include nitridation
One or more combinations of titanium (TiN), Titanium silicide (TiSix), cobalt silicide (CoSix) and nickel silicide (NiSix)；Institute
State the first wordline, second wordline, the bit line, the first metal layer, the second metal layer, the first electrode
The resistivity of layer, the second electrode lay, the first gate electrode and second gate electrode between 2 × 10-8 Ω m to 1 ×
102Ω·m。
Optionally, the active layer include silicon epitaxy layer or polysilicon layer, and the thickness of the active layer between 3nm extremely
2000nm。
Optionally, the material of first work-function layer and second work-function layer includes titanium nitride (TiN) or doping
Polysilicon, and there are work function difference, second work contents in the first protuberance road area of first work-function layer and the active layer
There are work function differences in second protuberance road area of several floor and the active layer.
Optionally, the first medium layer, the second dielectric layer, first gate dielectric layer and second gate medium
The material of layer includes one or more combinations of silicon nitride (SiN), silicon oxynitride (SiON) and silica (SiO2), and have
Between 2 × 1011 Ω m to the resistivity of 1 × 1025 Ω m.
Optionally, the material of the first capacitor dielectric layer and the second capacitor dielectric layer include zirconium oxide (ZrOx),
Hafnium oxide (HfOx), titanium oxide zirconium (ZrTiOx), ruthenium-oxide (RuOx), the one kind or more for aoxidizing (SbOx) and aluminium oxide (AlOx)
The combination of kind, and with the relative dielectric constant more than 10.
Optionally, in the storage unit repetitive unit area multiplying for 2 times of half spacing of wordline and 2 times of half spacing of bit line
Product.
Optionally, the first capacitance top crown, the first capacitor dielectric layer, the first capacitance bottom crown form the
One capacitance, the second capacitance top crown, the second capacitor dielectric layer, the second capacitance bottom crown form the second capacitance,
First capacitance and the second capacitance are cylindric capacitance.
Optionally, the first angle is between 25 degree to 35 degree, and the second angle is between 12 degree to 60 degree, the third
Angle is between 28 degree to 90 degree.
Optionally, the figure of any first work-function layer and the figure of second work-function layer include arc
Or rectangle.
The embodiment of the present invention also provides a kind of memory, and the memory includes at least the described storage of above-described embodiment
Unit.
As described above, manufacturing method, storage unit and the memory of the storage unit of the present invention, have below beneficial to effect
Fruit：By providing substrate, and in formation is buried by first medium layer on the substrate the first wordline and the second wordline；Based on
One litho pattern etches first medium layer, in forming the first gate groove in the first wordline, in the second gate groove in the second wordline；In
Filling grid metal forms first gate electrode in first gate groove and second gate, and second is formed in filling grid metal in the second gate groove
Gate electrode；Based on the first litho pattern, in forming the first work-function layer in first gate electrode, and in the first work-function layer surface shape
Into the first gate dielectric layer；In forming the second work-function layer on the second gate electrode, and second gate is formed in the second work-function layer surface
Dielectric layer；Wherein, the length direction of first work-function layer and the length direction of the first wordline and the second work-function layer with
Second wordline, into first angle；Active layer is deposited, the first protuberance road area is formed in the active layer for covering the first work-function layer,
The second protuberance road area is formed in the active layer for covering the second work-function layer, between the first work-function layer and the second work-function layer
Active layer forms drain region, the first source region is formed in the remaining active layer close to the first work-function layer, in close to the second work-function layer
Remaining active layer formed the second source region；Second dielectric layer is formed in active layer surface；In the corresponding second medium of the first source region
Layer side, the corresponding second dielectric layer side in the corresponding second dielectric layer side of the second source region and drain region form the first material
The first side wall；The second side wall of the second material is formed in the first side wall side；Based on the second litho pattern, etch on drain region
First side wall forms drain electrode groove, and in forming drain electrode in the drain electrode groove；It is formed in being deposited on the drain electrode
Bit line, the bit line and drain electrode are in electrical contact, the extending direction of the bit line and active layer into second angle, with the first wordline and
Second wordline is respectively into third angle；Protective layer is formed in the top of bit line and side；The first material of alternating deposit and successively
Two materials form multi-medium-layer with multi-layer structure；Based on third litho pattern, the first material of autoregistration selective etch and
Second material includes the first capacitance ditch of multiple step structures until exposure active layer in formation in the first source region of active layer
Slot and include the second capacitance groove of multiple step structures in being formed in the second source region of active layer；In the first capacitance ditch
The first capacitance bottom crown, the first capacitor dielectric layer, the first capacitance top crown are sequentially formed in slot, forms the first capacitance；In second
The second capacitance bottom crown, the second capacitor dielectric layer, the second capacitance top crown are sequentially formed in capacitance groove, forms the second capacitance；
In forming top electrode on the first capacitance top crown and the second capacitance top crown.Transistor is grand in storage unit prepared by this method
Track lifting area is distributed along the side of work-function layer and top surface, the transistor arrangement of vertical-channel is formed, accordingly even when in transverse direction
Upper channel dimensions reduce, and protuberance road area are still remained in vertical direction, so as to inhibit short-channel effect so that transistor can
Still there is superperformance in technique micro；Moreover, the capacitance being electrically connected with transistor, employs stair-stepping groove
It is prepared, and the capacitance has two-layered medium layer, increases effectively the area of capacitance, and then improve capacitance；It in addition, should
Repetitive unit area occupied in storage unit can reach 4F2, have very high integrated level.
Description of the drawings
Fig. 1 is shown as a kind of flow diagram of memory unit making process provided in an embodiment of the present invention.
Fig. 2 to Figure 20 is shown as the structural representation of each step of manufacturing method of storage unit provided in an embodiment of the present invention
Figure.
Component label instructions
11 first litho patterns
12 second litho patterns
13 third litho patterns
14 the 4th litho patterns
100 substrates
101 first medium layers
102 active layers
1021 first protuberance road areas
1022 second protuberance road areas
1023 drain regions
1024 first source regions
1025 second source regions
103 second dielectric layer
104th, 1041,1042,1,043 first side wall
105 second side walls
106 drain electrodes
1061 the first metal layers
1062 second metal layers
107 multi-medium-layers
1071st, 1072,1073,1074 material layer
110 first gate electrodes
111 first work-function layers
112 first gate dielectric layers
120 second gate electrodes
121 second work-function layers
122 second gate dielectric layers
201 first wordline
202 second wordline
300 bit lines
401 first capacitance grooves
402 second capacitance grooves
410 first capacitance bottom crowns
411 first capacitor dielectric layers
412 first capacitance top crowns
420 second capacitance bottom crowns
421 second capacitor dielectric layers
422 second capacitance top crowns
500 top electrodes
5001 first electrode layers
5002 the second electrode lays
S1~S10 steps
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
It please refers to Fig.1 to Figure 20.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, package count when only display is with related component in the present invention rather than according to actual implementation in illustrating then
Mesh, shape and size are drawn, and kenel, quantity and the ratio of each component can be a kind of random change during actual implementation, and its
Assembly layout kenel may also be increasingly complex.
Fig. 1 is referred to, for a kind of flow diagram of the manufacturing method of storage unit provided in an embodiment of the present invention, the system
The method of making includes the following steps：
Step S1：Substrate 100 is provided, and in the first wordline that formation is buried by first medium layer 101 on the substrate 100
201 and second wordline 202；
Step S2：The first medium layer 101 is etched based on the first litho pattern 11 so that in first wordline 201
The first gate groove of upper formation and in forming the second gate groove in second wordline 202, and cause in the first grid ditch
Filling grid metal forms first gate electrode 110 and forms the second gate electrode in filling grid metal in second gate groove in slot
120；
Step S3：Based on first litho pattern 11, in forming the first work-function layer in the first gate electrode 110
111 and it is embossed on the first medium layer 101, and form the first grid in the embossed surface of first work-function layer 111 and be situated between
Matter layer 112；In forming the second work-function layer 121 on second gate electrode 120 and embossed on the first medium layer 101,
And the second gate dielectric layer 122 is formed in the embossed surface of second work-function layer 121, wherein, first work-function layer 111
Length direction and first wordline 201 between angle and second work-function layer 121 length direction with it is described
Angle between second wordline 202 is into the first angle more than 0 degree and less than 90 degree, first work-function layer 111 and the
The overlapping part of one wordline 201 is symmetrical arranged with the overlapping part of 121 and second wordline 202 of the second work-function layer；
Step S4：In depositing active layer 102 on the first medium layer 101, the active layer 102 includes climbing described
First protuberance road area 1021 of the first work-function layer 111, the second protuberance road area for climbing second work-function layer 121
1022nd, it is connected between the first protuberance road area 1021 and the second protuberance road area 1022 and in the drain region of paddy shape recess
1023rd, the described first the first source region 1024 swelled road area 1021 and be formed on the first medium floor 101, connection are connected to
Road area 1022 and the second source region 1025 being formed on the first medium floor 101 are swelled in described second；
Step S5：Second dielectric layer 103 is formed in 102 surface of active layer, is corresponded in the second dielectric layer 103 described
First source region 1024 has with being respectively formed on the lateral surface of second source region 1025 and the drain region 1023 corresponding to described
102 side of active layer and the first side wall 104 of first material in center, in corresponding to described the first of 102 side of active layer
The edge of 104 side of side wall, the edge of the second dielectric layer 103 and the active layer 102 forms the second of the second material
Side wall 105；
Step S6：Based on the second litho pattern 12, the first side for corresponding to active layer center on drain region 1023 is etched
Wall 104 forms drain electrode groove, and in formation drain electrode 106 in the drain electrode groove；
Step S7：Bit line 300 is formed in deposition on the drain electrode 106, the bit line 300 is in electrical contact with drain electrode 106,
The extending direction of the bit line 300 and active layer 102 is into second angle, between the bit line 300 and first wordline 201
Angle and angle between second wordline 202 form protection into third angle in the top of bit line 300 and side
Layer；
Step S8：The first material of alternating deposit and the second material form multi-medium-layer 107 with multi-layer structure, base successively
In third litho pattern 13, the first material of autoregistration selective etch and the second material, corresponding to 102 side of active layer
First side wall 104 is until the exposure active layer 102 so that includes in being formed in the first source region 1024 of active layer 102
First capacitance groove 401 of multiple step structures and in the second source region 1025 of active layer 102 formed include multiple ranks
Second capacitance groove 402 of ladder configuration；
Step S9：In sequentially forming the first capacitance bottom crown 410, the first capacitor dielectric layer in the first capacitance groove 401
411st, the first capacitance top crown 412 forms the first capacitance；In sequentially forming the second capacitance bottom crown in the second capacitance groove 402
420th, the second capacitor dielectric layer 421, the second capacitance top crown 422 form the second capacitance；
Step S10：In formation top electrode 500 on the first capacitance top crown 412 and the second capacitance top crown 422.
In step sl, the flow diagram of the manufacturing method of storage unit shown in Figure 1 and referring also to Fig. 2,
Structure as shown in Figure 2 is divided into first area and second area, it should be noted that can form first in first area
Storage unit can form the second storage unit on the second region, for a clear description the treatment process at storage unit edge,
Fig. 2 to Figure 20 in the embodiment of the present invention shows the structure diagram including at least 2 storage units；Moreover, because storage
The manufacturing method of unit is consistent with structure, and for convenience, the embodiment of the present invention is only with the storage unit in first area
It is described in detail for manufacturing method and structure.
In embodiments of the present invention, substrate 100 can be the silicon substrates such as silicon on silicon epitaxial wafer, insulating layer, or GaN
Deng the substrate of other semi-conducting materials, and the substrate 100 can be intrinsic semiconductor substrate or carry out n-type doping or
The Semiconductor substrate of person's p-type doping, does not limit in embodiments of the present invention.It is formed with first medium layer on the substrate 100
101, the first wordline 201 and the second wordline 202 are buried by first medium layer 101, in order to form structure shown in Fig. 2, step
S1 may comprise steps of：
Step S11：The first medium layer 101 of the first material is formed in 100 surface of substrate.
The first medium layer 101 of the first material is formed in 100 surface of substrate, wherein, the first medium layer 101 is used
The first material can be SiN, SiON and SiO2One or more combinations of material.In the specific implementation, original can be passed through
Sublayer deposition (English：Atomic Layer Deposition, referred to as：ALD), physical vapour deposition (PVD) (English：Physical
Vapor Deposition, referred to as：PVD) and chemical vapor deposition is (English：Chemical Vapor Deposition, referred to as：
CVD) the methods of, forms the first medium layer 101；Moreover, in one exemplary embodiment, the electricity of the first medium layer 101
Resistance rate is between 2 × 1011 Ω m (ohm meter) to 1 × 1025 Ω m (ohm meter), the thickness of the first medium layer 101
Degree is between 3nm (nanometer) to 2000nm (nanometer).
Step S12：In deposition wordline metal layer on first medium layer 101.
The methods of again may be by ALD, PVD or CVD deposits wordline metal layer.
Step S13：The wordline metal layer is etched, obtains the first wordline 201 and the second wordline 202.
The shape and spacing of the first wordline 201 and the second wordline 202 are defined by the mask plate with wordline litho pattern,
And the wordline metal layer is etched, so as to obtain the first wordline 201 and the second wordline 202.In embodiments of the present invention, to described
The shape and spacing of first wordline 201 and the second wordline 202 do not limit, and 201 and second wordline 202 of the first wordline can be with
For the wordline of arbitrary shape, such as strip etc., and also first wordline, 201 and second wordline 202 may have spacing, phase
It is mutually parallel.The embodiment of the present invention will be with the first wordline 201 being mutually parallel, strip shown in Fig. 3 and the second wordline 202
The manufacturing method of storage unit is discussed in detail in example.In one exemplary embodiment, 201 and second wordline 202 of the first wordline
It can include the one or more of W, Ti, Ni, Al, Pt and DOPOS doped polycrystalline silicon, and first wordline, 201 and second wordline 202
Resistivity between 2 × 10-8 Ω m (ohm meter) to 1 × 102 Ω m (ohm meter).
Step S14：Depositing first material buries the first wordline 201 and the second wordline 202.
It is defined by step S13 after completing the first wordline 201 and the second wordline 202, continues depositing first material and bury
First wordline 201 and the second wordline 202, form new first medium layer 101.
In step s 2, showing for the first litho pattern used in step S2 is performed for the embodiment of the present invention referring to Fig. 3
It is intended to, referring also to Fig. 4 is the cross section structure schematic diagram in A-A directions shown in Fig. 3 provided in an embodiment of the present invention.Such as Fig. 3 institutes
Show, which defines multiple rectangular apertures, the length direction of the rectangular aperture and the first wordline 201 or the
Two wordline 202 are there are first angle α, moreover, the rectangular aperture partially overlaps with the first wordline 201 and the second wordline 202；
First litho pattern is used to define gate electrode in subsequent step, work-function layer and swells region and the shape in road area.
Certainly, it should be noted that opening is only an exemplary embodiment defined in first litho pattern, in the specific implementation,
Or other shapes than rectangular, such as ellipse, fan ring-shaped etc., it does not limit in embodiments of the present invention；
In a preferred embodiment, the shape of the opening can be arc, can define gate electrode, the work-function layer of arc in this way
And protuberance road area, as long as and first litho pattern 11 defined in opening there are setting sides shown in Fig. 3 with wordline
Formula should all fall into protection scope of the present invention.
As shown in figure 4, based on the first litho pattern 11, etching first medium layer 101, in forming the in the first wordline 201
One gate groove (does not identify) in figure, in forming the second gate groove (not identified in figure) in the second wordline 202；In the first gate groove and
Fill grid metal in second gate groove, so as to form 110 and second gate electrode 120 of first gate electrode, first gate electrode 110 with
First wordline 201 is in electrical contact, and the second gate electrode 120 is in electrical contact with the second wordline 202.According to defined in the first litho pattern 11
Opening, the length direction of first gate electrode 110 and the first wordline 201 and the second gate electrode 120 and the second wordline 202 into
First angle α, the portion bottom surface of first gate electrode 110 coincide with the first wordline 201, the portion bottom surface of the second gate electrode 120
It coincides with the second wordline 202.Preferably, 110 and first wordline of first gate electrode, 201 overlapping area and first gate electrode 110
The ratio of the ratio of floor space and the second gate electrode 120 and 120 floor space of 202 overlapping area of the second wordline and the second gate electrode
Example is between 35% to 99.8%.Wherein, 110 and second gate electrode 120 of first gate electrode can use TiN, TiSix、
CoSixAnd NiSixOne or more combinations, resistivity is between 2 × 10-8 Ω m between 1 × 102 Ω m.
In step s3, see also Fig. 3 and Fig. 4, based on being open defined in the first litho pattern 11, in first grid electricity
The first work-function layer 111 is formed on pole 110, and the first gate dielectric layer 112 is formed in 111 surface of the first work-function layer；In second
The second work-function layer 121 is formed on gate electrode 120, and the second gate dielectric layer 122 is formed in 121 surface of the second work-function layer；Its
In, the length direction of first work-function layer 111 and the length direction of the first wordline 201 and the second work-function layer 121 with
Second wordline 202 is into first angle α.Optionally, the first angle α in the embodiment of the present invention is between 25 degree to 35 degree, in this way
By controlling first angle α, the arrangement of storage unit can be optimized so that can when preparing memory using the storage unit
It is optimal layout, so as to improve the integrated level of memory.Moreover, the friendship of 111 and first wordline 201 of the first work-function layer
Folded part, is symmetrical arranged with the overlapping part of 121 and second wordline 202 of the second work-function layer, in an exemplary embodiment
In, described be symmetrical arranged can be understood as being symmetrical arranged along device extending direction A-A directions for example shown in Fig. 3.In addition, institute
TiN layer or doped polysilicon layer can be used by stating the first work-function layer 111 and the second work-function layer 121, by regulating and controlling the first work(
111 and second work-function layer 121 of function layer and the work function difference of active layer 102, can be in protuberance road area accordingly in formation
Potential is built, such as enhanced transistor, can be exhausted by the way that work function difference is controlled to be formed in active layer 102
Area, and then offset Built-in potential, control raceway groove conducting by applying gate voltage.In addition, for the first gate dielectric layer 112 and
Two gate dielectric layers 122, when 111 and second work-function layer 121 of the first work-function layer be TiN when can be by way of deposition
The first gate dielectric layer 112 and are respectively formed in the top surface and two sides of the first work-function layer 111 and the second work-function layer 121
Two gate dielectric layers 122；When 111 and second work-function layer 121 of the first work-function layer is polysilicon, oxidation can be passed through
Mode is respectively formed the first gate dielectric layer in the top surface and two sides of the first work-function layer 111 and the second work-function layer 121
112 and second gate dielectric layer 122；First gate dielectric layer, 112 and second gate dielectric layer 122 can be SiN, SiON and SiO2
One or more combinations, and resistivity is between 2 × 1011 Ω m (ohm meter) to 1 × 1025 Ω m (ohms
Rice).
In step s 4, referring to Fig. 5, active layer 102 is deposited, is formed in the active layer 102 for covering the first work-function layer 111
First protuberance road area 1021 forms the second protuberance road area 1022, in first in the active layer 102 for covering the second work-function layer 121
Active layer 102 between 111 and second work-function layer 121 of work-function layer forms drain region 1023, in close to the first work-function layer 111
Remaining active layer 102 formed the first source region 1024, in close to the second work-function layer 121 remaining active layer 102 formed second
Source region 1025.It should be noted that as shown in figure 5, the first protuberance road area 1021 is is covered in first work-function layer
111 two sides and the active layer 102 of top surface, the second protuberance road area 1022 is to be covered in the first work-function layer 111
Two sides and the active layer 102 of top surface；The drain region 1023 is between the first work-function layer 111 and the second work-function layer 121
Active layer 102；First source region 1024 is is distributed in 111 edge of the first work-function layer, on first medium layer 101
Active layer 102, second source region 1025 is is distributed in 121 edge of the second work-function layer, on first medium layer 101
Active layer 102.In embodiments of the present invention, the active layer 102 can be silicon epitaxy layer or polysilicon layer, and described active
Layer 102 can carry out N-type or p-type doping, doping concentration not limited in embodiments of the present invention, those skilled in the art
Can corresponding doping concentration be set according to actual transistor demand；Moreover, the thickness of the active layer 102 (is received between 3nm
Rice) to 2000nm (nanometer).
In step s 5, second dielectric layer 103 is formed in 102 surface of active layer；In the first source region 1024 corresponding second
103 side of dielectric layer, 1025 corresponding 103 side of second dielectric layer of the second source region and 1023 corresponding second medium of drain region
103 side of layer form the first side wall 104 of the first material；The second side wall of the second material is formed in 104 side of the first side wall
105.See also Fig. 5, as shown in figure 5, forming second dielectric layer 103, the second dielectric layer 103 in 102 surface of active layer
Can be SiN, SiON and SiO2One or more combinations, resistivity between 2 × 1011 Ω m (ohm meter) to 1 ×
Between 1025 Ω m (ohm meter), and the second dielectric layer 103 can select the material identical with the second side wall 105
That is the second material.In order to form the first side wall 104 and the second side wall 105, in embodiments of the present invention, step S5 can also be wrapped
It includes：
Step S51：Based on the 4th litho pattern, the active layer 102 of etched edge and second dielectric layer 103.
It is a kind of structure diagram of 4th litho pattern provided in an embodiment of the present invention referring to Fig. 6, referring also to Fig. 7,
Section B-B schematic diagram for the memory cell structure formed according to litho pattern shown in fig. 6.4th litho pattern 14
It is identical with the arragement direction of the first litho pattern 11, for forming protection side wall between adjacent storage unit.According to Fig. 6 institutes
The 4th litho pattern 14 shown, the active layer 102 and second dielectric layer 103 at etching storage unit edge, so as to be formed such as Fig. 7 institutes
The structure shown.
Step S52：Depositing first material, in 1024 corresponding 103 side of second dielectric layer of the first source region, the second source region
1025 corresponding 103 sides of second dielectric layer and 1023 corresponding 103 side of second dielectric layer of drain region form the first material
First side wall 104.
As shown in figure 8, depositing first material, thus in the top of the first source region 1024, the side of second dielectric layer 103
Formed the first side wall 1041, the side of the top of the second source region 1025, second dielectric layer 103 formed the first side wall 1042, with
And the first side wall 1043 is formed in the side of the top in drain region 1023, second dielectric layer 103, while in this step, the first side
Wall 104 is also covered in the side at storage unit edge.
Step S53：Based on the 4th litho pattern 14, the first side wall 104 of etched edge.
Referring to Fig. 9, based on the 4th litho pattern 14, first side wall 104 at etching storage unit edge.
Under the first performance, when performing step S53, it can be performed etching, known according to the 4th litho pattern 14
Until road exposure first medium layer 101.
Under second of performance, the 4th litho pattern 14 is also based on, in the first side wall 104 for etching away edge
Later, continue the first medium layer 101 of etched edge, first for making 101 top surface of first medium layer after etching and not etching is situated between
There are space Ds for 101 top surface of matter layer, ultimately form structure as shown in Figure 9.Moreover, in the specific implementation, the space D between
The 1% to 98% of first work-function layer, 111 height or 121 height of the second work-function layer.
Step S54：The dielectric layer of depositing second material forms the second side wall 105, and throw in the side of the first side wall 104
Light is with the top surface of the first side wall 104 of exposure.
Referring to Figure 10, in the dielectric layer of the surface depositing second material of storage unit, polish and expose the first side wall 104
Top surface thus forms respectively the second side wall 105, the second side in the side of the first side wall 1041 and the first side wall 1042
Wall 105 is prevented to interfere or be punctured for two adjacent storage units of electrical insulation.Moreover, second material can
Think SiN, SiON and SiO2One or more combinations, and resistivity between 2 × 1011 Ω m (ohm meter) to 1 ×
1025 Ω m (ohm meter), but second material and the first material need difference in embodiments of the present invention, and
In the presence of the difference of selectivity when etching, such as first material can be SiO2, second material can be SiN
Deng certainly in the specific implementation, the combination using different the first material and the second material can be selected, in the embodiment of the present invention
In do not limit.
In step s 6, it is a kind of schematic diagram of second litho pattern provided in an embodiment of the present invention referring to Figure 11, it is described
It is consistent with the angle of wordline with the angle of wordline with the first litho pattern 11 on second litho pattern, 12 length direction, described second
Photoetching Figure 12 shapes are used to define the drain electrode 106 shared in each storage unit.As shown in figure 12, based on the second litho pattern
12, the first side wall 1043 on drain region 1023 is etched, forms drain electrode groove, and in forming drain electrode in the drain electrode groove
106；In one exemplary embodiment, the drain electrode 106 can include the first metal layer 1061 and second metal layer 1062, tool
The forming process of the drain electrode 106 of body can include：In depositing the first metal layer 1061 in drain electrode groove, then in the first gold medal
Belong to depositing second metal layer 1062 on layer 1061 and fill up the drain electrode groove.In the specific implementation, the first metal layer
1061 include TiN, TiSix、CoSixAnd NiSixOne or more combinations, the second metal layer 1062 include W, Ti,
One or more combinations of Ni, Al, Pt and DOPOS doped polycrystalline silicon, and the first metal layer 1061 and second metal layer 1062
Resistivity between 2 × 10-8 Ω m (ohm meter) to 1 × 102 Ω m (ohm meter).
In the step s 7, referring to the structure diagram of Figure 13 bit lines formed by the embodiment of the present invention, referring also to scheme
14, it is the sectional view along D-D directions of structure shown in Figure 13, is being formed on drain electrode 106 defined in the second litho pattern 12
Bit line 300, the bit line 300 are in electrical contact with drain electrode 106.The 4th litho pattern 14 is also shown simultaneously in fig. 13, due to
4th photoetching Figure 14 shapes are used to separate adjacent storage unit, therefore the 4th active layer 102 along storage unit of litho pattern 14
Extending direction cover corresponding storage unit, as shown in figure 13 in this way, bit line 300 prolongs with the active layer 102 of storage unit
Stretching direction, there are second angle β；Moreover, the first wordline 201 and the second wordline 202 are mutually parallel in embodiments of the present invention, because
This bit line 300 is equal with the first wordline 201 and the second wordline 202 difference angulation, i.e., there are third angle γ.In order to protect
Demonstrate,prove the Optimal Distribution of multiple storage units, optionally, the second angle between 12 ° to 60 °, the third angle between
28 degree to 90 degree.In embodiments of the present invention, the bit line 300 include W, Ti, Ni, Al, Pt and DOPOS doped polycrystalline silicon one kind or
A variety of combinations, resistivity is between 2 × 10-8 Ω m (ohm meter) to 1 × 102 Ω m (ohm meter).Referring to Figure 14,
By depositing second dielectric layer 103, protective layer is formed in the top of bit line 300 and side；Certainly it should be noted that as position
The protective layer of line 300 can not select second dielectric layer 103, can also be that the insulating materials of any other material is used as protection
Layer, does not limit in embodiments of the present invention.
In step s 8, referring to Figure 15, the first material of alternating deposit and the second material are formed with multi-layer structure successively
Multi-medium-layer 107.In one exemplary embodiment, the multilayer dielectricity layer includes 4 layer of material, i.e. material layer 1071, material
Layer 1072, material layer 1073 and material layer 1074, wherein material layer 1071 and the material layer that material layer 1073 is the first material, material
The bed of material 1072 and the material layer that material layer 1074 is the second material.Certainly, in the specific implementation, the multi-medium-layer 107 can be with
Include the material layer of arbitrary multilayer, such as 6 layers, 8 layers etc., do not limit in embodiments of the present invention.Referring to Figure 16, for the present invention
The structure diagram for the third litho pattern that embodiment provides, the third litho pattern 13 are used to define the position of the first capacitance
Region and the band of position of the second capacitance, moreover, defining the first capacitance in the first source region 1024 by third litho pattern 13
On corresponding position, the second capacitance is defined on 1025 corresponding position of the second source region.It is the E-E directions shown in Figure 16 referring to Figure 17
Sectional view, based on third litho pattern 13, the first material of autoregistration selective etch and the second material are until exposure active layer
102, pass through 107 and first side wall 1041 of multi-medium-layer for etching away 13 definition regions of third litho pattern and in this way
One side wall 1042, in the first capacitance groove 401 is formed in the first source region 1024 of active layer 102 and in active layer 102
The second capacitance groove 402 is formed in two source regions 1025；It is carved moreover, because the first material and the second material have when etching
Difference is lost, such as the first material is SiO2, the second material is SiN, and most first material is etched away, the second of fraction
Material is etched away, and forms stair-stepping capacitance groove.The embodiment of the present invention is replaced by the different material layer of multi-medium-layer 107
Setting and selective etch mode can define complicated capacitance groove, for increase capacity area and then increase electricity
Capacity provides basis, and since capacitance alignment is defined in the first source region 1024 and the second source region 1025, also can be further
The area of storage unit is reduced, improves integrated level.
In step s 9, referring to Figure 18 to Figure 20 in sequentially forming the first capacitance bottom crown in the first capacitance groove 401
410th, the first capacitor dielectric layer 411, the first capacitance top crown 412 form the first capacitance；In in the second capacitance groove 402 successively
The second capacitance bottom crown 420, the second capacitor dielectric layer 421, the second capacitance top crown 422 are formed, forms the second capacitance.Show one
In example property embodiment, step S9 can also include：
Step S91：In forming the first capacitance bottom crown 410 in the first capacitance groove 401, in the second capacitance groove 402
The second capacitance bottom crown 420 is formed, the first capacitance bottom crown 410 and the first capacitance groove 401 are conformal, the second capacitance bottom crown
420 is conformal with the second capacitance groove 402.
As shown in figure 18, the pole under the first capacitance bottom crown 410 of formation in the first capacitance groove 401, first capacitance
Plate 410 is covered on the inner wall of the first capacitance groove 401, is formed and the first conformal capacitance bottom crown of the first capacitance groove 401
410；In forming the second capacitance bottom crown 420 in the second capacitance groove 402, the second capacitance bottom crown 420 is covered in second
On 402 inner wall of capacitance groove, formed and the second conformal capacitance bottom crown 420 of the second capacitance groove 402.In the embodiment of the present invention
In, the first capacitance bottom crown 410 and the second capacitance bottom crown 420 can be selected including TiN, TiSix、CoSixAnd NiSix
One or more combinations.
Step S92：Etch second material at 107 top of multi-medium-layer on bit line 300, and the first material of exposure.
See also Figure 18, based on dielectric layer litho pattern, the material at 107 top of multi-medium-layer on bit line 300 is etched
Layer 1074 and part the first capacitance bottom crown 410 and the second capacitance bottom crown 420, and expose material layer 1073, wherein material
The bed of material 1074 is the material layer of the second material, and material layer 1073 is the material layer of the first material.
Step S93：The first material that etching off exposes.
As shown in figure 19, the first all materials that etching off exposes, including material layer 1073 and material layer 1071,
Such first capacitance bottom crown 410 and material layer 1072, material layer 1074 form the frame structure for preparing the first capacitance, equally
Ground, the second capacitance bottom crown 420 and material layer 1072, material layer 1074 form the frame structure for preparing the second capacitance.
Step S94：The first capacitance bottom crown 410 is formed in the inner wall of the first capacitance bottom crown 410 and the outer wall of exposure, in
The inner wall of second capacitance bottom crown 420 and the outer wall of exposure form the second capacitor dielectric layer 421.
See also Figure 19, the first capacitor dielectric layer is formed in the inner wall of the first capacitance bottom crown 410 and the outer wall of exposure
411, the second capacitor dielectric layer 421 is formed in 420 inner wall of the second capacitance bottom crown and the outer wall of exposure, due to pole under the first capacitance
411 He of the first capacitor dielectric layer is all deposited respectively on the inner wall and partial outer wall of 410 and second capacitance bottom crown 420 of plate
Second capacitor dielectric layer 421 can form the capacitance of sandwich structure in this way, further increase the effective area of capacitance so as to
Increase capacitance.Moreover, in embodiments of the present invention, in order to ensure high capacitance, the first capacitor dielectric layer 411 and the second capacitance
Dielectric layer 421 selects the material that relative dielectric constant is more than 10, such as the first capacitor dielectric layer 411 and the second capacitor dielectric
Layer 421 can include ZrOx、HfOx、ZrTiOx、RuOx、SbOxAnd AlOxOne or more combinations.
Step S95：In forming upper first capacitance top crown 412 on the first capacitance bottom crown 410, in the second capacitor dielectric layer
The second capacitance top crown 422 is formed on 421.
As shown in figure 19, it continues on the first capacitor dielectric layer 411 and forms the first capacitance top crown 412, in the second electricity
Hold and form the second capacitance top crown 422 on dielectric layer 421；In this way, the first capacitance bottom crown 410 and the first capacitance top crown 412
The first capacitor dielectric layer 411 is clamped jointly, forms the first capacitance of sandwich structure；Second capacitance bottom crown 420 and the second electricity
Hold top crown 422 and clamp the second capacitor dielectric layer 421 jointly, form the second capacitance of sandwich structure.In addition, it is desirable to explanation
It is the capacitance shape according to defined in the litho pattern of Figure 16, first capacitance and the second capacitance in embodiments of the present invention
It is columned capacitance.
In step slo, it see also Figure 19, is formed on the first capacitance top crown 412 and the second capacitance top crown 422
Top electrode 500.In one exemplary embodiment, the top electrode 500 includes first electrode layer 5001 and the second electrode lay 5002.
The forming process of the top electrode 500 can include：In the surface deposition of first electrode layer 5001 of storage unit, and first electricity
Pole layer 5001 fills up the first capacitance groove 401 and the second capacitance groove 402；The second electricity is formed in deposition in first electrode layer 5001
Pole layer 5002.Wherein, the first electrode layer 5001 can include the one or more of W, Ti, Ni, Al, Pt and DOPOS doped polycrystalline silicon
Combination, the second electrode lay 5002 can include TiN, TiSix、CoSixAnd NiSixOne or more combinations, and
First electrode layer 5001 and the resistivity of the second electrode lay 5002 are between 2 × 10-8 Ω m to 1 × 102 Ω m.
Referring to Figure 20, the storage unit that the embodiment of the present invention is provided includes two transistors and two capacitances, wherein two
A transistor shares a drain electrode 106, when as replicated blocks work in memory, transistor and corresponding
Capacitance can as a repetitive unit and complete data storage and reading operation.As shown in figure 20, the repetitive unit
The area of occupancy is the product of 2 times of half spacing 2HPBL of wordline and 2 times of half spacing 2HPWL of bit line, wherein half spacing of wordline and bit line
Half spacing can be equal using F as label as minimum dimension, then the occupied area of the repetitive unit is 4F2, thus this hair
The storage unit that bright embodiment provides can realize 4F2Dense arrangement is so as to very high integrated level.
By the description of above-described embodiment as it can be seen that a kind of manufacturing method of storage unit provided in an embodiment of the present invention, passes through
Substrate 100 is provided, and in formation is buried by first medium layer 101 on the substrate 100 the first wordline 201 and the second wordline
202；Based on the first litho pattern 11 etching first medium layer 101, in forming the first gate groove in the first wordline 201, in second
Second gate groove in wordline 202；First gate electrode 110 is formed in filling grid metal in the first gate groove and second gate, in second
Filling grid metal forms the second gate electrode 120 in gate groove；Based on the first litho pattern 11, formed in first gate electrode 110
First work-function layer 111, and form the first gate dielectric layer 112 in 111 surface of the first work-function layer；In on the second gate electrode 120
The second work-function layer 121 is formed, and the second gate dielectric layer 122 is formed in 121 surface of the second work-function layer；Wherein, described first
The length direction and the second wordline of the length direction of work-function layer 111 and the first wordline 201 and the second work-function layer 121
202, into first angle；Active layer 102 is deposited, the first protuberance road is formed in the active layer 102 for covering the first work-function layer 111
Area 1021 forms the second protuberance road area 1022, in the first work-function layer 111 in the active layer 102 for covering the second work-function layer 121
And the second active layer 102 between work-function layer 121 forms drain region 1023, it is active in the residue close to the first work-function layer 111
Layer 102 forms the first source region 1024, and the second source region 1025 is formed in the remaining active layer 102 close to the second work-function layer 121；In
102 surface of active layer forms second dielectric layer 103；In 1024 corresponding 103 side of second dielectric layer of the first source region, the second source region
1025 corresponding 103 sides of second dielectric layer and 1023 corresponding 103 side of second dielectric layer of drain region form the first material
First side wall 104；The second side wall 105 of the second material is formed in 104 side of the first side wall；Based on the second litho pattern 12, carve
The first side wall 104 on drain region 1023 is lost, forms drain electrode groove, and in formation drain electrode 106 in the drain electrode groove；In
On the drain electrode 106 deposition form bit line 300, the bit line 300 is in electrical contact with drain electrode 106, the bit line 300 with it is active
The extending direction of layer 102 is into second angle, with the first wordline 201 and the second wordline 202 respectively into third angle；In bit line 300
Top and side formed protective layer；The first material of alternating deposit and the second material form multimedium with multi-layer structure successively
Layer 107；Based on third litho pattern 13, the first material of autoregistration selective etch and the second material until exposure active layer 102,
Include the first capacitance groove 401 of multiple step structures and in active in being formed in the first source region 1024 of active layer 102
The the second capacitance groove 402 for including multiple step structures is formed in second source region 1025 of layer 102；In the first capacitance groove
The first capacitance bottom crown 410, the first capacitor dielectric layer 411, the first capacitance top crown 412 are sequentially formed in 401, forms the first electricity
Hold；In sequentially forming the second capacitance bottom crown 420, the second capacitor dielectric layer 421 in the second capacitance groove 402, on the second capacitance
Pole plate 422 forms the second capacitance；In formation top electrode 500 on the first capacitance top crown 412 and the second capacitance top crown 422.It should
The protuberance road area of transistor is distributed along the side of work-function layer and top surface in storage unit prepared by method, forms vertical-channel
Transistor arrangement, accordingly even when in the horizontal channel dimensions reduce, still remain in vertical direction protuberance road area, so as to
Inhibit short-channel effect so that transistor can still have superperformance in technique micro；Moreover, with transistor electricity
The capacitance of connection employs stair-stepping groove and is prepared, and the capacitance has two-layered medium layer, increases effectively capacitance
Area, and then improve capacitance；In addition, the repetitive unit area occupied in the storage unit can reach 4F2, have very high
Integrated level.
Corresponding with a kind of manufacturing method of storage unit provided in an embodiment of the present invention, the embodiment of the present invention additionally provides
A kind of storage unit, as shown in figure 19, the storage unit include：
The first medium layer 101 of substrate 100 and setting on the substrate 100；
First wordline 201 and the second wordline 202,201 and second wordline 202 of the first wordline are buried in described first and are situated between
It is spaced from each other in matter layer 101 and by the first medium layer 101；
110 and second gate electrode 120 of first gate electrode, the first gate electrode 110 are set across the first medium layer 101
It is placed in the first wordline 201, partially overlaps with the first wordline 201；Second gate electrode 120 is set across the first medium layer 101
It is placed in the second wordline 202, partially overlaps with the second wordline 202；
First work-function layer 111 and the second work-function layer 121, first work-function layer 111 are set to first gate electrode
110 top surface, second work-function layer 121 are set to the top surface of the second gate electrode 120；The length of first work-function layer 111
Direction and the length direction and the second wordline 202 of the first wordline 201 and the second work-function layer 121, into first angle；And
And the overlapping part of 111 and first wordline 201 of the first work-function layer, with 121 and second wordline of the second work-function layer
202 overlapping part is symmetrical arranged；
First gate dielectric layer 112 and the second gate dielectric layer 122, first gate dielectric layer 112 are formed in the first work function
The surface of layer 111, second gate dielectric layer 122 are formed in the surface of the second work-function layer 121；
Active layer 102, the active layer 102 are covered in first medium layer 101, the first gate dielectric layer 112, the second gate medium
The surface of layer 122；The active layer 102 includes swelling road area 1021, along the second work(along first that the first work-function layer 111 set
Second protuberance road area 1022 of the setting of function floor 121 is set between the first work-function layer 111 and the second work-function layer 121
Drain region 1023, the close to the first source region 1024 of the first work-function layer 111 setting and close to the setting of the second work-function layer 121
Two source regions 1025；
Drain electrode 106 and bit line 300, the drain electrode 106 are set on drain region 1023 and are in electrical contact with drain region 1023；
The bit line 300 is in electrical contact with drain electrode 106, the extending direction of the bit line 300 and active layer 102 into second angle, with the
One wordline 201 and the second wordline 202 are respectively into third angle；
Second dielectric layer 103, the second dielectric layer 103 are covered on active layer 102, bit line 300 and drain electrode 106；
First capacitance groove 401 and the second capacitance groove 402, the first capacitance groove 401 are set to the first source region
On 1024, the second capacitance groove 402 is set in the second source region 1025；
First capacitance bottom crown 410 and the second capacitance bottom crown 420, the first capacitance bottom crown 410 and the first source region
1024 electrical contact, the first capacitance bottom crown 410 along the first capacitance groove 401 inner wall to far from substrate 100 side
To extension, the first capacitance bottom crown 410 includes multiple step structures；The second capacitance bottom crown 420 and the second source
Area 1025 is in electrical contact, and the second capacitance bottom crown 420 is along the inner wall of the second capacitance groove 402 to far from substrate 100
Direction extends, and the second capacitance bottom crown 420 includes multiple step structures；
First capacitor dielectric layer 411 and the second capacitor dielectric layer 421, the first capacitor dielectric layer 411 are formed in first
The surface that capacitance bottom crown 410 exposes, the second capacitor dielectric layer 421 are formed in the table of the second capacitance bottom crown 420 exposure
Face；
First capacitance top crown 412 and the second capacitance top crown 422, the first capacitance top crown 412 are formed in first
The surface that capacitor dielectric layer 411 exposes, the second capacitance top crown 422 are formed in the table of the second capacitor dielectric layer 421 exposure
Face；
The top electrode 500 being in electrical contact with the first capacitance top crown 412 and the second capacitance top crown 422.
The drain electrode 106 includes the first metal layer 1061 and be arranged on the first metal layer 1061 second
Metal layer 1062；The first metal layer 1061 is in electrical contact with drain region 1023；
The top electrode 500 includes first electrode layer 5001 and be deposited in the first electrode layer 5001 second
Electrode layer 5002, the first electrode layer 5001 are in electrical contact with the first capacitance top crown 412 and the second capacitance top crown 422；
First wordline 201, the second wordline 202, bit line 300, first electrode layer 5001 and second metal layer 1062 are wrapped
Include one or more combinations of W, Ti, Ni, Al, Pt and DOPOS doped polycrystalline silicon；The second electrode lay 5002, the first metal layer
1061st, 110 and second gate electrode 120 of first gate electrode respectively includes TiN, TiSix、CoSixAnd NiSixIt is one or more
Combination；First wordline 201, the second wordline 202, bit line 300, the first metal layer 1061, the 1062, first electricity of second metal layer
Pole layer 5001, the second electrode lay 5002,110 and second gate electrode 120 of first gate electrode resistivity between 2 × 10-8 Ω m
To 1 × 102 Ω m.
The active layer 102 include silicon epitaxy layer or polysilicon layer, and the thickness of the active layer 102 between 3nm extremely
Between 2000nm.
First work-function layer, 111 and second work-function layer 121 includes TiN layer or doped polysilicon layer, and described the
First protuberance road area 1021 of one work-function layer 111 and active layer 102 there are work function difference, second work-function layer 121 with
There are work function differences in second protuberance road area 1022 of active layer 102.
The first medium layer 101, second dielectric layer 103, the first gate dielectric layer 112 and the second gate dielectric layer 122 include
SiN, SiON and SiO2One or more combinations, and resistivity is between 2 × 1011 Ω m to 1 × 1025 Ω m.
The first capacitor dielectric layer 411 and the second capacitor dielectric layer 421 include ZrOx、HfOx、ZrTiOx、RuOx、SbOx
And AlOxOne or more combinations, and relative dielectric constant is more than 10.
The memory cell area is 2 times of half spacing of wordline and the product of 2 times of half spacing of bit line.
The first capacitance top crown 412, the first capacitor dielectric layer 411, the first capacitance bottom crown 410 form the first electricity
Hold, the second capacitance top crown 422, the second capacitor dielectric layer 421, the second capacitance bottom crown 420 form the second capacitance, described
First capacitance and the second capacitance are cylindric capacitance.
First angle is between 25 degree to 35 degree, and the second angle is between 12 degree to 60 degree, and the third angle is between 28
Degree is to 90 degree.
The embodiment of the present invention and above-mentioned manufacturing method embodiment something in common, reference can be made to above-mentioned manufacturing method embodiment is retouched
It states, details are not described herein.
The embodiment of the present invention additionally provides a kind of memory, which includes at least above-mentioned manufacturing method and storage unit
The described storage unit of device embodiment.
Referring to Figure 20, in the storage unit adjacent along wordline extending direction, the first capacitance of same storage unit and second
The first capacitance or the second capacitance of capacitance and another storage unit, are connected with each other, structure by triangle top electrode 500
Into a capacitance group；Moreover, in storage unit arrangement, the first capacitance and the second capacitor connection direction in a storage unit, with
In an other storage unit in the first capacitance and an above-mentioned storage unit angle δ in the second capacitor connection direction between 58 degree to 62
Degree, so as to form the arrangement mode of triangle.Certainly it should be noted that the arrangement mode of said memory cells is only an example
Property embodiment, in the specific implementation, every capacitance by consecutive storage unit should all be fallen into a manner that angle δ is arranged
Protection scope of the present invention.
In conclusion the present invention provides a kind of manufacturing method of storage unit, storage unit and memories.Storage unit
In transistor use vertical channel structure so that the protuberance road area of transistor is distributed along the side of work-function layer and top surface；
Capacitance in storage unit employs the structure of two-sided capacitance by forming the capacitance frame of step structure, increases capacitance
Area.So the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (17)
1. a kind of manufacturing method of storage unit, which is characterized in that the manufacturing method includes at least following steps：
Substrate is provided, and in formation is buried by first medium layer on the substrate the first wordline and the second wordline；
The first medium layer is etched based on the first litho pattern so that in formed in first wordline the first gate groove and
In forming the second gate groove in second wordline, and to form the first grid in filling grid metal in first gate groove
Electrode and in second gate groove fill grid metal formed the second gate electrode；
Based on first litho pattern, embossed it is situated between in described first in forming the first work-function layer in the first gate electrode
On matter layer, and the first gate dielectric layer is formed in the embossed surface of first work-function layer；It is formed on second gate electrode
Second work-function layer and it is embossed on the first medium layer, and form second gate in the embossed surface of second work-function layer
Dielectric layer, wherein, angle and second work(between the length direction of first work-function layer and first wordline
Angle between the length direction of function layer and second wordline is described into the first angle more than 0 degree and less than 90 degree
The overlapping part of first work-function layer and the first wordline is symmetrically set with the overlapping part of second work-function layer and the second wordline
It puts；
Active layer is deposited on the first medium layer, it is first grand to include climbing first work-function layer for the active layer
Track lifting area, is connected to the first protuberance road area and described second at the second protuberance road area for climbing second work-function layer
Between protuberance road area and it is in the drain region of paddy shape recess, is connected to the first protuberance road area and is formed on the first medium floor
The first source region, be connected to the second protuberance road area and the second source region for being formed on the first medium floor；
Second dielectric layer is formed in the surface of the active layer；
It is respectively formed corresponding to the active layer side with central the first side wall including the first material in the second medium
Layer corresponds on the lateral surface of first source region, the lateral surface of second source region and the drain region；
The second side wall of the second material is formed in the first side wall side of the correspondence active layer side, the second medium
The edge of layer and the edge of the active layer；
Based on the second litho pattern, etching removes first side wall for corresponding to active layer center on the drain region, with
Drain electrode groove is formed, and in forming drain electrode in the drain electrode groove；
Deposition forms bit line on the drain electrode, and the bit line is in electrical contact with the drain electrode, the bit line with it is described active
Angle between the extending direction of layer is into second angle, angle between the bit line and first wordline and with described second
Angle between wordline is into third angle；
Protective layer is formed in the top of the bit line and side；
The first material of alternating deposit and the second material successively, to form multi-medium-layer with multi-layer structure；
Based on third litho pattern, the first material of autoregistration selective etch and the second material, corresponding to the active layer side
First side wall until the exposure active layer so that include multiple ladders in being formed in the first source region of the active layer
First capacitance groove of shape structure and being formed includes the second capacitance groove of multiple step structures in the of the active layer
In two source regions；
The first capacitance bottom crown, the first capacitor dielectric layer, the first capacitance top crown are sequentially formed in the first capacitance groove,
To form the first capacitance, and the second capacitance bottom crown, the second capacitor dielectric layer, the second capacitance top crown are sequentially formed in described
In second capacitance groove, to form the second capacitance；And
Top electrode is formed on the first capacitance top crown and the second capacitance top crown.
2. the manufacturing method of storage unit according to claim 1, which is characterized in that described the step of providing substrate wraps
It includes：
The first medium layer of the first material is formed in the substrate surface；
Wordline metal layer is deposited on the first medium layer；
The wordline metal layer is etched, obtains first wordline and second wordline；And
Depositing first material buries first wordline and second wordline.
3. the manufacturing method of storage unit according to claim 1, which is characterized in that the part bottom of the first gate electrode
Face locally coincides with first wordline, and the portion bottom surface of second gate electrode locally coincides with second wordline；
And ratio relative to the first gate electrode floor space of the first gate electrode and the first wordline overlapping area, Yi Jisuo
The second gate electrode and the second wordline overlapping area are stated relative to the ratio of the second gate electrode floor space between 35%
To 99.8%.
4. the manufacturing method of storage unit according to claim 1, which is characterized in that forming first side wall and institute
During stating the second side wall, including：
Based on the 4th litho pattern, etching forms the active layer and the edge of the second dielectric layer；
In a manner of depositing first material, first side wall for forming the first material is situated between in first source region corresponding second
Matter layer side, the corresponding second dielectric layer side in the corresponding second dielectric layer side of second source region and the drain region；
Based on the 4th litho pattern, etching forms the edge of first side wall, corresponding to the active layer side；And
In a manner of the dielectric layer of depositing second material, second side wall is formed in the side of first side wall, and polish
With the top surface of exposure first side wall.
5. the manufacturing method of storage unit according to claim 4, which is characterized in that before depositing second material, also wrap
It includes：
Based on the 4th litho pattern, the first medium layer except the active layer overlay area is etched, after making etching
There are spacing for first medium layer top surface and the first medium layer top surface that does not etch, and the spacing is between the first work function floor height
The 1% to 98% of degree or the second work-function layer height.
6. the manufacturing method of storage unit according to claim 1, which is characterized in that in first capacitance and described the
In the forming process of two capacitances, including：
The first capacitance bottom crown is formed in the first capacitance groove, the second capacitance bottom crown of formation is in the second capacitance ditch
In slot, the first capacitance bottom crown and the first capacitance groove are conformal, the second capacitance bottom crown and the described second electricity
It is conformal to hold groove；
Etch the second material at the top of multi-medium-layer on the bit line, and the first material of exposure；
Etching off exposes the first material；
The first capacitor dielectric layer is formed in the inner wall of the first capacitance bottom crown and the outer wall of exposure, and forms the second capacitance
Dielectric layer is in the inner wall of the second capacitance bottom crown and the outer wall of exposure；And
Upper first capacitance top crown is formed on the first capacitor dielectric layer, and the second capacitance top crown of formation is in described the
On two capacitor dielectric layers.
7. the manufacturing method of storage unit according to claim 1, which is characterized in that the first angle between 25 degree extremely
35 degree, the second angle is between 12 degree to 60 degree, and the third angle is between 28 degree to 90 degree, any first work content
Several layers of figure and the figure of second work-function layer include arc or rectangle.
8. a kind of storage unit, which is characterized in that the storage unit includes at least：
The first medium layer of substrate and setting over the substrate；
First wordline and the second wordline are buried in the first medium layer and are spaced from each other by the first medium layer；
First gate electrode and the second gate electrode, the first gate electrode pass through the first medium layer and are set to first word
It is overlapped on line and with first word line portion, second gate electrode passes through the first medium layer and is set to described second
It is overlapped in wordline and with second word line portion；
First work-function layer and the second work-function layer, first work-function layer are set to the top surface of the first gate electrode and float
It dashes forward on the first medium layer, second work-function layer is set to the top surface of second gate electrode and embossed in described
On one dielectric layer, angle and second work content between the length direction of first work-function layer and first wordline
Angle between several layers of length direction and second wordline is into the first angle more than 0 degree and less than 90 degree, and described the
The overlapping part of one work-function layer and the first wordline is symmetrically set with the overlapping part of second work-function layer and the second wordline
It puts；
First gate dielectric layer and the second gate dielectric layer, first gate dielectric layer are formed in the embossed table of first work-function layer
Face, second gate dielectric layer are formed in the embossed surface of second work-function layer；
Active layer is deposited on the first medium layer, and the active layer includes climbing the first of first work-function layer
Protuberance road area, is connected to the first protuberance road area and described the at the second protuberance road area for climbing second work-function layer
Between two protuberance road areas and it is in the drain region of paddy shape recess, is connected to the first protuberance road area and is formed in the first medium floor
On the first source region, be connected to the second protuberance road area and the second source region for being formed on the first medium floor；
Drain electrode and bit line, the drain electrode be set on the drain region and with the drain region be in electrical contact, the bit line with it is described
Drain electrode is in electrical contact, and the extending direction of the bit line and the active layer is into second angle, the bit line and first wordline
Between angle and angle between second wordline into third angle；
Second dielectric layer is at least covered on the active layer；And
First capacitance groove and the second capacitance groove, the first capacitance groove are set in first source region, and described second
Capacitance groove is set in second source region.
9. storage unit according to claim 8, which is characterized in that the storage unit further includes：
First capacitance bottom crown and the second capacitance bottom crown, the first capacitance bottom crown are in electrical contact with first source region, institute
It states the first capacitance bottom crown along the inner wall of the first capacitance groove to the direction far from the substrate to extend, first capacitance
Bottom crown includes multiple step structures, and the second capacitance bottom crown is in electrical contact with second source region, second capacitance
Bottom crown extends along the inner wall of the second capacitance groove to the direction far from the substrate, and the second capacitance bottom crown includes
Multiple step structures；
First capacitor dielectric layer and the second capacitor dielectric layer, the first capacitor dielectric layer are formed in the first capacitance bottom crown
Exposed surface, the second capacitor dielectric layer are formed in the surface of the second capacitance bottom crown exposure；
First capacitance top crown and the second capacitance top crown, the first capacitance top crown are formed in the first capacitor dielectric layer
Exposed surface, the second capacitance top crown are formed in the surface of the second capacitor dielectric layer exposure；And
The top electrode being in electrical contact with the first capacitance top crown and the second capacitance top crown.
10. storage unit according to claim 9, which is characterized in that
The drain electrode includes the first metal layer and the second metal layer being deposited on the first metal layer, first gold medal
Belong to layer to be in electrical contact with the drain region；
Wherein, the top electrode includes first electrode layer and the second electrode lay being deposited in the first electrode layer, described
First electrode layer is in electrical contact with the first capacitance top crown and the second capacitance top crown.
11. storage unit according to claim 10, which is characterized in that first wordline, second wordline, described
The material of bit line, the first electrode layer and the second metal layer includes tungsten (W), titanium (Ti), nickel (Ni), aluminium (Al), platinum
(Pt) and one or more combinations of DOPOS doped polycrystalline silicon；The second electrode lay, the first metal layer, first grid electricity
The material of pole and second gate electrode includes titanium nitride (TiN), Titanium silicide (TiSix), cobalt silicide (CoSix) and nisiloy
Compound (NiSix) one or more combinations；First wordline, second wordline, the bit line, first metal
Layer, the second metal layer, the first electrode layer, the second electrode lay, the first gate electrode and second gate electricity
The resistivity of pole is between 2 × 10-8Ω m to 1 × 102Ω·m。
12. storage unit according to claim 8, which is characterized in that first work-function layer and second work content
Several layers of material includes titanium nitride (TiN) or DOPOS doped polycrystalline silicon, and the first of first work-function layer and the active layer is grand
Track lifting area is there are work function difference, and there are work function differences in the second protuberance road area of second work-function layer and the active layer.
13. storage unit according to claim 8, which is characterized in that the first medium layer, the second dielectric layer,
The material of first gate dielectric layer and second gate dielectric layer includes silicon nitride (SiN), silicon oxynitride (SiON) and oxidation
Silicon (SiO2) one or more combinations, and between 2 × 1011Ω m to 1 × 1025Resistivity between Ω m.
14. storage unit according to claim 9, which is characterized in that the first capacitor dielectric layer and second electricity
The material for holding dielectric layer includes zirconium oxide (ZrOx), hafnium oxide (HfOx), titanium oxide zirconium (ZrTiOx), ruthenium-oxide (RuOx), oxidation
(SbOx) and aluminium oxide (AlOx) one or more combinations, and with more than 10 relative dielectric constant.
15. storage unit according to claim 9, which is characterized in that the area of repetitive unit is 2 in the storage unit
The product of times half spacing of wordline and 2 times of half spacing of bit line, the first capacitance top crown, the first capacitor dielectric layer, the first capacitance
Bottom crown forms the first capacitance, and the second capacitance top crown, the second capacitor dielectric layer, the second capacitance bottom crown form the second electricity
Hold, first capacitance and the second capacitance are cylindric capacitance.
16. storage unit according to claim 8, which is characterized in that the first angle between 25 degree to 35 degree,
The second angle is between 12 degree to 60 degree, and the third angle is between 28 degree to 90 degree, and any described first
The figure of work-function layer and the figure of second work-function layer include arc or rectangle.
17. a kind of memory, which is characterized in that the memory is included at least as described in claim 8 to 16 any one
Storage unit.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710294055.1A CN107275286B (en) | 2017-04-28 | 2017-04-28 | A kind of manufacturing method of storage unit, storage unit and memory |
| CN201710476291.5A CN107230675B (en) | 2017-04-28 | 2017-04-28 | A kind of storage unit and memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710294055.1A CN107275286B (en) | 2017-04-28 | 2017-04-28 | A kind of manufacturing method of storage unit, storage unit and memory |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710476291.5A Division CN107230675B (en) | 2017-04-28 | 2017-04-28 | A kind of storage unit and memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107275286A CN107275286A (en) | 2017-10-20 |
| CN107275286B true CN107275286B (en) | 2018-06-19 |
Family
ID=59935725
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710294055.1A Active CN107275286B (en) | 2017-04-28 | 2017-04-28 | A kind of manufacturing method of storage unit, storage unit and memory |
| CN201710476291.5A Active CN107230675B (en) | 2017-04-28 | 2017-04-28 | A kind of storage unit and memory |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710476291.5A Active CN107230675B (en) | 2017-04-28 | 2017-04-28 | A kind of storage unit and memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN107275286B (en) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10304680B1 (en) * | 2017-12-22 | 2019-05-28 | Macronix International Co., Ltd. | Fabricating semiconductor devices having patterns with different feature sizes |
| KR102369509B1 (en) * | 2018-01-08 | 2022-03-02 | 삼성전자주식회사 | Semiconductor device and method for fabricating the same |
| US20200211968A1 (en) * | 2018-12-27 | 2020-07-02 | Nanya Technology Corporation | Semiconductor structure and manufacturing method thereof |
| EP3787022B1 (en) * | 2019-03-26 | 2024-07-31 | Shenzhen Goodix Technology Co., Ltd. | Capacitor and manufacturing method therefor |
| KR102683677B1 (en) * | 2019-07-12 | 2024-07-11 | 에스케이하이닉스 주식회사 | Vertical memory device |
| US11217589B2 (en) * | 2019-10-04 | 2022-01-04 | Nanya Technology Corporation | Semiconductor device and method of manufacturing the same |
| CN113707608B (en) | 2020-05-20 | 2023-09-26 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
| CN113707609B (en) * | 2020-05-20 | 2023-07-18 | 长鑫存储技术有限公司 | Method for preparing semiconductor structure |
| CN114284215B (en) * | 2020-09-27 | 2024-10-15 | 长鑫存储技术有限公司 | Semiconductor structure, preparation method thereof and storage device |
| CN114446889B (en) * | 2020-11-05 | 2024-07-12 | 长鑫存储技术有限公司 | Manufacturing method of capacitor connecting wire of memory and memory |
| US12004343B2 (en) | 2020-11-05 | 2024-06-04 | Changxin Memory Technologies, Inc. | Method of manufacturing capacitor connecting line of memory |
| CN112768490B (en) * | 2021-02-04 | 2023-01-20 | 长江先进存储产业创新中心有限责任公司 | Phase change memory and manufacturing method thereof |
| CN113206093B (en) * | 2021-04-29 | 2022-10-21 | 复旦大学 | Dynamic random access memory and preparation method thereof |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7577040B2 (en) * | 2006-07-18 | 2009-08-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dual port memory device with reduced coupling effect |
| US9646973B2 (en) * | 2015-03-27 | 2017-05-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dual-port SRAM cell structure with vertical devices |
| US9646978B2 (en) * | 2015-06-03 | 2017-05-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Self-aligned flash memory device with word line having reduced height at outer edge opposite to gate stack |
-
2017
- 2017-04-28 CN CN201710294055.1A patent/CN107275286B/en active Active
- 2017-04-28 CN CN201710476291.5A patent/CN107230675B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN107230675A (en) | 2017-10-03 |
| CN107275286A (en) | 2017-10-20 |
| CN107230675B (en) | 2018-06-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107275286B (en) | A kind of manufacturing method of storage unit, storage unit and memory | |
| US11296088B2 (en) | Semiconductor device including air gaps and method for fabricating the same | |
| US11462545B2 (en) | Semiconductor device and method for fabricating the same | |
| US9412665B2 (en) | Semiconductor device and method of fabricating the same | |
| KR102152798B1 (en) | Semiconductor device with line type air gap and method for fabricating the same | |
| US8999837B2 (en) | Semiconductor device with air gap | |
| US9245976B2 (en) | Vertical channel transistor with self-aligned gate electrode and method for fabricating the same | |
| US9997462B2 (en) | Semiconductor memory devices | |
| TWI570782B (en) | Mos capacitor, method of fabricating the same, and semiconductor device using the same | |
| US10991699B2 (en) | Semiconductor memory devices | |
| JP2012089744A (en) | Semiconductor device manufacturing method | |
| CN112786527B (en) | Semiconductor structure and manufacturing method thereof | |
| KR20070027122A (en) | Method for forming semiconductor memory device | |
| US6563161B2 (en) | Memory-storage node and the method of fabricating the same | |
| US20230328961A1 (en) | Semiconductor device | |
| US20210296167A1 (en) | Methods for reliably forming microelectronic devices with conductive contacts to silicide regions, and related systems | |
| TW201711169A (en) | Cell contact structure | |
| TWI812547B (en) | Semiconductor memory device | |
| TWI850845B (en) | Semiconductor device | |
| US11843039B2 (en) | Semiconductor device | |
| KR20240111164A (en) | Semiconducter device and method for fabricating thereof | |
| CN118804586A (en) | Semiconductor memory device having a memory cell with a memory cell having a memory cell with a memory cell |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20180930 Address after: 230601 room 630, Hai Heng mansion 6, Cui Wei Road, Hefei economic and Technological Development Zone, Anhui Patentee after: Changxin Storage Technology Co., Ltd. Address before: 230000 room 526, Hai Heng mansion 6, Cui Wei Road, Hefei economic and Technological Development Zone, Anhui Patentee before: Ever power integrated circuit Co Ltd |