CN107256852B - It improves the metal bonding lattice array of arrangement mode and has the semiconductor devices of the array - Google Patents
It improves the metal bonding lattice array of arrangement mode and has the semiconductor devices of the array Download PDFInfo
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- CN107256852B CN107256852B CN201710470556.0A CN201710470556A CN107256852B CN 107256852 B CN107256852 B CN 107256852B CN 201710470556 A CN201710470556 A CN 201710470556A CN 107256852 B CN107256852 B CN 107256852B
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- H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
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Abstract
The present invention discloses a kind of semiconductor devices of metal bonding lattice array for improving arrangement mode, is formed by two panels silicon wafer that top layer is dielectric layer and metallic bond chalaza is hybrid bonded, the metal bonding point forms the identical array of pitch and is uniformly distributed in the silicon chip surface；When hybrid bonded, two panels silicon wafer is face to face, stacked on top, metallic bond chalaza in each silicon chip arrays corresponds, it is in contact with each other, which is characterized in that metallic bond chalaza is not of uniform size in the array of each silicon wafer, it is alternately intervally arranged in dielectric layer surface, the array arrangement between two silicon wafers of bonding corresponds to each other the corresponding arrangement of bonding point size between two silicon wafers.The present invention makes full use of existing bonding apparatus, in the case of avoiding fine pith, because of the uneven distribution of interconnection resistance between silicon wafer caused by register partial difference, improves bonding technology controllability.
Description
Technical field
The present invention relates to IC manufacturing field, in particular to a kind of metal bonding dot matrix hybrid bonded for silicon wafer
Column and the semiconductor devices with the metal bonding lattice array.
Background technique
With the development of IC industry, the requirement to various aspects such as chip functions, integrated level, speed and power consumptions is more next
Higher, industry continually develops three-dimensional interconnection technology thus, by two and multiple integrated chips together by way of meet
Demand.Wherein, the chip Stack Technology of interconnection is directly realized by chip chamber, compared with three-dimensional packaging technology: can be reduced significantly
Product size, promotes properties of product at extended products function (capacity), is a kind of more advanced integrated chip mode.The skill at present
Art uses in the products such as back-illuminated type CMOS imaging sensor, high-end DRAM memory.
Hybrid bonded is a kind of emerging chip Stack Technology, the physical adhesion of 2 silicon wafers may be implemented and by simultaneously
It realizes electrical connection, there are some clear superiorities compared to other techniques, comprising:
It can be directly realized by silicon wafer-wafer bonding, compared with chip-chip and chip-wafer bonding, production efficiency
Highest；
Smaller bonding point pitch (spacing of adjacent bonding dot center) may be implemented, have reached 6 microns of minimum at present,
And have further miniature ability, and such as miniature solder bump (the Micro Solder of other stacked interconnected technologies
Bumping), minimum pitch is then at 10 microns or more.
It is hybrid bonded to have become in the prior art the most high integration of practical value and application potential in view of above-mentioned advantage
Wafer bonding technology, its main implementation method is as follows at present:
As shown in Figure 1, A and B is 2 silicon wafers to be bonded, top layer includes dielectric layer 1 and is opened on dielectric layer surface
2,2 silicon wafers of metal bonding lattice array on metallic bond chalaza size, arrangement it is identical: bonding point side length be a, bonding point spacing
It is c for b, bonding point pitch, and arrangement position corresponds.
As shown in Fig. 2, the hybrid bonded of perfect condition is, silicon wafer A is face-down, and silicon wafer B is face-up, stacked on top, in key
Close equipment in by surface treatment, alignment, physical contact and etc. realize silicon wafer A/B topsheet surface dielectric layer bonding, make 2
Piece silicon wafer physical adhesion；Again by techniques such as annealing, the metal bonding of top-level metallic bonding point is realized, 2 silicon wafer realizations are electrically connected
It connects.
It can be seen that silicon chip surface flatness is to realize ideal hybrid bonded key factor.For this purpose, before bonding, work
Chemically mechanical polishing CMP process is generally carried out to top-level metallic in skill, while being designed evenly arranged using metallic bond chalaza
Mode.Then, further according to the actual needs of circuit connection, part metals bonding point connect d with up/down layer metal；Part does not connect
It connects, if e, the dummy pad as just CMP play uniformly arrangement raising CMP uniformity, optimization silicon chip surface flatness
Effect.
For hybrid bonded technology, the alignment precision that its further miniature key factor is bonding apparatus is restricted.With existing
For having attainable best alignment precision 3sigma≤0.2 micron of technology.
As shown in figure 3, the left side is bonding there are when register partial difference, pair of metallic bond chalaza in the silicon wafer A and B of stacked on top
Quasi- perspective view, the right are that there are the sectional views that metallic bond chalaza when register partial difference connects for bonding.
When the side length a of metallic bond chalaza is 1.5 microns, metallic bond chalaza pitch b is 3 microns, and metallic bond chalaza spacing c is
At 1.5 microns, ideal bond contact area a2For 1.5*1.5=2.25 microns of ^2.It is 0.2 micron extreme in register partial difference
In the case of, actual bond contact area is (a- register partial difference)2For 1.3*1.3=1.69 microns of ^2, about ideal value
75%, reduce 25%；
When metallic bond chalaza pitch is further reduced to 1.5 microns, metallic bond chalaza side length is 0.75 micron, desired contact
Area is 0.5625 micron of ^2；In the case where register partial difference is 0.2 micron of extreme case, actual bond contact area is 0.55*
0.55=0.3025 microns of ^2, only the 54% of ideal value, reduce nearly half.In this case, two panels silicon wafer passes through metallic bond
The interconnection resistance that chalaza is realized is because the influence that contact area changes, can also fluctuate, out in 54% to 100% section of ideal value
Now each bonding point resistance is uneven.
As it can be seen that in the prior art, between silicon wafer caused by the register partial difference introduced as the functional limitation of above-mentioned hardware device
Between the different bonding points that interconnection resistance fluctuation is likely to be present in same silicon wafer, it is also possible to be present between different silicon wafers, this will be right
Design and simulation has an impact.It is more close with equipment register partial difference value with the diminution of bonding spot size, bonding resistance point
The big small drop of cloth range can be more serious.When fluctuation range is excessive, it may cause design and simulation and fail most deterioration
It takes into account, causes emulation to be distorted, or lead to most deterioration in order to balance and sacrifice the whole of the semiconductor devices bonded together to form
Body performance.Similarly, since bonding result is fluctuated because equipment alignment precision changes every time, the controllable of bonding technology is directly affected
Property.
It is well known that improving the alignment performance of equipment, it is huge and interminable for putting into the R&D cycle, therefore, it is necessary to
It proposes a kind of metal bonding lattice array for improving arrangement mode and the semiconductor devices for having the array, can make full use of existing
Hybrid bonded equipment, in the case of avoiding fine pith, because hybrid bonded equipment register partial difference caused by silicon wafer or semiconductor devices it
Between interconnection resistance be unevenly distributed, improve bonding technology controllability, realize reduce manufacturing cost, improve the final purpose of yield.
Summary of the invention
The technical problem to be solved by the present invention is to make full use of existing hybrid bonded equipment, in the case of avoiding fine pith,
Because hybrid bonded equipment register partial difference caused by between silicon wafer interconnection resistance uneven distribution, improve bonding technology controllability, it is real
Manufacturing cost is now reduced, the final purpose of yield is improved.
In order to solve the above technical problems, partly leading the invention proposes a kind of metal bonding lattice array for improving arrangement mode
Body device is formed by two panels silicon wafer that top layer is dielectric layer and metallic bond chalaza is hybrid bonded, and the metal bonding point forms section
The silicon chip surface is uniformly distributed in away from identical array；When hybrid bonded, two panels silicon wafer face to face, stacked on top, each silicon
Metallic bond chalaza in chip arrays corresponds, and is in contact with each other, which is characterized in that metal bonding in the array of each silicon wafer
Point is not of uniform size, is alternately intervally arranged in dielectric layer surface, the array arrangement between two silicon wafers of bonding corresponds to each other；
Optionally, the two panels silicon wafer size is identical；
Optionally, position can exchange up and down when the two panels wafer bonding of stacked on top；
Optionally, the metallic bond chalaza pitch range are as follows: 500nm-5000nm；
Optionally, metallic bond chalaza is divided to big bonding point and small bonding point two classes in the array of each silicon wafer, and by it is big,
It is small to be alternately intervally arranged；
Preferably, the large and small metallic bond chalaza being alternately intervally arranged, the section that the side length of big bonding point is 1/2
Away from the pitch and hybrid bonded equipment register that the sum of with hybrid bonded equipment alignment precision, the side length of the small bonding point is 1/2
The difference of precision；
Preferably, the alignment precision of the hybrid bonded equipment is its registration error 3sigma statistical value, range are as follows:
50nm-500nm；
Preferably, described be alternately intervally arranged refers to that around each big bonding point be small bonding point, and vice versa；
Optionally, the array arrangement between two silicon wafers of the bonding, which corresponds to each other, refers to, upper a piece of big bonding point exists
The position of position in array small bonding point a piece of under corresponding in an array, upper a piece of small bonding point are a piece of under then corresponding to
Big bonding point；
Optionally, the silica that the top layer dielectric layer of the semiconductor devices is 400nm to 4000nm by thickness range
The combined films such as film or silica, silicon nitride, silicon oxynitride are constituted.
The invention proposes the semiconductor devices of a kind of metal bonding lattice array for improving arrangement mode and the tool array.Make
For a kind of emerging chip Stack Technology, the hybrid bonded physical adhesion that 2 silicon wafers may be implemented simultaneously is completed at the same time electrical connection.This
Two panels silicon wafer top layer is dielectric layer and the metallic bond chalaza for being opened on dielectric layer surface in invention, and the metal bonding point is formed
The identical array of pitch is uniformly distributed in the silicon chip surface, and the metallic bond chalaza size in array is interlocked, in dielectric layer surface
It is alternately intervally arranged, and metallic bond chalaza pitch is identical.When hybrid bonded, two panels silicon wafer stacked on top, the big key of upper silicon wafer
The small bonding point of chalaza contact lower silicon slice；The big bonding point of the small bonding point contact lower silicon slice of upper silicon wafer.The big bonding point
The pitch and the sum of hybrid bonded equipment alignment precision that side length is 1/2, the side length of small bonding point for 1/2 pitch with mix key
Close the difference of equipment alignment precision.
Because using the intrinsic register partial difference of existing hybrid bonded equipment as one of the factor for determining bonding point size, originally
Interconnection resistance hinders between invention can be substantially reduced the silicon wafer as caused by the introducing para-linkage point contact area fluctuation of register partial difference
It is worth the inhomogeneities of variation, can be improved the controllability of bonding technology in actual production.It is with conventional metallic bond chalaza pitch
For 1.5 microns, 0.2 micron of bonding apparatus alignment precision.The a little bigger side length of metallic bond chalaza is 0.75+0.1=0.85 microns, small
Point side length is 0.75-0.1=0.65 microns.As it can be seen that minimum contact area is 0.65*0.65, about ideal value (0.75*075)
75%.Due to a little bigger side length-dot side length=alignment precision, it is hereby ensured that using arrangement mode of the present invention, after bonding,
Small bonding point can be entirely fallen in big bonding point range, completely attached to, to guarantee contact area, and then be kept in contact therewith
Resistance is constant.
Semiconductor devices of the present invention, for silicon wafer to be bonded preceding road manufacturing process there is no limit.Two panels silicon
Piece is respectively completed that (N or M can depend on product design requirement and technique energy from 1 to 20 layer to N or M by standard technology
Power) layer metal；Then dielectric layer deposited.Dielectric layer can be thickness can in 400nm to 4000nm, by silicon dioxide film, or
Person is that the combined films such as silica, silicon nitride, silicon oxynitride are constituted；Then, using conventional dual damascene process, pass through light
The techniques such as quarter, etching, metal filling, chemical mechanical grinding form metallic bond chalaza.According to the design needs, metallic bond chalaza can
To be connected by N or M layers of metal of lower section through-hole and lower layer；Or lower section does not have through-hole, does not only connect as one
Metallic bond chalaza, for guaranteeing the uniformity of chemical mechanical grinding.Bonding is finally completed using existing hybrid bonded equipment.
In conclusion the metal bonding lattice array of this improvement arrangement mode proposed by the present invention and partly leading for the tool array
Body device can make full use of existing hybrid bonded equipment, in the case of avoiding fine pith, because the register of hybrid bonded equipment is inclined
Difference causes interconnection resistance between silicon wafer or semiconductor devices to be unevenly distributed, and improves bonding technology controllability, and realizing reduces manufacture
Cost improves the final purpose of yield.
Detailed description of the invention
Fig. 1 is the arrangement schematic diagram of the hybrid bonded metallic bond chalaza of the prior art.
Fig. 2 is perfect condition hybrid bonded rear metallic bond chalaza sectional view in the prior art.
Fig. 3 is the hybrid bonded status diagram for metallic bond chalaza after register partial difference occur of the prior art.
Fig. 4 is the arrangement schematic diagram of metallic bond chalaza on upper and lower silicon wafer to be bonded in the present invention.
Fig. 5 is metallic bond chalaza sectional view after the present invention is hybrid bonded.
Specific embodiment
To keep the contents of the present invention more clear and easy to understand, below in conjunction with Figure of description, the contents of the present invention are made into one
Walk explanation.Certainly the invention is not limited to the specific embodiment, general replacement known to those skilled in the art
It is included within the scope of protection of the present invention.
Secondly, the present invention carries out detailed statement using schematic diagram, in detail that example of the present invention, for ease of description,
Schematic diagram is not partially enlarged in proportion to the general scale, should not be in this, as limitation of the invention.
It is explained one by one with reference to the manufacturing process that attached drawing arranges to hybrid bonded metallic bond chalaza proposed by the present invention.
In the present embodiment, the alignment precision of hybrid bonded equipment is 300nm.
1. substrate A is silicon wafer to be bonded, silicon wafer has passed through standard technology and has been completed to the 7th layer of metal；
2. depositing one layer of dielectric layer on the 7th layer of metal, dielectric layer is that thickness is 4000nm silicon dioxide film；
3. on the dielectric layer deposited, using conventional dual damascene process, filled by photoetching, etching, metal,
The techniques such as chemical mechanical grinding form metallic bond chalaza；According to the design needs, part metals bonding point is by lower section through-hole under
Layer metal connection；Beneath portions do not have through-hole, the metallic bond chalaza only not connected as one, for guaranteeing that chemical machinery is ground
The uniformity of mill；
4. the material of metallic bond chalaza is copper；
5. metal bonding presses a constant pitch and uniformly arranges on substrate A, as shown in figure 4, the pitch b of the present embodiment is
1500nm；
6. metal bonding point is staggered by size on substrate A, wherein the side length of big bonding point a1 is 1/2 (pitch+set
Quasi- precision) 900nm, the side length of small bonding point a2 is 1/2 (pitch-alignment precision) 600nm；The difference of the two is exactly to be bonded to set
Standby alignment precision value.
7. substrate B is another silicon wafer to be bonded, die size is consistent with substrate A, is completed to by standard technology
5th layer of metal；
8. repeating the above steps 2~4, top layer medium and large and small metallic bond chalaza are formed on substrate B
9. substrate B metal bonding presses pitch same as substrate A and uniformly arranges, pitch 1500nm.
10. substrate B metal bonding point is staggered by size, the side length of medium and small bonding point a11 is 1/2 (pitch-set
Quasi- precision) 600nm, the side length of big bonding point a21 is 1/2 (pitch+alignment precision) 900nm.
It arranges 11. substrate B metallic bond chalaza and substrate A metallic bond chalaza correspond, wherein the big bonding point pair of substrate A
Answer the small bonding point of substrate B, the big bonding point of the small bonding point corresponding substrate B of substrate A.So no matter bonding apparatus register shape
Under state how, bonding result can guarantee that small bonding point is entirely fallen in the range of the big bonding point of side silicon wafer, to guarantee key
Contact area after conjunction is constant.
12. progress is hybrid bonded, substrate A is face-down, and substrate B is face-up, passes through in bonding apparatus and is surface-treated, is right
Quasi-, physical contact and etc. realize the bonding of surface media, achieve the effect that 2 silicon wafer physical adhesions；Pass through annealing etc. again
Technique realizes the metal bonding of metallic bond chalaza, achievees the effect that 2 silicon wafer electrical connections, as shown in Figure 5.
Foregoing description is only the description to the embodiment of the present invention, not to any restriction of the scope of the invention, present invention neck
Any change, the modification that the those of ordinary skill in domain does according to the disclosure above content, belong to the protection scope of claims.
Claims (9)
1. a kind of semiconductor devices for the metal bonding lattice array for improving arrangement mode, is dielectric layer and metallic bond chalaza by top layer
The hybrid bonded composition of two panels silicon wafer, the metal bonding point forms the identical array of pitch and is uniformly distributed in the silicon wafer table
Face；When hybrid bonded, face to face, stacked on top, the metallic bond chalaza in each silicon chip arrays corresponds two panels silicon wafer, each other
Contact, which is characterized in that metallic bond chalaza is not of uniform size in the array of each silicon wafer, is alternately spaced in dielectric layer surface
It arranges, the array arrangement between two silicon wafers of bonding corresponds to each other, so that the position of the big bonding point of upper a piece of silicon wafer in an array
Set the position of the small bonding point of a piece of silicon wafer under corresponding in an array, a piece of silicon wafer under the small bonding point of upper a piece of silicon wafer then corresponds to
Big bonding point, so that it is guaranteed that bonding after contact area it is constant.
2. semiconductor devices as described in claim 1, which is characterized in that the two panels silicon wafer size is identical.
3. semiconductor devices as described in claim 1, which is characterized in that position when the two panels silicon wafer of stacked on top is hybrid bonded
It can exchange up and down.
4. semiconductor devices as described in claim 1, which is characterized in that the metallic bond chalaza pitch range are as follows: 500nm-
5000nm。
5. semiconductor devices as described in claim 1, which is characterized in that metallic bond chalaza point in the array of each silicon wafer
Two class of big bonding point and small bonding point, and be alternately intervally arranged by large and small.
6. semiconductor devices as claimed in claim 5, which is characterized in that the large and small metallic bond being alternately intervally arranged
Chalaza, the side length of big bonding point are the sum of 1/2 pitch and hybrid bonded equipment alignment precision, the side length of the small bonding point
For 1/2 pitch and the difference of hybrid bonded equipment alignment precision.
7. semiconductor devices as claimed in claim 6, which is characterized in that the alignment precision of the hybrid bonded equipment is its set
Quasi- error 3sigma statistical value, range are as follows: 50nm-500nm.
8. such as semiconductor devices described in claim 5 or 6, which is characterized in that it is described be alternately intervally arranged refer to it is each big
It is small bonding point around bonding point, vice versa.
9. semiconductor devices as described in claim 1, which is characterized in that the top layer dielectric layer of the semiconductor devices is by thickness
Range is that the combined films such as silicon dioxide film or silica, silicon nitride, the silicon oxynitride of 400nm to 4000nm are constituted.
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| CN110010479B (en) * | 2018-10-10 | 2021-04-06 | 浙江集迈科微电子有限公司 | Fan-out packaging process of radio frequency chip |
| CN111244123A (en) * | 2020-02-03 | 2020-06-05 | 长江存储科技有限责任公司 | Semiconductor structure and preparation method thereof |
| US11233088B2 (en) * | 2020-06-12 | 2022-01-25 | Omnivision Technologies, Inc. | Metal routing in image sensor using hybrid bonding |
| WO2023178112A1 (en) * | 2022-03-16 | 2023-09-21 | Adeia Semiconductor Bonding Technologies Inc. | Expansion control for bonding |
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