CN107256192A - A kind of monitoring method of clock failure, device and server - Google Patents
A kind of monitoring method of clock failure, device and server Download PDFInfo
- Publication number
- CN107256192A CN107256192A CN201710401195.4A CN201710401195A CN107256192A CN 107256192 A CN107256192 A CN 107256192A CN 201710401195 A CN201710401195 A CN 201710401195A CN 107256192 A CN107256192 A CN 107256192A
- Authority
- CN
- China
- Prior art keywords
- clock
- waveform
- target
- clock signal
- failure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/32—Monitoring with visual or acoustical indication of the functioning of the machine
- G06F11/321—Display for diagnostics, e.g. diagnostic result display, self-test user interface
- G06F11/322—Display of waveforms, e.g. of logic analysers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3051—Monitoring arrangements for monitoring the configuration of the computing system or of the computing system component, e.g. monitoring the presence of processing resources, peripherals, I/O links, software programs
Abstract
The present invention provides a kind of monitoring method of clock failure, device and server, by obtaining the target clock signal that system clock is sent, and the reference clock signal that reference clock is sent；According to the target clock signal, target waveform is obtained；According to the reference clock signal, reference waveform is obtained；Judge whether the target waveform matches with the reference waveform；When the target waveform and the reference waveform are mismatched, send and recording clock fault message, the clock failure information is abnormal for describing system clock generation.System clock is verified by using reference clock, can effective monitoring system clock whether there is without output and the mistake such as frequency anomaly, when system clock occurs abnormal, record in time and send clock failure information, it is convenient to carry out malfunction elimination, improve the ease for maintenance and reliability of server.
Description
Technical field
The present invention relates to field of computer technology, more particularly to a kind of monitoring method of clock failure, device and service
Device.
Background technology
System clock is very important part in server.In the server, system clock is produced by clock source,
And it is divided into multichannel respectively to central processing unit（English：Central Processing Unit, referred to as：CPU）, in platform courses
The heart（English：Platform Controller Hub, referred to as：PCH）、PCIE（English：peripheral component
Interconnect express, Chinese：High speed serialization computer expansion bus standard）Groove, baseboard management controller（English：
Baseboard Management Controller, referred to as：BMC）Clock is provided etc. equipment.
Required precision of the server to system clock is very high, if timing uncertainty occurs for system clock, it is easy to cause clothes
Device reliability of being engaged in reduction, machine etc. of even delaying.Moreover, in current server system design, seldom being carried out to system clock quality
Monitoring, when system breaks down because of clock problem, it is impossible to where quick location-server system problem, and need engineer
Field adjustable is analyzed, and the maintenance to server causes difficulty.
Therefore, the ease for maintenance and reliability for how improving server are that the technology of those skilled in the art's urgent need to resolve is asked
Topic.
The content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of monitoring side of clock failure
Method, device and server, for solving the problem of server hardly possible is safeguarded, reliability is low in the prior art.
In order to achieve the above objects and other related objects, according to the first aspect of the invention, the embodiment of the present invention provides one
The monitoring method of clock failure is planted, is comprised the following steps：
Obtain the target clock signal that system clock is sent, and the reference clock signal that reference clock is sent；
According to the target clock signal, target waveform is obtained；
According to the reference clock signal, reference waveform is obtained；
Judge whether the target waveform matches with the reference waveform；
When the target waveform and the reference waveform are mismatched, send and recording clock fault message, the clock failure
Information is used to describe system clock generation exception.
Alternatively, it is described according to target clock signal, target waveform is obtained, including：
Target clock signal is counted；
When counting reaches first predetermined value, high impulse is exported.
Alternatively, it is described according to reference clock signal, reference waveform is obtained, including：
While being counted to the target clock signal, the reference clock signal is counted；
When counting reaches second predetermined value, high level is exported；
When counting reaches third predetermined value, low level is exported.
Alternatively, judge whether the target waveform matches with the reference waveform, including：
When target waveform and reference waveform are high level, determine that the target waveform is matched with the reference waveform；Or,
When target waveform is high level, and reference waveform is when being low level, determines the target waveform and the reference waveform not
Matching.
Alternatively, judge whether the target waveform matches with the reference waveform, including：
When reference waveform high impulse occurs in high level scope, and target waveform, the target waveform and the ginseng are determined
Examine Waveform Matching；Or,
When reference waveform be in high level scope, and target waveform be steady waveform when, determine the target waveform and the ginseng
Examine waveform mismatch.
Alternatively, the second predetermined value is less than or equal to the first predetermined value, the second predetermined value and described the
The difference of one predetermined value is more than the width of the high impulse.
According to the second aspect of the invention, the embodiment of the present invention also provides a kind of supervising device of clock failure, the monitoring
Device includes monitoring chip, reference clock and Management Controller, wherein：
The monitoring chip is electrically connected with system clock and reference clock, for obtaining the target clock letter that system clock is sent
Number, and the reference clock signal that reference clock is sent；According to the target clock signal, target waveform is obtained；According to described
Reference clock signal, obtains reference waveform；Judge whether the target waveform matches with the reference waveform；
The monitoring chip is also communicated to connect with the Management Controller, for when the target waveform and the reference waveform not
During matching, clock failure information is sent to the Management Controller, the clock failure information is used to describe system clock
Parameter information during failure；The Management Controller is used for clock failure information described in stored record.
Alternatively, the monitoring chip includes fpga chip.
Alternatively, the Management Controller includes memory, and the reference clock includes the clock being made up of multiple clocks
Group.
According to the third aspect of the invention we, the embodiment of the present invention also provides a kind of server, including system clock, Yi Jishang
State the supervising device described by embodiment
As described above, monitoring method, device and the server of the clock failure of the present invention, have the advantages that：The present invention
By obtaining the target clock signal that system clock is sent, and the reference clock signal that reference clock is sent；According to the mesh
Clock signal is marked, target waveform is obtained；According to the reference clock signal, reference waveform is obtained；Judge the target waveform with
Whether the reference waveform matches；When the target waveform and the reference waveform are mismatched, send and recording clock failure
Information, the clock failure information is used to describe system clock generation exception.System clock is carried out by using reference clock
Verification, can effective monitoring system clock whether there is without output and the mistake such as frequency anomaly, occur in system clock abnormal
When, record in time and send clock failure information, it is convenient to carry out malfunction elimination, improve the ease for maintenance and reliability of server.
Brief description of the drawings
Fig. 1 is a kind of schematic flow sheet of the monitoring method of clock failure provided in an embodiment of the present invention.
Fig. 2 is a kind of schematic flow sheet of target waveform generation method provided in an embodiment of the present invention.
Fig. 3 is a kind of schematic flow sheet of reference waveform generation method provided in an embodiment of the present invention.
Fig. 4 is a kind of schematic flow sheet of Waveform Matching determination methods provided in an embodiment of the present invention.
Fig. 5 is the schematic flow sheet of another Waveform Matching determination methods provided in an embodiment of the present invention.
Fig. 6 is a kind of structural representation of the supervising device of clock failure provided in an embodiment of the present invention.
Fig. 6 symbol is expressed as：
1- monitoring chips, 2- reference clocks, 3- Management Controllers, 4- system clocks, 41- clock sources, 42- clock buffers, 5-
Terminal.
Embodiment
In order that those skilled in the art more fully understand the technical scheme in the present invention, below in conjunction with of the invention real
The accompanying drawing in example is applied, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described implementation
Example only a part of embodiment of the invention, rather than whole embodiments.Based on the embodiment in the present invention, this area is common
The every other embodiment that technical staff is obtained under the premise of creative work is not made, should all belong to protection of the present invention
Scope.
Fig. 1 is referred to Fig. 6.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, only display is with relevant component in the present invention rather than according to package count during actual implement in illustrating then
Mesh, shape and size are drawn, and kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its
Assembly layout kenel may also be increasingly complex.
It is a kind of schematic flow sheet of the monitoring method of clock failure provided in an embodiment of the present invention referring to Fig. 1.Such as Fig. 1
Shown, the monitoring method comprises the following steps：
Step S101：Obtain the target clock signal that system clock is sent, and the reference clock signal that reference clock is sent.
The monitoring chip being built in embodiments of the present invention in server can be electrically connected with system clock in server,
So monitoring chip can obtain the clock signal that the system clock of server to be monitored is sent, and by the clock of system clock
Signal is as target clock signal, using the basis in subsequent step as Determination.Wherein, in the specific implementation, it is described
Monitoring chip can be FPGA（English：Field Programmable Gate Array, Chinese：Field programmable gate array）
Chip, or CPLD（English：Complex Programmable Logic Device, Chinese：CPLD）
The control chips such as chip, are not limited in embodiments of the present invention.
Moreover, the monitoring chip can also be electrically connected with a reference clock, such monitoring chip is when getting system
While the target clock signal that clock is sent, the clock signal that reference clock is sent, and the clock that reference clock is sent are obtained
Signal is as reference clock signal, to be verified in subsequent step according to reference clock signal to target clock signal.
It should be noted that clock failure will be described in detail using monitoring chip as subject of implementation in the embodiment of the present invention
Monitoring method.
Step S102：According to the target clock signal, target waveform is obtained.
Monitoring chip is obtained after the target clock signal, and the target clock signal is handled, target ripple is obtained
Shape.
It is a kind of schematic flow sheet of target waveform generation method provided in an embodiment of the present invention referring to Fig. 2.Such as Fig. 2 institutes
Show, this method includes：
Step S1021：Target clock signal is counted.
In the specific implementation, target clock can be believed by counting the rising edge or trailing edge of target clock signal and realizing
Number counting.
Step S1022：When counting reaches first predetermined value, high impulse is exported.
When counting reaches first predetermined value, a high impulse is exported, wherein, the first predetermined value can be to preset
Any number, such as can be 10,20, do not limited in inventive embodiments.Moreover, the width of the high impulse, i.e.,
The high level lasting time of high impulse, can also be set to any number, such as tens microseconds or milli according to specific detection demand
Second etc..
So, the signal waveform obtained by above-mentioned steps is used as target waveform.
Step S103：According to the reference clock signal, reference waveform is obtained.
Equally, while carrying out target waveform output, according to reference clock signal, reference waveform is obtained.
It is a kind of schematic flow sheet of reference waveform generation method provided in an embodiment of the present invention referring to Fig. 3.Such as Fig. 3 institutes
Show, this method includes：
Step S1031：While counting to the target clock signal, the reference clock signal is counted.
While being counted to target clock signal, reference clock signal is also counted, specifically technical side
Method, may refer to step S1021 description, will not be repeated here.
Step S1032：When counting reaches second predetermined value, high level is exported.
When counting reaches second predetermined value, high level is exported.Under the first performance, the second predetermined value can
With equal to the first predetermined value, so while target waveform is high impulse, obtained reference waveform is also high level.
Under second of performance, the second predetermined value can be less than the first predetermined value, the second predetermined value and described the
Gap between one predetermined value before such target waveform is high impulse, high level can occur with 2 to 10 etc. in reference waveform.
Step S1033：When counting reaches third predetermined value, low level is exported.
When counting reaches third predetermined value, low level is exported.In an exemplary implementation, the second predetermined value and institute
The width of high impulse of target waveform can be more than by stating the difference of first predetermined value, and so, the high impulse of target waveform may be at
In the range of the high level of reference waveform.
So, the signal waveform obtained by above-mentioned steps can be used as reference waveform.
In order to ensure the precision of reference waveform, in an exemplary implementation, the multigroup ginseng sent by reference clock can be obtained
Clock signal is examined, in the specific implementation, the reference clock can include multigroup clock, and every group of clock sends reference clock all the way
Signal.Such as described reference clock includes 3 groups of clocks, i.e. the first reference clock, the second reference clock and the 3rd reference clock lead to
The first reference waveform of the first reference clock, the second reference waveform of the second reference clock and can be obtained by crossing above-mentioned steps
3rd reference waveform of three reference clocks, from the first reference waveform, the second reference waveform and the 3rd reference waveform, is selected
2 nearest reference waveforms of skew, and subsequent step and target waveform are carried out with any one in 2 reference waveforms
Verification.
Step S104：Judge whether the target waveform matches with the reference waveform.
Under the first performance, in order to judge whether the target waveform matches with the reference waveform, referring to figure
4, it is a kind of schematic flow sheet of Waveform Matching determination methods provided in an embodiment of the present invention.As shown in figure 4, this method includes：
Step S1041：When target waveform and reference waveform are high level, the target waveform and the reference waveform are determined
Matching.
When target waveform is high level, whether be high level, if target waveform and reference waveform if judging reference waveform
It is high level, it is determined that target waveform is matched with reference waveform, system clock is normal.Further, monitoring chip can be reset
Counter register, return to step S102, is counted to get target waveform and reference waveform again.
Step S1042：When target waveform be high level, and reference waveform be low level when, determine the target waveform with
The reference waveform is mismatched.
When target waveform is high level, if reference waveform is low level, it is determined that target waveform and reference waveform are not
Matching, system clock is abnormal, and system clock exception is handled into subsequent step.
In the first above-mentioned performance, can effective monitoring system clock whether there is it is abnormal without output etc. so that
Ensure the precision of clock failure monitoring.
Under second of performance, in order to judge whether the target waveform matches with the reference waveform, referring to figure
5, it is the schematic flow sheet of another Waveform Matching determination methods provided in an embodiment of the present invention.As shown in figure 5, this method bag
Include：
Step S1043：When reference waveform high impulse occurs in high level scope, and target waveform, the target ripple is determined
Shape is matched with the reference waveform.
When reference waveform is in the range of high level, if there is high impulse in target waveform correspondence, it is determined that target waveform
Matched with reference waveform, system clock is normal.Further, monitoring chip can reset counter register, and return to step S102 enters
Row counts to get target waveform and reference waveform again.
Step S1044：When reference waveform be in high level scope, and target waveform be steady waveform when, determine the mesh
Waveform is marked to mismatch with the reference waveform.
When reference waveform is in high level scope, target waveform is that high impulse is not present in steady waveform, it is determined that mesh
Mark waveform to mismatch with reference waveform, system clock is abnormal, system clock exception is handled into subsequent step.
In second of performance, due to target waveform and the possible concussion of reference waveform, pass through target waveform
High impulse whether correspond to the high level scope of reference waveform, can interpolate that system clock whether in the normal range (NR), and
And due to there is wrong redundancy, effectively prevent erroneous judgement.
Step S105：When the target waveform and the reference waveform are mismatched, send and recording clock fault message,
The clock failure information is used to describe system clock generation exception.
According to step S104 judgement, if target waveform is mismatched with the reference waveform, system clock is characterized different
Often.Further, monitoring chip can be sent and recording clock fault message, or monitoring chip can be sent to Management Controller
Clock failure information, is recorded by Management Controller to clock failure information.Wherein, the clock failure information can include
Occur the time of clock failure, obtained target clock frequency is counted from target clock signal and is united from reference clock signal
Reference clock frequency that meter is obtained etc., by the clock failure information, technical staff can know that system clock may in time
Generation is abnormal, and by the analysis to clock failure information, system clock abnormal conditions are estimated.Monitoring chip is in hair
Go out after clock failure information, individual count register can also be reset, so that return to step S102, counts to get target ripple again
Shape and reference waveform.
From the description of above-described embodiment, a kind of monitoring method of clock failure provided in an embodiment of the present invention, the prison
Prosecutor method includes obtaining the target clock signal that system clock is sent, and the reference clock signal that reference clock is sent；According to
The target clock signal, obtains target waveform；According to the reference clock signal, reference waveform is obtained；Judge the target
Whether waveform matches with the reference waveform；When the target waveform and the reference waveform are mismatched, when sending and recording
Clock fault message, the clock failure information is used to describe system clock generation exception.During by using reference clock to system
Clock is verified, can effective monitoring system clock whether there is without output and the mistake such as frequency anomaly, in system clock hair
When raw abnormal, record in time and send clock failure information, it is convenient to carry out malfunction elimination, improve server ease for maintenance and can
By property.
The description of embodiment of the method more than, it is apparent to those skilled in the art that the present invention can
Realized by the mode of software plus required general hardware platform, naturally it is also possible to by hardware, but in many cases the former
It is more preferably embodiment.Understood based on such, technical scheme substantially makes tribute to prior art in other words
The part offered can be embodied in the form of software product, and the computer software product is stored in a storage medium, bag
Some instructions are included to cause a computer equipment（Can be personal computer, server, or network equipment etc.）Perform
The all or part of step of each embodiment methods described of the invention.And foregoing storage medium includes：Read-only storage
（ROM）, random access memory（RAM）, magnetic disc or CD etc. are various can be with the medium of store program codes.
It is corresponding with the monitoring method embodiment of a kind of clock control that the present invention is provided, present invention also offers it is a kind of when
The supervising device of clock failure.
It is a kind of structural representation of the supervising device of clock failure provided in an embodiment of the present invention, such as Fig. 6 referring to Fig. 6
Shown, the supervising device includes monitoring chip 1, reference clock 2 and Management Controller 3.
Wherein, the monitoring chip 1 is electrically connected with system clock 4 and reference clock 2.The monitoring chip 1 can be obtained
The target clock signal for taking system clock 4 to send；In the specific implementation, the system clock 4 generally include clock source 41 and when
Clock buffer 42, the clock source 41 includes quartz oscillator and positive feedback oscillating circuit, for producing frequency stabilization
Pulse signal, clock source 41 is connected with clock buffer 42, and is multiple terminals 5 in server by clock buffer 42
Clock signal is provided.It is that monitoring chip 1 separates clock signal all the way by clock buffer 42, such monitoring chip 1 can be obtained
The clock signal that system clock 4 is sent is got, and the clock signal that system clock 4 is sent is used as target clock signal.
The monitoring chip 1 can also obtain reference clock signal from reference clock 2, and the reference clock signal can be managed
Solve the clock signal sent for reference clock 2；Further, monitoring chip 1 obtains target ripple according to the target clock signal
Shape, and according to the reference clock signal, obtain reference waveform；Judge the target waveform and the reference waveform whether
Match somebody with somebody.
The monitoring chip 1 is also communicated to connect with the Management Controller 3.When monitoring chip 1 judges target waveform and ginseng
When examining waveform mismatch, clock failure information is sent to the Management Controller 3, the clock failure information is used to describe system
Parameter information when clock 2 breaks down.
Moreover, the Management Controller 3 can store the clock failure information, and when notification technique personnel occur in time
Clock fault message, and facilitate technical staff by analyzing the clock failure information, server is safeguarded.
In the specific implementation, the monitoring chip 1 can be fpga chip, CPLD chips etc..In the Management Controller 3
The memories such as flash memory, hard disk are also provided with, for clock failure information described in stored record.
In order to improve the judgement precision of clock failure, in one exemplary embodiment, the reference clock can include by
The clock group that multiple clocks are constituted.The multichannel reference clock signal that monitoring chip 1 is sent according to clock group, obtains reference waveform,
And then judge whether target waveform matches with reference waveform.
In addition, it is necessary to explanation, the embodiment of the present invention and the monitoring method embodiment something in common of above-mentioned clock failure,
Reference can be made to the description of above-described embodiment, will not be repeated here.
The embodiment of the present invention also provides a kind of server, and the server includes system clock, and above example institute
The supervising device of description.Moreover, the monitoring chip in the supervising device can be configured as performing the prison of above-mentioned clock failure
Control the monitoring method described by embodiment of the method.
Certainly, the monitoring method and supervising device of the described clock failure of present invention implementation can also be applied to other bands
Have in the equipment of system clock, such as in PC, industrial computer and embedded device, and be not limited to server.
Each embodiment in this specification is described by the way of progressive, identical similar portion between each embodiment
Divide mutually referring to what each embodiment was stressed is the difference with other embodiment.Especially for device or
For system embodiment, because it is substantially similar to embodiment of the method, so describing fairly simple, related part is referring to method
The part explanation of embodiment.Apparatus and system embodiment described above is only schematical, wherein the conduct
The unit that separating component illustrates can be or may not be it is physically separate, the part shown as unit can be or
Person may not be physical location, you can with positioned at a place, or can also be distributed on multiple NEs.Can root
Some or all of module therein is factually selected to realize the purpose of this embodiment scheme the need for border.Ordinary skill
Personnel are without creative efforts, you can to understand and implement.
It should be noted that herein, the relational terms of such as " first " and " second " or the like are used merely to one
Individual entity or operation make a distinction with another entity or operation, and not necessarily require or imply these entities or operate it
Between there is any this actual relation or order.Moreover, term " comprising ", "comprising" or its any other variant are intended to
Cover including for nonexcludability, so that process, method, article or equipment including a series of key elements not only include those
Key element, but also other key elements including being not expressly set out, or also include for this process, method, article or set
Standby intrinsic key element.In the absence of more restrictions, the key element limited by sentence "including a ...", it is not excluded that
Also there is other identical element in the process including the key element, method, article or equipment.
Described above is only the embodiment of the present invention, is made skilled artisans appreciate that or realizing this hair
It is bright.A variety of modifications to these embodiments will be apparent to one skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, it is of the invention
The embodiments shown herein is not intended to be limited to, and is to fit to and principles disclosed herein and features of novelty phase one
The most wide scope caused.
Claims (10)
1. a kind of monitoring method of clock failure, it is characterised in that including：
Obtain the target clock signal that system clock is sent, and the reference clock signal that reference clock is sent；
According to the target clock signal, target waveform is obtained；
According to the reference clock signal, reference waveform is obtained；
Judge whether the target waveform matches with the reference waveform；
When the target waveform and the reference waveform are mismatched, send and recording clock fault message, the clock failure
Information is used to describe system clock generation exception.
2. the monitoring method of clock failure according to claim 1, it is characterised in that described according to target clock signal,
Target waveform is obtained, including：
Target clock signal is counted；
When counting reaches first predetermined value, high impulse is exported.
3. the monitoring method of clock failure according to claim 2, it is characterised in that described according to reference clock signal,
Reference waveform is obtained, including：
While being counted to the target clock signal, the reference clock signal is counted；
When counting reaches second predetermined value, high level is exported；
When counting reaches third predetermined value, low level is exported.
4. the monitoring method of clock failure according to claim 3, it is characterised in that judge the target waveform with it is described
Whether reference waveform matches, including：
When target waveform and reference waveform are high level, determine that the target waveform is matched with the reference waveform；Or,
When target waveform is high level, and reference waveform is when being low level, determines the target waveform and the reference waveform not
Matching.
5. the monitoring method of clock failure according to claim 3, it is characterised in that judge the target waveform with it is described
Whether reference waveform matches, including：
When reference waveform high impulse occurs in high level scope, and target waveform, the target waveform and the ginseng are determined
Examine Waveform Matching；Or,
When reference waveform be in high level scope, and target waveform be steady waveform when, determine the target waveform and the ginseng
Examine waveform mismatch.
6. the monitoring method of clock failure according to claim 3, it is characterised in that the second predetermined value is less than or waited
In the first predetermined value, the difference of the second predetermined value and the first predetermined value is more than the width of the high impulse.
7. a kind of supervising device of clock failure, it is characterised in that including monitoring chip, reference clock and Management Controller, its
In：
The monitoring chip is electrically connected with system clock and reference clock, for obtaining the target clock letter that system clock is sent
Number, and the reference clock signal that reference clock is sent；According to the target clock signal, target waveform is obtained；According to described
Reference clock signal, obtains reference waveform；Judge whether the target waveform matches with the reference waveform；
The monitoring chip is also communicated to connect with the Management Controller, for when the target waveform and the reference waveform not
During matching, clock failure information is sent to the Management Controller, the clock failure information is used to describe system clock
Parameter information during failure；The Management Controller is used for clock failure information described in stored record.
8. the supervising device of clock failure according to claim 7, it is characterised in that the monitoring chip includes FPGA cores
Piece.
9. the supervising device of clock failure according to claim 7, it is characterised in that the Management Controller includes storage
Device, the reference clock includes the clock group being made up of multiple clocks.
10. a kind of server, it is characterised in that including system clock, and the monitoring as described in any one of claim 7 to 9
Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710401195.4A CN107256192A (en) | 2017-05-31 | 2017-05-31 | A kind of monitoring method of clock failure, device and server |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710401195.4A CN107256192A (en) | 2017-05-31 | 2017-05-31 | A kind of monitoring method of clock failure, device and server |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107256192A true CN107256192A (en) | 2017-10-17 |
Family
ID=60028234
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710401195.4A Pending CN107256192A (en) | 2017-05-31 | 2017-05-31 | A kind of monitoring method of clock failure, device and server |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107256192A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109342917A (en) * | 2018-08-31 | 2019-02-15 | 青岛海信电器股份有限公司 | The verification method and device of clock signal |
| CN109857192A (en) * | 2019-02-27 | 2019-06-07 | 苏州浪潮智能科技有限公司 | A kind of signal processing method, device, system, equipment and readable storage medium storing program for executing |
| CN111611768A (en) * | 2020-05-21 | 2020-09-01 | 北京百度网讯科技有限公司 | Method and apparatus for monitoring a clock signal |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102062817A (en) * | 2009-11-13 | 2011-05-18 | 中兴通讯股份有限公司 | Frequency offset detection method and device for crystal oscillator of electronic product |
| CN102692563A (en) * | 2012-05-18 | 2012-09-26 | 大唐微电子技术有限公司 | Clock frequency detector |
| CN103647552A (en) * | 2013-12-03 | 2014-03-19 | 北京中电华大电子设计有限责任公司 | Clock frequency detection circuit |
-
2017
- 2017-05-31 CN CN201710401195.4A patent/CN107256192A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102062817A (en) * | 2009-11-13 | 2011-05-18 | 中兴通讯股份有限公司 | Frequency offset detection method and device for crystal oscillator of electronic product |
| CN102692563A (en) * | 2012-05-18 | 2012-09-26 | 大唐微电子技术有限公司 | Clock frequency detector |
| CN103647552A (en) * | 2013-12-03 | 2014-03-19 | 北京中电华大电子设计有限责任公司 | Clock frequency detection circuit |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109342917A (en) * | 2018-08-31 | 2019-02-15 | 青岛海信电器股份有限公司 | The verification method and device of clock signal |
| CN109857192A (en) * | 2019-02-27 | 2019-06-07 | 苏州浪潮智能科技有限公司 | A kind of signal processing method, device, system, equipment and readable storage medium storing program for executing |
| CN111611768A (en) * | 2020-05-21 | 2020-09-01 | 北京百度网讯科技有限公司 | Method and apparatus for monitoring a clock signal |
| CN111611768B (en) * | 2020-05-21 | 2023-04-25 | 北京百度网讯科技有限公司 | Method and device for monitoring clock signals |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10931511B2 (en) | Predicting computer network equipment failure | |
| US7181711B2 (en) | Prioritizing of nets for coupled noise analysis | |
| US20150369865A1 (en) | Detection of fault injection attacks using high-fanout networks | |
| CN107256192A (en) | A kind of monitoring method of clock failure, device and server | |
| CN111414268B (en) | Fault processing method and device and server | |
| CN112327766B (en) | High-frequency pulse counting system and measuring method of nuclear safety level DCS (distributed control System) | |
| CN113037595B (en) | Abnormal device detection method and device, electronic device and storage medium | |
| CN110727556A (en) | BMC health state monitoring method, system, terminal and storage medium | |
| EP2631803A1 (en) | Methods and apparatus for automatic fault detection | |
| CN108763071A (en) | A kind of webpage test method and terminal device | |
| CN109995612A (en) | A kind of service method for inspecting, device and electronic equipment | |
| CN107526664A (en) | A kind of server exception power down method for rapidly positioning and device | |
| CN114020511A (en) | FPGA-based fault detection method, device, equipment and readable storage medium | |
| US8073587B2 (en) | Diagnostic method for locating a failure in a complex system, and a device for implementing said method | |
| KR20140093521A (en) | Multi-core device, test device and method for diagnosing failure | |
| TW202038053A (en) | Coverage based microelectronic circuit, and method for providing a design of a microelectronic circuit | |
| CN113407391A (en) | Fault processing method, computer system, substrate management controller and system | |
| TW202248616A (en) | Method and electronic device for detecting abnormality of stamping equipment | |
| Usas | A totally self-checking checker design for the detection of errors in periodic signals | |
| US20100162269A1 (en) | Controllable interaction between multiple event monitoring subsystems for computing environments | |
| WO2023045248A1 (en) | Detection apparatus for power supply voltage of hard disk | |
| CN111459734A (en) | Method and system for testing fault monitoring period and computer storage medium | |
| CN110147140A (en) | A kind of clock signal, which is intersected, compares monitoring method and circuit | |
| US10831686B1 (en) | Method of determining hard disk operation status | |
| CN114329108B (en) | Production condition analysis method and system based on chip functional circuit simulation test |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20171017 |
|
| RJ01 | Rejection of invention patent application after publication |