CN1072529A - Data transmission circuit - Google Patents
Data transmission circuit Download PDFInfo
- Publication number
- CN1072529A CN1072529A CN92112356A CN92112356A CN1072529A CN 1072529 A CN1072529 A CN 1072529A CN 92112356 A CN92112356 A CN 92112356A CN 92112356 A CN92112356 A CN 92112356A CN 1072529 A CN1072529 A CN 1072529A
- Authority
- CN
- China
- Prior art keywords
- input
- bit line
- line
- linked
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 title claims abstract description 32
- 239000004065 semiconductor Substances 0.000 claims description 7
- 238000002955 isolation Methods 0.000 description 6
- SVTBMSDMJJWYQN-UHFFFAOYSA-N 2-methylpentane-2,4-diol Chemical compound CC(O)CC(C)(C)O SVTBMSDMJJWYQN-UHFFFAOYSA-N 0.000 description 4
- ANNNBEZJTNCXHY-NSCUHMNNSA-N Isorhapontigenin Chemical compound C1=C(O)C(OC)=CC(\C=C\C=2C=C(O)C=C(O)C=2)=C1 ANNNBEZJTNCXHY-NSCUHMNNSA-N 0.000 description 3
- JXASPPWQHFOWPL-UHFFFAOYSA-N Tamarixin Natural products C1=C(O)C(OC)=CC=C1C1=C(OC2C(C(O)C(O)C(CO)O2)O)C(=O)C2=C(O)C=C(O)C=C2O1 JXASPPWQHFOWPL-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
Abstract
A kind of data transmission circuit is when carrying out data write operation, by suppressing the generation of DC current, with the I/O of high speed processing data after data reading operation.Data transmission circuit has a shared input/output line, is used for the sensing transistor circuit of potential difference (PD) between the sensing bit line, is used to receive the input transistors circuit of data and the output transistor circuit that is used for deal with data.Shared input/output line electrically isolates from input transistors circuit and sensing transistor circuit during data write operation.
Description
The present invention relates to the data transmission circuit of dynamic random access memory (DRAM), more specifically say, relate to and being used for the integrated data transmission circuit of the height of high speed processing data.
Recently, SIC (semiconductor integrated circuit) has developed into and has made circuit height integrated and be operated at a high speed stage.But if obtained highly integrated circuit, then its travelling speed will reduce.On the contrary, if the energy high-speed cruising is difficult to then realize that the height to circuit is integrated.Therefore, obtaining high-speed cruising and highly integrated circuit simultaneously is that of SIC (semiconductor integrated circuit) field has problem to be solved.Specifically, because the data transmission circuit that is used in the SIC (semiconductor integrated circuit) is influential to high-speed cruising and highly integrated circuit, therefore, the circuit structure of data transmission circuit and to the suitable selection of its element for the SIC (semiconductor integrated circuit) that realizes high-speed cruising with highly integrated cause close important.
Referring to Fig. 1, traditional data transmission circuit shown in the figure, it comprises memory cell 9 and 10, word line 11 and 12, bit line 15 and 16, be associated in the sensor amplifier 7 between bit line 15 and 16, be used for isolated transistor 1 that memory cell 9 and 10 is kept apart from bit line 15 and 16,2,3,4, input/output transistors 5 and 6 with source-leakage passage, the terminal of each source-leakage passage is linked on bit line 15 and 16, be connected to the public input/ output line 13 and 14 and be associated in I/O sensor amplifier 8 on public input/ output line 13 and 14 on each source-other terminals of leakage passage of input/output transistors 5 and 6.
The work of Fig. 1 is described in conjunction with Fig. 2 A to 2D now.After data are read from memory cell 9, be associated in isolated transistor 1 and 2 conductings on the memory cell 9, simultaneously, isolated transistor 3 and 4 turn-offs.In addition, the word line 11 that is associated on the memory cell 9 is selected, so that the data of memory cell 9 are transferred to bit line 15.So, the potential difference (PD) that sensor amplifier 7 amplifies between the bit line 15 and 16.If CSL is effective for column selection line signal, then the data on bit line 15 and 16 are transferred to input/ output line 13 and 14 through input/output transistors 5 and 6.The potential difference (PD) of the data on the input/ output line 13 and 14 of being left behind by the stray capacitance of input/ output line 13 and 14 is transfused to/exports sensor amplifier 8 again and amplifies.The principal character of this data transmission circuit is, input/output transistors 5 and source-leakage passage of 6 be associated in respectively bit line 15 and 16 and input/ output line 13 and 14 between.Shown in Fig. 2 B and 2C, as the potential difference (PD) △ of bit line 15 and 16 V
BLWhen being about 1 volt, then column selection line signal CSL as logic " height " level and effectively.In addition, because column selection line signal CSL must be just effective after the potential difference (PD) of bit line 15 and 16 is sufficiently amplified, the reduction of the travelling speed that caused time delay by column selection line signal CSL appears thus.In addition, because the data that are transferred on input/ output line 13 and 14 are passed input/output transistors 5 and 6, so produce the voltage drop identical with the threshold voltage of input/output transistors 5 and 6.In addition, when input/output transistors 5 and 6 conductings, because input/ output line 13 and 14 and bit line 15 and 16 be associated in input/output transistors 5 and 6, then stray capacitance increases, the potential difference (PD) that is transferred to the data on input/ output line 13 and 14 will further reduce.As a result, the sensing ability of input/output line sensor amplifier 8 will worsen.
Fig. 3 provides another kind of conventional data transmission circuit, and wherein the problem in the circuit is solved among Fig. 1.This data transmission circuit discloses in the korean patent application 91-123283 that submitted on July 31st, 1991.For the I/O that makes data operates at a high speed, then first and second output transistors 31 and 32 grid directly are linked to bit line 23 and 24 respectively, and the source of first and second input transistors 33 and 34-leakage passage be associated in respectively data input/ output line 35 and 36 and bit line 23 and 24 between.In addition, in order to obtain the circuit of high integration, then input/ output line 35 and 36 is used as a pair of public input/output line, reduces transistorized number thus.Reference number 37 to 44 constitutes a write circuit, and square frame A and B shown in broken lines have indicated write driver respectively.
With reference now to Fig. 4 A to 4D, the operation of Fig. 3 is described.When data are read from memory cell 21, word line WL(L) selected, the data that are stored in the memory cell 21 are transferred on the bit line 23.Subsequently, bit line 23 and 24 current potential are transformed into a mains voltage level Vcc and a ground voltage level Vss respectively by a sensor amplifier 29.Like this, if it is effective to read column selection line signal RCSL, then discharge transistor 30 conductings, and first and second output transistors 31 and 32 are worked with a current sense amplifier.Should be appreciated that the current potential of input/output line 35 remains on its level when first output transistor 31 turn-offs.Simultaneously, because second output transistor 32 is carved conducting at this moment, then the current potential of input/output line 36 discharges through discharge transistor 30 voltage-to-ground terminals.Subsequently, the potential difference (PD) between first and second input/ output lines 35 and 36 be transfused to/output line sensor amplifier 45 amplifies to a greater degree, and the output of this sensor amplifier 45 is transferred to the periphery of storing apparatus.Above-mentionedly read operation and carry out with following speed, this speed is higher than the data of bit line through the source-leakage channel transfer of input/output transistors shown in Figure 1 speed to the input/output line.
Below, data of description is write operation.If data inputs is added on Sheffer stroke gate 37 and 38, and be changed to logic " height " with imitating signal Phi WI, then write driver A and B respectively with the data transmission of input on input/output line 35 and 36.In this case, input/output line sensor amplifier 45 is in illegal state.Subsequently, if it is effective to write column selection line signal WSCL, then data are transferred on bit line 23 and 24 through first and second input transistors 33 and 34, and are stored among memory cell 21 or 22.
In a word, because the stray capacitance of data input/output line is higher than about 10 times of the stray capacitance of bit line, then first and second input transistors 33 and source-leakages channel size of 34 are answered less shared to realize suitable charging.Subsequently, bit line 23 and 24 current potential do not change to required state rapidly, thereby the time period that a current potential remains on an intermediateness occurs.As a result, a direct current electric current flows with the direction of arrow shown in Figure 3, and current drain is increased.In addition, because the current potential of bit line has the time period of the state that mediates, when carrying out the read-modify-write operation, the write operation that makes after read operation effectively constantly will postpone to arrive.The read-modify-write operation is a kind of mode of operation of dynamic ram, and the data input that wherein is added to data input pin is changed and is the output of the data on data output end.
The object of the present invention is to provide a kind of data transmission circuit, be used for suppressing to produce DC current and improve the characteristic that read-modify-write is operated.
According to an aspect of the present invention, the data transmission circuit that is used for having the semiconductor memory device of first and second storaging array modules has a plurality of memory cells, each memory cell is used for storage input data, wherein each all jointly is linked on the pair of bit lines on first and second storaging array modules, be used for bit line is kept apart or bit line is linked to the first and second isolated transistor circuit on first or second storaging array module from first or second storaging array module, and the bit line sensor amplifier that is used to amplify the potential difference (PD) between bit line, it also comprises a pair of shared input/output line of the data that are used for jointly transmitting first and second storaging array modules; Be used between the sensing bit line potential difference (PD) be associated in sensing circuit between earth potential terminal and the public input/output line; Be connected in the input circuit between bit line and the public input/output line, according to first control signal, by public input/output line being linked on the bit line and will import data and be transferred on the bit line through public input/output line; And be associated in output circuit between sensing circuit and the public input/output line, be used for will being stored in data transmission in the memory cell to public input/output line according to second control signal.
Fig. 1 illustrates a circuit diagram of the example of a conventional data transmission circuit;
Fig. 2 A to 2D is the sequential chart during the read operation of Fig. 1;
Fig. 3 illustrates the circuit diagram of another example of conventional data transmission circuit;
Fig. 4 A to 4D is the sequential chart during the read operation of Fig. 3;
Fig. 5 is a circuit diagram of the data transmission circuit of one embodiment of the invention;
Fig. 6 A to 6I is sequential chart Fig. 5, read-modify-write operating period.
Referring to Fig. 5, the part of having improved is compared in square frame shown in broken lines 100 representatives with traditional circuit, and following description will be ignored the part except square frame 100.Square frame 100 comprise its grid be linked to respectively on pair of bit lines 53 and 54 first and second sensing transistors 59 and 60 and source-leakage passage on, a terminal of each source-leakage passage is linked on the ground voltage terminal Vss.Also comprise first and second output transistors 61 and 62, its grid is connected to jointly to be read on the column selection line signal RCSL, and source-leakage passage is associated in respectively between other terminals and a pair of data input/ output line 65 and 66 of source-leakage passage of first and second sensing transistors 59 and 60.Also comprise first and second input transistors 63 and 64 in addition, its grid are linked to mutually jointly to be write on the column selection line signal WCSL, and source-leakage passage be associated in respectively input/ output line 65 and 66 and bit line 53 and 54 between.Should be noted that memory cell 51 and 52 is present in (not shown) in the different storaging array modules in this embodiment according to the present invention, and a data transmission circuit is controlled storaging array module on two jointly.
To describe in detail Fig. 5 with reference to Fig. 6 A to 6I.
At first, data are therefrom read, and for example the read operation of reading from memory cell 51 will be given description.Before describing, suppose, when memory cell 51 or 52 is all not selected, that is to say, for a pre-charge state, the isolation signals ISOL that is added to isolated transistor 55 and 56 grids is maintained at power source voltage Vcc with the isolation signals ISOR that is added to isolated transistor 57 and 58 grids; If memory cell 51 is selected, the current potential of isolation signals ISOL becomes Vpp=Vcc+Vt, and the current potential of isolation signals ISOR becomes Vss=OV.Like this, if memory cell 51 is selected, because the current potential of isolation signals ISOL and ISOR is respectively Vpp and OV, word line WL(L) effectively, and the data that are stored in the memory cell 51 are shared with the current potential charging of bit line 53.Subsequently, bit line sensor amplifier 67 sensing bit lines 53 and 54 potential difference (PD) that increase, and respectively bit line 53 and 54 is become power source voltage Vcc level and ground voltage Vss level.Like this, first sensing transistor, 59 conductings.If it is very short effective time to read column selection line signal RCSL, then between input/ output line 65 and 66, produce a given potential difference (PD).At this moment, it is effective quickly to read comparable time shown in Figure 6 of effective time of column selection line signal RCSL.That is to say that if the data that are stored in the memory cell 51 are the logic " high " state, then first sensing transistor, 59 conductings are so the current potential step-down of input/output line 65 is a ground voltage level.In this case, at the waveform of the potential difference (PD) of input/output line 65 shown in Fig. 6 F and 66, and, further strengthens I/O sensor amplifier 69 owing to making the potential difference (PD) between input/output line 65 and 66.Like this, the data of reading from memory cell 51 are output to the periphery of circuit.
Below, the data of description write operation.If be added on the write circuit 68, be added to write circuit 68 by data input DIO and DIO mutually and be transferred to respectively on input/ output line 65 and 66 with imitating signal Phi WI.In addition, if it is selected to write column selection line signal WCSL, then input/ output line 65 and 66 data are transferred to respectively on bit line 53 and 54 through first and second input transistors 63 and 64.In this case, because the current potential of isolation signals ISOL is Vpp, then isolated transistor 55 and 56 conductings.Subsequently, the data of bit line 53 are stored in the memory cell 51 through isolated transistor 55.During write operation, because first and second output transistors 61 and 62 turn-off, then the generation of DC current is suppressed, and thus, the write operation after read operation is not delayed effective time, thereby has improved the characteristic of storing apparatus.
As mentioned above, when after read operation, carrying out write operation, for example in the read-modify-write pattern, shown in data transmission circuit suppress the generation of DC current, can realize the high-speed cruising of data I/O thus.In addition, can obtain the stable operation of integrated circuit and be easy to obtain highly integrated circuit.
Claims (9)
1, the data transmission circuit that is used for having the semiconductor memory device of first and second storaging array modules has a plurality of memory cells, each memory cell is used for storage input data, wherein each all jointly is linked to the pair of bit lines on first and second storaging array modules, be used for the pair of bit lines of described bit line from described first or second storaging array module, be used for described bit line is kept apart or described bit line is linked to the first and second isolated transistor circuit on described first or second storaging array module from described first or second storaging array module, and the bit line sensor amplifier that is used to amplify the potential difference (PD) between described bit line, it is characterized in that described circuit comprises:
Be used for transmitting jointly a pair of shared input/output line of the data of described first and second storaging array modules;
The sensing device between ground voltage terminal and the described public input/output line of being associated in that is used for potential difference (PD) between the described bit line of sensing;
Be connected in the input media between described bit line and the described public input/output line, according to first control signal, with the data transmission of described public input/output line to described bit line;
Be connected in the output unit between described sensing device and described public input/output line, be used for to be stored in data transmission among the memory cell to public input/output line according to second control signal.
2, data transmission circuit as claimed in claim 1 is characterized in that: described first and second control signals are respectively to be write column selection line signal and reads column selection line signal.
3, data transmission circuit as claimed in claim 1, it is characterized in that: described sensing device comprises first and second sensing transistors, its grid is linked to respectively on the described bit line, and has its source-leakage passage, the terminal of described source-leakage passage jointly is linked to described ground voltage terminal, and other terminal of described source-leakage passage is linked to respectively on the described public input/output line.
4, data transmission circuit as claimed in claim 3, it is characterized in that: described output unit comprises first and second output transistors, its grid is linked on described second control signal jointly, and its source-leakage passage is associated in respectively between the terminal and described public input/output line of described source-leakage passage of described first and second sensing transistors.
5, data transmission circuit as claimed in claim 1, it is characterized in that: described input media comprises first and second input transistors, its grid is linked on described first control signal jointly, and its source-leakage passage is associated in respectively between described bit line and the described public input/output line.
6, data transmission circuit as claimed in claim 1 is characterized in that: during write operation, the data of described public input/output line are electrically insulated from described sensing device and described output unit.
7, the data transmission circuit that is used for having the semiconductor memory device of first and second storaging array modules has a plurality of memory cells, each memory cell is used for storage input data, wherein each all jointly is linked to the pair of bit lines on described first and second storaging array modules, be used for described bit line is kept apart or described bit line is linked to the first and second isolated transistor circuit on described first or second storaging array module from described first or second storaging array module, and the bit line sensor amplifier that is used to amplify the potential difference (PD) between described bit line, it is characterized in that described circuit comprises:
Be used for transmitting jointly a pair of shared input/output line of the data of described first and second storaging array modules;
First and second sensing transistors, its grid is linked to respectively on the described bit line, and comprising its source-leakage passage, the terminal of described source-leakage passage is linked on the ground voltage terminal jointly, and other terminals of described source-leakage passage are linked to respectively on the described public input/output line;
First and second input transistors, its grid are linked on first control signal jointly, and its source-leakage passage is associated in respectively between described bit line and the described public input/output line;
First and second output transistors, its grid are linked on second control signal jointly, and its source-leakage passage is associated in respectively between the terminal and described public input/output line of described source-leakage passage of described first and second sensing transistors.
8, data transmission circuit as claimed in claim 7 is characterized in that described first and second control signals are respectively to write column selection line signal and read column selection line signal.
9, data transmission circuit as claimed in claim 7 is characterized in that: during write operation, the data of described public input/output line are electrically insulated from described first and second sensing transistors and described first and second output transistors.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR18833/91 | 1991-10-25 | ||
| KR1019910018833A KR930008857A (en) | 1991-10-25 | 1991-10-25 | Data transmission circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1072529A true CN1072529A (en) | 1993-05-26 |
Family
ID=19321776
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN92112356A Pending CN1072529A (en) | 1991-10-25 | 1992-10-24 | Data transmission circuit |
Country Status (7)
| Country | Link |
|---|---|
| JP (1) | JPH0713869B2 (en) |
| KR (1) | KR930008857A (en) |
| CN (1) | CN1072529A (en) |
| DE (1) | DE4235176A1 (en) |
| FR (1) | FR2683077A1 (en) |
| GB (1) | GB2260839A (en) |
| IT (1) | IT1255903B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE69322237T2 (en) * | 1992-11-12 | 1999-07-08 | United Memories Inc | Sense amplifier for an integrated memory |
| JP2004095017A (en) * | 2002-08-30 | 2004-03-25 | Fujitsu Ltd | Sense amplifier |
| US8796863B2 (en) * | 2010-02-09 | 2014-08-05 | Samsung Electronics Co., Ltd. | Semiconductor memory devices and semiconductor packages |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02246516A (en) * | 1989-03-20 | 1990-10-02 | Hitachi Ltd | Semiconductor device |
| JPH03283179A (en) * | 1990-03-30 | 1991-12-13 | Fujitsu Ltd | Semiconductor storage device |
-
1991
- 1991-10-25 KR KR1019910018833A patent/KR930008857A/en not_active IP Right Cessation
-
1992
- 1992-10-12 FR FR9212155A patent/FR2683077A1/en active Pending
- 1992-10-19 DE DE4235176A patent/DE4235176A1/en not_active Ceased
- 1992-10-22 IT ITMI922419A patent/IT1255903B/en active IP Right Grant
- 1992-10-23 JP JP4286224A patent/JPH0713869B2/en not_active Expired - Lifetime
- 1992-10-24 CN CN92112356A patent/CN1072529A/en active Pending
- 1992-10-26 GB GB9222496A patent/GB2260839A/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| ITMI922419A0 (en) | 1992-10-22 |
| GB9222496D0 (en) | 1992-12-09 |
| GB2260839A (en) | 1993-04-28 |
| JPH0713869B2 (en) | 1995-02-15 |
| JPH05210968A (en) | 1993-08-20 |
| FR2683077A1 (en) | 1993-04-30 |
| IT1255903B (en) | 1995-11-17 |
| DE4235176A1 (en) | 1993-04-29 |
| ITMI922419A1 (en) | 1994-04-22 |
| KR930008857A (en) | 1993-05-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5999439A (en) | Ferroelectric memory using ferroelectric reference cells | |
| JPH0527194B2 (en) | ||
| EP0185451B1 (en) | Semiconductor memory device with sense amplifiers | |
| KR950000958B1 (en) | Semiconductor memory circuit | |
| US4533843A (en) | High performance dynamic sense amplifier with voltage boost for row address lines | |
| US5299157A (en) | Semiconductor memories with serial sensing scheme | |
| EP0398245A3 (en) | Dynamic type random-access memory | |
| IE51239B1 (en) | A semiconductor memory device | |
| EP0499478A2 (en) | Semiconductor memory unit array | |
| KR940004515B1 (en) | Dynamic semiconductor memory device | |
| EP0388176B1 (en) | Semiconductor memory device | |
| JPH0836885A (en) | Dynamic random-access memory | |
| GB2264376A (en) | Bit line control in a semiconductor memory device | |
| US5361233A (en) | Semiconductor memory apparatus | |
| US6049493A (en) | Semiconductor memory device having a precharge device | |
| EP0048464B1 (en) | Semiconductor memory device | |
| JPS5894188A (en) | Amplifier | |
| US5406512A (en) | Semiconductor memory device using compensation capacitors | |
| EP0454061A2 (en) | Dynamic random access memory device with improved power supply system for speed-up of rewriting operation on data bits read-out from memory cells | |
| EP0398244A2 (en) | Dynamic type random-acces memory | |
| TW394954B (en) | Semiconductor memory device | |
| KR950014256B1 (en) | Semiconductor memory device using low source voltage | |
| US5835403A (en) | Multiplication of storage capacitance in memory cells by using the Miller effect | |
| KR20010014011A (en) | Variable voltage isolation gate | |
| US5563831A (en) | Timing reference circuit for bitline precharge in memory arrays |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C01 | Deemed withdrawal of patent application (patent law 1993) | ||
| WD01 | Invention patent application deemed withdrawn after publication |