KR930008857A - Data transmission circuit - Google Patents

Data transmission circuit Download PDF

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Publication number
KR930008857A
KR930008857A KR1019910018833A KR910018833A KR930008857A KR 930008857 A KR930008857 A KR 930008857A KR 1019910018833 A KR1019910018833 A KR 1019910018833A KR 910018833 A KR910018833 A KR 910018833A KR 930008857 A KR930008857 A KR 930008857A
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KR
South Korea
Prior art keywords
channel
output
circuit
bit line
signal
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Application number
KR1019910018833A
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Korean (ko)
Inventor
유승문
Original Assignee
김광호
삼성전자 주식회사
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Priority to KR1019910018833A priority Critical patent/KR930008857A/en
Priority to FR9212155A priority patent/FR2683077A1/en
Priority to DE4235176A priority patent/DE4235176A1/en
Priority to ITMI922419A priority patent/IT1255903B/en
Priority to JP4286224A priority patent/JPH0713869B2/en
Priority to CN92112356A priority patent/CN1072529A/en
Priority to GB9222496A priority patent/GB2260839A/en
Publication of KR930008857A publication Critical patent/KR930008857A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

본 발명은 반도체 집적회로의 데이터 전송 회로에 관한 것으로, 칩의 고집적화 할수 있으면서도 고속동작을 실현할 수 있는 데이터 전송회로를 위하여, 데이터의 입출력선을 한쌍의 공통 입출력선으로 하고 비트라인의 전위차를 감지하기 위한 감지용 트랜지스터, 데이터의 입력용 트랜지스터, 쎌 데이터의 출력용 트랜지스터를 각각 한쌍으로 하되 소정의 라이트 동작시에 상기 공통 입출력선에 실리는 데이터가 상기 입력용 트랜지스터 및 상기 감지용 트랜지스터와 절연관계에 놓이도록 설계하므로서, 예를 들어 리드-모디파이-라이트 동작시에 그 동작 완료 시간이 고속화되고 또한 그 동작특성이 안정화되어 메모리 소자로서의 성능을 향상시킬 뿐만 아니라 구성방식도 콤팩트하여 고집적화 할 수 있는 잇점이 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer circuit of a semiconductor integrated circuit, and has a pair of common input / output lines of data and detects a potential difference between bit lines for a data transfer circuit capable of high integration and high-speed operation of a chip. And a pair of sensing transistors, a data input transistor, and a data output transistor, each of which is in an insulated relationship with the input transistor and the sensing transistor in a predetermined write operation. By designing this, for example, in the read-modify-write operation, the operation completion time is increased and the operation characteristics are stabilized, thereby improving the performance as a memory device, and the configuration method is compact and highly integrated. have.

Description

데이터 전송 회로Data transmission circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제5도는 본 발명에 따른 데이터 전송 회로.5 is a data transmission circuit according to the present invention.

제6도는 제5도의 리드-모디파이-라이트시의 동작 타이밍도.6 is an operation timing diagram at the time of read-modify-write in FIG.

Claims (9)

소정의 데이타를 저장하는 다수개의 메모리 셀이 각각 존재하는 제1 및 제2메모리 어레이블록과 상기 제1 및 제2메모리 어레이블록에 공통으로 연결되는 비트라인 BL,와 상기 비트라인 BL,상에 설치되어 상기 제1 또는 상기 제2 메모리 어레이블록을 선택하기 위한 분리트랜지스터와 상기 비트라인 BL,의 전위차를 증폭하기 위한 비트라인센스엠프를 가지는 반도체 메모리 장치에 있어서, 상기 제1 및 제2메모리 어레이 블록의 게이타를 전송하기 위한 한쌍의 공통입출력선과?? 소정의 접지전압단 및 상기 공통 입출력선사이에 채널이 형성되고 상기 비트라인 BL,에 제어단자가 연결되어 상기 비트라인 BL,의 전위차를 감지하기 위한 감지회로와, 상기 비트라인 BL,및 상기 공통입출력선 사이에 체널이 형성되고 소정의 제1신호에 제어단자가 접속된 입력회로와, 상기 감지회로의 채널 및 상기 공통 입출력선 사이에 채널이 형성되고 소정의 제2신호에 제어단자가 접속된 출력회로로 이루어짐을 특징으로 하는 데이타 전송회로.First and second memory array blocks each having a plurality of memory cells storing predetermined data and bit lines BL commonly connected to the first and second memory array blocks; And the bit line BL, A isolation transistor and the bit line BL, each of which is installed on the first transistor to select the first or second memory array block; 12. A semiconductor memory device having a bit line sense amplifier for amplifying a potential difference of a semiconductor memory device, comprising: a pair of common input / output lines for transferring the gait of the first and second memory array blocks; A channel is formed between a predetermined ground voltage terminal and the common input / output line, and the bit line BL, A control terminal is connected to the bit line BL, A sensing circuit for sensing a potential difference between the bit line BL, And an input circuit having a channel formed between the common input / output lines and a control terminal connected to a predetermined first signal, and a channel formed between the channel of the sensing circuit and the common input / output line and a control terminal connected to the predetermined second signal. Data transmission circuit, characterized in that consisting of the output circuit connected. 제1항에 있어서, 상기 제1 및 제2신호는 각각 라이트용 컬럼선택신호 및 리드용 컬럼선택선신호임을 특징으로 하는 데이타 전송 회로.The data transfer circuit according to claim 1, wherein the first and second signals are respectively a column select signal for writing and a column select line signal for read. 제1항에 있어서, 상기 감지회로사 상기 비트라인 BL 및 BL에 각각 제어단자가 접속되고 소정의 접지전압단에 채널의 일단이 공통으로 접속되고 상기 한쌍의 공통 입출력선에 채널의 타단이 각각 연결되는 제1 및 제2감지용 트랜지스터(59)(60)로 이루어짐을 특징으로 하는 데이터 전송회로.The control circuit of claim 1, wherein a control terminal is connected to the bit lines BL and BL, respectively, and one end of a channel is commonly connected to a predetermined ground voltage terminal, and the other end of the channel is connected to the pair of common input / output lines, respectively. And a first and second sensing transistor (59) (60). 제3항에 있어서, 상기 출력회로가 상기 제2신호에 공통으로 제어단자가 접속되고 상기 제1 및 제2감지용 트랜지스터(59)(60)의 체널의 각 양단과 상기 공통 입출력사이에 체널의 양단이 각각 접속되는 제1 및 제출력용 츠랜지스터(61)(62)로 이루어짐을 특징으로 하는 데이타 전송 회로.4. A channel according to claim 3, wherein said output circuit is connected to a control terminal in common with said second signal, and between said both ends of a channel of said first and second sensing transistors (59, 60) and said common input / output. A data transfer circuit comprising first and second output transistors (61, 62) connected at both ends thereof. 제1항에 있어서, 상기 입력회로가 상기 제1신호에 공통으로 제어잔자가 접속되고 상기 비트라인 BL,과 상기 한쌍의 공통 입출력선에 채널의 양단이 각각 접속되는 제1 및 제2입력용 트랜지스터(63)(64)로 이루어짐을 특징으로 하는 데이타 전송 회로.The method of claim 1, wherein the input circuit is connected to the control signal in common to the first signal and the bit line BL, And first and second input transistors (63, 64) connected at both ends of the channel to the pair of common input / output lines, respectively. 제1항에 있어서, 상기 데이터 전송 회로가 소정의 라이트 동작시에 상기 한쌍의 공통 입출력선에 실리는 데이터가 상기 감지회로 및 상기 출력회로와 서로 절연관계에 놓이게 됨을 특징으로 하는 데이타 전송 회로.The data transfer circuit according to claim 1, wherein the data carried on the pair of common input / output lines is insulated from the sensing circuit and the output circuit during a predetermined write operation. 소정의 데이타를 저장하는 다수개의 메모리 쎌이 각각 존재하는 제1 및 제2메모리 어레이블록과 상기 제1 및 제2메모리 어레이블록에 공통으로 연결되는 비트라인 BL,와 상기 비트라인 BL,상에 설치되어 상기 제1 또는 상기 제2메모리 어레이블록을 선택하기 위한 분리트랜지스터와 상기 비트라인 BL,의 전위차를 증폭하시 위한 비트라인센스엠프를 가지는 반도체 메모리 장치에 있어서, 상기 제1 및 제2메모리 어레이 블록의 데이타를 전송하기 위한 한쌍의 공통입출력선과, 상기 비트라인 BL 및에 각각 제어단자가 접속되고 소정의 접지전압단에 채널의 일단이 공통으로 접속되고 상기 한쌍의 공통 입출력선에 채널의 타단이 각각 연결되는 제1 및 제2감지용 트랜지??터(59)(60)와, 상기 제1신호에 공통으로 제어단자가 접속되고 상기 비트라인 BL,과 상기 한쌍의 공통 입출력선에 채널의 양단이 각각 접속되는 제1 및 제2입력용 트랜지스터(63)(64)와, 상기 제2신호에 공통으로 제어단자가 접속되고 상??L 제1 및 제2감지용 트랜지스터(59)(60)의 채널의 각 양단과 상기 공통 입출력선사이에 채널의 양단이 각각 접속되는 제1 및 제2출력용 트랜지스터(61)(62)로 이루어짐을 특징으로 하는 데이타 전송 회로.A first and second memory array blocks each having a plurality of memory chips for storing predetermined data and a bit line BL commonly connected to the first and second memory array blocks; And the bit line BL, A isolation transistor and the bit line BL, each of which is installed on the first transistor to select the first or second memory array block; 11. A semiconductor memory device having a bit line sense amplifier for amplifying a potential difference of a semiconductor memory device, comprising: a pair of common I / O lines for transferring data of the first and second memory array blocks, the bit lines BL and First and second sensing transistors 59 each of which has a control terminal connected thereto, one end of a channel commonly connected to a predetermined ground voltage terminal, and the other end of the channel connected to the pair of common input / output lines, respectively. 60 and a control terminal connected in common to the first signal, the bit line BL, And first and second input transistors 63 and 64 connected at both ends of the channel to the pair of common input / output lines, respectively, and a control terminal connected to the second signal in common. Data transfer characterized in that the first and second output transistors 61 and 62 are connected between both ends of the channels of the second sensing transistors 59 and 60 and the both ends of the channel between the common input and output lines, respectively. Circuit. 제7항에 있어서, 상기 제1 및 제2신호는 각각 라이트용 컬럼선택선신호 및 리드용 컬럼선택신호임을 특징으로 하는 데이타 전송 회로.8. The data transfer circuit according to claim 7, wherein the first and second signals are respectively a column select line signal for writing and a column select signal for read. 제7항에 있어서, 상기 데이터 전송 회로가 소정의 라이트 동작시에 상기 한쌍의 공통 입출력선에 실리는 데이타가 상기 감지회로 및 상기 출력회로와 서로 절연관계에 놓이게 됨을 특징으로 하는 데이타 전송 회로.8. The data transfer circuit according to claim 7, wherein the data carried on the pair of common input / output lines is insulated from each other in the sensing circuit and the output circuit during a predetermined write operation. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910018833A 1991-10-25 1991-10-25 Data transmission circuit KR930008857A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
KR1019910018833A KR930008857A (en) 1991-10-25 1991-10-25 Data transmission circuit
FR9212155A FR2683077A1 (en) 1991-10-25 1992-10-12 DATA TRANSMISSION CIRCUIT, AND ESPECIALLY FOR HIGHLY INTEGRATED DATA TRANSMISSION CIRCUIT FOR PROCESSING HIGH SPEED DATA.
DE4235176A DE4235176A1 (en) 1991-10-25 1992-10-19 DATA TRANSFER CIRCUIT
ITMI922419A IT1255903B (en) 1991-10-25 1992-10-22 DATA TRANSMISSION CIRCUIT IN PARTICULAR FOR SEMICONDUCTOR MEMORY DEVICES.
JP4286224A JPH0713869B2 (en) 1991-10-25 1992-10-23 Data transmission circuit
CN92112356A CN1072529A (en) 1991-10-25 1992-10-24 Data transmission circuit
GB9222496A GB2260839A (en) 1991-10-25 1992-10-26 Data transmission circuit for a semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910018833A KR930008857A (en) 1991-10-25 1991-10-25 Data transmission circuit

Publications (1)

Publication Number Publication Date
KR930008857A true KR930008857A (en) 1993-05-22

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Application Number Title Priority Date Filing Date
KR1019910018833A KR930008857A (en) 1991-10-25 1991-10-25 Data transmission circuit

Country Status (7)

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JP (1) JPH0713869B2 (en)
KR (1) KR930008857A (en)
CN (1) CN1072529A (en)
DE (1) DE4235176A1 (en)
FR (1) FR2683077A1 (en)
GB (1) GB2260839A (en)
IT (1) IT1255903B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69333909T2 (en) 1992-11-12 2006-07-20 Promos Technologies, Inc. Sense amplifier with local write drivers
JP2004095017A (en) * 2002-08-30 2004-03-25 Fujitsu Ltd Sense amplifier
US8796863B2 (en) * 2010-02-09 2014-08-05 Samsung Electronics Co., Ltd. Semiconductor memory devices and semiconductor packages

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02246516A (en) * 1989-03-20 1990-10-02 Hitachi Ltd Semiconductor device
JPH03283179A (en) * 1990-03-30 1991-12-13 Fujitsu Ltd Semiconductor storage device

Also Published As

Publication number Publication date
ITMI922419A1 (en) 1994-04-22
ITMI922419A0 (en) 1992-10-22
JPH0713869B2 (en) 1995-02-15
GB9222496D0 (en) 1992-12-09
GB2260839A (en) 1993-04-28
CN1072529A (en) 1993-05-26
FR2683077A1 (en) 1993-04-30
IT1255903B (en) 1995-11-17
DE4235176A1 (en) 1993-04-29
JPH05210968A (en) 1993-08-20

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