CN107239594B - Analog circuit dispersibility optimization method based on PSPICE - Google Patents
Analog circuit dispersibility optimization method based on PSPICE Download PDFInfo
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Abstract
The invention discloses a PSPICE-based analog circuit dispersibility optimization method, which comprises the following steps: s1, constructing a simulation circuit and constructing a transfer function of a key characteristic index; s2, carrying out sensitivity analysis and determining key devices; s3, performing first-round simulation; s4, determining a function between the key characteristic index and the key device; s5, performing robustness optimization design on the function, and determining a mean value, a standard upper limit value and a standard lower limit value; s6, optimizing parameters of key devices, performing a second round of simulation, and determining the yield; s7, when the yield meets the preset judgment index, skipping to the step S8; otherwise, jumping to step S2; and S8, analyzing the simulation circuit, judging whether a device under the action of overstress exists, modifying a derating factor of the device if the device under the action of overstress exists, repeating the step S8, and otherwise, obtaining design parameters to finish the design of the simulation circuit. The invention has the advantage of improving the stability and reliability of the optimized design circuit.
Description
Technical Field
The invention relates to the field of analog circuit optimization design, in particular to a PSPICE-based analog circuit dispersity optimization method.
Background
The traditional circuit optimization design and analysis method comprises a tolerance design method, a Monte Carlo simulation method and the like, but the traditional method focuses on local problems of circuit device tolerance, circuit manufacturing qualification rate and the like, and global and systematic solutions are lacked for the dispersion problems of circuit key characteristics (such as performance indexes are out of tolerance, drift, instability and the like). Therefore, it is of practical significance to study the dispersion problem of the key characteristics of the circuit.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the technical problems in the prior art, the invention provides the PSPICE-based analog circuit dispersity optimization method which can analyze the dispersity problem of the key characteristics of the circuit from the perspective of the whole situation and the system and optimize and design the circuit, thereby improving the dispersity capability of the circuit for resisting elements and improving the stability and the reliability of the circuit.
In order to solve the technical problems, the technical scheme provided by the invention is as follows: a PSPICE-based analog circuit dispersibility optimization method comprises the following steps:
s1, constructing a simulation circuit and constructing a transfer function of a key characteristic index of the simulation circuit;
s2, carrying out sensitivity analysis on the simulation circuit, and determining key devices influencing the key characteristic indexes;
s3, performing a first round of simulation to obtain a first round of simulation value of the key characteristic index of the simulation circuit, wherein the first round of simulation value comprises an input value and an output value of the key characteristic index;
s4, determining a function between the key characteristic index and the key device;
s5, performing robustness optimization design on the function, and determining the mean value, the standard upper limit value and the standard lower limit value of the key characteristic index;
s6, optimizing parameters of the key device according to the mean value, performing a second round of simulation to obtain a second round of simulation value of key characteristic indexes of the simulation circuit, and determining the yield of the simulation circuit according to the second round of simulation value;
s7, when the yield meets a preset judgment index, skipping to the step S8; otherwise, jumping to step S2;
s8, Smok analysis is carried out on the simulation circuit, whether a device under the action of overstress exists in the simulation circuit is judged according to the Smok analysis result, if yes, a derating factor of the device is modified, the step S8 is repeated, and if not, design parameters of the simulation circuit are obtained, and simulation circuit design is completed.
As a further improvement of the present invention, the step of constructing the simulation circuit in step S1 includes: and selecting a device from the reference model library to construct a simulation circuit by taking the PSPICE AA model library as the reference model library, and supplementing tolerance information of the device.
As a further improvement of the present invention, the specific steps of determining the key device affecting the key characteristic index in step S2 are as follows: and sequencing the devices according to the sensitivity analysis result by using the influence degree of the key index, and taking the device with the influence degree in a preset sequencing range as a key device.
As a further improvement of the present invention, the preset ordering range is a range with influence degree of the first 5 to 10 bits.
As a further improvement of the invention, the number of times of the first round simulation is not less than 100.
As a further improvement of the present invention, the specific steps of step S4 include: selecting N groups of samples from the first round of simulation values, and determining a function between the key characteristic index and the key device by a response surface method, a random response method or a chaotic polynomial method, as shown in formula (1):
Y＝F(X) (1)
in the formula (1), Y is an output value of a key characteristic index of the simulation circuit, f (X) is the function, and X ═ X1,X2…Xk]，XiAnd i is 1,2, …, and k is the ith key device.
As a further improvement of the invention, the value of N is greater than or equal to 20.
As a further improvement of the present invention, the specific steps of step S5 include: constructing a robustness optimization model as shown in formula (2):
in the formula (2), σYIs the standard deviation, mu, of the key property index YYIs the mean value of the key characteristic index Y, YLIs the lower limit of the specification for Y, YUIs the upper limit of the specification for Y,
mean of the ith critical device, D.V is the design variable;
determining a mean μ of the key characteristic indicators according to the robustness optimization modelYUpper limit of specification YULower limit of specification YL。
As a further improvement of the present invention, when the step S6 optimizes the parameters of the critical device according to the mean value, the variance of the critical device is guaranteed to be unchanged.
As a further improvement of the invention, the number of times of the second round simulation is not less than 1000, and the yield of the simulation circuit is the probability that the average value of the simulation values of the second round falls into the range of [ lower limit value of specification, upper limit value of specification ].
Compared with the prior art, the invention has the advantages that:
1. the invention provides a solution for the dispersibility of key characteristic indexes of a circuit, which aims at the problems of overlarge dispersibility of key characteristic indexes of the circuit, parameter drift and the like, carries out sensitivity analysis and identifies which components have the greatest contribution to the dispersibility of the circuit; then, carrying out robustness optimization design, and on the premise that the circuit key characteristic index value meets the established technical specification, the dispersity is minimum and the performance is optimal; carrying out yield analysis, and calculating the yield of the manufactured circuit on the premise of the tolerance of the existing device, so that the dispersion level of the product can be mastered in the research and development stage; and finally, Smoke analysis is carried out, derating design is carried out on devices with overstress, the capability of the circuit for resisting the dispersity of the devices is improved, and the stability and the reliability of the circuit are improved.
Drawings
FIG. 1 is a schematic flow chart of an embodiment of the present invention.
Detailed Description
The invention is further described below with reference to the drawings and specific preferred embodiments of the description, without thereby limiting the scope of protection of the invention.
As shown in fig. 1, the PSPICE-based analog circuit dispersibility optimization method of this embodiment includes the steps of: s1, constructing a simulation circuit and constructing a transfer function of a key characteristic index of the simulation circuit; s2, carrying out sensitivity analysis on the simulation circuit, and determining key devices influencing the key characteristic indexes; s3, performing a first round of simulation to obtain a first round of simulation value of the key characteristic index of the simulation circuit, wherein the first round of simulation value comprises an input value and an output value of the key characteristic index; s4, determining a function between the key characteristic index and the key device; s5, performing robustness optimization design on the function, and determining the mean value, the standard upper limit value and the standard lower limit value of the key characteristic index; s6, optimizing parameters of the key device according to the mean value, performing a second round of simulation to obtain a second round of simulation value of key characteristic indexes of the simulation circuit, and determining the yield of the simulation circuit according to the second round of simulation value; s7, when the yield meets a preset judgment index, skipping to the step S8; otherwise, jumping to step S2; s8, Smok analysis is carried out on the simulation circuit, whether a device under the action of overstress exists in the simulation circuit is judged according to the Smok analysis result, if yes, a derating factor of the device is modified, the step S8 is repeated, and if not, design parameters of the simulation circuit are obtained, and simulation circuit design is completed.
In this embodiment, the step of building the simulation circuit in step S1 includes: and selecting a device from the reference model library to construct a simulation circuit by taking the PSPICE AA model library as the reference model library, and supplementing tolerance information of the device according to a device manual. After the simulation circuit is constructed, a transfer function of key characteristic indexes including but not limited to indexes such as gain, bandwidth and delay time is created in a probe window. By constructing a transfer function of the key characteristic index, the value of the key characteristic index can be obtained during each simulation.
In step S2 in this embodiment, sensitivity analysis is performed on the constructed simulation circuit, and according to the sensitivity analysis result, the devices are sorted from high to low according to the influence of the critical index, and the device with the influence in a preset sorting range is used as a critical device. The predetermined ordering range is a range of the influence degree of the first 5 to 10 bits.
In this embodiment, a first round of simulation is performed on the simulation circuit by a monte carlo simulation method, and the number of times of the first round of simulation is not less than 100. Each time Monte Carlo simulation is carried out, input values and output values of a group of key characteristic indexes can be obtained, a group of samples are obtained, and 100 groups of samples can be obtained after 100 Monte Carlo simulations are carried out.
In this embodiment, N sets of samples are selected from 100 sets of samples of the first round of simulated values, where the value of N is greater than or equal to 20, and a function between the key characteristic indicator and the key device is determined by a response surface method, a random response method, or a chaotic polynomial method, as shown in equation (1):
Y＝F(X) (1)
in the formula (1), Y is an output value of a key characteristic index of the simulation circuit, f (X) is the function, and X ═ X1,X2…Xk]，XiAnd i is 1,2, …, and k is the ith key device.
In this embodiment, the specific step of step S5 includes: constructing a robustness optimization model as shown in formula (2):
in the formula (2), σYIs the standard deviation, mu, of the key property index YYIs the mean value of the key characteristic index Y, YLIs the lower limit of the specification for Y, YUIs the upper limit of the specification for Y,
D.V design variables (design variables) for the mean of the ith critical device; determining a mean μ of the key characteristic indicators according to the robustness optimization modelYUpper limit of specification YULower limit of specification YL. Through the constraint condition of the robustness optimization model, the lower limit value Y of the specification can be determinedLAnd a specification upper limit value YURange of composition [ YL,YU]And determining the mean of the critical devices. And optimizing parameters of the key devices in the simulation circuit by using the mean value of the key devices, keeping the variance of the key devices unchanged, and updating the simulation circuit. And performing Monte Carlo simulation again, namely performing simulation of the second round, wherein the number of times of the simulation of the second round is not less than 1000. And acquiring a second round simulation value of the key characteristic indexes of the simulation circuit, wherein the second round simulation value comprises the input value and the output value of the key characteristic indexes, and calculating the mean value of the second round simulation value. The mean value of 1000 second round simulation values is calculated to fall into the lower limit value and the upper limit value of the specification]And obtaining the yield of the simulation circuit according to the probability of the range. And when the genuine product rate of the simulation circuit meets the preset qualification judgment standard, performing the next processing on the simulation circuit, otherwise, skipping to the step S2 to perform sensitivity analysis on the simulation circuit again, and entering a new round of optimization design process.
In this embodiment, when the yield of the simulation circuit meets a preset qualification criterion, a cookie (cookie analysis is a proprietary analysis tool in software, and is "smoking" analysis as the name implies, and is used for researching whether a circuit device can bear excessive heat and electric stress, and if the answer is exceeded, a derating design of response is carried out) analysis is carried out on the simulation circuit, whether a device subjected to an over-stress effect exists in the simulation circuit is judged according to a cookie analysis result, if so, a derating factor of the device is modified, and a targeted derating process is carried out to improve the capability of the circuit for resisting the dispersion of components, and step S8 is repeated, otherwise, design parameters of the simulation circuit are obtained, the design parameters are output, and the simulation circuit design is completed.
The embodiment provides a solution for the dispersibility of the key characteristic indexes of the circuit, and aims at the problems of overlarge dispersibility of the key characteristic indexes of the circuit, parameter drift and the like, sensitivity analysis is carried out to identify which components have the greatest contribution to the dispersibility of the circuit; then, carrying out robustness optimization design, and on the premise that the circuit key characteristic index value meets the established technical specification, the dispersity is minimum and the performance is optimal; by carrying out yield analysis and calculating the yield of the circuit after manufacturing on the premise of the tolerance of the existing device, the dispersion level of the product can be mastered in the research and development stage; and finally, Smoke analysis is carried out, derating design is carried out on devices with overstress, the capability of the circuit for resisting the dispersity of the devices is improved, and the stability and the reliability of the circuit are improved.
The foregoing is considered as illustrative of the preferred embodiments of the invention and is not to be construed as limiting the invention in any way. Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical spirit of the present invention should fall within the protection scope of the technical scheme of the present invention, unless the technical spirit of the present invention departs from the content of the technical scheme of the present invention.
Claims (10)
1. A PSPICE-based analog circuit dispersibility optimization method is characterized by comprising the following steps:
s1, constructing a simulation circuit and constructing a transfer function of a key characteristic index of the simulation circuit;
s2, carrying out sensitivity analysis on the simulation circuit, and determining key devices influencing the key characteristic indexes;
s3, performing a first round of simulation to obtain a first round of simulation value of the key characteristic index of the simulation circuit, wherein the first round of simulation value comprises an input value and an output value of the key characteristic index;
s4, determining a function between the key characteristic index and the key device;
s5, performing robustness optimization design on the function, and determining the mean value, the standard upper limit value and the standard lower limit value of the key characteristic index;
s6, optimizing parameters of the key device according to the mean value, performing a second round of simulation to obtain a second round of simulation value of key characteristic indexes of the simulation circuit, and determining the yield of the simulation circuit according to the second round of simulation value;
s7, when the yield meets a preset judgment index, skipping to the step S8; otherwise, jumping to step S2;
s8, Smok analysis is carried out on the simulation circuit, whether a device under the over-stress action exists in the simulation circuit is judged according to the Smok analysis result, if yes, a derating factor of the device is modified, the step S8 is repeated, and if not, design parameters of the simulation circuit are obtained, and simulation circuit design is completed;
the key characteristic indexes include gain, bandwidth and delay time.
2. The PSPICE-based analog circuit dispersibility optimization method according to claim 1, wherein the step of constructing the simulation circuit in step S1 includes: and selecting a device from the reference model library to construct a simulation circuit by taking the PSPICE AA model library as the reference model library, and supplementing tolerance information of the device.
3. The PSPICE-based analog circuit dispersibility optimization method according to claim 2, wherein the specific steps of determining the key devices affecting the key characteristic index in the step S2 are as follows: and sequencing the devices according to the sensitivity analysis result by using the influence degree of the key index, and taking the device with the influence degree in a preset sequencing range as a key device.
4. The PSPICE-based analog circuit dispersibility optimization method of claim 3, wherein: the preset sequencing range is a range with influence degree of the first 5-10 bits.
5. The PSPICE-based analog circuit dispersibility optimization method of claim 4, wherein: the number of times of the first round of simulation is not less than 100.
6. The PSPICE-based analog circuit dispersibility optimization method according to claim 3, 4 or 5, wherein the specific steps of the step S4 include: selecting N groups of samples from the first round of simulation values, and determining a function between the key characteristic index and the key device by a response surface method, a random response method or a chaotic polynomial method, as shown in formula (1):
Y＝F(X) (1)
in the formula (1), Y is an output value of a key characteristic index of the simulation circuit, f (X) is the function, and X ═ X1,X2…Xk]，XiAnd i is 1,2, …, and k is the ith key device.
7. The PSPICE-based analog circuit dispersibility optimization method of claim 6, wherein the value of N is greater than or equal to 20.
8. The PSPICE-based analog circuit dispersibility optimization method according to claim 7, wherein the specific steps of the step S5 include: constructing a robustness optimization model as shown in formula (2):
in the formula (2), σYIs the standard deviation, mu, of the key property index YYIs the mean value of the key characteristic index Y, YLIs the lower limit of the specification for Y, YUIs the upper limit of the specification for Y,
mean of the ith critical device, D.V is the design variable;
determining a mean μ of the key characteristic indicators according to the robustness optimization modelYUpper limit of specification YULower limit of specification YL。
9. The PSPICE-based analog circuit dispersibility optimization method of claim 8, wherein: and step S6, when the parameters of the key device are optimized according to the mean value, the variance of the key device is ensured to be unchanged.
10. The PSPICE-based analog circuit dispersibility optimization method of claim 9, wherein: the number of times of the second round of simulation is not less than 1000, and the yield of the simulation circuit is the probability that the mean value of the simulation values of the second round falls into the range of the lower limit value and the upper limit value of the specification.
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| CN102314522B (en) * | 2010-06-30 | 2013-03-06 | 中国科学院微电子研究所 | Design optimization method for analog integrated circuit |
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| "基于关键元器件退化的模拟电路行为分析及模型建立";陈诚;《中国优秀硕士学位论文全文数据库 信息科技辑》;20150215(第02期);I135-244 * |
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