CN107239432A - A kind of server with novel topological structure - Google Patents
A kind of server with novel topological structure Download PDFInfo
- Publication number
- CN107239432A CN107239432A CN201710670978.2A CN201710670978A CN107239432A CN 107239432 A CN107239432 A CN 107239432A CN 201710670978 A CN201710670978 A CN 201710670978A CN 107239432 A CN107239432 A CN 107239432A
- Authority
- CN
- China
- Prior art keywords
- cpu
- node
- server
- qpi
- node controller
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/161—Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
Abstract
The invention discloses a kind of server with novel topological structure, including at least one node, node includes Node Controller and at least N number of CPU, CPU and Node Controller are respectively provided with N number of QPI ports, any two CPU is connected by respective QPI ports, and any one CPU is connected by respective QPI ports with Node Controller；Wherein, N is the positive integer more than or equal to 2.As can be seen here, a node includes at least N number of CPU in server, CPU and Node Controller are respectively provided with N number of QPI ports, that is CPU is equal with the QPI ports on Node Controller and CPU number, and each CPU is connected with Node Controller, and connected between any two CPU also by QPI ports, and then improve QPI port resources utilization rate and data transmission efficiency.
Description
Technical field
The present invention relates to computer application field, more particularly to a kind of server with novel topological structure.
Background technology
At present, divide by CPU interconnection architectures, server can be divided into 2 classes, a class is symmetric multiprocessor structure SMP, separately
One class is nonuniformity storage access structure NUMA.
SMP structure service devices refer to that multiple CPU symmetrically work in server, no primary and secondary and subordinate relation, in server
Memory, which is concentrated, to be placed, and each CPU shares identical physical memory, and the delay that each CPU accesses memory is equal, but such as
Fruit can not just carry out the interconnection of more multi -CPU not against Node Controller, i.e. SMP structure services device scalability is limited.
Fig. 1 is server internal structural representation in the prior art, as shown in figure 1, NUMA structure services device 10 is with more
Kind of implementation, is generally divided into multiple nodes 11, each node is made up of multiple CPU 102, and with it is independent it is local in
Deposit, the interconnection architectures of CPU 102 are that 2 CPU102 or 4 CPU 102 and a Node Controller 101 are mutual in a node 11
Interconnection forms more massive system between connection, Node Controller 101.It can pass through Node Controller between each node 11
101 are attached, and its major function is to interconnect at a high speed between the node for realizing multi-CPU system.The characteristics of framework, visits for local cpu
Ask that the speed of other CPU in node is significantly larger than the speed that local cpu accesses CPU in the other nodes in distal end.
Either limited bandwidth problem, can all occur in SMP structure services device or NUMA architecture server, and bandwidth refers to
The data quantity that regular time can transmit, i.e., can transmit the ability of data in transmission pipeline.Fig. 2 is a section in Fig. 1
Point internal structure schematic diagram, is all that 2 CPU 102 share a Node Controller 101,1 node control as depicted in figs. 1 and 2
Under 2 CPU102 of the correspondence of device 101 processed, the identical quantity sizes of CPU 102 of same system, the required quantity of Node Controller 101
It is more, and QPI port resources can not be made full use of.And under Fig. 2 frameworks, on the inner opposite angle line of node 11 between CPU 102
, it is necessary to be forwarded by CPU forwardings or Node Controller during exchanging visit, cause delay, limit fractional bandwidth.
As can be seen here, how to overcome in server node caused by CPU exchanges visits that QPI port resource utilization rates are low and data
The problem of efficiency of transmission is low is those skilled in the art's urgent problem to be solved.
The content of the invention
The embodiment of the present application provides a kind of server with novel topological structure, to solve QPI ends in the prior art
Mouthful resource utilization is low and the problem of low data transmission efficiency.
In order to solve the above technical problems, the invention provides a kind of server with novel topological structure, including at least
One node, the node is respectively provided with N number of including Node Controller and at least N number of CPU, the CPU and the Node Controller
QPI ports, CPU described in any two is connected by the respective QPI ports, and any one of CPU is by respective
The QPI ports be connected with the Node Controller；Wherein, N is the positive integer more than or equal to 2.
Preferably, the N is equal to 3.
Preferably, the server is that nonuniformity stores access structure NUMA servers.
Preferably, when the number of nodes is more than 1, connected between the Node Controller by network interface, so as to
CPU between multiple nodes carries out data transmission.
Preferably, the network interface is NI EBIs.
Preferably, the Node Controller is standard controller NC.
Preferably, the CPU is Intel X86CPU.
Compared to prior art, the server provided by the present invention with novel topological structure, including at least one section
Point, node includes Node Controller and at least N number of CPU, CPU and Node Controller is respectively provided with N number of QPI ports, any two CPU
Connected by respective QPI ports, and any one CPU is connected by respective QPI ports with Node Controller；Wherein, N
For the positive integer more than or equal to 2.As can be seen here, on the one hand, a node includes at least N number of CPU, CPU and section in server
Base site controller is respectively provided with N number of QPI ports, i.e. CPU is equal with the QPI ports on Node Controller and CPU number, and each
CPU is connected with Node Controller, caused service when overcoming QPI port resources waste in the prior art and data transfer
Device delay issue, and then improve QPI port resources utilization rate and data transmission efficiency.On the other hand, any two CPU it
Between also by QPI ports connect, further increase QPI port resources utilization rate and data transmission efficiency.
Brief description of the drawings
Fig. 1 is server internal structural representation in the prior art；
Fig. 2 is an intra-node structural representation in Fig. 1；
An intra-node structural representation in the server that Fig. 3 is provided by the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present application, the technical scheme in the embodiment of the present application is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
The core of the present invention is to provide a kind of server with novel topological structure, can improve QPI port resources profit
With rate and data transmission efficiency.
In order that those skilled in the art more fully understand the present invention program, with reference to the accompanying drawings and detailed description
The present invention is described in further detail.
An intra-node structural representation in the server that Fig. 3 is provided by the embodiment of the present invention, as shown in figure 3, this
Inventing a kind of server 10 with novel topological structure provided includes at least one node 11, and node 11 includes node control
Device 101 processed and at least N number of CPU, CPU and Node Controller 101 are respectively provided with N number of QPI ports, and any two CPU passes through respective
QPI ports are connected, and any one CPU is connected by respective QPI ports with Node Controller 101；Wherein, N be more than
Or the positive integer equal to 2.
Topology refers to entity is abstracted into " point " unrelated with its size, shape, and the circuit of connection entity is abstracted into
" line ", and then in graph form come the method for representing relation between these points and line, its object is to study between these point, lines
Annexation.The figure of relation is referred to as topology diagram between expression Points And lines.Novel topological structure server is exactly to service
Annexation in device 10 between the internal module of each node 11.The inside of server 10 includes at least one node 11, that is, takes
Business device 10 inside be possible to multiple nodes 11, it is also possible in only one of which node 11, Fig. 3 be a node 11 in it is interior
Portion's structure chart, includes Node Controller 101 and at least N number of CPU, and CPU and Node Controller 101 again in each node 11
Be respectively provided with N number of QPI ports, that is to say, that CPU is equal with the number of the QPI ports on Node Controller and CPU number, i.e., one
Having in individual node 11 will be respectively to that should have several QPI ports on several CPU, Node Controller 101 and CPU.If for example, one
There are 5 CPU in individual node 11, CPU QPI ports will be to that there should be 5, and the QPI ports of Node Controller 101 also can be to that should have
5.Any two CPU is connected by respective QPI ports, and any one CPU passes through respective QPI ports and node control
Device 101 processed is connected, i.e. be all connection between all CPU in node 11, between all CPU and Node Controller 101
It is connection.This annexation in correspondence and node 11 on initial quantity, will solve QPI port resources waste with
And the problem of server delays.Previously mentioned N is the positive integer more than or equal to 2.
In order that those skilled in the art is better understood from an intra-node annexation in the embodiment of the present application, with
N is equal to exemplified by 3, and the present invention is described in further detail.
Table 1 is the connection relational table of CPU and other node cpus between CPU and in the node in the corresponding nodes of Fig. 3,
As shown in table 1：
N refers to CPU number, while also referring to the QPI port numbers on CPU and Node Controller 101, when N is 3, i.e.,
There are 3 CPU in one node 11, CPU0 301, CPU1302 and CPU2 303, and CPU0 301, CPU1 are denoted as respectively
302nd, there are 3 QPI ports respectively on CPU2 303 and Node Controller 101, QPI port orders are denoted as P0, P1, P2 respectively.On
3 CPU are stated while be connected with a Node Controller 101, between 3 CPU and the company between CPU and Node Controller 101
The relation of connecing can refer to Fig. 3 and table 1, and this connected mode can realize the exchanging visit between 3 CPU in the node 11, can also be real
The now access in the node between CPU and Node Controller 101, while the exchanging visit of CPU between different nodes can be realized.
Table 1
Annexation is simple, clear and easy between the shared Node Controller of 3 CPU, module in one node
Realize.It is understood that N can be 3, can also be 4,5,6 etc., N be 3 be that one kind is preferably carried out mode, be one
Application scenarios are planted, does not represent and there was only a kind of this mode.CPU0, CPU1, CPU2 and QPI port order P0, P1, P2 are
It is artificial defined, is not changeless, can be changed according to personal habits.CPU naming method, QPI port are suitable
Sequence can't influence the realization of the embodiment of the present application.
Strictly speaking, node 11 is really non-existent, is intended merely to study a question what is conveniently artificially delimited, and delimit
Mode also without strict requirements, can arbitrarily be changed according to actual conditions.It is understood that CPU number and node
Number can't influence the realization of the embodiment of the present application.
Server provided by the present invention with novel topological structure a, on the one hand, node is included extremely in server
Few N number of CPU, CPU and Node Controller are respectively provided with N number of QPI ports, i.e. CPU and the QPI ports on Node Controller and CPU's
Number is equal, and each CPU is connected with Node Controller, overcomes QPI port resources in the prior art and wastes and number
According to caused server delays problem during transmission, and then improve QPI port resources utilization rate and data transmission efficiency.It is another
Connected between aspect, any two CPU also by QPI ports, further increase QPI port resources utilization rate and data are passed
Defeated efficiency.
On the basis of above-described embodiment, preferably embodiment, server is that (nonuniformity storage is accessed NUMA
Structure) server.
NUMA architecture server uses distributed memory pattern, and each CPU accesses the speed of other CPU in local node
Higher than the speed for accessing the CPU in some distant-end nodes.In other words, that is, access the time that CPU in different nodes is spent
It is unequal, the characteristics of NUMA had both had the application programming pattern of simplicity and had been easily managed, there is expandability again,
The scale of system can effectively be expanded.When NUMA architecture server, especially inside have more than 8 CPU interconnections, generally compare
Other servers are more economical and performance is higher.NUMA major advantage is retractility, and NUMA architecture server is compared to other
IA frame serverPC improves to some extent on scalability, and server scalability refers to when CPU number changes in server, service
The phenomenon that the disposal ability of device changes therewith, all internal storage access of general IA frame serverPC are all delivered to identical shared drive
Bus, this mode applies in general to the relatively small number of situation of CPU quantity, but is not suitable for a fairly large number of situations of CPU, because
CPU can vie each other the access to shared drive bus, NUMA by limit the CPU quantity on any rambus and according to
Interconnect to connect each node at a high speed by Node Controller, so as to avoid above mentioned problem.NUMA architecture server can be
Integrated multiple CPU in one server, make system have higher transaction capabilities.It is understood that server can be with
For NUMA architecture server, or qualified other servers, the type of server has no effect on the application implementation
The realization of example.
On the basis of above-described embodiment, preferably embodiment, when the quantity of node 11 is more than 1, node control
Connected between device 101 by network interface, so that the CPU 102 between multiple nodes 11 carries out data transmission.
There are in the server 10 multiple nodes 11, and local node CPU 102 is when needing to access distant-end node CPU,
It is accomplished by first transferring data to local node control by the progress of Node Controller 101 data forwarding, i.e. local node CPU 102
The data received are given distant-end node controller by device 101 processed, local node controller 101 by network interface transfers again, most
Distant-end node CPU is transferred data to by distant-end node controller afterwards, finally realizes that local node CPU 102 accesses distant-end node
CPU.The process can realize the data transfer of CPU between different nodes.In the embodiment of the present application, network interface can be NI
EBI, NI bus interface datas efficiency of transmission is high, it is of course also possible to be other qualified network interfaces, network connects
The type of mouth has no effect on the realization of the embodiment of the present application.
On the basis of above-described embodiment, preferably embodiment, Node Controller 101 is that (standard is controlled NC
Device).
Node Controller 101 plays an important role in the data transmission procedure of each node, and Node Controller is by each factory
Family realizes its specification and concrete function, and on each node, its major function is that the overall situation for realizing multicomputer system is delayed for distribution
Deposit and interconnected at a high speed between uniformity and node, realize the quick transmission access of data between CPU, the type of Node Controller and inside
Implementation has no effect on the realization of the embodiment of the present application.
On the basis of above-described embodiment, preferably embodiment, CPU is IntelX86CPU.
X86 is the standard number abbreviation of an Intel universal computer series, also identifies a set of general computer instruction
Set, X and CPU does not have any relation, and it is that a simple asterisk wildcard to all 86 systems is defined, and x86 instruction set is beautiful
Intel Company of state is what its first piece of 16 bit CPU was specially developed.IntelX86CPU manufacturing process is advanced, low in energy consumption, stably
Property strong, cost is low, monokaryon performance and power consumption control preferably, in a word, the clothes with topological structure that the embodiment of the present invention is provided
Business device, IntelX86CPU has higher performance, preferably faster speed, compatibility.Certainly, CPU type can't shadow
Ring the realization of the embodiment of the present application.
The server provided by the present invention with novel topological structure is described in detail above.Use herein
Several examples are set forth to the principle and embodiment of the present invention, and the explanation of above example is only intended to help and understood
The method and its core concept of the present invention；Simultaneously for those of ordinary skill in the art, according to the thought of the present invention, in tool
It will change in body embodiment and application, in summary, this specification content should not be construed as to the present invention
Limitation, those skilled in the art, on the premise of no creative work, to the present invention made modification, equivalent substitution,
Improve etc., it should be included in the application.
It should also be noted that, in this manual, such as CPU0 and CPU1 or the like relational terms be used merely to by
One operation makes a distinction with another operation, and not necessarily requires or imply these entities or exist between operating any
This actual relation or order.
Claims (7)
1. a kind of server with novel topological structure, it is characterised in that including at least one node, the node includes section
Base site controller and at least N number of CPU, the CPU and the Node Controller are respectively provided with N number of QPI ports, CPU described in any two
Connected by the respective QPI ports, and any one of CPU passes through the respective QPI ports and the node
Controller is connected；
Wherein, N is the positive integer more than or equal to 2.
2. server according to claim 1, it is characterised in that the N is equal to 3.
3. server according to claim 1, it is characterised in that the server is that nonuniformity stores access structure
NUMA servers.
4. server according to claim 1, it is characterised in that when the number of nodes is more than 1, the node control
Connected between device by network interface, so that the CPU between multiple nodes carries out data transmission.
5. server according to claim 4, it is characterised in that the network interface is NI EBIs.
6. server according to claim 1, it is characterised in that the Node Controller is standard controller NC.
7. the server according to claim 1-6 any one, it is characterised in that the CPU is Intel X86CPU.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710670978.2A CN107239432A (en) | 2017-08-08 | 2017-08-08 | A kind of server with novel topological structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710670978.2A CN107239432A (en) | 2017-08-08 | 2017-08-08 | A kind of server with novel topological structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107239432A true CN107239432A (en) | 2017-10-10 |
Family
ID=59988658
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710670978.2A Pending CN107239432A (en) | 2017-08-08 | 2017-08-08 | A kind of server with novel topological structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107239432A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107807900A (en) * | 2017-11-14 | 2018-03-16 | 浙江亿邦通信科技股份有限公司 | Data handling system and server |
| CN108337175A (en) * | 2018-01-31 | 2018-07-27 | 郑州云海信息技术有限公司 | A kind of multipath server and its node communication method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102141975A (en) * | 2011-04-01 | 2011-08-03 | 华为技术有限公司 | Computer system |
| CN102232218A (en) * | 2011-06-24 | 2011-11-02 | 华为技术有限公司 | Computer subsystem and computer system |
| CN102318275A (en) * | 2011-08-02 | 2012-01-11 | 华为技术有限公司 | Method, device, and system for processing messages based on CC-NUMA |
| CN103092807A (en) * | 2012-12-24 | 2013-05-08 | 杭州华为数字技术有限公司 | Node controller, parallel computing server system and route method |
-
2017
- 2017-08-08 CN CN201710670978.2A patent/CN107239432A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102141975A (en) * | 2011-04-01 | 2011-08-03 | 华为技术有限公司 | Computer system |
| CN102232218A (en) * | 2011-06-24 | 2011-11-02 | 华为技术有限公司 | Computer subsystem and computer system |
| CN102318275A (en) * | 2011-08-02 | 2012-01-11 | 华为技术有限公司 | Method, device, and system for processing messages based on CC-NUMA |
| CN103092807A (en) * | 2012-12-24 | 2013-05-08 | 杭州华为数字技术有限公司 | Node controller, parallel computing server system and route method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107807900A (en) * | 2017-11-14 | 2018-03-16 | 浙江亿邦通信科技股份有限公司 | Data handling system and server |
| CN107807900B (en) * | 2017-11-14 | 2021-02-19 | 浙江亿邦通信科技股份有限公司 | Data processing system and server |
| CN108337175A (en) * | 2018-01-31 | 2018-07-27 | 郑州云海信息技术有限公司 | A kind of multipath server and its node communication method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110741356B (en) | Relay coherent memory management in multiprocessor systems | |
| Arimilli et al. | The PERCS high-performance interconnect | |
| Ajima et al. | Tofu interconnect 2: System-on-chip integration of high-performance interconnect | |
| JP3836840B2 (en) | Multiprocessor system | |
| JP3836838B2 (en) | Method and data processing system for microprocessor communication using processor interconnections in a multiprocessor system | |
| CN103092807B (en) | Node Controller, parallel computation server system and method for routing | |
| CN101057223B (en) | Methods and apparatus for supporting multiple configurations in a multi-processor system | |
| US8352656B2 (en) | Handling atomic operations for a non-coherent device | |
| US20130346934A1 (en) | High-end fault-tolerant computer system and method for same | |
| CN104657308A (en) | Method for realizing server hardware acceleration by using FPGA (field programmable gate array) | |
| CN105207957B (en) | A kind of system based on network-on-chip multicore architecture | |
| US20210075745A1 (en) | Methods and apparatus for improved polling efficiency in network interface fabrics | |
| CN103440223A (en) | Layering system for achieving caching consistency protocol and method thereof | |
| CN105025070A (en) | Method to optimize network data flows within a constrained system | |
| CN103649923B (en) | A kind of NUMA Installed System Memory mirror configuration method, release method, system and host node | |
| Rettkowski et al. | RAR-NoC: A reconfigurable and adaptive routable Network-on-Chip for FPGA-based multiprocessor systems | |
| CN110442532A (en) | The whole world of equipment for being linked with host can store memory | |
| Micikevicius | Multi-GPU programming | |
| CN103106173A (en) | Interconnection method among cores of multi-core processor | |
| WO2013097394A1 (en) | Method and system for multiprocessors to share memory | |
| JP3836837B2 (en) | Method, processing unit, and data processing system for microprocessor communication in a multiprocessor system | |
| WO2018203754A1 (en) | Cache coherent node controller for scale-up shared memory systems | |
| CN102375789B (en) | Non-buffer zero-copy method of universal network card and zero-copy system | |
| CN106844263B (en) | Configurable multiprocessor-based computer system and implementation method | |
| Gustavson et al. | The scalable coherent interface (SCI) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20171010 |
|
| RJ01 | Rejection of invention patent application after publication |