CN107230631A - The preparation method of channel-type semiconductor device - Google Patents

The preparation method of channel-type semiconductor device Download PDF

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Publication number
CN107230631A
CN107230631A CN201610170343.1A CN201610170343A CN107230631A CN 107230631 A CN107230631 A CN 107230631A CN 201610170343 A CN201610170343 A CN 201610170343A CN 107230631 A CN107230631 A CN 107230631A
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China
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areas
layer
groove
formed
surface
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CN201610170343.1A
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Chinese (zh)
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马万里
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北大方正集团有限公司
深圳方正微电子有限公司
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Priority to CN201610170343.1A priority Critical patent/CN107230631A/en
Publication of CN107230631A publication Critical patent/CN107230631A/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET

Abstract

The present invention provides a kind of preparation method of channel-type semiconductor device, including:To the semiconductor silicon substrate with initial oxide layer, carrying out photoetching and etching formation includes the cellular region of at least one first groove and includes the ESD structural areas of the second groove of strip;Form gate oxide, polysilicon layer;The polysilicon layer in N-type epitaxy layer is etched away using dry etching;Carry out the injection of p-type ion and drive in form P bodies area;Form the first photoresist window, spaced second photoresist window, injection N-type ion the first N+ areas of formation and the 2nd N+ areas;Form the 3rd photoresist window, spaced 4th photoresist window, the first P+ areas of implanting p-type ion formation, the 2nd P+ areas;Dielectric layer, metal level are formed on whole device.Using the polysilicon layer in the method etching N-type epitaxy layer of etching, it is not necessary to use mask plate, reduce the cost of manufacture of channel-type semiconductor device.

Description

The preparation method of channel-type semiconductor device

Technical field

The present invention relates to field of semiconductor technology, more particularly to a kind of making side of channel-type semiconductor device Method.

Background technology

Groove-shaped semiconductor devices is the conventional device during industry makes, and with ESD structures Channel-type semiconductor device be widely used in every field.

In the prior art, the preparation method of channel-type semiconductor device is:In the table of semiconductor silicon substrate Formed on face after initial oxide layer, the N-type epitaxy layer to initial oxide layer and semiconductor silicon substrate is entered Row photoetching and etching, form multiple grooves being uniformly arranged, then grow grid in whole device surface Oxide layer, polysilicon layer;Photoetching and etching are carried out to polysilicon layer, the polysilicon layer of part is left; The injection of p-type ion is carried out into whole device and is driven in, P- bodies area is formed;The shape on whole device Into photoresist window, N-type ion is injected into whole device by photoresist window, in P- bodies area Middle formation N+ source regions;Then photoresist window is formed again, by photoresist window to whole device Middle implanting p-type ion, to be formed and the spaced P+ bodies area of N+ source regions;Then dielectric layer is formed And metal level;Wherein, it is cellular region to have fluted region, only has spaced N+ source regions Region with P+ bodies area is ESD structural areas.

But in the prior art, multiple grooves being uniformly arranged are being formed, then in whole device surface Grow after gate oxide, polysilicon layer, it is necessary to using mask plate polysilicon layer is carried out photoetching and Etching, to leave the polysilicon layer of part, so as to form member after the formation in Ge Ti areas after carrying out Born of the same parents area and ESD structural areas.Then, it is necessary to using covering when carrying out photoetching and etching to polysilicon Film version, so that the cost of manufacture of channel-type semiconductor device can be increased.

The content of the invention

The present invention provides a kind of preparation method of channel-type semiconductor device, right in the prior art to solve , it is necessary to mask plate be used, so that grooved semiconductor can be increased when polysilicon progress photoetching and etching The problem of cost of manufacture of device.

The present invention provides a kind of preparation method of channel-type semiconductor device, including:

The semiconductor silicon substrate for pair being provided with initial oxide layer carries out photoetching and etching, formed cellular region and ESD structural areas, wherein, the cellular region includes at least one first groove, the ESD structural areas Include the second groove of a strip, the semiconductor silicon substrate includes what is from bottom to top set gradually N-type substrate and N-type epitaxy layer;

Remove after the initial oxide layer, gate oxide, polysilicon layer are sequentially formed on whole device;

Using dry etching, the polysilicon layer in the N-type epitaxy layer is etched away, and in the N P- bodies area is formed in type epitaxial layer;

The first photoresist window is formed on the surface of the cellular region, and on the surface of the second groove It is upper to form spaced second photoresist window, pass through the first photoresist window, second light Photoresist window injects N-type ion into whole device, with the cellular region formed the first N+ areas and The 2nd N+ areas are formed in the second groove;

The 3rd photoresist window is formed on the surface of the cellular region, and on the surface of the second groove It is upper to form spaced 4th photoresist window, pass through the 3rd photoresist window, the 4th light Photoresist window implanting p-type ion into whole device, with formed in the cellular region with the first N+ it is interval every The first P+ areas set, and formed and the 2nd P+ areas of interval setting of the 2nd N+ areas in the second groove;

Dielectric layer and metal level are sequentially formed on the surface of whole device.

In method as described above, the semiconductor silicon substrate for pair being provided with initial oxide layer carry out photoetching and Before etching, in addition to:

In the environment of 900 degrees Celsius~1100 degrees Celsius, the shape on the surface of the semiconductor silicon substrate Into the initial oxide layer;

Wherein, the thickness of the initial oxide layer is 0.01 micron~0.20 micron.

In method as described above, gate oxide, polysilicon layer are sequentially formed on the whole device, is wrapped Include:

Gate oxide is formed in the N-type epitaxy layer and in the first groove, the second groove;

In the environment of 500 degrees Celsius~700 degrees Celsius, in the N-type epitaxy layer and described first The polysilicon layer is formed in groove, the second groove;

Wherein, the thickness of the polysilicon layer is 0.05 micron~2.0 microns.

In method as described above, the formation P- bodies area in the N-type epitaxy layer, including:

Above from whole device, it is 1.0E13~1.0E15/squares that implantation dosage is injected into whole device Centimetre boron ion, energy be 80 kiloelectron-volts~120 kiloelectron-volts;

It is 900 degrees Celsius~1200 degrees Celsius that progress, which drives in temperature, and the time is 60 minutes~180 minutes P-type ion drive in, to form P- bodies areas in the N-type epitaxy layer.

In method as described above, the first photoresist window is formed on the surface of the cellular region, and Spaced second photoresist window is formed on the surface of the second groove, passes through first photoetching Glue window, the second photoresist window inject N-type ion into whole device, with the cellular region Form the first N+ areas and the 2nd N+ areas are formed in the second groove, including:

The first photoresist layer is formed on the surface of whole device, photoetching is carried out to first photoresist layer, To form the first photoresist window on the surface of the cellular region, and on the surface of the second groove Form spaced second photoresist window;

By the first photoresist window, the second photoresist window injected into whole device phosphorus from Son, wherein, the implantation dosage of phosphonium ion is the boron ion of 1.0E15~1.0E16/square centimeter, energy For 100 kiloelectron-volts~150 kiloelectron-volts, to form the first N+ areas and described the in the cellular region The 2nd N+ areas are formed in two grooves;

Remove first photoresist layer.

In method as described above, the 3rd photoresist window of formation on the surface of the cellular region, and Spaced 4th photoresist window is formed on the surface of the second groove, passes through the 3rd photoetching Glue window, the 4th photoresist window implanting p-type ion into whole device, with the cellular region Formed and spaced first P+ areas of the 2nd N+ areas, and formed and the 2nd N+ in the second groove Area is arranged at intervals the 2nd P+ areas, including:

The second photoresist layer is formed on the surface of whole device, photoetching is carried out to second photoresist layer, To form the 3rd photoresist window on the surface of the cellular region, and on the surface of the second groove Form spaced 4th photoresist window;

By the 3rd photoresist window, the 4th photoresist window injected into whole device boron from Son, wherein, the implantation dosage of boron ion is the boron ion of 1.0E15~1.0E16/square centimeter, energy For 50 kiloelectron-volts~150 kiloelectron-volts, it is arranged at intervals with being formed in the cellular region with the first N+ areas The first P+ areas, and in the second groove formed with the 2nd N+ areas be arranged at intervals the 2nd P+ areas;

Remove second photoresist layer.

In method as described above, the surface in whole device forms dielectric layer, including:

Dielectric layer is formed on the surface of whole device, to the grid below the dielectric layer and the dielectric layer Oxide layer carries out photoetching and etching, to form the first contact hole on the cellular region and be tied in the ESD The second contact hole is formed in structure area;

Wherein, the dielectric layer is silicon dioxide layer.

In method as described above, the width of first contact hole is more than the width in the first P+ areas;

The width of second contact hole is less than the width of the second groove.

In method as described above, the forming metal layer on surface in whole device, including:

The metal of Al-Si-Cu alloy is grown on the surface of whole device by the way of sputtering;

Photoetching and etching are carried out to the Al-Si-Cu alloy, to form metal level, wherein, the metal level Maximum gauge be 0.01 micron~5.00 microns.

The present invention carries out photoetching and quarter by the N-type epitaxy layer to initial oxide layer and semiconductor silicon substrate Erosion, forms cellular region and ESD structural areas, cellular region includes at least one first groove, ESD structures Area includes the second groove of a strip;Remove initial oxide layer after, in N-type epitaxy layer with And gate oxide, polysilicon layer are sequentially formed in first groove, second groove;Using dry etching, carve Polysilicon layer in eating away N-type epitaxy layer, forms P- bodies area in N-type epitaxy layer;Table in cellular region The first photoresist window is formed on face, and forms on the surface of second groove spaced second photoetching Glue window, N-type ion is injected into whole device by the first photoresist window, the second photoresist window, To form the first N+ areas in cellular region and the 2nd N+ areas formed in second groove;Surface in cellular region The 3rd photoresist window of upper formation, and form on the surface of second groove spaced 4th photoresist Window, by the 3rd photoresist window, the 4th photoresist window implanting p-type ion into whole device, With cellular region formed with spaced first P+ areas of the first N+ areas, and in second groove formed with 2nd N+ areas are arranged at intervals the 2nd P+ areas;Dielectric layer and metal level are formed on the surface of whole device.From And there is provided a kind of preparation method of channel-type semiconductor device, can be etched in semiconductor silicon substrate The second groove of at least one first groove and a strip;Gate oxidation is formed on whole device After layer, polysilicon layer, it is possible to use only the polysilicon layer in the method etching N-type epitaxy layer of etching, Only retain the polysilicon layer in first groove, second groove;P-type ion is then injected into, so that in N-type P- bodies area is formed in epitaxial layer;The first photoresist window is formed on cellular region, and in the table of second groove Spaced second photoresist window is formed on face, so that inject after N-type ion, can be in cellular Area forms the first N+ areas and the 2nd N+ areas is formed in second groove;Then the shape on the surface of cellular region Into the 3rd photoresist window, spaced 4th photoresist window is formed on the surface of second groove, After implanting p-type ion, it can be formed and spaced first P+ areas of the first N+ areas in cellular region, Formed in second groove and be arranged at intervals the 2nd P+ areas with the 2nd N+ areas;Then on the surface of whole device Form dielectric layer and metal level.So as to etch the polycrystalline in N-type epitaxy layer only with the method for etching Silicon layer, only retains the polysilicon layer in first groove, second groove, it is not necessary to use mask plate, reduces The cost of manufacture of channel-type semiconductor device;Meanwhile, using the first groove in N-type epitaxy layer, Inject ion, formed after dielectric layer and metal level, this region constitutes cellular region, using N-type epitaxy layer On strip second groove, in injection ion, form dielectric layer and metal level after, this region structure Into ESD structural areas.

Brief description of the drawings

Fig. 1 is that the flow of the preparation method for the channel-type semiconductor device that the embodiment of the present invention one is provided is shown It is intended to;

Fig. 2 illustrates for the section of channel-type semiconductor device in step 101 implementation procedure of embodiment one Figure one;

Fig. 3 illustrates for the section of channel-type semiconductor device in step 101 implementation procedure of embodiment one Figure two;

Fig. 4 for embodiment one step 101 implementation procedure in channel-type semiconductor device top view;

Fig. 5 illustrates for the section of channel-type semiconductor device in step 102 implementation procedure of embodiment one Figure;

Fig. 6 illustrates for the section of channel-type semiconductor device in step 103 implementation procedure of embodiment one Figure one;

Fig. 7 illustrates for the section of channel-type semiconductor device in step 103 implementation procedure of embodiment one Figure two;

Fig. 8 illustrates for the section of channel-type semiconductor device in step 104 implementation procedure of embodiment one Figure;

Fig. 9 for embodiment one step 104 implementation procedure in channel-type semiconductor device top view;

Figure 10 shows for the section of channel-type semiconductor device in step 105 implementation procedure of embodiment one It is intended to;

Figure 11 for embodiment one step 105 implementation procedure in channel-type semiconductor device top view;

Figure 12 shows for the section of channel-type semiconductor device in step 106 implementation procedure of embodiment one It is intended to;

Figure 13 is the flow of the preparation method for the channel-type semiconductor device that the embodiment of the present invention two is provided Schematic diagram;

Figure 14 shows for the section of channel-type semiconductor device in step 1061 implementation procedure of embodiment two It is intended to;

Figure 15 for embodiment two step 1061 implementation procedure in channel-type semiconductor device vertical view Figure.

Embodiment

To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with this hair Accompanying drawing in bright embodiment, the technical scheme in the embodiment of the present invention is clearly and completely described, Obviously, described embodiment is a part of embodiment of the invention, rather than whole embodiments.It is based on Embodiment in the present invention, those of ordinary skill in the art are obtained under the premise of creative work is not made The every other embodiment obtained, belongs to the scope of protection of the invention.

Fig. 1 is the flow signal of the preparation method for the channel-type semiconductor device that the embodiment of the present invention one is provided Figure, in order to the method in the present embodiment understand the description of system, as shown in figure 1, including:

Step 101, the semiconductor silicon substrate for pair being provided with initial oxide layer carry out photoetching and etching, are formed Cellular region and ESD structural areas, wherein, cellular region includes at least one first groove, ESD structural areas Include the second groove of a strip, semiconductor silicon substrate includes the N-type from bottom to top set gradually Substrate and N-type epitaxy layer.

In the present embodiment, specifically, Fig. 2 is groove-shaped in step 101 implementation procedure of embodiment one The diagrammatic cross-section one of semiconductor devices, Fig. 3 is groove-shaped in step 101 implementation procedure of embodiment one The diagrammatic cross-section two of semiconductor devices, Fig. 4 is groove-shaped in step 101 implementation procedure of embodiment one The top view of semiconductor devices, as shown in Figure 2, Figure 3 and Figure 4, the semiconductor silicon substrate table of label 11 Show, N-type substrate label 12 is represented, N-type epitaxy layer label 13 is represented, initial oxide layer mark Numbers 14 are represented, cellular region label 15 represents that ESD structural areas label 16 is represented, first groove is used Label 17 represents that second groove label 18 is represented.

Wherein, semiconductor silicon substrate 11 can be semiconductor element, such as monocrystalline silicon, polysilicon or amorphous The silicon or SiGe (SiGe) of structure, or the semiconductor structure of mixing, such as carborundum, indium antimonide, Lead telluride, indium arsenide, indium phosphide, GaAs or gallium antimonide, alloy semiconductor or its combination.This implementation Example is not limited herein.Semiconductor silicon substrate 11 includes the N-type from bottom to top set gradually Substrate 12 and N-type epitaxy layer 13.

N-type epitaxy layer 13 to initial oxide layer 14 and semiconductor silicon substrate 11 carries out photoetching and etching, From etching multiple first grooves 17, and the second groove 18 of a strip is etched, so that with the The region of one groove 17 is cellular region 15, and the region with second groove 18 is ESD structural areas 16.

Step 102, remove initial oxide layer after, gate oxide is sequentially formed on whole device, many Crystal silicon layer.

In the present embodiment, specifically, Fig. 5 is groove-shaped in step 102 implementation procedure of embodiment one The diagrammatic cross-section of semiconductor devices, as shown in figure 5, gate oxide label 19 is represented, polysilicon layer Represented with label 20.

After removal initial oxide layer 14, then one layer of gate oxide of formation on the surface of whole device.Tool For body, oxygen is passed through in reacting furnace, at high temperature, the N-type extension in semiconductor silicon substrate 11 Gate oxide 19 is formed on the surface of layer 13 and in first groove 17, the surface of second groove 18.

Then low-pressure chemical vapor deposition method is used, silane (SiH is passed through in reacting furnace4) gas, Silane gas resolves into polysilicon at high temperature, polysilicon deposition on the surface of whole device so that Polysilicon is formed in the top of N-type epitaxy layer 13 and first groove 17, the inside of second groove 18 Layer 20.

Step 103, using dry etching, etch away the polysilicon layer in N-type epitaxy layer, and in N-type P- bodies area is formed in epitaxial layer.

In the present embodiment, specifically, in the present embodiment, specifically, Fig. 6 is the step of embodiment one The diagrammatic cross-section one of channel-type semiconductor device in rapid 103 implementation procedure, Fig. 7 is the step of embodiment one The diagrammatic cross-section two of channel-type semiconductor device in rapid 103 implementation procedure, as shown in Figure 6 and Figure 7, P- bodies area label 21 is represented.

Using dry etching, the polysilicon layer 20 on the surface of N-type epitaxy layer 13 is etched away, only retains each Polysilicon layer 20 in first groove 17 and second groove 18, as shown in Figure 6.

Then, from the top of whole device, the implanting p-type ion into whole device, now p-type ion Concentration it is relatively low, then carry out p-type ion and drive in, so as to form P- bodies areas in N-type epitaxy layer 13 21, as shown in Figure 7.

Step 104, the first photoresist window is formed on the surface of cellular region, and in the table of second groove Spaced second photoresist window is formed on face, passes through the first photoresist window, the second photoresist window Mouth injects N-type ion into whole device, to form the first N+ areas and in second groove in cellular region Form the 2nd N+ areas.

In the present embodiment, specifically, Fig. 8 is groove-shaped in step 104 implementation procedure of embodiment one The diagrammatic cross-section of semiconductor devices, Fig. 9 is in step 104 implementation procedure of embodiment one groove-shaped half The top view of conductor device, as shown in Figure 8 and Figure 9, the first photoresist window label 22 represent, Two photoresist window labels 23 represent that the first N+ areas label 24 is represented, the 2nd N+ areas label 25 represent.

Each the first photoresist window 22 is formed on the surface of cellular region 15, also, in second groove The second photoresist window 23 is formed on 18 surface, also, the second photoresist window 23 is interval setting 's.Then by each the first photoresist window 22, each the second photoresist window 23 to whole device Middle injection N-type ion, so that the first N+ areas 24 are formed in the P- bodies area 21 of cellular region 15, and Spaced 2nd N+ areas 25 are formed in the polysilicon layer 20 of second groove 18.

Step 105, the 3rd photoresist window of formation on the surface of cellular region, and in the table of second groove Spaced 4th photoresist window is formed on face, passes through the 3rd photoresist window, the 4th photoresist window Mouth implanting p-type ion into whole device, to be formed and the first N+ areas spaced first in cellular region P+ areas, and formed and the 2nd P+ areas of interval setting of the 2nd N+ areas in second groove.

In the present embodiment, specifically, Figure 10 is groove-shaped in step 105 implementation procedure of embodiment one The diagrammatic cross-section of semiconductor devices, Figure 11 is in step 105 implementation procedure of embodiment one groove-shaped half The top view of conductor device, as shown in Figure 10 and Figure 11, the 3rd photoresist window label 26 represent, 4th photoresist window label 27 represents that the first P+ areas label 28 is represented, the 2nd P+ areas mark Numbers 29 represent.

Photoresist in removal step 104 on whole device surface, the then shape on the surface of cellular region 15 Into each the 3rd photoresist window 26, the 4th photoresist window 27 is formed on the surface of second groove 18, Also, the 4th photoresist window 27 is spaced.By each the 3rd photoresist window 26, respectively Individual 4th photoresist window 27 implanting p-type ion into whole device, so as in cellular region 15 The first P+ areas 28 are formed, the first P+ areas 28 and the first N+ areas 24 are spaced;And in second groove The 2nd P+ areas 29 are formed in 18, the 2nd P+ areas 29 and the 2nd N+ areas 25 are arranged at intervals.

Step 106, on the surface of whole device sequentially form dielectric layer and metal level.

In the present embodiment, specifically, Figure 12 is groove-shaped in step 106 implementation procedure of embodiment one The diagrammatic cross-section of semiconductor devices, as shown in figure 12, dielectric layer label 30 represent that metal level is used Label 33 is represented.

Oxygen is passed through, dielectric layer 30 is formed on the surface of whole device.Then to dielectric layer 30 and Jie The gate oxide 19 of the lower section of matter layer 30 carries out photoetching and etching, so that in cellular region 15, ESD structural areas Contact hole on 16.

Then, metal is grown on the surface of whole device first, photoetching then is carried out to the metal of growth And etching, so as to form metal level 33.

The present invention carries out photoetching and quarter by the N-type epitaxy layer to initial oxide layer and semiconductor silicon substrate Erosion, forms cellular region and ESD structural areas, cellular region includes at least one first groove, ESD structures Area includes the second groove of a strip;Remove initial oxide layer after, in N-type epitaxy layer with And gate oxide, polysilicon layer are sequentially formed in first groove, second groove;Using dry etching, carve Polysilicon layer in eating away N-type epitaxy layer, forms P- bodies area in N-type epitaxy layer;Table in cellular region The first photoresist window is formed on face, and forms on the surface of second groove spaced second photoetching Glue window, N-type ion is injected into whole device by the first photoresist window, the second photoresist window, To form the first N+ areas in cellular region and the 2nd N+ areas formed in second groove;Surface in cellular region The 3rd photoresist window of upper formation, and form on the surface of second groove spaced 4th photoresist Window, by the 3rd photoresist window, the 4th photoresist window implanting p-type ion into whole device, With cellular region formed with spaced first P+ areas of the first N+ areas, and in second groove formed with 2nd N+ areas are arranged at intervals the 2nd P+ areas;Dielectric layer and metal level are formed on the surface of whole device.From And there is provided a kind of preparation method of channel-type semiconductor device, can be etched in semiconductor silicon substrate The second groove of at least one first groove and a strip;Gate oxidation is formed on whole device After layer, polysilicon layer, it is possible to use only the polysilicon layer in the method etching N-type epitaxy layer of etching, Only retain the polysilicon layer in first groove, second groove;P-type ion is then injected into, so that in N-type P- bodies area is formed in epitaxial layer;The first photoresist window is formed on cellular region, and in the table of second groove Spaced second photoresist window is formed on face, so that inject after N-type ion, can be in cellular Area forms the first N+ areas and the 2nd N+ areas is formed in second groove;Then the shape on the surface of cellular region Into the 3rd photoresist window, spaced 4th photoresist window is formed on the surface of second groove, After implanting p-type ion, it can be formed and spaced first P+ areas of the first N+ areas in cellular region, Formed in second groove and be arranged at intervals the 2nd P+ areas with the 2nd N+ areas;Then on the surface of whole device Form dielectric layer and metal level.So as to etch the polycrystalline in N-type epitaxy layer only with the method for etching Silicon layer, only retains the polysilicon layer in first groove, second groove, it is not necessary to use mask plate, reduces The cost of manufacture of channel-type semiconductor device;Meanwhile, using the first groove in N-type epitaxy layer, Inject ion, formed after dielectric layer and metal level, this region constitutes cellular region, using N-type epitaxy layer On strip second groove, in injection ion, form dielectric layer and metal level after, this region structure Into ESD structural areas.

Figure 13 is that the flow of the preparation method for the channel-type semiconductor device that the embodiment of the present invention two is provided is shown It is intended to, on the basis of above-described embodiment, in order to carry out understanding retouching for system to the method in the present embodiment State, as shown in figure 13:

Before step 101, in addition to:

Step 201, in the environment of 900 degrees Celsius~1100 degrees Celsius, on the surface of semiconductor silicon substrate Upper formation initial oxide layer;Wherein, the thickness of initial oxide layer is 0.01 micron~0.20 micron.

In the present embodiment, specifically, to being passed through oxygen, at high temperature, semiconductor silicon in reacting furnace Initial oxide layer 14 is formed on the surface of N-type epitaxy layer 13 in substrate 11, wherein, initial oxide layer 14 growth temperature is 900 degrees Celsius~1100 degrees Celsius, and the thickness of the initial oxide layer formed is 0.01 micron~0.20 micron.

In step 102 after initial oxide layer is removed, specifically include:

Gate oxide is formed in N-type epitaxy layer and in first groove, second groove;It is Celsius 500 Form many in the environment of~700 degrees Celsius of degree, in N-type epitaxy layer and in first groove, second groove Crystal silicon layer;

Wherein, the thickness of polysilicon layer is 0.05 micron~2.0 microns.

In the present embodiment, specifically, after eliminating initial oxide layer 14, oxygen is passed through in reacting furnace Gas, at high temperature, on the surface of the N-type epitaxy layer 13 in semiconductor silicon substrate 11 and the first ditch Gate oxide 19 is formed on groove 17, the surface of second groove 18.

Then low-pressure chemical vapor deposition method is used, silane (SiH is passed through in reacting furnace4) gas, , can be in N-type epitaxy layer 13 and first groove in the environment of 500 degrees Celsius~700 degrees Celsius 17th, polysilicon layer 20 is formed in second groove 18, wherein, the thickness of polysilicon layer 20 is 0.05 micron ~2.0 microns.

P- bodies area is formed in N-type epitaxy layer in step 103, is specifically included:

Above from whole device, it is 1.0E13~1.0E15/squares that implantation dosage is injected into whole device Centimetre boron ion, energy be 80 kiloelectron-volts~120 kiloelectron-volts;

It is 900 degrees Celsius~1200 degrees Celsius that progress, which drives in temperature, and the time is 60 minutes~180 minutes P-type ion drive in, to form P- bodies areas in N-type epitaxy layer.

In the present embodiment, specifically, from the top of whole device, into whole device implanting p-type from Son, the implantation dosage of boron ion is 1.0E13~1.0E15/square centimeter, energy is 80 kiloelectron-volts~ 120 kiloelectron-volts.Then p-type ion is carried out in high temperature furnace pipe to drive in, drive in temperature Celsius for 900 ~1200 degrees Celsius of degree, drives in the time for 60 minutes~180 minutes, so as in N-type epitaxy layer P- bodies area 21 is formed in 13.

Step 104, including:

Step 1041, the first photoresist layer of surface formation in whole device, are carried out to the first photoresist layer Photoetching, to form the first photoresist window, and the shape on the surface of second groove on the surface of cellular region The the second photoresist window set at interval;

Step 1042, phosphorus injected into whole device by the first photoresist window, the second photoresist window Ion, wherein, the implantation dosage of phosphonium ion is the boron ion of 1.0E15~1.0E16/square centimeter, energy Measure as 100 kiloelectron-volts~150 kiloelectron-volts, to form the first N+ areas and in second groove in cellular region The 2nd N+ areas of middle formation;

Step 1043, the first photoresist layer of removal.

In the present embodiment, specifically, forming one layer of first photoresist layer on the surface of whole device first, Then photoetching is carried out to the first photoresist layer, so as to form each the first photoetching on the surface of cellular region 15 Glue window 22, also, the second photoresist window 23 is formed on the surface of second groove 18, also, Second photoresist window 23 is spaced.

Then by each the first photoresist window 22, each the second photoresist window 23 to whole device Middle injection N-type ion, wherein, the implantation dosage of phosphonium ion is 1.0E15~1.0E16/square centimeter Boron ion, energy be 100 kiloelectron-volts~150 kiloelectron-volts so that the P- bodies area in cellular region 15 The first N+ areas 24 are formed in 21, and form spaced in the polysilicon layer 20 of second groove 18 2nd N+ areas 25.

Finally remove the first photoresist layer.

Step 105, including:

Step 1051, the second photoresist layer of surface formation in whole device, are carried out to the second photoresist layer Photoetching, to form the 3rd photoresist window, and the shape on the surface of second groove on the surface of cellular region The 4th photoresist window set at interval;

Step 1052, boron injected into whole device by the 3rd photoresist window, the 4th photoresist window Ion, wherein, the implantation dosage of boron ion is the boron ion of 1.0E15~1.0E16/square centimeter, energy Measure as 50 kiloelectron-volts~150 kiloelectron-volts, to form spaced with the first N+ areas in cellular region First P+ areas, and formed and the 2nd P+ areas of interval setting of the 2nd N+ areas in second groove;

Step 1053, the second photoresist layer of removal.

In the present embodiment, specifically, forming one layer of second photoresist on the surface of whole device first Layer, then to the second photoresist layer carry out photoetching so that formed on the surface of cellular region 15 each the 3rd Photoresist window 26, the 4th photoresist window 27 of formation on the surface of second groove 18, also, the Four photoresist windows 27 are spaced.

Noted by each the 3rd photoresist window 26, each the 4th photoresist window 27 into whole device Enter p-type ion, wherein, the implantation dosage of boron ion for 1.0E15~1.0E16/square centimeter boron from Son, energy is 50 kiloelectron-volts~150 kiloelectron-volts, so as to form first in cellular region 15 P+ areas 28, the first P+ areas 28 and the first N+ areas 24 are spaced;And in second groove 18 shape Into the 2nd P+ areas 29, the 2nd P+ areas 29 and the 2nd N+ areas 25 are arranged at intervals.

Step 106, including:

Step 1061, the surface formation dielectric layer in whole device, below dielectric layer and dielectric layer Gate oxide carries out photoetching and etching, to form the first contact hole on cellular region and on ESD structural areas Form the second contact hole;Wherein, dielectric layer is silicon dioxide layer.

In the present embodiment, specifically, Figure 14 is groove in step 1061 implementation procedure of embodiment two The diagrammatic cross-section of type semiconductor devices, Figure 15 is groove in step 1061 implementation procedure of embodiment two The top view of type semiconductor devices, as shown in Figure 14 and Figure 15, the first contact hole label 31 represent, Second contact hole label 32 is represented.

Oxygen is passed through, dielectric layer 30 is formed on the surface of whole device.Then to dielectric layer 30 and Jie The gate oxide 19 of the lower section of matter layer 30 carries out photoetching and etching, is connect so as to form first on cellular region 15 Contact hole 31, and form on ESD structural areas 16 second contact hole 32.

Dielectric layer 30 is silicon dioxide layer, and the width of the first contact hole 31 is more than the width in the first P+ areas; The width of second contact hole 32 is less than the width of second groove.

In the present embodiment, specifically, dielectric layer 30 is silicon dioxide layer.To dielectric layer 30 and Jie The gate oxide 19 of the lower section of matter layer 30 is carried out after photoetching and etching, first formed on cellular region 15 The width of contact hole 31 is more than the width in the first P+ areas 28, and can be seen by the first contact hole 31 Most first N+ areas 24;The width of the second contact hole 32 formed on ESD structural areas 16 is small In the width of second groove 18.

Step 1062, by the way of sputtering on the surface of whole device grow Al-Si-Cu alloy metal; Photoetching and etching are carried out to Al-Si-Cu alloy, to form metal level, wherein, the maximum gauge of metal level is 0.01 micron~5.00 microns.

In the present embodiment, specifically, by the way of sputtering, aluminium is grown on the surface of whole device The metal of silicon copper, then carries out photoetching to Al-Si-Cu alloy and etching forms metal level 33, also, The maximum gauge of metal level 33 is 0.01 micron~5.00 microns.So as to be filled in the first contact hole 31 Metal level 33, and in the second contact hole 32 it is filled with metal level 33.

The present embodiment is 1.0E13~1.0E15/squares lis by injecting implantation dosage into whole device The boron ion of rice, energy is 80 kiloelectron-volts~120 kiloelectron-volts, and it is 900 then to carry out driving in temperature Degree Celsius~1200 degrees Celsius, the time drove in for the p-type ion of 60 minutes~180 minutes, so as to To form P- bodies area;Phosphorus is injected into whole device by the first photoresist window, the second photoresist window Ion, the implantation dosage of phosphonium ion is the boron ion of 1.0E15~1.0E16/square centimeter, and energy is 100 kiloelectron-volts~150 kiloelectron-volts, so as to form N+ areas;By the 3rd photoresist window, 4th photoresist window injects boron ion into whole device, the implantation dosage of boron ion for 1.0E15~ The boron ion of 1.0E16/square centimeter, energy is 50 kiloelectron-volts~150 kiloelectron-volts, so as to Form P+ areas., can be in semiconductor silicon so as to provide a kind of preparation method of channel-type semiconductor device The second groove of at least one first groove and a strip is etched in substrate;In whole device After upper formation gate oxide, polysilicon layer, it is possible to use only in the method etching N-type epitaxy layer of etching Polysilicon layer, only retain first groove, the polysilicon layer in second groove;P-type ion is then injected into, So as to form P- bodies area in N-type epitaxy layer;The first photoresist window is formed on cellular region, and Spaced second photoresist window is formed on the surface of two grooves, so that inject after N-type ion, The first N+ areas can be formed in cellular region and the 2nd N+ areas are formed in second groove;Then in cellular region Surface on formed the 3rd photoresist window, spaced 4th light is formed on the surface of second groove After photoresist window, implanting p-type ion, it can be formed in cellular region and the first N+ areas spaced the One P+ areas, form in second groove and are arranged at intervals the 2nd P+ areas with the 2nd N+ areas;Then in whole device The surface of part forms dielectric layer and metal level.So as to etch N-type epitaxy layer only with the method for etching On polysilicon layer, only retain first groove, the polysilicon layer in second groove, it is not necessary to use mask Version, reduces the cost of manufacture of channel-type semiconductor device;Meanwhile, using first in N-type epitaxy layer Groove, after injection ion, formation dielectric layer and metal level, this region constitutes cellular region, using N The second groove of strip on type epitaxial layer, after injection ion, formation dielectric layer and metal level, This region constitutes ESD structural areas.

Finally it should be noted that:The above embodiments are merely illustrative of the technical solutions of the present invention, rather than to it Limitation;Although the present invention is described in detail with reference to the foregoing embodiments, the ordinary skill of this area Personnel should be understood:It can still modify to the technical scheme described in foregoing embodiments, or Person carries out equivalent substitution to which part technical characteristic;And these modifications or replacement, do not make corresponding skill The essence of art scheme departs from the spirit and scope of various embodiments of the present invention technical scheme.

Claims (9)

1. a kind of preparation method of channel-type semiconductor device, it is characterised in that including:
The semiconductor silicon substrate for pair being provided with initial oxide layer carries out photoetching and etching, formed cellular region and ESD structural areas, wherein, the cellular region includes at least one first groove, the ESD structural areas Include the second groove of a strip, the semiconductor silicon substrate includes what is from bottom to top set gradually N-type substrate and N-type epitaxy layer;
Remove after the initial oxide layer, gate oxide, polysilicon layer are sequentially formed on whole device;
Using dry etching, the polysilicon layer in the N-type epitaxy layer is etched away, and in the N P- bodies area is formed in type epitaxial layer;
The first photoresist window is formed on the surface of the cellular region, and on the surface of the second groove It is upper to form spaced second photoresist window, pass through the first photoresist window, second light Photoresist window injects N-type ion into whole device, with the cellular region formed the first N+ areas and The 2nd N+ areas are formed in the second groove;
The 3rd photoresist window is formed on the surface of the cellular region, and on the surface of the second groove It is upper to form spaced 4th photoresist window, pass through the 3rd photoresist window, the 4th light Photoresist window implanting p-type ion into whole device, with formed in the cellular region with the first N+ it is interval every The first P+ areas set, and formed and the 2nd P+ areas of interval setting of the 2nd N+ areas in the second groove;
Dielectric layer and metal level are sequentially formed on the surface of whole device.
2. according to the method described in claim 1, it is characterised in that pair be provided with initial oxide layer Semiconductor silicon substrate is carried out before photoetching and etching, in addition to:
In the environment of 900 degrees Celsius~1100 degrees Celsius, the shape on the surface of the semiconductor silicon substrate Into the initial oxide layer;
Wherein, the thickness of the initial oxide layer is 0.01 micron~0.20 micron.
3. according to the method described in claim 1, it is characterised in that sequentially formed on the whole device Gate oxide, polysilicon layer, including:
Gate oxide is formed in the N-type epitaxy layer and in the first groove, the second groove;
In the environment of 500 degrees Celsius~700 degrees Celsius, in the N-type epitaxy layer and described first The polysilicon layer is formed in groove, the second groove;
Wherein, the thickness of the polysilicon layer is 0.05 micron~2.0 microns.
4. according to the method described in claim 1, it is characterised in that described in the N-type epitaxy layer Middle formation P- bodies area, including:
Above from whole device, it is 1.0E13~1.0E15/squares that implantation dosage is injected into whole device Centimetre boron ion, energy be 80 kiloelectron-volts~120 kiloelectron-volts;
It is 900 degrees Celsius~1200 degrees Celsius that progress, which drives in temperature, and the time is 60 minutes~180 minutes P-type ion drive in, to form P- bodies areas in the N-type epitaxy layer.
5. according to the method described in claim 1, it is characterised in that the shape on the surface of the cellular region Into the first photoresist window, and form on the surface of the second groove spaced second photoresist Window, N is injected by the first photoresist window, the second photoresist window into whole device Type ion, to form the first N+ areas in the cellular region and the 2nd N+ areas formed in the second groove, Including:
The first photoresist layer is formed on the surface of whole device, photoetching is carried out to first photoresist layer, To form the first photoresist window on the surface of the cellular region, and on the surface of the second groove Form spaced second photoresist window;
By the first photoresist window, the second photoresist window injected into whole device phosphorus from Son, wherein, the implantation dosage of phosphonium ion is the boron ion of 1.0E15~1.0E16/square centimeter, energy For 100 kiloelectron-volts~150 kiloelectron-volts, to form the first N+ areas and described the in the cellular region The 2nd N+ areas are formed in two grooves;
Remove first photoresist layer.
6. according to the method described in claim 1, it is characterised in that the shape on the surface of the cellular region Into the 3rd photoresist window, and form on the surface of the second groove spaced 4th photoresist Window, P is injected by the 3rd photoresist window, the 4th photoresist window into whole device Type ion, to be formed and spaced first P+ areas of the 2nd N+ areas in the cellular region, and described Formed in second groove and be arranged at intervals the 2nd P+ areas with the 2nd N+ areas, including:
The second photoresist layer is formed on the surface of whole device, photoetching is carried out to second photoresist layer, To form the 3rd photoresist window on the surface of the cellular region, and on the surface of the second groove Form spaced 4th photoresist window;
By the 3rd photoresist window, the 4th photoresist window injected into whole device boron from Son, wherein, the implantation dosage of boron ion is the boron ion of 1.0E15~1.0E16/square centimeter, energy For 50 kiloelectron-volts~150 kiloelectron-volts, it is arranged at intervals with being formed in the cellular region with the first N+ areas The first P+ areas, and in the second groove formed with the 2nd N+ areas be arranged at intervals the 2nd P+ areas;
Remove second photoresist layer.
7. according to any described methods of claim 1-6, it is characterised in that described in whole device Surface forms dielectric layer, including:
Dielectric layer is formed on the surface of whole device, to the grid below the dielectric layer and the dielectric layer Oxide layer carries out photoetching and etching, to form the first contact hole on the cellular region and be tied in the ESD The second contact hole is formed in structure area;
Wherein, the dielectric layer is silicon dioxide layer.
8. method according to claim 7, it is characterised in that the width of first contact hole is big Width in the first P+ areas;
The width of second contact hole is less than the width of the second groove.
9. according to any described methods of claim 1-6, it is characterised in that described in whole device Forming metal layer on surface, including:
The metal of Al-Si-Cu alloy is grown on the surface of whole device by the way of sputtering;
Photoetching and etching are carried out to the Al-Si-Cu alloy, to form metal level, wherein, the metal level Maximum gauge be 0.01 micron~5.00 microns.
CN201610170343.1A 2016-03-23 2016-03-23 The preparation method of channel-type semiconductor device CN107230631A (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020056883A1 (en) * 2000-11-16 2002-05-16 Baliga Bantval Jayant Radio frequency (RF) power devices having faraday shield layers therein
US20100258853A1 (en) * 2009-04-10 2010-10-14 Wei-Chieh Lin Trench semiconductor device and method of making the same
US8084304B2 (en) * 2007-11-29 2011-12-27 Alpha & Omega Semiconductor, Inc. Method for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop
CN104347422A (en) * 2013-08-09 2015-02-11 上海华虹宏力半导体制造有限公司 Manufacturing method of groove type MOS (Metal Oxide Semiconductor) transistor with electrostatic discharge protection circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020056883A1 (en) * 2000-11-16 2002-05-16 Baliga Bantval Jayant Radio frequency (RF) power devices having faraday shield layers therein
US8084304B2 (en) * 2007-11-29 2011-12-27 Alpha & Omega Semiconductor, Inc. Method for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop
US20100258853A1 (en) * 2009-04-10 2010-10-14 Wei-Chieh Lin Trench semiconductor device and method of making the same
CN104347422A (en) * 2013-08-09 2015-02-11 上海华虹宏力半导体制造有限公司 Manufacturing method of groove type MOS (Metal Oxide Semiconductor) transistor with electrostatic discharge protection circuit

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