CN107229012A - Measurement jig and its arrangement method for testing pin hole - Google Patents
Measurement jig and its arrangement method for testing pin hole Download PDFInfo
- Publication number
- CN107229012A CN107229012A CN201710443285.XA CN201710443285A CN107229012A CN 107229012 A CN107229012 A CN 107229012A CN 201710443285 A CN201710443285 A CN 201710443285A CN 107229012 A CN107229012 A CN 107229012A
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- Prior art keywords
- test
- pin hole
- measurement jig
- integrated circuit
- tested
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The present invention is the arrangement method on measurement jig and its test pin hole.The measurement jig that one embodiment of the invention is provided is included：Testing base, it can test zone provided with the test pinhole definitions by array arrangement；It is described can test zone be configured to integrated circuit to be tested packaging body suitable for plurality of specifications；And test frame, it is configured to be mounted in the testing base so as to can further define a Validity Test region on test zone described, and the Validity Test region can test zone less than or equal to described in；The one kind of the Validity Test region suitable for the integrated circuit to be tested packaging body of the plurality of specifications.The embodiment of the present invention can test the integrated antenna package of the plurality of specifications with different pin number and layout, reduce testing cost.
Description
Technical field
The present invention relates to the arrangement method of semiconductor applications, more particularly to measurement jig and its test pin hole.
Background technology
In information age today, with the fast development of electronics industry, the product such as computer, mobile phone becomes increasingly popular.
Functional requirement of the people to electronic product is more and more, more and more stronger to performance requirement, and volume requirement is less and less, weight
It is required that more and more lighter.This just promotes electronic product to develop to multi-functional, high-performance and miniaturization, lightweight direction.To realize this
One target, the size of integrated circuit package body will be less and less, and complexity is continuously increased, then, the input/output of circuit
Port (I/O ports) will be more and more, and density will be continuously increased.In order to adapt to this demand for development, some advanced height
Density encapsulation technology is arisen at the historic moment, and for example (Ball Grid Array Package, hereinafter referred to as " BGA is sealed BGA Package
Dress ") and flip-chip (hereinafter referred to as " Flip chip ").
Integrated circuit package body after completion has to pass through open circuit/short circuit (hereinafter referred to as " O/S ") test before from factory, with true
Recognize its design function and indeed reach requirement.However, the quantity and layout of the pin of various sizes of integrated circuit package body
(layout) also differ.Therefore, in the prior art, in order to test various sizes of integrated circuit package body, it is necessary to be each
The integrated circuit package body for planting size designs a testing jig special, causes testing cost to remain high.
Thus, need badly offer it is a kind of can test the measurement jig of various sizes of integrated circuit package body, to reduce survey
Try cost.
The content of the invention
An object of the present invention is one measurement jig of offer, and it can be tested with different pin number and layout
Plurality of specifications integrated circuit package body, so as to reduce testing cost.
Another object of the present invention is to a kind of arrangement method for the multiple test pin holes for providing measurement jig.
According to one embodiment of the invention, a measurement jig, it is included：Testing base, it is provided with the survey by array arrangement
Try pinhole definitions can test zone；This can test zone be configured to suitable for plurality of specifications integrated circuit to be tested encapsulate
Body；And test frame, it is configured to be mounted in testing base so as to can further boundary on test zone
A fixed Validity Test region, the Validity Test region is less than or equal to can test zone；Validity Test region is applied to a variety of rule
One kind in the integrated circuit to be tested packaging body of lattice.
In another embodiment of the invention, testing base be provided with groove, can test zone be located at the groove；Test frame
It is configured to the part or all of test pin hole that embedded groove pluggablely and exposure can be in test zones；Testing base is provided with the
One mounting hole, test frame is provided with the first installation through-hole, and the first connector, which is configured to run through, inserts the after the first installation through-hole
One mounting hole is so that test frame is locked in testing base；Testing base is provided with the second mounting hole, and the second connector is configured
With after the second mounting hole insert printed substrate with by measurement jig locking on a printed-wiring board；First connector and/
Or second connector be screw；During the arrangement of multiple test pin holes is in the pin numbering increase of integrated antenna package to be tested
Heart divergence expression is arranged, wherein the pin of the integrated circuit package body to be tested corresponding to the test pin hole closer to central area
Numbering is smaller；Can test zone and Validity Test region be square, multiple test pin holes are surveyed with the center one positioned at square
Test point hole is arranged in left-handed or dextrorotation, or with the central area of square at least two test pin holes around the center of square
Arranged in left-handed or dextrorotation；The integrated circuit to be tested packaging body of plurality of specifications is with the to be tested integrated of different pin numbers
Circuit package.
Another embodiment of the present invention additionally provides the arrangement method of the test pin hole of a measurement jig, and it is included：
The specification of integrated circuit package body to be tested is determined, including determines the pin of integrated circuit package body to be tested
Quantity；
Line number and columns according to needed for identified pin number determines test pin hole arrangement, wherein line number and columns phase
Together, and by line number and columns the quantity of the test pin hole defined is more than or equal to pin number；
According to determine test pin hole line number and columns determine square can test zone；
When institute's line number and columns are odd number, by can be where the central point of test zone test pin hole numbering be 1, and enclose
Select closest another test pin hole spiral successively by mode clockwise or counterclockwise around the test pin hole where central point
Be numbered so that can test zone test pin hole in center divergence expression arrange；
When line number and columns are even number, by can be where the central area of test zone four test pin holes in it is adjacent
Both number consecutivelies are 1,2, and around can the central point of test zone by mode clockwise or counterclockwise select closest another
Two test pin holes be spirally numbered successively so that can test zone test pin hole in center divergence expression arrangement.
In another embodiment of the invention, measurement jig is test noted above tool.
Measurement jig provided in an embodiment of the present invention and its arrangement method for testing pin hole, can test and draw with different
The integrated antenna package of the plurality of specifications of pin quantity and layout.Compared to the integrated antenna package that conventional art is each size
A testing jig special is designed, testing cost can be greatly reduced in measurement jig provided in an embodiment of the present invention.
Brief description of the drawings
It is the floor map of measurement jig according to an embodiment of the invention shown in Fig. 1
It is the floor map of the testing base of measurement jig in Fig. 1 shown in Fig. 2
It is the floor map of the framework of measurement jig in Fig. 1 shown in Fig. 3
It is the cross sectional schematic diagram of measurement jig according to an embodiment of the invention when in use shown in Fig. 4
It is the plane signal of the arrangement method of multiple testing needles of measurement jig according to an embodiment of the invention shown in Fig. 5
Figure
Embodiment
Spirit for a better understanding of the present invention, makees furtherly below in conjunction with the part preferred embodiment of the present invention to it
It is bright.
It is the floor map of measurement jig 100 according to an embodiment of the invention shown in Fig. 1.In shown in Fig. 2 being Fig. 1
The floor map of the testing base 10 of measurement jig 100.It is the test frame 14 of the measurement jig 100 in Fig. 1 shown in Fig. 3
Floor map.
Specifically, as Figure 1-3, measurement jig 100 includes testing base 10 and test frame 14.Testing base 10
Be provided with groove 101, be provided with the groove 101 by multiple test pin holes 20 of array arrangement define can test zone 102, this
This in embodiment can test zone 102 for square.All or part of test pin hole 20 in the plurality of test pin hole 20 can
It is correspondingly arranged with the pin 32 (referring to Fig. 4) of the integrated circuit package body 30 to be tested of sizes, for example, can covers ability
Domain fertile maximum sized integrated circuit package body 30 and minimum dimension integrated circuit package body 30.Test frame 14
It is configured to be mounted in testing base 10 further define a Validity Test area on test zone 102
Domain 120, Validity Test region 120 is less than or equal to can test zone 102, and the correspondence plurality of specifications of Validity Test region 120
One kind in integrated circuit to be tested packaging body 30.Similar, the Validity Test of this in the present embodiment region 120 is square.
Test pin hole in other words, the test pin hole 20 in testing base 10 is for including maximum specification integrated electricity to be tested
The integrated circuit to be tested packaging body 30 of plurality of specifications including road packaging body 30 is provided can test zone 102, and test frame
14 define Validity Test region 120 further directed to specific test object, when the integrated circuit package body of test maximum specification
When 30, this can test zone 102 it is identical with the Validity Test region 120.In the present embodiment, " the collection to be tested of plurality of specifications
Into circuit package " it is the integrated circuit to be tested packaging body with different pin numbers.It is preferred that, the plurality of test pin hole 20
Arrangement with the pin numbering increase of integrated circuit package body 30 to be tested in the arrangement of center divergence expression, i.e. more central area
The pin numbering of integrated circuit package body 30 to be tested corresponding to test pin hole 20 is smaller.Specific diffusion mode has many
Kind, for example when can test zone 102 and Validity Test region 120 for square when, multiple test pin holes 20 are with positioned at square
The test pin hole 20 of center one arranged in left-handed or dextrorotation, or with least two test pin hole 20 in the central area of square
Around the center of square in left-handed or dextrorotation arrangement (for details, reference can be made to Fig. 5).The different test frame 14 of test pin hole can have
Identical exterior contour 145 and various sizes of opening 141, to ensure that different test frames 14 can be arranged on same test
It can be adapted on base 10 and with various sizes of integrated circuit to be tested packaging body 30 exterior contour 39 and engage it
In on test frame 14.The numbering of each testing needle 16 (referring to Fig. 4) used in test is corresponding with the numbering for testing pin hole 20,
It can be configured to be electrically connected to the corresponding of integrated circuit package body 30 to be tested by the test pin hole 20 being correspondingly arranged
Pin 32 is with to the progress electrical testing of integrated circuit package body 30.
Test frame 14 is configured to embedded groove 101 pluggablely, and the opening 141 of test frame 14 is configured to survey
The part or all of test pin hole 20 that exposure can be in test zone 102 during the examination insertion groove 101 of framework 14 is so as to defining effective survey
Try region 120.
The first mounting hole 103 can be further provided with testing base 10, test frame 14 is provided with the first installation through-hole 143,
First connector 50 is configured to insert the first mounting hole 103 to lock test frame 14 after running through the first installation through-hole 143
In the groove 101 of testing base 10.Testing base 10 can also be provided with the second mounting hole 105, and the second connector 52 is configured to
Test is inserted after the second mounting hole 105 with printed circuit board (PCB) 80 (PCB, Printed Circuit Board) to test
Tool 100 is locked on a printed circuit.In the present embodiment, the first connector 50 and the second connector 52 can be screws, its
In its embodiment, the first connector 50 and the second connector 52 are further selected from its with connection locking effect commonly used in the art
Its part.
It is the cross sectional schematic diagram of measurement jig 100 according to an embodiment of the invention when in use shown in Fig. 4
Specifically, when being tested using the measurement jig 100, being selected according to the specification of integrated circuit package body 30 to be tested
Fixed required test frame 14, run through using the first connector 50 after the first installation through-hole 143 insert the first mounting hole 103 with incite somebody to action
Test frame 14 is locked in the groove 101 of testing base 10, and testing base 10 is locked in into survey by the second connector 52
On printed circuit board (PCB) on probation, so that corresponding to the quantity and layout (layout) of the pin 32 of integrated circuit to be tested packaging body 30
Testing needle 16 stretch out the test pin hole 20 in the Validity Test region 120 defined by test frame 14, so as to further be electrically connected
Connect the pin 32 of corresponding integrated circuit to be tested packaging body 30.Pin hole is tested when integrated circuit package body 30 to be tested is survey
When trying the full-size designed by tool 100, whole test pin holes 20 that can be in test zone 102 of testing base 10 are tested
The opening 141 of examination framework 14 exposes, so as to be corresponded with the pin 32 of integrated circuit package body 30 to be tested；And with treating
The size of the integrated circuit package body 30 of test reduces, and the amount of the test pin hole 20 in required Validity Test region 120 is also got over
Come fewer.
It can be seen that, measurement jig 100 provided in an embodiment of the present invention can be encapsulated according to the integrated circuit to be tested of different size
Body 30 uses different test frames 14, and the measurement jig 100 different without being provided separately is tested into so as to effectively reduction
This.
The embodiment of the present invention additionally provides the arrangement method test pin hole of the test pin hole of measurement jig 100.
In one embodiment of this invention, this method is included：
The specification of integrated circuit package body 30 to be tested is first determined, including determines integrated circuit package body 30 to be tested
Pin 32 quantity.
According to needed for the pin number of identified integrated circuit package body 30 to be tested determines that test pin hole 20 is arranged
Line number and columns, the line number is identical with columns, and the quantity of test pin hole 20 that the line number and columns are defined need to be more than or equal to
The quantity of the pin 32 of integrated circuit package body 30 to be tested.Line number and columns according to test pin hole is determined determine square
Shape can test zone 102.
When the line number or columns are odd number, by the test where central point square determined by the line number or columns
The numbering of pin hole 20 is 1 (other embodiments can be compiled as 0 or other set lowest number), and around the survey where the central point
Test point hole 20, selects closest another test pin hole 20 to be spirally numbered successively by mode clockwise or counterclockwise, from
And make can test zone 102 test pin hole 20 in center divergence expression arrange.
And when the line number or columns are even number, by four test pin holes that can be where the central area of test zone 102
Both adjacent number consecutivelies in 20 are 1,2 (other embodiments can be compiled as 0,1 or other set lowest number), and around this
The central point of square selects closest another two to test by mode clockwise or counterclockwise, and pin hole 20 is spiral successively to be carried out
Numbering so that can test zone 102 test pin hole 20 in center divergence expression arrangement.
As skilled in the art to understand, above-mentioned square central diffusion type arrangement is being preferable to carry out for the present invention
Example, this area can make certain change or adjustment according to above-mentioned teaching, do not depart from so above-mentioned teaching central diffusion type arrangement or
Substantial central diffusion type arrangement, such as rectangle, circle, such as its nucleus are arranged in above-mentioned square center diffusion type
Cloth all should be within protection scope of the present invention.
It is that the arrangement method of the test pin hole 20 of measurement jig 100 according to an embodiment of the invention is obtained shown in Fig. 5
The floor map that test pin hole 20 in Validity Test region 120 is arranged.
Specifically, in the present embodiment, the specification of integrated circuit package body 30 to be tested is 8*8 flip-chip, i.e.
The quantity of pin 32 is 8*8=64.
According to the quantity of the pin 32 determine the test pin hole 20 that can be on test zone 102 of measurement jig 100 be expert at and
Quantity on row is 8, i.e. even number.Choose four test pin holes that can be where the central area of test zone 102 of square
In 20 it is adjacent both, the thicker frames for example chosen in two tests pin hole 20, i.e. Fig. 5 being located on the left of central area are square
In outline four test pin holes 20 of shape it is adjacent both from the bottom to top number consecutively be 1,2, and around the square central point
Select closest another two test pin hole 20 that (the dextrorotation dotted line in such as Fig. 5 is spirally numbered successively by clock-wise fashion
Shown clockwise direction), it is 3,4,5,6 ... 64 to mark each to test pin hole 20.Each square frame shown in Fig. 5 is only used for representing
The quantity and layout (layout) of multiple test pin holes 20, are not used to limit the spies such as concrete shape, the size of test pin hole 20
Property.And sequence number 1 in the square frame shown in Fig. 5,2,3 ... 64 be only explanation test pin hole 20 sequence, be not used to mark
The reference of element.
Multiple testing needles 16 of measurement jig 100 are arranged successively by above-mentioned mark is ascending, can make to be located at centre bit
The test pin hole 20 put is preferentially used for testing needle 16 with the electric connection of corresponding pin 32 to carry out integrated circuit package body 30
O/S is tested, so that it is guaranteed that when changing various sizes of test frame 14 in testing base 10, testing needle 16 can have
Sequence it is arranged in the Validity Test region 120 defined by test frame 14, passes through the test pin hole in Validity Test region 120
20 are electrically connected with to realize the test to integrated circuit package body 30 with pin 32.
The technology contents and technical characterstic of the present invention have revealed that as above, but those skilled in the art still may base
Make a variety of replacements and modification without departing substantially from spirit of the present invention in teachings of the present invention and announcement.Therefore, protection model of the invention
The content disclosed in embodiment should be not limited to by enclosing, and should include various replacements and modification without departing substantially from the present invention, and be this patent
Application claims are covered.
Claims (10)
1. a kind of measurement jig, it is included：
Testing base, it can test zone provided with the test pinhole definitions by array arrangement；It is described can test zone be configured
With the integrated circuit to be tested packaging body suitable for plurality of specifications；And
Test frame, its be configured to be mounted in the testing base so as to it is described can test zone enterprising one
Step defines a Validity Test region, and the Validity Test region can test zone less than or equal to described in；The Validity Test area
The one kind of domain suitable for the integrated circuit to be tested packaging body of the plurality of specifications.
2. measurement jig according to claim 1, wherein the testing base is provided with groove, it is described can test zone be located at
The groove；The test frame be configured to the embedded groove pluggablely and exposure it is described can be in test zone it is described
Partly or entirely test pin hole.
3. measurement jig according to claim 1, wherein the testing base is provided with the first mounting hole, the test frame
Provided with the first installation through-hole, the first connector be configured to run through first installation through-hole after insert first mounting hole with
The test frame is locked in the testing base.
4. measurement jig according to claim 3, wherein the testing base is provided with the second mounting hole, the second connector warp
Configure to insert printed substrate after second mounting hole measurement jig being locked in the printed substrate
On.
5. measurement jig according to claim 4, wherein first connector and/or second connector are spiral shell
Nail.
6. measurement jig according to claim 1, wherein the arrangement of the multiple test pin hole is with integrated electricity to be tested
The pin numbering increase of road encapsulation is in the arrangement of center divergence expression, wherein to be measured corresponding to pin hole closer to testing for central area
The pin numbering of the integrated circuit package body of examination is smaller.
7. measurement jig according to claim 6, wherein it is described can test zone and the Validity Test region be pros
Shape, the multiple test pin hole to be arranged positioned at the square test pin hole of center one in left-handed or dextrorotation, or with positioned at
At least two test pin holes are arranged around the square center in left-handed or dextrorotation in the square central area.
8. measurement jig according to claim 1, wherein the integrated circuit to be tested packaging body of the plurality of specifications is tool
There is the integrated circuit to be tested packaging body of different pin numbers.
9. a kind of arrangement method of the test pin hole of measurement jig, it is included：
The specification of integrated circuit package body to be tested is determined, including determines the pin of the integrated circuit package body to be tested
Quantity；
Line number and columns according to needed for identified pin number determines test pin hole arrangement, wherein the line number and columns phase
Together, and by the line number and columns the quantity of the test pin hole defined is more than or equal to the pin number；
According to determine test pin hole line number and columns determine square can test zone；
It is 1 by the test pin hole numbering that can be where the central point of test zone when the line number and columns are odd number, and
Around the test pin hole where the central point closest another test pin hole is selected by mode clockwise or counterclockwise successively
Spirally be numbered so that it is described can test zone test pin hole in center divergence expression arrange；
When the line number and columns are even number, by four test pin holes that can be where the central area of test zone
Both adjacent number consecutivelies are 1,2, and around it is described can the central point of test zone selected most by mode clockwise or counterclockwise
Neighbouring another two test pin hole is spirally numbered successively so that it is described can test zone test pin hole in center hair
Dissipate formula arrangement.
10. arrangement method according to claim 9, wherein the measurement jig is test according to claim 1
Tool.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710443285.XA CN107229012A (en) | 2017-06-13 | 2017-06-13 | Measurement jig and its arrangement method for testing pin hole |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710443285.XA CN107229012A (en) | 2017-06-13 | 2017-06-13 | Measurement jig and its arrangement method for testing pin hole |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107229012A true CN107229012A (en) | 2017-10-03 |
Family
ID=59935858
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710443285.XA Pending CN107229012A (en) | 2017-06-13 | 2017-06-13 | Measurement jig and its arrangement method for testing pin hole |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107229012A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114778902A (en) * | 2022-06-27 | 2022-07-22 | 武汉永鼎光通科技有限公司 | PCBA adds electric testing arrangement and prevents to cross anchor clamps of inserting |
| CN117673046A (en) * | 2024-01-31 | 2024-03-08 | 深圳市航瑞芯科技有限公司 | Integrated circuit package and detection device |
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| TW200823459A (en) * | 2006-11-30 | 2008-06-01 | Global Master Tech Co Ltd | Multifunctional adjustable tester |
| CN201319056Y (en) * | 2008-09-23 | 2009-09-30 | 陈涛 | Universal switching device and universal fixture used for special testing machine for testing circuit board |
| CN201508403U (en) * | 2009-06-29 | 2010-06-16 | 自然兴电通科技股份有限公司 | General-purpose fixture for tester of printed circuit board |
| CN201508399U (en) * | 2009-07-31 | 2010-06-16 | 陈涛 | Testing jig of tester special for testing wiring board |
| CN206863173U (en) * | 2017-06-13 | 2018-01-09 | 日月光封装测试(上海)有限公司 | Measurement jig |
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2017
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200823459A (en) * | 2006-11-30 | 2008-06-01 | Global Master Tech Co Ltd | Multifunctional adjustable tester |
| CN201319056Y (en) * | 2008-09-23 | 2009-09-30 | 陈涛 | Universal switching device and universal fixture used for special testing machine for testing circuit board |
| CN201508403U (en) * | 2009-06-29 | 2010-06-16 | 自然兴电通科技股份有限公司 | General-purpose fixture for tester of printed circuit board |
| CN201508399U (en) * | 2009-07-31 | 2010-06-16 | 陈涛 | Testing jig of tester special for testing wiring board |
| CN206863173U (en) * | 2017-06-13 | 2018-01-09 | 日月光封装测试(上海)有限公司 | Measurement jig |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114778902A (en) * | 2022-06-27 | 2022-07-22 | 武汉永鼎光通科技有限公司 | PCBA adds electric testing arrangement and prevents to cross anchor clamps of inserting |
| CN117673046A (en) * | 2024-01-31 | 2024-03-08 | 深圳市航瑞芯科技有限公司 | Integrated circuit package and detection device |
| CN117673046B (en) * | 2024-01-31 | 2024-05-14 | 深圳市航瑞芯科技有限公司 | Detection device for integrated circuit package |
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Effective date of registration: 20210105 Address after: No. 669, GuoShouJing Road, Pudong New Area pilot Free Trade Zone, Shanghai, 201203 Applicant after: Rirong semiconductor (Shanghai) Co.,Ltd. Address before: 6th floor, no.669 GuoShouJing Road, Pudong New Area pilot Free Trade Zone, Shanghai 201203 Applicant before: ASE ASSEMBLY & TEST (SHANGHAI) Ltd. |
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