CN107204748A - Operational amplification circuit - Google Patents
Operational amplification circuit Download PDFInfo
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- CN107204748A CN107204748A CN201710470056.7A CN201710470056A CN107204748A CN 107204748 A CN107204748 A CN 107204748A CN 201710470056 A CN201710470056 A CN 201710470056A CN 107204748 A CN107204748 A CN 107204748A
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- 230000003321 amplification Effects 0.000 title claims abstract description 87
- 238000003199 nucleic acid amplification method Methods 0.000 title claims abstract description 87
- 230000000694 effects Effects 0.000 claims description 19
- 230000005669 field effect Effects 0.000 claims description 5
- 102100027241 Adenylyl cyclase-associated protein 1 Human genes 0.000 description 6
- 108010077333 CAP1-6D Proteins 0.000 description 6
- 108010031970 prostasin Proteins 0.000 description 6
- 230000005611 electricity Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45112—Indexing scheme relating to differential amplifiers the biasing of the differential amplifier being controlled from the input or the output signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45354—Indexing scheme relating to differential amplifiers the AAC comprising offset means
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45586—Indexing scheme relating to differential amplifiers the IC comprising offset generating means
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
The invention discloses a kind of operational amplification circuit, amplify sub-circuit including the first order, amplify the compensating electric capacity that sub-circuit is connected with the first order, the second level amplification sub-circuit being connected with the compensating electric capacity, the current offset sub-circuit being connected with first order amplification sub-circuit and second level amplification sub-circuit and the biased electrical pressure side being connected with the current offset sub-circuit, the first order amplification sub-circuit receives the differential signal of input and the second level amplification sub-circuit is sent to after being amplified, high gain is provided for the operational amplification circuit, the second level amplification sub-circuit is exported after being amplified to the signal received, enough output voltage swings are provided for the operational amplification circuit, the compensating electric capacity controls the loop stability of the operational amplification circuit, and influence the startup time of the operational amplification circuit.The startup time of operational amplification circuit can be brought up to nanosecond by the present invention.
Description
Technical field
It is more particularly to a kind of to realize the operational amplification circuit quickly started the present invention relates to integrated circuit fields.
Background technology
Operational amplification circuit is the indispensable module of numerous systems in the design of chip, in some special application systems
In system, there is very high requirement for the startup time of operational amplification circuit, therefore, it is possible to realize that quick start just seems particularly heavy
Will.
The stabilization of loop is generally reached using miller-compensated technology to two-stage calculation amplifying circuit in the art existing,
But charged for excessive miller-compensated electric capacity, the increase that amplifier starts the time is result in, this kind of fortune is even more limited
Calculate use of the amplifying circuit in quick startup structure.
Therefore, it is necessary to provide a kind of operational amplification circuit that can be realized and quickly start.
The content of the invention
It is an object of the invention to overcome the deficiencies of the prior art and provide a kind of operation amplifier that can be realized and quickly start
Circuit.
The purpose of the present invention is achieved through the following technical solutions：A kind of operational amplification circuit, including the first order are put
Big sub-circuit, the compensating electric capacity being connected with first order amplification sub-circuit, the second level being connected with the compensating electric capacity are amplified
Sub-circuit, amplify with the first order sub-circuit and second level amplification sub-circuit is connected be used for for the operation amplifier it is electric
Road the current offset sub-circuit of bias current is provided and be connected with the current offset sub-circuit for the operational amplification circuit
The biased electrical pressure side of bias voltage is provided, the first order amplification sub-circuit receives the differential signal of input and passed after being amplified
The second level amplification sub-circuit is delivered to, high gain is provided for the operational amplification circuit, sub-circuit is amplified in the second level
Exported after being amplified to the signal received, enough output voltage swings, the compensation electricity are provided for the operational amplification circuit
Hold the loop stability of the control operational amplification circuit, and influence the startup time of the operational amplification circuit.
Second effect that the first order amplification sub-circuit includes the first FET, is connected with first FET
Ying Guan, the 3rd FET, the 4th FET being connected with the 3rd FET, it is first FET, described
Second FET, the 3rd FET and the 4th FET have collectively constituted the first of Foldable cascade
Level amplification sub-circuit；The second level amplification sub-circuit includes the 5th FET；The current offset sub-circuit includes the 6th
FET, the 7th FET, the 8th FET, the 9th FET and the institute being connected with the 7th FET
State the tenth connected FET of the 9th FET, the 11st FET being connected with the 9th FET and institute
State the 12nd connected FET of the tenth FET, the 13rd FET being connected with the 7th FET and
The 14th connected FET of 3rd FET, the 15th FET being connected with the 4th FET,
The 16th FET being connected with the 8th FET and the compensating electric capacity and be connected with the compensating electric capacity
17 FETs；The biased electrical pressure side include the first biased electrical pressure side, the second biased electrical pressure side, the 3rd biased electrical pressure side and
4th biased electrical pressure side.
The grid of the grid of first FET and second FET receives the differential signal of input respectively,
The source electrode of first FET is connected the drain electrode of the 6th FET with the source electrode of second FET jointly,
The drain electrode of first FET is connected with the drain electrode of the source electrode and the 15th FET of the 4th FET；
The drain electrode of second FET is connected with the drain electrode of the source electrode and the 14th FET of the 3rd FET.
Grid, the grid of the 4th FET, the grid of the 7th FET of 3rd FET
And the grid of the 8th FET connects the first biased electrical pressure side, the drain electrode of the 3rd FET and institute jointly
State the draining of the 7th FET, the grid of the 9th FET, the grid and the described tenth of the tenth FET
The drain electrode of one FET is connected.
The drain electrode of 4th FET and grid, the drain electrode of the 8th FET of the 5th FET
And the drain electrode of the 12nd FET is connected；The grid of 6th FET and the second biased electrical pressure side phase
Even；The source electrode of 7th FET is connected with the drain electrode of the 13rd FET.
The source electrode of 8th FET is connected the compensating electric capacity jointly with the drain electrode of the 16th FET
One end；The drain electrode of 9th FET is connected with the source electrode of the 11st FET；Tenth FET
Drain electrode be connected with the source electrode of the 12nd FET；The grid of 11st FET and described 12nd effect
Should the grid of pipe connect the 3rd biased electrical pressure side jointly.
Grid, the grid of the 14th FET, the 15th FET of 13rd FET
Grid, the grid of the 16th FET and the grid of the 17th FET connect the 4th biasing jointly
Voltage end；The other end of the draining of 5th FET, the drain electrode of the 17th FET and the compensating electric capacity
Common connection output end.
Source electrode, the source electrode of the 6th FET, the source electrode of the 9th FET of 5th FET
And the source electrode of the tenth FET connects power end jointly；The source electrode of 13rd FET, described 14th
The source electrode of effect pipe, the source electrode of the 15th FET, the source electrode of the 16th FET and described 17th
The source electrode of effect pipe connects ground terminal jointly.
First FET, second FET, the 5th FET, the 6th FET,
9th FET, the tenth FET, the 11st FET, the 12nd FET are p-type
FET, the 3rd FET, the 4th FET, the 7th FET, the 8th FET,
13rd FET, the 14th FET, the 15th FET, the 16th FET,
17th FET is N-type FET.
The beneficial effects of the invention are as follows：The startup time of operational amplification circuit can be brought up to nanosecond, be that computing is put
Big circuit is applied in quick start system provide a solution.
Brief description of the drawings
Fig. 1 is the structured flowchart of operational amplification circuit of the present invention；
Fig. 2 is the particular circuit configurations figure of operational amplification circuit of the present invention.
Embodiment
Technical scheme is described in further detail below in conjunction with the accompanying drawings, but protection scope of the present invention is not limited to
It is as described below.
As shown in figure 1, operational amplification circuit of the present invention includes first order amplification sub-circuit, amplifies sub-circuit phase with the first order
Compensating electric capacity even, the second level being connected with compensating electric capacity amplification sub-circuit and the first order amplify sub-circuit and the second level is amplified
The connected current offset sub-circuit of sub-circuit and the biased electrical pressure side being connected with current offset sub-circuit.
Wherein, first order amplification sub-circuit is used to receive the differential signal of input and be sent to the second level after being amplified to put
Big sub-circuit, high gain is provided for operational amplification circuit, after second level amplification sub-circuit is amplified to the signal received
Output, enough output voltage swings are provided for operational amplification circuit, and compensating electric capacity is used for the loop stability for controlling operational amplification circuit
Property, and the startup time of operational amplification circuit is affected, current offset sub-circuit is used to provide biased electrical for operational amplification circuit
Stream, biased electrical pressure side provides bias voltage for operational amplification circuit.
Please refer to Fig. 2, Fig. 2 is the particular circuit configurations figure of operational amplification circuit of the present invention.In the present invention, first
Level amplification sub-circuit includes the first FET M1, the second FET M2 being connected with the first FET M1, the 3rd effect
Should pipe M3, the 4th FET M4 that is connected with the 3rd FET M3, the first FET M1, the second FET M2,
Three FET M3 and the 4th FET M4 have collectively constituted the first order amplification sub-circuit of Foldable cascade, wherein,
First FET M1 and the second FET M2 be Differential Input to pipe, the differential signal for receiving input；Compensating electric capacity
For compensating electric capacity CAP1；Second level amplification sub-circuit includes the 5th FET M5；Current offset sub-circuit includes the 6th effect
Should pipe M6, the 7th FET M7, the 8th FET M8 being connected with the 7th FET M7, the 9th FET M9, with
Connected 9th FET M9 the tenth FET M10, the 11st FET M11 being connected with the 9th FET M9,
The 12nd FET M12 being connected with the tenth FET M10, the 13rd FET being connected with the 7th FET M7
M13, the 14th FET M14 being connected with the 3rd FET M3, the 15th be connected with the 4th FET M4 effect
Should pipe M15, with the 8th FET M8 and compensating electric capacity CAP1 the 16th FET M16 being connected and with compensating electric capacity CAP1
The 17th connected FET M17；Biased electrical pressure side includes the first biased electrical pressure side VB1, the second biased electrical pressure side VB2, the
Three biased electrical pressure side VB3 and the 4th biased electrical pressure side VB4.
The physical circuit annexation of operational amplification circuit of the present invention is as follows：First FET M1 grid and second
Effect pipe M2 grid receives differential signal INP, INN of input, the first FET M1 source electrode and the second field-effect respectively
Pipe M2 source electrode connects the 6th FET M6 drain electrode jointly, and the first FET M1 drain electrode is with the 4th FET M4's
Source electrode and the 15th FET M15 drain electrode are connected；Second FET M2 drain electrode and the 3rd FET M3 source electrode
Drain electrode with the 14th FET M14 is connected；3rd FET M3 grid, the 4th FET M4 grid, the 7th
FET M7 grid and the 8th FET M8 grid connect the first biased electrical pressure side VB1, the 3rd FET jointly
M3 drain electrode and the 7th FET M7 drain electrode, the 9th FET M9 grid, the tenth FET M10 grid and the
11 FET M11 drain electrode is connected；4th FET M4 drain electrode and the 5th FET M5 grid, the 8th effect
Should pipe M8 drain electrode and the 12nd FET M12 drain electrode be connected；6th FET M6 grid and the second bias voltage
VB2 is held to be connected；7th FET M7 source electrode is connected with the 13rd FET M13 drain electrode；8th FET M8's
Source electrode and the common one end for being connected compensating electric capacity CAP1 of the 16th FET M16 drain electrode；9th FET M9 drain electrode
It is connected with the 11st FET M11 source electrode；Tenth FET M10 drain electrode and the 12nd FET M12 source electrode
It is connected；11st FET M11 grid is connected the 3rd biased electrical pressure side jointly with the 12nd FET M12 grid
VB3；13rd FET M13 grid, the 14th FET M14 grid, the 15th FET M15 grid,
16th FET M16 grid and the 17th FET M17 grid connect the 4th biased electrical pressure side VB4 jointly；The
Five FET M5 drain electrode, the 17th FET M17 drain electrode and the compensating electric capacity CAP1 other end connects output jointly
Hold OUT；5th FET M5 source electrode, the 6th FET M6 source electrode, the 9th FET M9 source electrode and the tenth
Effect pipe M10 source electrode connects power end ACDD jointly；13rd FET M13 source electrode, the 14th FET M14
Source electrode, the 15th FET M15 source electrode, the 16th FET M16 source electrode and the 17th FET M17 source electrode
Common connection ground terminal AGND.
Wherein, in the present embodiment, the first FET M1, the second FET M2, the 5th FET M5, the 6th
Effect pipe M6, the 9th FET M9, the tenth FET M10, the 11st FET M11, the 12nd FET M12 are
P-type FET, the 3rd FET M3, the 4th FET M4, the 7th FET M7, the 8th FET M8, the tenth
Three FET M13, the 14th FET M14, the 15th FET M15, the 16th FET M16, the 17th
Effect pipe M17 is N-type FET, in other embodiments, and above-mentioned FET be able to can be realized identical for other structures
The component of function, however it is not limited to this.
The operation principle of operational amplification circuit of the present invention is as follows：
Differential signal INP, INN are separately input into the first FET M1 and second effect in first order amplification sub-circuit
Should pipe M2, the bias current needed for the whole circuit of current offset sub-circuit generation, to ensure the field-effect in operational amplification circuit
Guan Jun works in normal zone of saturation, the first FET M1, the second FET M2, the 3rd FET M3 and the 4th effect
Should pipe M4 constitute folding cascade the first order amplification sub-circuit, input differential signal by the first order amplification son electricity
Road is exported after being amplified with second level amplification sub-circuit by output end OUT.First order amplification sub-circuit is operational amplification circuit
There is provided high gain, compensating electric capacity CAP1 improves loop stability, while affecting the startup time of whole circuit, second
Level amplification sub-circuit provides enough output voltage swings for operational amplification circuit.
Operational amplification circuit of the present invention is by the input pattern of differential pair tube, while improving electricity using electric current folding
The output voltage swing of pressure, isolates the coupled capacitor path of Compensation Feedback, then lead on the common grid end of folding two identical roads in parallel
Bias current sources drain terminal of the overcompensation electric capacity from output coupling to folding carrys out the phase margin of compensation loop, this compensation way
Compensating electric capacity is much smaller compared to miller-compensated electric capacity, and charging rate is fast, so as to reach the purpose quickly started.
In summary, the startup time of operational amplification circuit can be brought up to nanosecond by operational amplification circuit of the present invention,
It is applied in quick start system provide a solution for operational amplification circuit.
Claims (9)
1. a kind of operational amplification circuit, it is characterised in that：The operational amplification circuit include the first order amplification sub-circuit, with it is described
The connected compensating electric capacity of first order amplification sub-circuit, the second level being connected with the compensating electric capacity amplify sub-circuit and described the
What one-level amplification sub-circuit was connected with second level amplification sub-circuit is used to provide bias current for the operational amplification circuit
Current offset sub-circuit and be connected with the current offset sub-circuit provide bias voltage for the operational amplification circuit
Biased electrical pressure side, the first order amplification sub-circuit receives the differential signal of input and is sent to the second level after being amplified
Amplify sub-circuit, high gain is provided for the operational amplification circuit, sub-circuit is amplified to the signal that receives in the second level
Exported after being amplified, enough output voltage swings are provided for the operational amplification circuit, the compensating electric capacity controls the computing
The loop stability of amplifying circuit, and influence the startup time of the operational amplification circuit.
2. operational amplification circuit according to claim 1, it is characterised in that：The first order amplification sub-circuit includes first
FET, the second FET being connected with first FET, the 3rd FET and the 3rd FET
The 4th connected FET, first FET, second FET, the 3rd FET and described
Four FETs have collectively constituted the first order amplification sub-circuit of Foldable cascade；The second level amplification sub-circuit includes
5th FET；The current offset sub-circuit includes the 6th FET, the 7th FET and the 7th field-effect
The 8th connected FET of pipe, the 9th FET, the tenth FET being connected with the 9th FET, with it is described
The 11st connected FET of 9th FET, the 12nd FET being connected with the tenth FET and institute
State the 13rd connected FET of the 7th FET, the 14th FET being connected with the 3rd FET and
The 15th connected FET of 4th FET, the be connected with the 8th FET and the compensating electric capacity
16 FETs and the 17th FET being connected with the compensating electric capacity；The biased electrical pressure side includes the first biased electrical
Pressure side, the second biased electrical pressure side, the 3rd biased electrical pressure side and the 4th biased electrical pressure side.
3. operational amplification circuit according to claim 2, it is characterised in that：The grid of first FET with it is described
The grid of second FET receives the differential signal of input, the source electrode of first FET and described second effect respectively
Should the source electrode of pipe connect the drain electrode of the 6th FET, the drain electrode of first FET and described 4th effect jointly
Should the drain electrode of source electrode and the 15th FET of pipe be connected；The drain electrode of second FET and described 3rd effect
Should the drain electrode of source electrode and the 14th FET of pipe be connected.
4. operational amplification circuit according to claim 3, it is characterised in that：It is the grid of 3rd FET, described
Connection is described jointly for the grid of the grid of 4th FET, the grid of the 7th FET and the 8th FET
First biased electrical pressure side, drain electrode and the draining of the 7th FET, the 9th field-effect of the 3rd FET
The drain electrode of the grid of pipe, the grid of the tenth FET and the 11st FET is connected.
5. operational amplification circuit according to claim 4, it is characterised in that：The drain electrode of 4th FET with it is described
The grid of 5th FET, the drain electrode of the 8th FET and the drain electrode of the 12nd FET are connected；It is described
The grid of 6th FET is connected with the second biased electrical pressure side；The source electrode and the described 13rd of 7th FET
The drain electrode of FET is connected.
6. operational amplification circuit according to claim 5, it is characterised in that：The source electrode of 8th FET with it is described
The drain electrode of 16th FET connects one end of the compensating electric capacity jointly；The drain electrode of 9th FET and described the
The source electrode of 11 FETs is connected；The drain electrode of tenth FET is connected with the source electrode of the 12nd FET；
The grid of 11st FET is connected the 3rd biased electrical pressure side jointly with the grid of the 12nd FET.
7. operational amplification circuit according to claim 6, it is characterised in that：The grid of 13rd FET, institute
State grid, the grid of the 15th FET, the grid of the 16th FET and the institute of the 14th FET
The grid for stating the 17th FET connects the 4th biased electrical pressure side jointly；It is the draining of 5th FET, described
The drain electrode of 17th FET and the other end of the compensating electric capacity connect output end jointly.
8. operational amplification circuit according to claim 7, it is characterised in that：It is the source electrode of 5th FET, described
The source electrode of the source electrode of 6th FET, the source electrode of the 9th FET and the tenth FET connects power supply jointly
End；The source electrode of 13rd FET, the source electrode of the 14th FET, the source of the 15th FET
The source electrode of pole, the source electrode of the 16th FET and the 17th FET connects ground terminal jointly.
9. operational amplification circuit according to claim 2, it is characterised in that：First FET, described second
Effect pipe, the 5th FET, the 6th FET, the 9th FET, the tenth FET, institute
The 11st FET, the 12nd FET are stated for p-type FET, the 3rd FET, described 4th
Effect pipe, the 7th FET, the 8th FET, the 13rd FET, the 14th field-effect
Pipe, the 15th FET, the 16th FET, the 17th FET are N-type FET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710470056.7A CN107204748A (en) | 2017-06-20 | 2017-06-20 | Operational amplification circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710470056.7A CN107204748A (en) | 2017-06-20 | 2017-06-20 | Operational amplification circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107204748A true CN107204748A (en) | 2017-09-26 |
Family
ID=59907103
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710470056.7A Pending CN107204748A (en) | 2017-06-20 | 2017-06-20 | Operational amplification circuit |
Country Status (1)
| Country | Link |
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| CN (1) | CN107204748A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108183691A (en) * | 2017-12-28 | 2018-06-19 | 上海贝岭股份有限公司 | Folded-cascode op amp |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6412706A (en) * | 1987-07-07 | 1989-01-17 | Nec Corp | Operational amplifier circuit |
| CN206041945U (en) * | 2016-09-14 | 2017-03-22 | 成都锐成芯微科技股份有限公司 | High power supply rejection ratio operational amplifier circuit |
| CN206878786U (en) * | 2017-06-20 | 2018-01-12 | 成都锐成芯微科技股份有限公司 | Operational amplification circuit |
-
2017
- 2017-06-20 CN CN201710470056.7A patent/CN107204748A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6412706A (en) * | 1987-07-07 | 1989-01-17 | Nec Corp | Operational amplifier circuit |
| CN206041945U (en) * | 2016-09-14 | 2017-03-22 | 成都锐成芯微科技股份有限公司 | High power supply rejection ratio operational amplifier circuit |
| CN206878786U (en) * | 2017-06-20 | 2018-01-12 | 成都锐成芯微科技股份有限公司 | Operational amplification circuit |
Non-Patent Citations (1)
| Title |
|---|
| MEYSAM AKBARI等: ""High Gain and High CMRR Two-Stage Folded Cascode OTA with Nested Miller Compensation"", 《JOURNAL OF CIRCUITS, SYSTEMS AND COMPUTERS》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108183691A (en) * | 2017-12-28 | 2018-06-19 | 上海贝岭股份有限公司 | Folded-cascode op amp |
| CN108183691B (en) * | 2017-12-28 | 2021-05-07 | 上海贝岭股份有限公司 | Folded cascode operational amplifier |
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Application publication date: 20170926 |