CN107203482A - It is a kind of to realize the method that VR chips adapt to different CPU - Google Patents
It is a kind of to realize the method that VR chips adapt to different CPU Download PDFInfo
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- CN107203482A CN107203482A CN201710418355.6A CN201710418355A CN107203482A CN 107203482 A CN107203482 A CN 107203482A CN 201710418355 A CN201710418355 A CN 201710418355A CN 107203482 A CN107203482 A CN 107203482A
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- chips
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- General Engineering & Computer Science (AREA)
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- Multi Processors (AREA)
Abstract
The present invention discloses a kind of method for realizing the different CPU of VR chips adaptation, is related to CPU power supply technique fields；VID order transfer links are set between different CPU and VR chips, the VID orders transfer link is connected using SVID buses, and the parallel increase CPLD chips in SVID buses, and CPLD receives VID orders, the VID orders that response VR chips are not supported, realize support of the VR chips to different CPU；The present invention can realize the support to different CPU processors on the premise of VR chips are not changed.
Description
Technical field
The present invention discloses a kind of method for realizing the different CPU of VR chips adaptation, is related to CPU power supply technique fields.
Background technology
Nowadays the development of computer processor technology is more and more faster, and the time of update is also shorter and shorter, causes periphery
The updating speed of chip is also more and more faster.And the power supply chip of one of peripheral components the most key to CPU supports, i.e. VR chips
Such as only it is to support different SVID orders to the means suitable difference of VR chips before and after often because of CPU, it is upgraded, with regard to carrying out VR cores
If piece is upgraded, then cost can be caused to greatly increase, be unfavorable for the saving of cost.The present invention proposes one kind and realizes that VR chips are fitted
The method for answering different CPU, can realize the support to different CPU processors on the premise of VR chips are not changed.
VR chips in the present invention refer to that the voltage powered for CPU adjusts chip.
SVID refers to the universal serial bus connected between CPU and VR chips, is that CPU enters using between VID orders and VR chips
The link of row communication.Pressure adjusting command is such as sent, VR chip registers is accessed, receives data that VR is sent etc..
The content of the invention
The present invention provides a kind of method for realizing the different CPU of VR chips adaptation, with spies such as simple and feasible, highly versatiles
Point, has broad application prospects.
Concrete scheme proposed by the present invention is：
It is a kind of to realize the method that VR chips adapt to different CPU：
VID order transfer links are set between different CPU and VR chips, and the VID orders transfer link uses SVID buses
Connection, and the parallel increase CPLD chips in SVID buses, CPLD receive VID orders, the VID that response VR chips are not supported
Order, realizes support of the VR chips to different CPU.
The VID orders that the different CPU VID orders to be sent are supported with VR chips are compared, and obtain both areas
Other data, the VID orders that VR chips are not supported are responded by CPLD programming realizations.
The CPLD chips respond CPU configuration order, and the process matched with the VID configuration orders is sent to VR chips
Order after conversion makes CPU correctly configure VR chips to VR chips.
The CPLD chips respond VID orders in the free time of SVID buses.
The CPLD chips do main equipment in use, first calculating SVID bus-free times, Yi Mianying when CPU accesses VR
Ring the proper communication of CPU and VR chips.
It is a kind of to realize the system that VR chips adapt to different CPU, including different CPU, VR chips and VID order transfer links,
VID order transfer links are set wherein between different CPU and VR chips, and the VID orders transfer link uses SVID
Bus is connected, and the parallel increase CPLD chips in SVID buses, and CPLD receives VID orders, and response VR chips are not supported
VID orders, realize support of the VR chips to different CPU.
The VID orders that the difference CPU VID orders to be sent are supported with VR chips in described system are compared,
Both distinguishes datas are obtained, the VID orders that VR chips are not supported are responded by CPLD programming realizations.
Usefulness of the present invention is：
The present invention provides a kind of method for realizing the different CPU of VR chips adaptation, sets VID to order between different CPU and VR chips
Transfer link is made, the VID orders transfer link is connected using SVID buses, and the parallel increase CPLD cores in SVID buses
Piece, CPLD receives VID orders, and support of the VR chips to different CPU is realized in the VID orders that response VR chips are not supported；Make
Different CPU can be responded before and after VR chip upgrades, cost is not only reduced, also allows for realizing and operates, before wide application
Scape.
Brief description of the drawings
The block schematic illustration of Fig. 1 present systems；
Fig. 2 the inventive method schematic flow sheets.
Embodiment
The present invention provides a kind of method for realizing the different CPU of VR chips adaptation：
VID order transfer links are set between different CPU and VR chips, and the VID orders transfer link uses SVID buses
Connection, and the parallel increase CPLD chips in SVID buses, CPLD receive VID orders, the VID that response VR chips are not supported
Order, realizes support of the VR chips to different CPU.
A kind of system for realizing the different CPU of VR chips adaptation is provided simultaneously, including different CPU, VR chips and VID orders turn
Change link,
VID order transfer links are set wherein between different CPU and VR chips, and the VID orders transfer link uses SVID
Bus is connected, and the parallel increase CPLD chips in SVID buses, and CPLD receives VID orders, and response VR chips are not supported
VID orders, realize support of the VR chips to different CPU.
With reference to accompanying drawing, the present invention will be further described.
With reference to Fig. 1, connected between CPU and VR chips by SVID buses, between CPLD parallel connection access CPU and VR chips；
When it is implemented, CPU can use Intel E7 series processors, VR chips can use the MP2955A of MPS companies, and CPLD can
Using Altera EPM1270, then specific response command is ICCMAX 0XC8H；
Different CPU or different are different for VID orders required between CPU, and the VID orders that VR chips are supported are
Fixed, CPLD realizes that the order do not supported only in response to VR chips, i.e. VID orders transfer link are total using SVID in the present invention
Line is connected, and the parallel increase CPLD chips in SVID buses, and CPLD receives VID orders, and response VR chips are not supported
VID orders, realize support of the VR chips to different CPU.
If the form of VID orders is inconsistent between wherein fruit CPU and VR chips, CPLD realizes turning for both sides' command format
Change, show that CPLD chips respond CPU configuration order, pass through association to what the transmission of VR chips and the VID configuration orders matched
Order after view conversion makes CPU correctly configure VR chips to VR chips.Above-mentioned protocol conversion only makes when needing configuration VR chips
With when only needing to obtain VR chip status without conversion, CPLD feeds back correct state directly in response to CPU request.
And CPLD chips respond VID orders in the free time of SVID buses, especially when CPLD configures VR chips,
CPLD chips do main equipment in use, first calculating SVID bus-free times when CPU accesses VR, in order to avoid influence CPU and VR cores
The proper communication of piece.
In addition, in the specific implementation can first by different CPU, the VID orders to be sent and VR chips be supported
VID orders are compared, and obtain both distinguishes datas, and the VID lives that VR chips are not supported are responded by CPLD programming realizations
Order, specifically can obtain the VID orders that VR chips are supported by checking databook or measuring the bracket signal of normal work.
It can be realized using the invention described above method and system on the premise of VR chips are not changed to different CPU processors
Support.
Claims (7)
1. a kind of realize the method that VR chips adapt to different CPU, it is characterized in that
VID order transfer links are set between different CPU and VR chips, and the VID orders transfer link uses SVID buses
Connection, and the parallel increase CPLD chips in SVID buses, CPLD receive VID orders, the VID that response VR chips are not supported
Order, realizes support of the VR chips to different CPU.
2. according to the method described in claim 1, it is characterized in that the difference CPU VID orders to be sent are supported with VR chips
VID orders be compared, obtain both distinguishes data, the VID that VR chips are not supported responded by CPLD programming realizations
Order.
3. method according to claim 1 or 2, it is characterized in that the CPLD chips respond CPU configuration order, to VR cores
Piece sends the order after conversion matched with the VID configuration orders to VR chips, CPU is correctly configured VR chips.
4. method according to claim 3, it is characterized in that the CPLD chips respond VID in the free time of SVID buses
Order.
5. method according to claim 4, it is characterized in that the CPLD chips do main equipment in use, first calculating CPU
SVID bus-free times when accessing VR, in order to avoid the proper communication of influence CPU and VR chips.
6. a kind of realize the system that VR chips adapt to different CPU, it is characterized in that being changed including different CPU, VR chips and VID orders
Link,
VID order transfer links are set wherein between different CPU and VR chips, and the VID orders transfer link uses SVID
Bus is connected, and the parallel increase CPLD chips in SVID buses, and CPLD receives VID orders, and response VR chips are not supported
VID orders, realize support of the VR chips to different CPU.
7. system according to claim 6, it is characterized in that the different CPU VID orders to be sent and VR chips institute
The VID orders of support are compared, and obtain both distinguishes datas, respond what VR chips were not supported by CPLD programming realizations
VID orders.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710418355.6A CN107203482A (en) | 2017-06-06 | 2017-06-06 | It is a kind of to realize the method that VR chips adapt to different CPU |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710418355.6A CN107203482A (en) | 2017-06-06 | 2017-06-06 | It is a kind of to realize the method that VR chips adapt to different CPU |
Publications (1)
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| CN107203482A true CN107203482A (en) | 2017-09-26 |
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| CN201710418355.6A Pending CN107203482A (en) | 2017-06-06 | 2017-06-06 | It is a kind of to realize the method that VR chips adapt to different CPU |
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| CN102478942A (en) * | 2010-11-30 | 2012-05-30 | 鸿富锦精密工业（深圳）有限公司 | Voltage identification signal setting device and computer |
| CN102692983A (en) * | 2011-03-22 | 2012-09-26 | 和硕联合科技股份有限公司 | Method for adjusting operation voltage of central processing unit and computer system of central processing unit |
| CN102879631A (en) * | 2012-09-18 | 2013-01-16 | 华为技术有限公司 | Voltage detection device, system and method |
| CN104137024A (en) * | 2011-12-22 | 2014-11-05 | 英特尔公司 | A method, apparatus, and system for energy efficiency and energy conservation including energy efficient processor thermal throttling using deep power down mode |
| CN105376070A (en) * | 2015-10-16 | 2016-03-02 | 盛科网络（苏州）有限公司 | Method and system of power chip for adaptively supplying operating voltage to Ethernet packet switching chip |
| CN105631129A (en) * | 2015-12-29 | 2016-06-01 | 山东海量信息技术研究院 | Power supply circuit design method based on the OpenPOWER platform |
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2017
- 2017-06-06 CN CN201710418355.6A patent/CN107203482A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101344815A (en) * | 2008-08-22 | 2009-01-14 | 华硕电脑股份有限公司 | Computer system for regulating electric voltage and frequency of CPU |
| CN102478942A (en) * | 2010-11-30 | 2012-05-30 | 鸿富锦精密工业（深圳）有限公司 | Voltage identification signal setting device and computer |
| CN102130899A (en) * | 2010-12-28 | 2011-07-20 | 华为技术有限公司 | Power protocol management method, device and applied power system |
| CN102692983A (en) * | 2011-03-22 | 2012-09-26 | 和硕联合科技股份有限公司 | Method for adjusting operation voltage of central processing unit and computer system of central processing unit |
| CN104137024A (en) * | 2011-12-22 | 2014-11-05 | 英特尔公司 | A method, apparatus, and system for energy efficiency and energy conservation including energy efficient processor thermal throttling using deep power down mode |
| CN102879631A (en) * | 2012-09-18 | 2013-01-16 | 华为技术有限公司 | Voltage detection device, system and method |
| CN105376070A (en) * | 2015-10-16 | 2016-03-02 | 盛科网络（苏州）有限公司 | Method and system of power chip for adaptively supplying operating voltage to Ethernet packet switching chip |
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Application publication date: 20170926 |
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