CN107195562B - The method for measuring lightly doped drain section length in array substrate - Google Patents

The method for measuring lightly doped drain section length in array substrate Download PDF

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Publication number
CN107195562B
CN107195562B CN201611228707.3A CN201611228707A CN107195562B CN 107195562 B CN107195562 B CN 107195562B CN 201611228707 A CN201611228707 A CN 201611228707A CN 107195562 B CN107195562 B CN 107195562B
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array substrate
lightly doped
layer
doped drain
electrode
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CN107195562A (en
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孟林
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10Measuring as part of the manufacturing process
    • H01L22/12Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

The present invention provides a kind of method for measuring lightly doped drain section length in array substrate, first successively corrode the film layer of the source electrode (251) of removing TFT (2) with drain electrode (252) and thereon using strong alkali solution, the gate insulating layer (22) for reusing strongly acidic solution corrosion removing interlayer insulating film (24) and not covered by grid (23), finally using the overhead view image of electronic scanner microscope shooting array substrate, the physical length of edge to the lightly doped drain (212) of grid (23) and the length, that is, lightly doped drain (212) of heavily doped region (213) boundary line is measured on the overhead view image, it being capable of effective monitoring LDD dopping process, promote the Stability and dependability of product.

Description

The method for measuring lightly doped drain section length in array substrate
Technical field
The present invention relates to lightly doped drain section lengths in display device detection field more particularly to a kind of measurement array substrate Method.
Background technique
Thin film transistor (TFT) (Thin Film Transistor, TFT) is current liquid crystal display device (Liquid Crystal Display, LCD) and active matrix drive type organic electroluminescence display device and method of manufacturing same (Active Matrix Organic Light- Emitting Diode, AMOLED) in main driving element, the display performance of direct relation panel display apparatus.
Thin film transistor (TFT) has various structures, and the material for preparing the thin film transistor (TFT) of corresponding construction also has a variety of, low temperature Polysilicon (Low Temperature Poly-silicon, LTPS) material be it is wherein more preferred a kind of, since low temperature is more The atomic rule of crystal silicon arranges, and carrier mobility is high, for the LCD of voltage driven type, LTPS TFT due to its have compared with High mobility, the TFT that small volume can be used is realized to the deflection driven of liquid crystal molecule, is largely reduced Volume shared by TFT increases glazed area, obtains higher brightness and resolution;For the AMOLED of current-driven, LTPS TFT can better meet the requirement of driving current.
LCD and AMOLED includes tft array (Array) substrate.LTPS array substrate has viewing area, in viewing area TFT have lightly doped drain (Lightly Doped Drain, LDD).Make LDD be LTPS array substrate processing procedure in extremely One important of dopping process obtains the Stability and dependability of TFT because the leakage current of LTPS TFT can be obviously reduced in LDD To promotion.
However when producing LTPS array substrate, existing producing line is only capable of estimating the length of LDD by the length of photoresist, without It can be carried out the characterization and measurement of actual product.Such as Fig. 1 a, Fig. 1 b, with shown in Fig. 1 c, LDD is by polysilicon (poly-Si) What Doped ions were formed, after ion implanted polysilicon, through subsequent activation processing procedure, it will do it a small amount of diffusion, the length of practical LDD Degree can and discreet value have certain deviation, so the side of the existing lightly doped drain section length for estimating TFT in LTPS array substrate Method can not effective monitoring LDD dopping process.
Summary of the invention
The purpose of the present invention is to provide a kind of methods of lightly doped drain section length in measurement array substrate, can effectively supervise LDD dopping process is controlled, the Stability and dependability of product is promoted.
To achieve the above object, the present invention provides a kind of method for measuring lightly doped drain section length in array substrate, including Following steps:
Step S1, array basal plate is provided;
The array substrate has multiple pixel regions in array arrangement, and each pixel region includes at least substrate base Plate, the TFT of the buffer layer for covering underlay substrate and setting on the buffer layer;
The TFT includes setting active layer on the buffer layer, covers active layer gate insulating layer is located at gate insulator Grid on layer, covering grid and gate insulating layer interlayer insulating film and be located at layer insulation respectively at the two sides of grid Source electrode and drain electrode on layer;
The active layer includes channel region, lightly doped drain and heavily doped region, the lightly doped drain be located at channel region with Between heavily doped region;
Step S2, the array substrate is placed in strong alkali solution and is heated, to source electrode and drain electrode and film layer thereon into Row corrosion removing;
Step S3, the above-mentioned array substrate carried out after corrosion removing is dried up, places it in heating plate, titrates dropwise Strongly acidic solution carries out corrosion removing to interlayer insulating film and the gate insulating layer not by grid covering;
Step S4, the array substrate is placed under electronic scanner microscope, shot using electronic scanner microscope described in The overhead view image of array substrate;
Step S5, the edge of grid is measured on the overhead view image of the array substrate of electronic scanner microscope shooting to gently mixing Length, that is, lightly doped drain physical length in miscellaneous drain region and heavily doped region boundary line.
Each pixel region of the array substrate further include covering source electrode, drain electrode, with the flatness layer of interlayer insulating film, set Bottom electrode on flatness layer, covering bottom electrode and flatness layer protective layer and set top layer electrode on the protection layer;Institute It states top layer electrode and contacts drain electrode with the via hole on flatness layer across protective layer;
The step S2 further includes being carried out using strong alkali solution to top layer electrode, protective layer, bottom electrode and flatness layer Corrosion removing.
Strong alkali solution in the step S2 is potassium hydroxide solution.
The temperature heated in the step S2 is 100 DEG C.
Strongly acidic solution in the step S3 is hydrofluoric acid.
The temperature of heating plate is 70 DEG C in the step S3.
Further include step S4 ' between the step S3 and step S4, clean the array substrate and dry up.
The step S4 ' cleans the array substrate using distilled water.
In the step S4, electronic scanner microscope selects secondary electron in landing voltage to shoot institute under conditions of 1KV State the overhead view image of array substrate.
The material of the bottom electrode and top layer electrode is ITO.
Beneficial effects of the present invention: a kind of method measuring lightly doped drain section length in array substrate provided by the invention, The source electrode and drain electrode and film layer thereon for first successively corroding removing TFT using strong alkali solution, reuse strongly acidic solution corrosion The gate insulating layer removing interlayer insulating film and not covered by grid, finally using electronic scanner microscope shooting array substrate Overhead view image, measures edge to the lightly doped drain of grid on the overhead view image and the length of heavily doped region boundary line is gently mixed The physical length in miscellaneous drain region, can effective monitoring LDD dopping process, promote the Stability and dependability of product.
Detailed description of the invention
For further understanding of the features and technical contents of the present invention, it please refers to below in connection with of the invention detailed Illustrate and attached drawing, however, the drawings only provide reference and explanation, is not intended to limit the present invention.
In attached drawing,
Fig. 1 a is the schematic diagram of internal structure of polysilicon;
Fig. 1 b is the schematic diagram of internal structure of ion implanted polysilicon;
Fig. 1 c is the schematic diagram of internal structure after ion implanted polysilicon is activated again;
Fig. 2 is the flow chart of the method for lightly doped drain section length in measurement array substrate of the invention;
Fig. 3 is the schematic diagram of the step S1 of the method for lightly doped drain section length in measurement array substrate of the invention;
Fig. 4 is the schematic diagram of the step S2 of the method for lightly doped drain section length in measurement array substrate of the invention;
Fig. 5 is the schematic diagram of the step S3 of the method for lightly doped drain section length in measurement array substrate of the invention;
Fig. 6 is the schematic diagram of the step S5 of the method for lightly doped drain section length in measurement array substrate of the invention.
Specific embodiment
Further to illustrate technological means and its effect adopted by the present invention, below in conjunction with preferred implementation of the invention Example and its attached drawing are described in detail.
Referring to Fig. 2, the present invention provides a kind of method for measuring lightly doped drain section length in array substrate, including walk as follows It is rapid:
Step S1, array basal plate is provided.
The array substrate has multiple pixel regions in array arrangement, as shown in figure 3, each pixel region is at least Including underlay substrate 1, cover the buffer layer 11 of underlay substrate 1 and the TFT 2 that is arranged on underlay substrate 1.
The TFT 2 includes the active layer 21 being arranged on buffer layer 11, the gate insulating layer 22 for covering active layer 21, sets Grid 23, covering grid 23 on gate insulating layer 22 is with the interlayer insulating film 24 of gate insulating layer 22 and respectively at grid The two sides of pole 23 are located at source electrode 251 and drain electrode 252 on interlayer insulating film 24.
The active layer 21 includes channel region 211, lightly doped drain 212 and heavily doped region 213,211 quilt of channel region Grid 23 covers, and the lightly doped drain 212 is between channel region 211 and heavily doped region 213.Lightly doped drain 212 from Sub- implantation concentration is smaller, and the ion implantation concentration of heavily doped region 213 is larger.
The source electrode 251 passes through the heavy doping of the via hole contact active layer 21 on interlayer insulating film 24 and gate insulating layer 22 Area 213, the drain electrode 252 pass through the heavily doped region of the via hole contact active layer 21 on interlayer insulating film 24 and gate insulating layer 22 213。
Further, each pixel region of the array substrate further include covering source electrode 251, drain electrode 252, it is exhausted with interlayer The flatness layer 3 of edge layer 24, the bottom electrode 4 being located on flatness layer 3, covering bottom electrode 4 and flatness layer 3 protective layer 5 and set Top layer electrode 6 on the protective layer 5;The top layer electrode 6 passes through protective layer 5 and contacts drain electrode 252 with the via hole on flatness layer 3.
Wherein, the preferred glass substrate of the underlay substrate 1;The material of the bottom electrode 4 and top layer electrode 6 is oxidation Indium tin (Indium Tin Oxide, ITO).
Step S2, it is heated as shown in figure 4, the array substrate is placed in strong alkali solution, to source electrode 251 and drain electrode 252 and top layer electrode 6 thereon, protective layer 5, bottom electrode 4, flatness layer 3 carry out corrosion removing.
Specifically, the strong alkali solution in step S2 is preferably potassium hydroxide (KOH) solution, and the temperature of heating is 100 ℃。
Step S3, as shown in figure 5, the above-mentioned array substrate carried out after corrosion removing of drying, places it in heating plate On, strongly acidic solution is titrated dropwise, and corrosion stripping is carried out with the gate insulating layer 22 not covered by grid 23 to interlayer insulating film 24 From.
Specifically, the strongly acidic solution in step S3 is preferably hydrofluoric acid (HF);The temperature of heating plate is 70 DEG C.
After completing the step 3, the lightly doped drain 212 of the active layer 21 and heavily doped region 213 are just exposed to surface layer.
Step S4 ', it cleans the array substrate and dries up.
Specifically, step S4 ' cleans the array substrate using distilled water.
Step S4, the array substrate is placed under electronic scanner microscope, shot using electronic scanner microscope described in The overhead view image of array substrate.
Specifically, in step S4, electronic scanner microscope selects secondary electron to clap under conditions of landing voltage is 1KV Take the photograph the overhead view image of the array substrate.
Because lightly doped drain 212 is different from the ion implantation concentration of heavily doped region 213, the two resistance is different, electron scanning The accumulation degree being imaged under microscope is just different, to can distinguish between lightly doped drain 212 and heavily doped region 213 brighter Aobvious boundary line.
Step S5, as shown in fig. 6, measuring grid 23 on the overhead view image of the array substrate of electronic scanner microscope shooting Edge to lightly doped drain 212 and 213 boundary line of heavily doped region length, that is, lightly doped drain 212 physical length.
Specifically, the software that step S5 utilizes the electronic scanner microscope to carry passes through bowing for analysis array substrate The pixel density situation of visible image is had a common boundary come edge to the lightly doped drain 212 for measuring and obtaining grid 23 and heavily doped region 213 The length data of line.
The method of lightly doped drain section length can measure the actual (tube) length of lightly doped drain in measurement array substrate of the invention Degree estimates the length of LDD compared to using the prior art, can effective monitoring LDD dopping process, promoted the stability of product with can By property.
In conclusion in measurement array substrate of the invention lightly doped drain section length method, first use strong alkali solution Successively corrosion removing TFT source electrode and drain electrode and film layer thereon, reuse strongly acidic solution corrosion removing interlayer insulating film with The gate insulating layer not covered by grid is bowed finally using the overhead view image of electronic scanner microscope shooting array substrate at this Edge to the lightly doped drain of grid and length, that is, lightly doped drain actual (tube) length of heavily doped region boundary line are measured in visible image Degree, can effective monitoring LDD dopping process, promote the Stability and dependability of product.
The above for those of ordinary skill in the art can according to the technique and scheme of the present invention and technology Other various corresponding changes and modifications are made in design, and all these change and modification all should belong to the appended right of the present invention It is required that protection scope.

Claims (10)

1. a kind of method for measuring lightly doped drain section length in array substrate, which comprises the steps of:
Step S1, array basal plate is provided;
The array substrate has multiple pixel regions, and each pixel region includes at least underlay substrate (1), covering underlay substrate (1) the TFT (2) of buffer layer (11) and setting on buffer layer (11);
The TFT (2) includes the active layer (21) being arranged on buffer layer (11), the gate insulating layer for covering active layer (21) (22), the interlayer insulating film for being located at grid (23) on gate insulating layer (22), covering grid (23) and gate insulating layer (22) (24) and respectively at the two sides of grid (23) source electrode (251) being located on interlayer insulating film (24) and drain electrode (252);It is described Active layer (21) includes channel region (211), lightly doped drain (212) and heavily doped region (213), the lightly doped drain (212) Between channel region (211) and heavily doped region (213);
Step S2, the array substrate is placed in strong alkali solution and is heated, to source electrode (251) and drain electrode (252) and thereon Film layer carries out corrosion removing;
Step S3, the above-mentioned array substrate carried out after corrosion removing is dried up, places it in heating plate, titrates strong acid dropwise Property solution, to interlayer insulating film (24) with not by grid (23) cover gate insulating layer (22) carry out corrosion removing;
Step S4, the array substrate is placed under electronic scanner microscope, shoots the array using electronic scanner microscope The overhead view image of substrate;
Step S5, on the overhead view image of the array substrate of electronic scanner microscope shooting where the edge of measurement grid (23) Straight line and lightly doped drain (212) the i.e. physical length of lightly doped drain (212) at a distance from heavily doped region (213) boundary line.
2. measuring the method for lightly doped drain section length in array substrate as described in claim 1, which is characterized in that the array Each pixel region of substrate further include cover source electrode (251), drain electrode (252), with the flatness layer (3) of interlayer insulating film (24), The bottom electrode (4) that is located on flatness layer (3), covering bottom electrode (4) and flatness layer (3) protective layer (5) and be located at protection Top layer electrode (6) on layer (5);The top layer electrode (6) passes through protective layer (5) and contacts drain electrode with the via hole on flatness layer (3) (252);
The step S2 further include using strong alkali solution to top layer electrode (6), protective layer (5), bottom electrode (4), with it is flat Layer (3) carries out corrosion removing.
3. measuring the method for lightly doped drain section length in array substrate as described in claim 1, which is characterized in that the step Strong alkali solution in S2 is potassium hydroxide solution.
4. measuring the method for lightly doped drain section length in array substrate as claimed in claim 3, which is characterized in that the step The temperature heated in S2 is 100 DEG C.
5. measuring the method for lightly doped drain section length in array substrate as described in claim 1, which is characterized in that the step Strongly acidic solution in S3 is hydrofluoric acid.
6. measuring the method for lightly doped drain section length in array substrate as claimed in claim 5, which is characterized in that the step The temperature of heating plate is 70 DEG C in S3.
7. measuring the method for lightly doped drain section length in array substrate as described in claim 1, which is characterized in that the step Further include step S4 ' between S3 and step S4, clean the array substrate and dry up.
8. measuring the method for lightly doped drain section length in array substrate as claimed in claim 7, which is characterized in that the step S4 ' cleans the array substrate using distilled water.
9. measuring the method for lightly doped drain section length in array substrate as described in claim 1, which is characterized in that the step In S4, electronic scanner microscope selects vertical view of the secondary electron in landing voltage to shoot the array substrate under conditions of 1KV Image.
10. measuring the method for lightly doped drain section length in array substrate as claimed in claim 2, which is characterized in that the bottom The material of layer electrode (4) and top layer electrode (6) is ITO.
CN201611228707.3A 2016-12-27 2016-12-27 The method for measuring lightly doped drain section length in array substrate Active CN107195562B (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1801470A (en) * 2005-01-06 2006-07-12 中芯国际集成电路制造(上海)有限公司 Method for affirming fatal fault in deep-sub-micrometer semiconductor device
CN103137603A (en) * 2011-11-23 2013-06-05 上海华虹Nec电子有限公司 Test structure and method for monitoring light dope injection stability under side walls of polycrystalline silicon
CN105552027A (en) * 2016-02-14 2016-05-04 武汉华星光电技术有限公司 Production method of array substrate and array substrate

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001284593A (en) * 2000-03-29 2001-10-12 Matsushita Electric Ind Co Ltd Semiconductor device, manufacturing method thereof, and liquid-crystal display device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1801470A (en) * 2005-01-06 2006-07-12 中芯国际集成电路制造(上海)有限公司 Method for affirming fatal fault in deep-sub-micrometer semiconductor device
CN103137603A (en) * 2011-11-23 2013-06-05 上海华虹Nec电子有限公司 Test structure and method for monitoring light dope injection stability under side walls of polycrystalline silicon
CN105552027A (en) * 2016-02-14 2016-05-04 武汉华星光电技术有限公司 Production method of array substrate and array substrate

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