CN107180651B

CN107180651B - Storage element and memory array

Info

Publication number: CN107180651B
Application number: CN201610589985.5A
Authority: CN
Inventors: 陈志欣; 王世辰; 赖宗沐
Original assignee: eMemory Technology Inc
Current assignee: eMemory Technology Inc
Priority date: 2016-03-10
Filing date: 2016-07-25
Publication date: 2020-06-23
Anticipated expiration: 2036-07-25
Also published as: TW201732819A; CN107180651A; TWI602183B

Abstract

The invention discloses a storage element, which comprises a storage unit and a voltage transmission device. The memory cell includes a floating gate transistor, a word line transistor, a first capacitive element, and a second capacitive element. The floating grid transistor is provided with a first end, a second end and a floating grid, and the first end of the floating grid transistor receives a bit line signal. The first terminal of the word line transistor is coupled to the second terminal of the floating gate transistor, the second terminal of the word line transistor receives the third voltage, and the control terminal of the word line transistor receives the word line signal. The voltage transmitting means outputs the second voltage during the inhibiting operation and outputs the first voltage during the writing operation or the erasing operation. The first capacitor element is coupled to the voltage transmission device and the floating gate and receives a first control signal. The second capacitive element receives a second control signal.

Description

Storage element and memory array

Technical Field

The present invention relates to a memory device, and more particularly, to a memory device having a voltage transfer apparatus.

Background

The electronic rewritable non-volatile memory is a memory which can store the stored information without power supply and can be rewritten by other programs after the memory is loaded. Since the non-volatile memory can be used in a wide range, it is a trend to embed the non-volatile memory and the main circuit in the same chip, especially in the application of personal electronic device, which has a strict limitation on the circuit area.

The prior art non-volatile memory device may include a floating gate transistor for storing data and one or two select transistors for controlling the floating gate transistor to perform corresponding operations. Since all operations of the memory cell, such as write operations, erase operations, inhibit operations and read operations, are controlled by the select transistor, the select transistor is usually operated at a high voltage, and must be implemented with a transistor having a high threshold voltage.

However, since the select transistor has a high threshold voltage, the read operation of the memory cell must be driven at a high voltage, thereby increasing the time required to read data and increasing unnecessary power consumption. Therefore, how to speed up the reading process and reduce the requirement of reading voltage becomes a problem to be solved.

Disclosure of Invention

In order to speed up the reading process of the memory cell and reduce unnecessary power consumption compared to the prior art, an embodiment of the invention provides a memory device. The memory element includes: a first voltage transmission device and a first memory cell.

The first voltage transmitting means outputs a voltage according to an operation of the storage element. The first memory cell includes a first floating gate transistor and a first capacitive element. The first floating gate transistor has a first end, a second end and a floating gate. The first end of the first floating grid transistor receives a first bit line signal. The first capacitor element has a first end, a second end, a control end and a base, the first end of the first capacitor element is coupled to the first voltage transmission device, the control end of the first capacitor element is coupled to the floating gate of the first floating gate transistor, and the base of the first capacitor element receives the first control signal.

The first capacitor and the first voltage transmission device are disposed in the first NWELL region. During a write operation or a clear operation of the first memory cell, the first terminal of the first capacitive element receives the first voltage output by the first voltage transmitting device. During the operation prohibition period of the first memory cell, the first terminal of the first capacitive element receives the second voltage output by the first voltage transmission device. The first voltage is greater than the second voltage.

An embodiment of the present invention provides a memory array including at least one column of storage elements. Each memory element in the same column comprises a first voltage transmission device, a second voltage transmission device, a first memory cell and a second memory cell.

The first voltage transmission device receives the operation inhibiting signal and outputs voltage according to the first transmission grid control signal. The second voltage transmission device receives the operation prohibition signal and outputs a voltage according to a second transmission gate control signal.

The first memory cell includes a first floating gate transistor, a first capacitive element, a first word line transistor, and a second capacitive element. The first floating grid transistor is provided with a first end, a second end and a floating grid, and the first end of the first floating grid transistor receives a first bit line signal. The first capacitor element has a first end, a second end, a control end and a base, the first end of the first capacitor element is coupled to the first voltage transmission device, the control end of the first capacitor element is coupled to the floating gate of the first floating gate transistor, and the base of the first capacitor element receives a first control signal. The first word line transistor has a first end, a second end and a control end, the first end of the first word line transistor is coupled to the second end of the first floating gate transistor, the second end of the first word line transistor receives the third voltage, and the control end of the first word line transistor is used for receiving a word line signal. The second capacitor element is coupled to the floating grid of the first floating grid transistor and receives a second control signal.

The second memory cell includes a second floating gate transistor, a third capacitive element, a second word line transistor, and a fourth capacitive element. The second floating grid transistor is provided with a first end, a second end and a floating grid, and the first end of the second floating grid transistor receives a second bit line signal. The third capacitive element has a first end, a second end, and a control end, i.e., a base, the first end of the third capacitive element is coupled to the second voltage transmitting device, the control end of the third capacitive element is coupled to the floating gate of the second floating gate transistor, and the base of the third capacitive element receives the first control signal. The second word line transistor has a first terminal, a second terminal, and a control terminal, the first terminal of the second word line transistor is coupled to the second terminal of the second floating gate transistor, the second terminal of the second word line transistor receives the third voltage, and the control terminal of the second word line transistor receives the word line signal. The fourth capacitive element is coupled to the floating gate of the second floating gate transistor and receives a second control signal.

The plurality of memory elements in the same row receive the same inhibit signal, the same first control signal, the same second control signal, and the same word line signal. The plurality of memory elements in the same row receive a plurality of different first bit line signals, a plurality of different second bit line signals, a plurality of different first transmission gate control signals, and a plurality of different second transmission gate control signals.

Drawings

FIG. 1 is a diagram of a memory device according to an embodiment of the invention.

Fig. 2 is a layout top view of the memory device of fig. 1.

Fig. 3 is a schematic structural diagram of the first capacitive element and the first voltage transmission device of fig. 2.

FIG. 4 is a diagram of a memory device according to another embodiment of the present invention.

FIG. 5 is a diagram of a memory device according to another embodiment of the present invention.

FIG. 6 is a schematic diagram of a memory array according to an embodiment of the invention.

FIG. 7 is a diagram of a memory device according to another embodiment of the present invention.

FIG. 8 is a diagram of a memory device according to another embodiment of the present invention.

FIG. 9 is a diagram of a memory device according to another embodiment of the present invention.

Fig. 10 is a schematic structural diagram of the first capacitive element and the first voltage transmission device of fig. 9.

FIG. 11 is a diagram of a memory device according to another embodiment of the present invention.

FIG. 12 is a diagram of a memory device according to another embodiment of the present invention.

Wherein the reference numerals are as follows:

10. 301 to 30K, 50, 60, memory element

70、80、90

100 first memory cell

110 first capacitance element

120 second capacitive element

130. 730 first voltage transmission device

FGT1 first floating gate transistor

WLT1 first word line transistor

PG1 first pass gate transistor

PG2 second pass gate transistor

PL, PL 1-PLK first transfer gate control signals

PL ', PL ' 1 to PL ' K second transfer gate control signals

WL, WL 1-WLM, word line signal

AWL1 to AWLN

GND third voltage

BL, BL1 to BLK, first bit line signal

ABL1 to ABLN

CS1 first control Signal

CS2 second control Signal

INH inhibit operation signal

NW1 first NWELL

PW 1P well region

NW2 second NWELL

AA1, AA2, AA3 active region

FG1 floating gate

131. 731 first terminal of first transfer gate transistor

132. 732 second terminal of the first pass gate transistor

133. 733 control terminal of first transmission grid transistor

134 first terminal of second pass gate transistor

135 second terminal of a second pass gate transistor

136 control terminal of a second pass gate transistor

P + P type doped region

230. 330 second voltage transmission device

PG3 third pass gate transistor

PG4 fourth pass gate transistor

310 third capacitive element

320 fourth capacitive element

BL ', BL ' 1 to BL ' K second bit line signals

FGT2 second floating-gate transistor

WLT2 second word line transistor

40 memory array

W1-WM character

5001 to 500N, 6001 to 600N, additional storage cell

8001 to 800N, 9001 to 900N

510. 610, 810, 910 first additional capacitive element

520 second additional capacitive element

AFGT additional floating gate transistor

AWLT additional word line transistor

Detailed Description

FIG. 1 is a diagram of a memory device 10 according to an embodiment of the invention. The memory device 10 includes a first memory cell 100 and a first voltage transmitting device 130. The first memory cell 100 includes a first floating-gate transistor FGT1, a first word-line transistor WLT1, a first capacitive element 110, and a second capacitive element 120. The first voltage transfer device 130 may output a voltage according to the operation of the memory element 10.

The first floating-gate transistor FGT1 has a first terminal, a second terminal, and a floating gate. A first terminal of the first floating-gate transistor FGT1 may receive the first bit-line signal BL. The word line transistor WLT1 has a first terminal, a second terminal, and a control terminal. The first terminal of the word line transistor WLT1 is coupled to the second terminal of the first floating-gate transistor FGT1, the second terminal of the word line transistor WLT1 receives the third voltage GND, and the control terminal of the word line transistor WLT1 receives the word line signal WL.

The first capacitive element 110 is coupled to the first voltage transmitting device 130 and the floating gate of the first floating-gate transistor FGT 1. The first capacitive element 110 can receive the first control signal CS1 and the voltage output by the first voltage transmitting device 130. The second capacitive element 120 is coupled to the floating gate of the first floating-gate transistor FGT1 and may receive a second control signal CS 2. The first voltage transmitting device 130 can output different voltages during different operations of the memory element 10 and can help prevent the first memory cell 100 from being written or erased.

Fig. 2 is a layout top view of the memory device 10 according to an embodiment of the invention. In FIG. 2, the first capacitive element 110 and the first voltage transmitting device 130 are substantially disposed in the active region AA1 of the first N-well region NW 1. The first floating gate transistor FGT1 and the first word line transistor WLT1 are partially disposed in the active region AA2 of the P-well region PW1 adjacent to the first N-well region NW1, and the second capacitive element 120 is substantially disposed in the active region AA3 of the second N-well region NW2 adjacent to the P-well region PW 1. The active regions AA1, AA2, and AA3 may include doped regions used to form a desired transistor architecture for the memory device 10. The floating gate FG1 of the first floating gate transistor FGT1 extends toward the first NW well region NW1 and the second NW well region NW2 to couple to the first capacitive element 110 and the second capacitive element 120. The first capacitive element 110 can receive the first control signal CS1 directly from the first NW well region 1, and the second capacitive element 120 can receive the second control signal CS2 directly from the second NW well region.

In fig. 2, the area of the floating gate FG1 over the first capacitive element 110 is larger than the area of the floating gate FG1 over the second capacitive element 120. However, in other embodiments of the present invention, the area ratio of the floating gate FG1 above the first capacitive element 110 and the second capacitive element 120 may also be adjusted according to system requirements to improve the efficiency of the write operation and/or the erase operation.

Fig. 3 is a schematic structural diagram of the first capacitive element 110 and the first voltage transmitting device 130 in fig. 2. In fig. 3, the first capacitor element 110 has a first terminal, a second terminal, a control terminal and a base. The first and second terminals of the first capacitive element 110 may be coupled to the first voltage transmitting device 130, and the control terminal of the first capacitive element 110 may be coupled to the floating gate FG1 of the first floating gate transistor FGT 1. The base of the first capacitive device 110 may be a portion of the first NW region 1 and may receive the first control signal CS 1.

The first voltage pass device 130 includes a first pass gate transistor PG1 and a second pass gate transistor PG 2. The first pass gate transistor PG1 has a first terminal 131, a second terminal 132, and a control terminal 133. The first terminal 131 and the second terminal 132 of the first pass gate transistor PG1 may be P-type doped regions, and the control terminal 133 of the first pass gate transistor PG1 may be a gate structure. The first terminal 131 of the first transfer gate transistor PG1 may receive the inhibit operation signal INH, the second terminal 132 of the first transfer gate transistor PG1 may be coupled to the first terminal of the first capacitive element 110, and the control terminal 133 of the first transfer gate transistor PG1 may receive the first transfer gate control signal PL.

The second pass gate transistor PG2 has a first terminal 134, a second terminal 135, and a control terminal 136. The first end 134 and the second end 135 of the second pass gate transistor PG2 may be P-type doped regions, and the control end 136 of the second pass gate transistor PG2 may be a gate structure. The first terminal 134 of the second pass gate transistor PG2 may be coupled to the second terminal of the first capacitive element 110, the second terminal 135 of the second pass gate transistor PG2 may receive the first voltage VPP or the first control signal CS1, and the control terminal 136 of the second pass gate transistor PG2 may receive the second pass gate control signal PL'.

By controlling the first pass gate transistor PG1 and the second pass gate transistor PG2, the first capacitive element 110 receives different voltages during different operations, so that the capacitance of the first capacitive element 110 can be adjusted, thereby preventing the first memory cell 100 from being written or erased.

Table 1 shows signal voltages received by the first memory cell 100 during different operations according to an embodiment of the present invention.

TABLE 1

The third voltage GND is smaller than the fourth voltage VDD, the fourth voltage VDD is smaller than the fifth voltage VX, the fifth voltage VX is smaller than the second voltage VZ, and the second voltage VZ is smaller than the first voltage VPP. For example, the third voltage GND may be a ground voltage, i.e., 0V, the second voltage VZ may be 4V, the first voltage VPP may be 10V, the fourth voltage VDD may be 0.5V to 1.2V, and the fifth voltage VX may be 3V.

In table 1, the first capacitive element 110 is primarily used for write operations, while the second capacitive element 120 is primarily used for clear operations. During a write operation of the first memory cell 100 of the memory device 10, the first control signal CS1 may be the first voltage VPP, the second control signal CS2 may be the first voltage VPP, the first bit line signal BL may be between the fourth voltage VDD and the third voltage GND, the word line signal WL may be between the fourth voltage VDD and the third voltage GND, the inhibit operation signal INH may be the second voltage VZ, the first transfer gate control signal PL may be the first voltage VPP, and the second transfer gate control signal PL' may be the fifth voltage VX.

That is, during the write operation of the first memory cell 100, the first pass gate transistor PG1 is turned off, and the second pass gate transistor PG2 is turned on. Therefore, the voltage output by the first control signal CS1 received by the first capacitive element 110 and the voltage output by the first voltage transmitting device 130 are both the first voltage VPP. The floating gate FG1 is coupled to a voltage high enough to generate Fowler Nordheim electron tunneling. In this way, the first memory cell 100 can be written.

During the write-inhibit operation of the first memory cell 100, the first control signal CS1 is the first voltage VPP, the second control signal CS2 is the first voltage VPP, the first bit line signal BL is between the fourth voltage VDD and the third voltage GND, the word line signal WL is between the fourth voltage VDD and the third voltage GND, the operation-inhibit signal INH is the second voltage VZ, the first transfer gate control signal PL is the fifth voltage VX, and the second transfer gate control signal PL' is the first voltage VPP.

That is, during the write-inhibit operation of the first memory cell 100, the first pass gate transistor PG1 is turned on, and the second pass gate transistor PG2 is turned off. Therefore, the first capacitive element 110 receives not only the first control signal CS1 at the first voltage VPP, but also the voltage output by the first voltage transmitting device 130, i.e., the second voltage VZ. Since the second voltage VZ is less than the first voltage VPP, the floating gate FG1 is not coupled to a high enough voltage to generate electron tunneling injection, and thus the first memory cell 100 is not written.

As a result, the first and second transmission gate control signals PL and PL' can control the first and second transmission gate transistors PG1 and PG2 to complete the write operation and inhibit the write operation of the first memory cell 100. Since the inhibit operation can be performed using the first voltage transmitting device 130, the first word line transistor WLT1 does not need to receive any high voltage. That is, the first word line transistor WLT1 operates at a low voltage and thus may also have a low threshold voltage. For example, the threshold voltage of the word line transistor in the prior art may be about 0.7V, while the threshold voltage of the first word line transistor WLT2 is about 0.3V to 0.4V. In some embodiments of the invention, the first word line transistor WLT1 may be fabricated by adjusting the thickness of the gate oxide layer, using native devices (native devices) or by implanting wells. In this way, the reading process of the memory cell can be completed at a low voltage, i.e. the third voltage GND and the fourth voltage VDD as shown in table 1. The low voltage operation helps to speed up the reading process and also helps to reduce power consumption.

In some embodiments of the present invention, all memory cells in a memory element may be initially erased, so that the memory element can control the state of each memory cell by a write operation and a write-inhibit operation. In this case, the clear operation may be regarded as a reset operation. That is, each memory cell is cleared and then written to before being written to. This type of storage element does not have to inhibit the clear operation.

However, in some embodiments of the present invention, all memory cells in a memory device may be initially written to. And the memory element may control the state of each memory cell by a clear operation and an inhibit clear operation. In this case, the write operation may be considered a reset operation. Table 2 shows signal voltages received by the first memory cell 100 during the differential operation according to another embodiment of the present invention. In table 2, the first capacitive element 110 is primarily used for the clear operation, while the second capacitive element 120 is primarily used for the write operation.

TABLE 2

In table 2, during the erase operation of the first memory cell 100, the first control signal CS1 is the first voltage VPP, the second control signal CS2 is the third voltage GND, the first bit line signal BL may be in a range from the fourth voltage VDD to the third voltage GND, the word line signal WL may be in a range from the fourth voltage VDD to the third voltage GND, the inhibit operation signal INH is the second voltage VZ, the first transfer gate control signal PL is the first voltage VPP, and the second transfer gate control signal PL' may be the fifth voltage VX.

That is, during the clear operation of the first memory cell 100, the first transfer gate PG1 is turned off, and the second transfer gate PG2 is turned on. Thus, the voltage output by the first control signal CS1 and the first voltage transmitting device 130 is the first voltage VPP. Since the second capacitive element 120 receives the third voltage GND, the voltage difference between the first capacitive element 110 and the second capacitive element 120 causes the fornor tunneling effect to release electrons, and thus the first memory cell 100 is erased.

During the erase prohibition operation of the first memory cell 100, the first control signal CS1 is the first voltage VPP, the second control signal CS2 is the third voltage GND, the first bit line signal BL can be in a range from the fourth voltage VDD to the third voltage GND, the word line signal WL can be in a range from the fourth voltage VDD to the third voltage GND, the operation prohibition signal INH is the second voltage VZ, the first transfer gate control signal PL is the fifth voltage VX, and the second transfer gate control signal PL' can be the first voltage VPP.

That is, during the erase disable operation of the first memory cell 100, the first transfer gate transistor PG1 is turned on, and the second transfer gate PG2 is turned off. Therefore, the first capacitive element 110 not only receives the first control signal CS1 with the voltage of the first voltage VPP, but also receives the voltage output by the first voltage transmitting device 130 with the voltage of the second voltage VZ. Since the second voltage VZ is smaller than the first voltage VPP, the voltage difference between the first capacitor element 110 and the second capacitor element 120 is not sufficient to generate the tunneling effect, so that electrons are not released from the floating gate, and the first memory cell 100 is not erased. As a result, the first and second transmission gate control signals PL and PL' can control the first and second transmission gate transistors PG1 and PG2 to complete the erase operation and inhibit the erase operation of the first memory cell 100. Since the inhibit operation can be accomplished by the first voltage transmitting device 130, the first word line transistor WLT1 does not need to receive a high voltage. That is, the first word line transistor WLT1 may operate at a low voltage and may have a low threshold voltage. Therefore, the reading operation of the memory element 10 can be completed at a low voltage, such as the third voltage GND and the fourth voltage VDD shown in table 2. Low voltage operation helps speed up the read process and reduce power consumption.

In some embodiments of the present invention, the storage elements may need to be write operation inhibited and clear operation inhibited. In this case, the storage element may also include a second voltage transmitting device coupled to the second capacitor element. FIG. 4 is a diagram of a memory device 20 according to another embodiment of the present invention.

The

memory elements

10 and 20 are similar in structure, but the memory element 20 further includes a second voltage transmitting device 230. The second capacitor element 120 of the memory element 20 can be coupled to the second voltage transmitting device 230 and can receive the voltage outputted by the second voltage transmitting device 230. The second voltage transmitting device 230 may output the first voltage VPP during a write operation or a clear operation of the first memory cell 100, and may output the second voltage VZ during an inhibit operation of the first memory cell 100. That is, if the first voltage transmission device 130 performs the write inhibit operation according to the signal voltage shown in table 1, the second voltage transmission device 230 may perform the erase inhibit operation according to the signal voltage shown in table 2. In this case, the memory element 20 may perform a write inhibit operation through the first voltage transmitting means 130, and may perform an erase inhibit operation through the second voltage transmitting means 230. Meanwhile, the first word line transistor WLT1 can still operate at a low voltage, so that the time and power consumption of the memory element 20 during a read operation can be reduced.

FIG. 5 is a diagram of a memory device 30 according to an embodiment of the invention. The memory element 30 includes a first memory cell 100, a second memory cell 300, a first voltage transfer device 130, and a second voltage transfer device 330. The second memory cell 300 is similar in structure to the first memory cell 100, with the difference being the received signal. The second memory cell 300 includes a second floating-gate transistor FGT2, a second word-line transistor WLT2, a third capacitive element 310, and a fourth capacitive element 320.

The second voltage transmitting device 330 includes a third pass gate transistor PG3 and a fourth pass gate transistor PG 4. The third pass gate transistor PG3 has a first terminal, a second terminal, and a control terminal. A first terminal of the third transfer gate transistor PG3 may receive the inhibit operation signal INH, and a control terminal of the third transfer gate transistor PG3 may receive the second transfer gate control signal PL'.

The fourth pass gate transistor PG4 has a first terminal, a second terminal, and a control terminal. A second terminal of the fourth pass gate transistor PG4 may receive the first voltage VPP or the first control signal CS1, and a control terminal of the fourth pass gate transistor PG4 may receive the first pass gate control signal PL.

The third capacitive element 310 may be coupled to the second terminal of the third pass gate transistor PG3 and the first terminal of the fourth pass gate transistor PG 4. The third capacitive element 310 can receive the first control signal CS1 and the voltage output by the second voltage transmitting device 330. The fourth capacitive element 320 may receive the second control signal CS 2.

In addition, the second floating-gate transistor FGT2 has a first terminal, a second terminal, and a floating gate FG 2. A first terminal of the second floating-gate transistor FGT2 may receive the second bit-line signal BL', and the floating gate FG2 of the second floating-gate transistor FGT2 may be coupled to the third capacitive element 310 and the fourth capacitive element 320. The second word line transistor WLT2 has a first terminal, a second terminal, and a control terminal. The first terminal of the second word line transistor WLT2 is coupled to the second terminal of the second floating-gate transistor FG2, the second terminal of the second word line transistor WLT2 receives the third voltage GND, and the control terminal of the second word line transistor WLT2 receives the word line signal WL.

In some embodiments of the present invention, the first transmission gate control signal PL and the second transmission gate control signal PL' may be complementary signals. Since the first pass gate transistor PG1 receives the first pass gate control signal PL and the third pass gate transistor PG3 receives the second pass gate control signal PL', the first pass gate transistor PG1 and the third pass gate transistor PG3 perform different operations. For example, when the first pass gate transistor PG1 is turned on, the third pass gate transistor PG3 is turned off. In addition, when the first transfer gate transistor PG1 is turned off, the third transfer gate transistor PG3 is turned on. Similarly, the second pass gate transistor PG2 and the fourth pass gate transistor PG4 receive the second pass gate control signal PL' and the first pass gate control signal PL, respectively, and therefore turn off and turn on at different timings. That is, when the floating gate FG1 of the first floating gate transistor FGT1 is written through the second transfer gate transistor PG2, the floating gate FG2 of the second floating gate transistor FGT2 is disabled from being written through the third transfer gate transistor PG 3. While the floating gate FG1 of the first floating gate transistor FGT1 is inhibited from writing through the first pass gate transistor PG1, the floating gate FG2 of the second floating gate transistor FGT2 is written through the fourth pass gate transistor PG 4.

That is, after the write operation of the memory element 30 is completed, the first memory cell 100 and the second memory cell 300 are in different states. Thus, the memory element 30 can output a differential signal according to system requirements.

Furthermore, since the pass gate transistor can control the output of the high voltage VPP, the first voltage transmission device 130 and the second voltage transmission device 330 can share the same high voltage driving circuit, thereby simplifying the design of the memory device. That is, in some embodiments of the present invention, the first voltage transmitting device 130 and the second voltage transmitting device 330 may be coupled to the same high voltage driving circuit to receive the first voltage VPP generated by the high voltage driving circuit.

FIG. 6 is a schematic diagram of a memory array 40 according to an embodiment of the invention. The memory array 40 includes M characters W1-WM, each of which W1-WM includes K storage elements 301-30K. Each memory element has a similar structure to the memory element 30 of fig. 5. The M words W1-WM may receive distinct first control signals CS 11-CS 1M, distinct second control signals CS 21-CS 2M, distinct inhibit signals INH 1-INHM, and distinct word line signals WL 1-WLM. Thus, the M characters W1 through WM are all independently operable.

In addition, the memory cells 301 to 30K in the same word, for example, the memory cells in the word W1, receive the different first bit line signals BL1 to BLK, the different second bit line signals BL '1 to BL' K, the different first transfer gate control signals PL1 to PLK, and the different second transfer gate control signals PL '1 to PL' K. Therefore, the memory elements 301 to 30K can also operate independently.

FIG. 7 is a diagram of a memory device 50 according to an embodiment of the present invention. The memory element 50 has a similar structure to the memory element 10. However, the memory element 50 additionally includes N additional memory cells 5001 through 500N. The N additional memory cells 5001-500N have a similar structure to the first memory cell 100. Each of the additional memory cells 5001 to 500N includes a first additional capacitive element 510, a second additional capacitive element 520, an additional floating gate transistor AFGT, and an additional word line transistor AWLT. N is a positive integer. In some embodiments of the present invention, the N first additional capacitive elements 510, the first capacitive element 110, and the first voltage transmitting device 130 of the N additional memory cells 5001-500N are disposed in the same Nwell region.

The N first additional capacitive elements 510 of the N additional memory cells 5001-500N have the same structure and are disposed in the same nwell region as the first capacitive element 110. The N first additional capacitive elements 510 of the N additional memory cells 5001-500N may be connected in series between the second terminal of the first capacitive element 110 and the first terminal of the second pass gate transistor PG 2. That is, the first terminal of the additional first capacitive element 510 of the additional memory cell 5001 is coupled to the second terminal of the first capacitive element 110, the first terminal of the additional first capacitive element 510 of the additional memory cell 5002 is coupled to the second terminal of the additional first capacitive element 510 of the additional memory cell 5001, and so on. Finally, the second terminal of the additional first capacitive element 510 of the additional memory cell 500N is coupled to the first terminal of the second pass gate transistor PG 2. The additional floating gate transistor AFGT has a first terminal, a second terminal, and a floating gate. The first terminal of each additional floating-gate transistor AFGT receives a corresponding one of the bit-line signals ABL 1-ABLN, and the floating gate of the additional floating-gate transistor AFGT is coupled to the corresponding first additional capacitive element 510 and the corresponding second additional capacitive element 520.

The additional word line transistor AWLT has a first terminal, a second terminal, and a control terminal. The first terminal of the additional word line transistor AWLT is coupled to the second terminal of the additional floating gate transistor AFGT, the second terminal of the additional word line transistor AWLT can receive the third voltage GND, and the control terminal of the additional word line transistor AWLT can receive corresponding ones of the word line signals AWL 1-AWLN.

Since voltage can be transmitted between the first additional capacitive element 510 and the first capacitive element 110 through the Nwell region, different memory cells can also share the same voltage transmission device, thereby saving the required circuit area. For example, in fig. 7, when the first pass gate transistor PG1 is turned on, the first additional capacitive element 510 of the additional memory cells 5001-500N receives the inhibit signal INH, which has the second voltage VZ. When the second pass gate transistor PG2 is turned on, the first additional capacitive element 510 of the additional memory cells 5001-500N receives the first control voltage CS1 (or the first voltage VPP) through the second pass gate transistor PG 2.

In some embodiments of the present invention, the N additional floating-gate transistors AFGT of the N additional memory cells 5001 to 500N may be controlled by distinct bit line signals ABL1 to ABLN, and the N additional word line transistors AWLT of the N additional memory cells 5001 to 500N may be controlled by distinct word line signals AWL1 to AWLM. However, in some embodiments, the N additional floating gate transistors AFGT of the N additional memory cells 5001-500N may also receive the same bit line signal. While the N additional word line transistors AWLT of the N additional memory cells 5001-500N may also receive the same word line signal. In this case, the N additional floating-gate transistors AFGT of the N additional memory cells 5001-500N are operated simultaneously and synchronously, i.e., written to or cleared simultaneously.

FIG. 8 is a diagram of a memory device 60 according to an embodiment of the present invention. The memory element 60 has a similar structure to the memory element 50. The storage element 60 has N additional storage cells 6001 to 600N instead of the additional storage cells 5001 to 500N. The additional memory cells 6001 through 600N have a similar structure to that of the additional memory cells 5001 through 500N, but have different signal connections.

The first additional capacitive elements 610 of the additional memory cells 6001 through 600N have similar structures and are disposed in the same NWELL region as the first capacitive element 110. The first additional capacitive element 610 of each additional memory cell 6001 through 600N has a first terminal, a second terminal, and a control terminal. The first terminal of the first additional capacitive element 610 is coupled to the first terminal of the first capacitive element, the second terminal of the first additional capacitive element 610 is coupled to the first terminal of the second pass gate transistor PG2, and the control terminal of the first additional capacitive element 610 is coupled to the floating gate of the corresponding additional floating gate transistor AFGT.

In fig. 8, when the first transfer gate transistor PG1 is turned on, the first additional capacitive element 610 of each additional storage cell 6001 through 600N receives the inhibit signal INH. In addition, when the second pass gate transistor PG2 is turned on, the first additional capacitance element 610 of each additional storage cell 6001-600N receives the first control voltage CS1 (or the first voltage VPP). In this case, different memory cells may share the same voltage transfer device, and the required circuit area can be reduced.

Furthermore, the

memory devices

50 and 60 may further include a high voltage driving circuit to provide the first voltage VPP required by all of the

memory devices

50 and 60, thereby further simplifying the design of the memory devices.

FIG. 9 is a diagram of a memory device 70 according to an embodiment of the invention. The memory element 70 includes a first memory cell 100 and a first voltage transmitting device 730. Fig. 10 is a schematic structural diagram of the first capacitive element 110 and the first voltage transmission device 730.

In fig. 10, the first voltage transmitting device 730 includes a first transmission gate transistor PG 1'. The first pass gate transistor PG 1' has a first terminal 731, a second terminal 732, and a control terminal 733. The first and second ends 731 and 732 of the first pass gate transistor PG1 'may be P-type doped regions, and the control end of the first pass gate transistor PG 1' is a gate structure. The first terminal 731 of the first transfer gate transistor PG1 ' may receive the inhibit control signal INH, the second terminal 732 of the first transfer gate transistor PG1 ' is coupled to the first terminal of the first capacitive element 110, and the control terminal 733 of the first transfer gate transistor PG1 ' may receive the first transfer gate control signal PL.

In this embodiment, the first terminal of the first capacitive element 110 is coupled to the first voltage transmitting device 730, and the control terminal of the first capacitive element 110 is coupled to the floating gate FG1 of the first floating gate transistor FGT 1. The base of the first capacitive device 110 is part of the first NW region 1 and is capable of receiving the first control signal CS 1. In addition, in fig. 10, the second end 112 of the first capacitive element 110 may be a floating P-type doped region. However, in some embodiments, the second end 112 of the first capacitive element 110 may also be implemented as a shallow trench isolation.

Table 3 shows the received signal voltages of the memory element 70 during different operations according to one embodiment of the present invention.

TABLE 3

In table 3, the first capacitive element 110 is primarily used for write operations, while the second capacitive element 120 is primarily used for clear operations. During a write operation of the first memory cell 100, the first control signal CS1 may be the first voltage VPP, the second control signal CS2 may be the first voltage VPP, the first bit line signal BL may be between the fourth voltage VDD and the third voltage GND, the word line signal BL may be between the fourth voltage VDD and the third voltage GND, the inhibit operation signal INH may be the first voltage VPP, and the first transfer gate control signal PL may be the fifth voltage VX.

That is, during the write operation of the memory cell 100 of the memory element 70, the first pass gate transistor PG 1' is turned on, and the operation inhibiting signal INH is the first voltage VPP. The voltage output by first voltage transfer device 730 is therefore first voltage VPP, such that floating gate FG1 is coupled to a voltage high enough to cause electron tunneling injection, and memory cell 100 of memory element 70 can be written to.

During the write-inhibit operation of the memory cell 100 of the memory device 70, the first control signal CS1 may be the first voltage VPP, the second control signal CS2 may be the first voltage VPP, the first bit line signal BL may be in a range from the fourth voltage VDD to the third voltage GND, the word line signal BL may be in a range from the fourth voltage VDD to the third voltage GND, the operation-inhibit signal INH may be the second voltage VZ, and the first transfer gate control signal PL may be the fifth voltage VX.

That is, during the write-inhibit operation of the first memory cell 100 of the memory element 70, the first pass gate transistor PG 1' is turned on, and the inhibit signal INH is the second voltage VZ. The voltage output by the first voltage transmitting device 730 is also the second voltage VZ. In this case, the first capacitive element 110 receives not only the first control signal CS1 at the first voltage VPP but also the second voltage VZ output by the first voltage transmitting device 730. Since second voltage VZ is less than first voltage VPP, floating gate FG1 will not be coupled to a voltage high enough to cause electron tunneling injection, and thus first memory cell 100 of memory element 70 will not be written to.

In this way, the first transmission gate control signal PL and the operation-inhibiting signal INH can be used to complete the write operation and the write-inhibiting operation of the memory device. Since the disable operation can be performed by the first voltage transmitting device 730, the first word line transistor WLT1 does not need to receive any high voltage signal. That is, the first word line transistor WLT1 may operate at a low voltage and have a low threshold voltage. The reading process of the memory element 70 can be completed at a low voltage such as the third voltage GND or the fourth voltage VDD shown in table 3. The low voltage operation helps to speed up the reading process and can reduce power consumption.

Table 4 shows the received signal voltages of the memory element 70 of another embodiment of the present invention during different operations. In table 4, the first capacitive element 110 is primarily used for erase operations, while the second capacitive element 120 is primarily used for write operations.

TABLE 4

In table 4, during the erase operation of the first memory cell 100 of the memory element 70, the first control signal CS1 may be the first voltage VPP, the second control signal CS2 may be the third voltage GND, the first bit line signal BL may be between the fourth voltage VDD and the third voltage GND, the word line signal BL may be between the fourth voltage VDD and the third voltage GND, the inhibit operation signal INH may be the first voltage VPP, and the first transfer gate control signal PL may be the fifth voltage VX.

That is, during the erase operation of the first memory cell 100 of the memory element 70, the first pass gate transistor PG 1' is turned on, and the inhibit signal INH is the first voltage VPP. Therefore, the voltage output by the first control signal CS1 and the first voltage transmitting device 730 is the first voltage VPP. Since the second capacitive element 120 is coupled to the third voltage GND, the voltage difference between the first capacitive element 110 and the second capacitive element 120 is sufficient to cause electron tunneling to release electrons, and the first memory cell 100 of the memory element 70 can be erased.

During the erase operation of the first memory cell 100 of the memory device 70, the first control signal CS1 may be the first voltage VPP, the second control signal CS2 may be the third voltage GND, the first bit line signal BL may be in the range from the fourth voltage VDD to the third voltage GND, the word line signal BL may be in the range from the fourth voltage VDD to the third voltage GND, the operation inhibiting signal INH may be the second voltage VZ, and the first transfer gate control signal PL may be the fifth voltage VX.

That is, during the erase-inhibited operation of the first memory cell 100 of the memory element 70, the first pass gate transistor PG 1' is turned on, and the inhibit operation signal INH is the second voltage VZ. Therefore, the first capacitive element 110 receives not only the first control signal CS1 at the first voltage VPP, but also the second voltage VZ output by the first voltage transmitting device 730. Since the second voltage VZ is smaller than the first voltage VPP, the voltage difference between the first capacitive element 110 and the second capacitive element 120 is not enough to cause electron tunneling, so that electrons are not released and the first memory cell 100 of the memory element 70 is not erased.

In this way, the first transfer gate control signal PL and the inhibit signal INH can be used to complete the erase operation and inhibit the erase operation of the memory device, and since the inhibit operation can be completed by the first voltage transfer device 730, the first word line transistor WLT1 does not need to receive any high voltage signal. That is, the first word line transistor WLT1 may operate at a low voltage and have a low threshold voltage. The reading process of the memory element 70 can be completed at a low voltage such as the third voltage GND or the fourth voltage VDD shown in table 4. The low voltage operation helps to speed up the reading process and can reduce power consumption.

In some embodiments of the present invention, the storage elements may need to be write operation inhibited and clear operation inhibited. In this case, the storage element may further include a second voltage transmission device 230. The second voltage transmitting device 230 may be coupled to the second capacitive element 120, i.e. the memory element 20 as shown in FIG. 4. In some embodiments of the present invention, the first voltage transmission device 130 and the second voltage transmission device 230 in the memory element 20 may be implemented by a structure similar to the voltage transmission device 730. The write inhibit operation and the erase inhibit operation are accomplished by the signal voltages listed in tables 3 and 4.

FIG. 11 is a diagram of a memory device 80 according to an embodiment of the invention.

Memory elements

70 and 80 have a similar structure. Storage element 80 further includes N additional storage units 8001 to 800N. N is a positive integer. The N first additional capacitive elements 810 of the N additional memory cells 8001-800N have the same structure as the first capacitive element 110, and are disposed in the same NWELL region as the first voltage transmitting device 730.

N first additional capacitive elements 810 of the N additional memory cells 8001 to 800N may be connected in series with the first capacitive element 110. That is, the first terminal of the first additional capacitive element 810 of the additional memory unit 8001 is coupled to the second terminal of the first capacitive element 110, the first terminal of the first additional capacitive element 810 of the additional memory unit 8002 is coupled to the second terminal of the first additional capacitive element 810 of the additional memory unit 8001, and so on. In addition, the second terminal of the first additional capacitive element 810 of the additional memory cell 800N may be in a floating state.

In fig. 11, when the first pass gate transistor PG 1' is turned on, the first additional capacitive elements 810 of the additional memory cells 8001 to 800N all receive the inhibit operation signal INH. Since the voltage can be transmitted between the nwell regions, different memory cells can also share the same voltage transmitting device 730, thereby saving the required circuit area. In some embodiments of the present invention, the N additional floating gate transistors AFGT of the N additional memory cells 8001 to 800N may be controlled by the distinct bit line signals ABL1 to ABLN, and the N additional word line transistors AWLT of the N additional memory cells 8001 to 800N may be controlled by the distinct word line signals AWL1 to AWLN.

However, in some embodiments of the invention, the N additional floating-gate transistors AFGT and the first floating-gate transistor FGT1 of the N additional memory cells 8001 through 800N may also receive the same bit line signal BL. Furthermore, the N additional word line transistors AWLT of the N additional memory cells 8001 to 800N may also receive the same word line signal WL as the first word line transistor WLT 1. In this case, the additional floating-gate transistor AFGT operates synchronously and simultaneously with the first floating-gate transistor FGT1, i.e. is written or cleared simultaneously.

FIG. 12 is a diagram of a memory device 90 according to an embodiment of the invention.

Memory elements

90 and 80 have similar structures. Storage element 90 includes N additional storage units 9001 to 900N instead of additional storage units 8001 to 800N. The N first additional capacitive elements 910 of the additional memory cells 9001 to 900N have the same structure as the first capacitive element 110, and are disposed in the same nwell region as the first voltage transmitting device 730.

The first additional capacitive element 910 of each additional memory cell 9001 to 900N has a first terminal, a second terminal and a control terminal. The first terminal of the first additional capacitive element 910 is coupled to the first terminal of the first capacitive element 110, the second terminal of the first additional capacitive element 910 is floating to the second terminal of the first capacitive element 110, and the control terminal of the first additional capacitive element 910 is coupled to the corresponding additional floating gate transistor AFGT in the additional memory units 9001 to 900N.

In fig. 12, when the first transfer gate transistor PG 1' is turned on, the first additional capacitive elements 910 of the additional memory cells 9001 to 900N all receive the inhibit operation signal INH. In this case, different memory cells can also share the same voltage transmission device 730, thereby saving the required circuit area.

In addition, the memory devices of the various embodiments described above may further include a plurality of select transistors, each of which may be coupled to a corresponding floating gate transistor to receive a corresponding bit line signal, which may also allow flexibility in inhibiting different bias conditions during operation. That is, the floating gate transistor may receive its bit line signal through the corresponding select transistor.

In summary, the memory device provided by the embodiments of the invention can perform the inhibit operation by the voltage transmitting device. The word line transistor can operate at a low voltage and can have a low threshold voltage, thereby helping to speed up the reading process of the memory device and reducing computer wear. In addition, since the transmission gate transistor can control a high voltage signal, the storage elements of the same character or the capacitor elements in the same storage element can share a high voltage power supply, thereby reducing the circuit area of the storage elements.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A memory element, comprising:

a first voltage transfer device for outputting a voltage according to an operation of the memory element, the first voltage transfer device including a first transfer gate transistor having a first terminal for receiving an inhibit signal, a second terminal, and a control terminal for receiving a transfer gate control signal; and

a first storage unit comprising:

a first floating gate transistor having a first end for receiving a first bit line signal, a second end, and a floating gate; and

a first capacitor element having a first terminal coupled to the second terminal of the first transmission gate transistor, a second terminal, and a control terminal coupled to the floating gate of the first floating gate transistor, and a base for receiving a first control signal;

wherein:

the first capacitor element and the first voltage transmission device are both arranged in the first N well region;

the first end of the first capacitance element receives a first voltage output by the first voltage transmission device during a write operation or a clear operation of the first memory cell;

the first terminal of the first capacitive element receives a second voltage output by the first voltage transmitting device during an inhibited operation of the first memory cell;

the first voltage is greater than the second voltage;

during the write operation of the first memory cell, the first control signal is at the first voltage, the first bit line signal is between a fourth voltage and a third voltage, the inhibit operation signal is at the first voltage, the pass gate control signal is at a fifth voltage, and the first terminal of the first pass gate transistor receives the first voltage;

during a write inhibit operation of the first memory cell, the first control signal is at the first voltage, the first bit line signal is in the range from the fourth voltage to the third voltage, the inhibit operation signal is at the second voltage, the pass gate control signal is at the fifth voltage, and the first terminal of the first pass gate transistor receives the second voltage; and

the third voltage is less than the fourth voltage, the fourth voltage is less than the fifth voltage, and the fifth voltage is less than the second voltage.

2. The memory element of claim 1, wherein said first memory cell further comprises:

a first word line transistor having a first terminal coupled to the second terminal of the first floating gate transistor, a second terminal for receiving the third voltage, and a control terminal for receiving a word line signal;

wherein:

during the write operation of the first memory cell, the word line signal is in a range from the fourth voltage to the third voltage; and

the word line signal is between the fourth voltage and the third voltage during the write inhibit operation of the first memory cell.

3. The memory element of claim 2 wherein said first wordline transistor has a low threshold voltage.

4. The memory element of claim 1, wherein said first memory cell further comprises:

a second capacitor element coupled to the floating gate of the first floating gate transistor and configured to receive at least one second control signal;

wherein:

the second control signal is at the first voltage during the write operation of the first memory cell; and

the second control signal is at the first voltage during the write-inhibit operation of the first memory cell.

5. A memory element, comprising:

a first storage unit comprising:

wherein:

the first voltage is greater than the second voltage;

during the clear operation of the first memory cell, the first control signal is at the first voltage, the first bit line signal is between a fourth voltage and a third voltage, the inhibit operation signal is at the first voltage, the pass gate control signal is at a fifth voltage, and the first terminal of the first pass gate transistor receives the first voltage;

during an erase inhibit operation of the first memory cell, the first control signal is at the first voltage, the first bit line signal is in the range from the fourth voltage to the third voltage, the erase inhibit signal is at the second voltage, the pass gate control signal is at the fifth voltage, and the first terminal of the first pass gate transistor receives the second voltage; and

6. The memory element of claim 5, wherein said first memory cell further comprises:

wherein:

the word line signal is between the fourth voltage and the third voltage during the clear operation of the first memory cell; and

the word line signal is between the range of the fourth voltage and the third voltage during the erase disable operation of the first memory cell.

7. The memory element of claim 6 wherein said first wordline transistor has a low threshold voltage.

8. The memory element of claim 5, wherein said first memory cell further comprises:

wherein:

the second control signal is at the third voltage during the clear operation of the first memory cell; and

the second control signal is at the third voltage during the inhibit clear operation of the first memory cell.

9. A memory element, comprising:

first voltage transmitting means for outputting a voltage according to an operation of the storage element, the first voltage transmitting means comprising:

a first transmission grid transistor, which is provided with a first end used for receiving the operation forbidding signal, a second end and a control end used for receiving a first transmission grid control signal; and

a second transmission grid transistor, having a first end, a second end for receiving the first voltage or the first control signal output by the first voltage transmission device, and a control end for receiving the second transmission grid control signal; and

a first storage unit comprising:

a first capacitor having a first terminal coupled to the second terminal of the first transmission gate transistor, a second terminal coupled to the first terminal of the second transmission gate transistor, a control terminal coupled to the floating gate of the first floating gate transistor, and a base for receiving the first control signal;

wherein:

the first terminal of the first capacitive element receives the first voltage during a write operation or a clear operation of the first memory cell;

the first voltage is greater than the second voltage;

during the write operation of the first memory cell, the first control signal is at the first voltage, the first bit line signal is between a fourth voltage and a third voltage, the inhibit operation signal is at the second voltage, the first transfer gate control signal is at the first voltage, and the second transfer gate control signal is at a fifth voltage;

during a write inhibit operation of the first memory cell, the first control signal is at the first voltage, the first bit line signal is in the range from the fourth voltage to the third voltage, the inhibit operation signal is at the second voltage, the first transfer gate control signal is at the fifth voltage, and the second transfer gate control signal is at the first voltage; and

10. The memory element of claim 9, wherein said first memory cell further comprises:

wherein:

11. The memory element of claim 9, wherein said first memory cell further comprises:

wherein:

12. A memory element, comprising:

a first storage unit comprising:

wherein:

the first voltage is greater than the second voltage;

during the clear operation of the first memory cell, the first control signal is at the first voltage, the first bit line signal is between a fourth voltage and a third voltage, the inhibit operation signal is at the second voltage, the first transfer gate control signal is at the first voltage, and the second transfer gate control signal is at a fifth voltage;

during an erase inhibit operation of the first memory cell, the first control signal is at the first voltage, the first bit line signal is in the range from the fourth voltage to the third voltage, the erase inhibit signal is at the second voltage, the first transfer gate control signal is at the fifth voltage, and the second transfer gate control signal is at the first voltage; and

13. The memory element of claim 12, wherein said first memory cell further comprises:

wherein:

14. The memory element of claim 12, wherein said first memory cell further comprises:

wherein:

15. A memory element, comprising:

a first storage unit comprising:

n additional storage units, each additional storage unit comprising:

a first additional capacitive element;

a second additional capacitive element;

an additional floating gate transistor having a first end for receiving a corresponding bit line signal, a second end, and a floating gate coupled to the first additional capacitive element and the second additional capacitive element; and

an additional word line transistor having a first terminal coupled to the second terminal of the additional floating gate transistor, a second terminal for receiving a third voltage, and a control terminal for receiving a corresponding word line signal;

wherein:

the first voltage is greater than the second voltage; and

n is a positive integer.

16. A memory element as recited in claim 15, wherein:

n first additional capacitive elements of the N additional memory cells are in series with the first capacitive element.

17. A memory element as recited in claim 15, wherein:

the first voltage transmitting device comprises a first transmission grid transistor, a second capacitor element and a control end, wherein the first transmission grid transistor is provided with a first end used for receiving an operation forbidding signal, a second end coupled to the first end of the first capacitor element, and the control end used for receiving a transmission grid control signal; and

the first additional capacitive element has a first terminal coupled to the first terminal of the first capacitive element, a second terminal coupled to the second terminal of the first capacitive element, and a control terminal coupled to the floating gate of the additional floating gate transistor.

18. A memory element as recited in claim 15, wherein:

the first voltage transmitting device includes:

a first transmission gate transistor having a first end for receiving an inhibit signal, a second end coupled to the first end of the first capacitive element, and a control end for receiving a first transmission gate control signal; and

a second transmission gate transistor having a first terminal, a second terminal for receiving the first voltage or the first control signal, and a control terminal for receiving a second transmission gate control signal; and

n first additional capacitive elements of the N additional memory cells are connected in series between the second terminal of the first capacitive element and the first terminal of the second pass gate transistor.

19. A memory element as recited in claim 15, wherein:

the first voltage transmitting device includes:

the first additional capacitive element has a first terminal coupled to the first terminal of the first capacitive element, a second terminal coupled to the first terminal of the second pass gate transistor, and a control terminal coupled to the floating gate of the additional floating gate transistor.

20. A memory element, comprising:

first voltage transmission means for outputting a voltage according to an operation of the storage element; and

a first storage unit comprising:

a first capacitor element having a first terminal coupled to the first voltage transmitting device, a second terminal, and a control terminal coupled to the floating gate of the first floating gate transistor, and a base for receiving a first control signal;

second voltage transmission means for outputting a first voltage during a write operation or a clear operation of the first memory cell and outputting a second voltage during an inhibit operation of the first memory cell; and

a second capacitor element coupled to the floating gate of the first floating gate transistor and the second voltage transmission device for receiving the voltage output by the second voltage transmission device

Wherein:

the first terminal of the first capacitive element receives the first voltage output by the first voltage transmitting device during the write operation or the clear operation of the first memory cell;

the first terminal of the first capacitive element receives the second voltage output by the first voltage transmitting means during the inhibit operation of the first memory cell; and

the first voltage is greater than the second voltage.

21. A memory array, comprising:

at least one column of memory elements, each memory element of a same column comprising:

the first voltage transmission device is used for receiving the operation forbidding signal and outputting voltage according to the first transmission grid control signal;

the second voltage transmission device is used for receiving the operation forbidding signal and outputting voltage according to a second transmission grid control signal;

a first storage unit comprising:

a first floating gate transistor having a first end for receiving a first bit line signal, a second end, and a floating gate;

a first capacitor element having a first terminal coupled to the first voltage transmitting device, a second terminal, a control terminal coupled to the floating gate of the first floating gate transistor, and a base for receiving a first control signal;

a first word line transistor having a first terminal coupled to the second terminal of the first floating gate transistor, a second terminal for receiving a third voltage, and a control terminal for receiving a word line signal; and

a second capacitive element coupled to the floating gate of the first floating gate transistor and configured to receive a second control signal; and

a second storage unit comprising:

a second floating gate transistor having a first end for receiving a second bit line signal, a second end, and a floating gate;

a third capacitive element having a first end coupled to the second voltage transmitting device, a second end, a control end coupled to the floating gate of the second floating gate transistor, and a base for receiving the first control signal;

a second word line transistor having a first terminal coupled to the second terminal of the second floating gate transistor, a second terminal for receiving the third voltage, and a control terminal for receiving the word line signal; and

a fourth capacitive element coupled to the floating gate of the second floating gate transistor and configured to receive the second control signal;

wherein:

the plurality of memory elements in the same row receive the same inhibit signal, the same first control signal, the same second control signal, and the same word line signal; and

the plurality of memory elements in the same row receive a plurality of different first bit line signals, a plurality of different second bit line signals, a plurality of different first transmission gate control signals, and a plurality of different second transmission gate control signals.

22. The memory array of claim 21, wherein:

the plurality of memory elements in different rows receive a plurality of different inhibit signals, a plurality of different first control signals, a plurality of different second control signals, and a plurality of different word line signals; and

the plurality of memory elements in different rows and in the same column receive the same first bit line signal, the same second bit line signal, the same first transmission gate control signal, and the same second transmission gate control signal.