CN107171548B - The charge pump circuit of nonvolatile memory - Google Patents
The charge pump circuit of nonvolatile memory Download PDFInfo
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- CN107171548B CN107171548B CN201710388216.3A CN201710388216A CN107171548B CN 107171548 B CN107171548 B CN 107171548B CN 201710388216 A CN201710388216 A CN 201710388216A CN 107171548 B CN107171548 B CN 107171548B
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- current path
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- negative pressure
- charge pump
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
- H02M3/077—Charge pumps of the Schenkel-type with parallel connected charge pump stages
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Read Only Memory (AREA)
Abstract
The invention discloses a kind of charge pump circuit of nonvolatile memory, charge pump circuit includes simultaneously positive/negative-pressure charge pump；It include that negative pressure is established and completes signal generating circuit in negative pressure charge pump, in start-up course, when third negative voltage reaches target value, negative pressure, which is established, to be completed the negative pressure of signal generating circuit output and establish that complete signal effective；It include that the second positive voltage establishes control circuit in positive pressure charge pump, when starting, the first positive voltage starts to start and start to target value, and the second positive voltage establishes control circuit and inputs the negative pressure foundation completion signal, before negative pressure foundation completion signal is effective, the second positive voltage remains 0V；After negative pressure foundation completion signal is effective, the second positive voltage starts to start and starts to target value.After the present invention is by being placed on the foundation completion of third negative voltage for the starting timing of the second positive voltage, third negative voltage can be reduced in the load of startup stage.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit, more particularly to the charge of nonvolatile memory (NVM) a kind of
Pump circuit.
Background technique
As shown in Figure 1, being the V diagram of existing nonvolatile memory such as quick flashing (FLASH) formula memory；It is non-easy
The property lost memory is needed during the work time using multiple voltage, such as positive high voltage (VPOS), positive pressure (VBL) and negative pressure (VNEG).
Voltage VPOS, VBL and VNEG are supplied to the storage array (array) 101 of nonvolatile memory, while storage array 101 is made
For the load (loading) of the charge pump (pump) of generation voltage VPOS, VBL and VNEG.Storage array 101 is single by multiple storages
The arrangement that first (cell) carries out row and column is formed.The storage unit of the storage array includes the storage tube 102 and selecting pipe
103, the source electrode of the storage tube 102 of the same storage unit connects the drain electrode of the selecting pipe 103, with each institute of a line
The grid for stating storage tube 102 all connects the first wordline WLS mutually to go together, and the grid with each selecting pipe 103 of a line all connects
The the second wordline WL mutually to go together is met, the drain electrode of each storage tube 102 of same row all connects the bit line Bl of same column, respectively
The source electrode of the selecting pipe 103 is all connected to source line SL, since storage array is by rows and columns, therefore the first wordline and the second word
Line also has multirow respectively, and every a line all respectively includes adding after WLS in a first wordline WLS and one second wordline WL, Fig. 1
[x] and [x] is added to indicate the corresponding WLS or WL of x-1 row after WL, x is integer, and two rows, corresponding x difference are shown in Fig. 1
For 0 and 1.Similarly, each column of storage array all include showing two bit line BL in bit line a BL, Fig. 1, and add after BL
[even] indicates the corresponding bit line of even column, and [odd] is added to indicate the corresponding bit line of odd column.
Voltage VPOS, VBL and VNEG not only can also deposit the charging of the parasitic capacitance of storage unit in establishment process
Under programming (PRG) mode in the electric leakage (leakage) of some pipes, such as under block mode (Bulk), the pipe of storage unit
The charge charging that needs with Cell itself of electric leakage can caused by voltage VNEG biggish load current i.e. high current, and when big
When electric current is maintained except the limit of long-range charge pump capacity, then charge pump there may be settling time it is too long or establish failure
Risk.Now with the load current of a specific example illustratively charge pump, with reference to as shown in following table one, in Flash Bulk
Voltage value under PRG mode are as follows:
The second all wordline WL voltages are all negative pressure VNEG, as negative pressure VNEG takes -4.3V.
The first all wordline WLS voltages are all positive high voltage VPOS, as positive high voltage VPOS takes 7.2V.
The voltage that each storage tube 102 is connected with the substrate of selecting pipe 103 i.e. underlayer voltage VBPW is negative pressure VNEG.
It defines and is programmed into 1, the voltage of bit line BL [0] is negative pressure VNEG, and even number even indicates 0 here, indicates that the 0th column add
1 can be written after negative pressure VNEG.
Definition is programmed into 0, and the voltage of bit line BL [1] is positive pressure VBL, if positive pressure VBL takes 1.2V, even number odd table here
Show 1,0 can be written after indicating the 1st column plus positive pressure VBL.
Source line SL floating (float).
Table one
| WL[x] | WLS[x] | BL[even] | BL[odd] | VBPW | SL | |
| Bulk PRG | VNEG | VPOS | VNEG | VBL | VNEG | float |
As seen from Figure 1, line SL in source is the structure i.e. common source shared by multi-bit memory cell, therefore is existed
Electric leakage, electric leakage are that there are VBL+ between bit line BL the reason of leaking electricity Ics shown in Fig. 1, generate Ics | VNEG | voltage
Difference generates electric leakage Ics by the voltage difference.Due to VBL+ | VNEG | voltage difference it is larger, therefore leak electricity Ics it is also larger.This started
The corresponding electric current of Cheng Zhong, positive high voltage VPOS is Ivpos, and direction is to flow to storage array；The corresponding electric current of high pressure VBl is Ivbl,
Direction is to flow to storage array；The corresponding electric current of negative pressure VNEG is Ivneg, and direction is outflow storage array, and last Ivneg is
The sum of Ivpos and Ivbl, Ics can also belong to a part of Ivbl and can be flowed out by Ivneg, therefore last Ivneg can be bigger,
Namely it is larger in the load of startup stage negative pressure VNGE, charge pump there may be settling time it is too long or establish failure wind
Danger.
Under above-mentioned Flash Bulk PRG mode, voltage VPOS, VNEG and VBL can charge pump enable signal it is effective
When all begin to work i.e. voltage VPOS, VNEG and VBL and can start simultaneously at starting, and due to existing between VBL and VNEG
The biggish electric leakage Ics that common source is generated, the settling time mistake so there are negative pressure VNEG load excessive, when starting
The defect of long such as 500 μ s or more；Meanwhile because programming time (PRG time) is fixed, because settling time is too long, can make effective
PRG Time shortens, and influences PRG effect.Serious situation will lead to negative pressure VNEG voltage to the not current potential of target, negative pressure
VNEG is unsatisfactory for the claimed range (spec) of design.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of charge pump circuits of nonvolatile memory, can be reduced negative
It is pressed in the load of startup stage.
In order to solve the above technical problems, the charge pump circuit of nonvolatile memory provided by the invention includes simultaneously positive pressure
Charge pump and negative pressure charge pump.
The positive pressure charge pump provides the first positive voltage and the second positive voltage, and the negative pressure charge pump provides third negative electricity
Pressure；First positive voltage is greater than second positive voltage；First positive voltage, second positive voltage and the third are negative
Voltage is all supplied to the storage array of nonvolatile memory；The volume for writing 1 of the storage tube of the storage unit of the storage array
Journey voltage determines by the difference of first positive voltage and the third negative voltage, and first positive voltage is added on corresponding described deposit
The grid of pipe is stored up, the third negative voltage is added on the bit line of the corresponding storage tube；The program voltage for writing 0 of the storage tube
Determine that first positive voltage is added on the corresponding storage tube by the difference of first positive voltage and second positive voltage
Grid, second positive voltage are added on the bit line of the corresponding storage tube.
It include that a negative pressure establishes completion signal generating circuit in the negative pressure charge pump, in the nonvolatile memory
Starting when, the third negative voltage starts to start, and when the third negative voltage reaches target value, the negative pressure, which is established, to be completed
It is effective that the negative pressure of signal generating circuit output establishes completion signal.
It include that the second positive voltage establishes control circuit in the positive pressure charge pump, in the starting of the nonvolatile memory
When, first positive voltage starts to start and start to target value, and it is described negative that second positive voltage establishes control circuit input
Pressure, which is established, completes signal, and before negative pressure foundation completion signal is effective, second positive voltage remains 0V；Described negative
Pressure establish complete signal it is effective after, second positive voltage starts to start and start to target value, by by second positive electricity
The starting timing of pressure be placed on the third negative voltage establish complete reduce the third negative voltage later in startup stage
Load.
A further improvement is that it includes a voltage comparator circuit, the electricity that the negative pressure, which establishes completion signal generating circuit,
Pressure comparison circuit compares the first comparison voltage and the second reference voltage, and first comparison voltage and the third negative voltage are real-time
Proportional and ratio value is the first value, and the target value of second reference voltage and the third negative voltage is proportional and ratio value
It also is the first value, when the third negative voltage reaches target value, the described of output end output of the voltage comparator circuit is born
Pressure, which is established, completes signal by being switched in vain effectively.
A further improvement is that the voltage comparator circuit include the first NMOS tube and the first PMOS tube, described first
The grid of NMOS tube connects first comparison voltage, the source electrode ground connection of first NMOS tube, the grid of first PMOS tube
Pole connects second reference voltage, and the source electrode of first PMOS tube connects supply voltage, the drain electrode of first NMOS tube
It is connected with the drain electrode of first PMOS tube and exports the negative pressure in tie point and establishes completion signal.
A further improvement is that it further includes one first phase inverter, second that the negative pressure, which establishes completion signal generating circuit,
PMOS tube and third PMOS tube.
The input terminal of first phase inverter connects the negative pressure and establishes completion signal, the output end of first phase inverter
It exports the negative pressure and establishes the inversion signal for completing signal.
The source electrode of second PMOS tube connects supply voltage, and the grid of second PMOS tube connects the first PMOS
The grid of pipe.
The source electrode of the third PMOS tube connects the drain electrode of second PMOS tube, the drain electrode connection of the third PMOS tube
The negative pressure, which is established, completes signal, and the grid of the third PMOS tube connects the negative pressure and establishes the inversion signal for completing signal.
It completes when signal is 1 to be useful signal a further improvement is that the negative pressure is established, 0 when is invalid signals.
A further improvement is that it includes the second NMOS tube, the 2nd NMOS that second positive voltage, which establishes control circuit,
Pipe connects to form voltage follower, and the grid of second NMOS tube connects the second positive voltage that the positive pressure charge pump generates
The source electrode of input signal, second NMOS tube exports second positive voltage, between the source electrode and ground of second NMOS tube
Including connecting between the drain electrode and supply voltage of second NMOS tube by the first current path and the second current path in parallel
It is connected to third current path.
When the negative pressure establishes completion invalidating signal, second current path and the third current path are all disconnected
It opens, the first current path conducting makes the second positive voltage 0V.
When the negative pressure establish complete signal it is effective when, first current path disconnects, second current path and
The third current path is all connected, the input for the second positive voltage that second positive voltage follows the positive pressure charge pump to generate
Signal intensity simultaneously starts to target value.
A further improvement is that it further includes third NMOS tube, the third that second positive voltage, which establishes control circuit,
NMOS tube connects to form voltage follower, and the grid of the third NMOS tube connects the second positive electricity that the positive pressure charge pump generates
The input signal of pressure, the source electrode of the third NMOS tube export second positive voltage, the source electrode connection of the third NMOS tube
The source electrode of second NMOS tube is connected with the 4th current path between the drain electrode and supply voltage of the third NMOS tube.
When the nonvolatile memory is block mode and negative pressure foundation completion signal is effective, the 4th electric current
Path conducting；When the nonvolatile memory is non-piece of mode, the 4th current path is disconnected.
A further improvement is that the nonvolatile memory be programming mode and the negative pressure establish complete signal without
When effect, second current path and the third current path are all disconnected, and the first current path conducting makes described second
Positive voltage is 0V；The nonvolatile memory be programming mode and the negative pressure establish complete signal it is effective when, described the
One current path disconnects, and second current path and the third current path are all connected, and second positive voltage follows institute
The input signal for stating the second positive voltage of positive pressure charge pump generation changes and starts to target value.
When the nonvolatile memory is non-programmed mode, second current path, the third current path
It is all disconnected with the 4th current path, the first current path conducting makes the second positive voltage 0V.
A further improvement is that when programming signal is 1, the nonvolatile memory is programming mode, when the programming
The nonvolatile memory is non-programmed mode when signal is 0.
When block signal is 1, the nonvolatile memory is block mode, described non-volatile when the block signal is 0
Memory is non-piece of mode.
The negative pressure, which is established, to be completed when signal is 1 to be useful signal, and 0 when is invalid signals.
A further improvement is that it includes control signal generating circuit, the control that second positive voltage, which establishes control circuit,
Signal generating circuit processed includes:
First NAND gate, the first input end of first NAND gate, which connects the negative pressure, to be established and completes signal, and described the
Second input terminal of one NAND gate connects the programming signal.
Second phase inverter, the input terminal of second phase inverter connect the output end of first NAND gate.
The first input end of second NAND gate, second NAND gate connects the block signal, second NAND gate
Second input terminal connects the output end of second phase inverter；The output end of second NAND gate exports first control signal.
Third phase inverter, the input terminal of the third phase inverter connect the output end of second phase inverter, the third
The output end of phase inverter exports second control signal.
The first control signal controls the conducting and disconnection of the 4th current path, and the second control signal is simultaneously
Control the conducting and disconnection of first current path, second current path and the third current path.
A further improvement is that first current path includes the 4th NMOS tube, the source electrode of the 4th NMOS tube is connect
Ground, draining for the 4th NMOS tube connect the source electrode of second NMOS tube, described in the grid connection of the 4th NMOS tube
Second control signal.
Second current path includes the 5th NMOS tube and second current path is by the 6th NMOS tube and the 4th
The image current of 5th current path of PMOS tube composition；The source electrode of 5th NMOS tube is grounded, the 5th NMOS tube
Drain electrode connects the source electrode of second NMOS tube；The grid of 5th NMOS tube connects grid and the leakage of the 6th NMOS tube
The drain electrode of pole and the 4th PMOS tube, the source electrode ground connection of the 6th NMOS tube, the source electrode connection of the 4th PMOS tube
The grid of bias current sources, the 4th PMOS tube connects the second control signal；The electric current of 5th current path is big
The small size for the bias current sources, the conducting electric current size of second current path and leading for the 5th current path
Galvanization size is proportional.
The third current path includes the 5th PMOS tube, and the source electrode of the 5th PMOS tube connects supply voltage, described
The drain electrode of 5th PMOS tube connects the drain electrode of second NMOS tube, the grid connection of the 5th PMOS tube second control
Signal.
4th current path includes the 6th PMOS tube, and the source electrode of the 6th PMOS tube connects supply voltage, described
The drain electrode of 6th PMOS tube connects the drain electrode of the third NMOS tube, the grid connection of the 6th PMOS tube first control
Signal, the conducting electric current size of the 4th current path and the conducting electric current size of the third current path are proportional.
A further improvement is that the conducting electric current of the conducting electric current of second current path and the 5th current path
Ratio value pass through the ratio of the channel width-over-length ratio of the 5th NMOS tube and the channel width-over-length ratio of the 6th NMOS tube determine.
The ratio value of the conducting electric current of the conducting electric current and third current path of 4th current path passes through institute
The ratio for stating the channel width-over-length ratio of the 6th PMOS tube and the channel width-over-length ratio of the 5th PMOS tube determines.
A further improvement is that the storage unit of the storage array includes the storage tube and selecting pipe, it is same described
The source electrode of the storage tube of storage unit connects the drain electrode of the selecting pipe, and the grid with each storage tube of a line all connects
The first wordline mutually gone together is connect, the grid with each selecting pipe of a line all connects the second wordline mutually gone together, same row
The drain electrode of each storage tube all connects the bit line of same column, and the source electrode of each selecting pipe is all connected to source line.
The present invention is arranged in negative pressure charge pump and bears by the way that charge pump is divided into positive pressure charge pump and negative pressure charge pump
Pressure, which establishes completion signal generating circuit and the second positive voltage is arranged in positive pressure charge pump, establishes control circuit, can be realized
Third negative voltage, which is established, completes the starting for starting to carry out the second positive voltage long later, and such second positive voltage can be in third negative electricity
Zero is all remained in the start-up course of pressure, is reduced so as to make to share the electric leakage generated due to source electrode, so as to reduce third
Load of the negative voltage in startup stage, so as to eliminate charge pump there may be settling time it is too long or establish failure wind
Danger, to can guarantee good programing effect and guarantee that third negative electricity pressure energy reaches target value.
Detailed description of the invention
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
Fig. 1 is the V diagram of existing nonvolatile memory；
Fig. 2 is the charge pump circuit block diagram of nonvolatile memory of the embodiment of the present invention；
Fig. 3 is that charge pump circuit starts timing diagram in the embodiment of the present invention；
Fig. 4 is that the negative pressure in the embodiment of the present invention establishes completion signal generating circuit figure；
Fig. 5 is that the second positive voltage in the embodiment of the present invention establishes electric operation control circuit figure；
Fig. 6 is the control signal generating circuit that the second positive voltage in the embodiment of the present invention establishes control circuit.
Specific embodiment
As shown in Fig. 2, being the charge pump circuit block diagram of nonvolatile memory of the embodiment of the present invention；The embodiment of the present invention is non-
The charge pump circuit of volatile memory includes simultaneously positive pressure charge pump 104 and negative pressure charge pump 105, and positive pressure charge pump 104 exists
It is also indicated with VPOS PUMP in Fig. 2, negative pressure charge pump 105 is also indicated with VNEG PUMP in Fig. 2.
The positive pressure charge pump 104 provides the first positive voltage VPOS and the second positive voltage VBL, the negative pressure charge pump 105
Third negative voltage VNEG is provided；The first positive voltage VPOS is greater than the second positive voltage VBL；First positive voltage
VPOS, the second positive voltage VBL and the third negative voltage VNEG are supplied to the storage array of nonvolatile memory；Institute
That states the storage tube 102 of the storage unit of storage array writes 1 program voltage by the first positive voltage VPOS and the third
The difference of negative voltage VNEG determines that the first positive voltage VPOS is added on the grid of the corresponding storage tube 102, and the third is negative
Voltage VNEG is added on the bit line BL of the corresponding storage tube 102；The storage tube 102 writes 0 program voltage by described
The difference of one positive voltage VPOS and the second positive voltage VBL determines that the first positive voltage VPOS is added on the corresponding storage
The grid of pipe 102, the second positive voltage VBL are added on the bit line BL of the corresponding storage tube 102.
Include that negative pressure is established and completes signal generating circuit in the negative pressure charge pump 105, non-volatile is deposited described
When the starting of reservoir, the third negative voltage VNEG starts to start, described when the third negative voltage VNEG reaches target value
It is effective that the negative pressure that negative pressure establishes completion signal generating circuit output establishes completion signal Pump_good.
It include that the second positive voltage establishes control circuit in the positive pressure charge pump 104, in the nonvolatile memory
When starting, the first positive voltage VPOS starts to start and start to target value, and second positive voltage establishes control circuit
Input signal PRG2_VBL is that the negative pressure establishes completion signal Pump_good, establishes in the negative pressure and completes signal Pump_
Before good is effective, the second positive voltage VBL remains 0V；After negative pressure foundation completion signal Pump_good is effective,
The second positive voltage VBL starts to start and start to target value, by placing the starting timing of the second positive voltage VBL
The third negative voltage VNEG is reduced later in the load of startup stage what third negative voltage VNEG foundation was completed.Such as figure
It is that charge pump circuit starts timing diagram in the embodiment of the present invention, the time between two vertical dotted lines is the starting time shown in 3
Trise, it can be seen that VPOS starts to 7.2V from 1.5V, and VNEG starts to -4.5V from 0V, and VNEG reaches after -4.5V
Pump_good is switched to 1.5V by 0V, and at this moment, VBL starts to start to 1.2V from 0V.
As shown in figure 4, being the negative pressure foundation completion signal generating circuit figure in the embodiment of the present invention, the embodiment of the present invention
In, it includes a voltage comparator circuit that the negative pressure, which is established and completes signal generating circuit, and the voltage comparator circuit compares the first ratio
Compared with voltage V101 and the second reference voltage V102, the first comparison voltage V101 and third negative voltage VNEG in real time at than
Example and ratio value are the first value, and the target value of the second reference voltage V102 and the third negative voltage VNEG are proportional and compare
Example value is also the first value, and when the third negative voltage VNEG reaches target value, the output end of the voltage comparator circuit is exported
The negative pressure establish complete signal Pump_good by be switched in vain effectively.The voltage comparator circuit includes the first NMOS
The grid of pipe MN1 and the first PMOS tube MP1, the first NMOS tube MN1 connect the first comparison voltage V101, and described first
The source electrode of NMOS tube MN1 is grounded, and the grid of the first PMOS tube MP1 connects the second reference voltage V102, and described first
The source electrode of PMOS tube MP1 connects supply voltage VDD, the drain electrode of the first NMOS tube MN1 and the leakage of the first PMOS tube MP1
Pole, which is connected and exports the negative pressure in tie point, establishes completion signal Pump_good.
It further includes one first phase inverter 106, the second PMOS tube MP2 and third that the negative pressure, which is established and completes signal generating circuit,
PMOS tube MP3.
The input terminal of first phase inverter 106 connects the negative pressure and establishes completion signal Pump_good, and described first is anti-
The output end of phase device 106 exports the negative pressure and establishes the inversion signal for completing signal Pump_good.
The source electrode of the second PMOS tube MP2 connects supply voltage VDD, and the grid of the second PMOS tube MP2 connects institute
State the grid of the first PMOS tube MP1.
The source electrode of the third PMOS tube MP3 connects the drain electrode of the second PMOS tube MP2, the third PMOS tube MP3
Drain electrode connect the negative pressure and establish and complete signal Pump_good, the grid of the third PMOS tube MP3 connects the negative pressure and builds
The vertical inversion signal for completing signal Pump_good.
In the embodiment of the present invention, the negative pressure, which is established, to be completed when signal Pump_good is 1 to be useful signal, and 0 when is invalid
Signal.
As shown in figure 5, being that the second positive voltage in the embodiment of the present invention establishes electric operation control circuit figure；Second positive voltage is built
Vertical control circuit includes the second NMOS tube MN2, and the second NMOS tube MN2 connects to form voltage follower, the 2nd NMOS
The grid of pipe MN2 connects the input signal VBLIN for the second positive voltage VBL that the positive pressure charge pump 104 generates, and described second
The source electrode of NMOS tube MN2 exports the second positive voltage VBL, includes by simultaneously between the source electrode and ground of the second NMOS tube MN2
The first current path and the second current path of connection, connect between the drain electrode and supply voltage VDD of the second NMOS tube MN2
There is third current path.
When negative pressure foundation completion signal Pump_good is invalid, second current path and the third electric current
Path all disconnects, and the first current path conducting makes the second positive voltage VBL 0V.
When negative pressure foundation completion signal Pump_good is effective, first current path is disconnected, second electricity
Flow path and the third current path are all connected, the second positive voltage VBL follow that the positive pressure charge pump 104 generates the
The input signal VBLIN of two positive voltage VBL changes and starts to target value.
It further includes third NMOS tube MN3 that second positive voltage, which establishes control circuit, the third NMOS tube MN3 connection shape
At voltage follower, the grid of the third NMOS tube MN3 connects the second positive voltage VBL that the positive pressure charge pump 104 generates
The source electrode of input signal VBLIN, the third NMOS tube MN3 export the second positive voltage VBL, the third NMOS tube
The source electrode of MN3 connects the source electrode of the second NMOS tube MN2, the drain electrode of the third NMOS tube MN3 and supply voltage VDD it
Between be connected with the 4th current path.
When the nonvolatile memory is block mode and negative pressure foundation completion signal Pump_good is effective, institute
State the conducting of the 4th current path；When the nonvolatile memory is non-piece of mode, the 4th current path is disconnected.
When the nonvolatile memory is programming mode and negative pressure foundation completion signal Pump_good is invalid,
Second current path and the third current path all disconnect, and the first current path conducting makes second positive voltage
VBL is 0V；When the nonvolatile memory is programming mode and negative pressure foundation completion signal Pump_good is effective,
First current path disconnects, and second current path and the third current path are all connected, second positive voltage
The input signal VBLIN for the second positive voltage VBL that VBL follows the positive pressure charge pump 104 to generate changes and starts to target value.
When the nonvolatile memory is non-programmed mode, second current path, the third current path
It is all disconnected with the 4th current path, the first current path conducting makes the second positive voltage VBL 0V.
When programming signal PRG2 is 1, the nonvolatile memory is programming mode, when the programming signal PRG2 is 0
Shi Suoshu nonvolatile memory is non-programmed mode.
When block signal BULK is 1, the nonvolatile memory is block mode, when the block signal BULK be 0 when described in
Nonvolatile memory is non-piece of mode.
The negative pressure, which is established, to be completed when signal Pump_good is 1 to be useful signal, and 0 when is invalid signals.
It includes control signal generating circuit that second positive voltage, which establishes control circuit, for according to programming mode and block mould
The control model of formula generates corresponding control signal to control the on-off of first to fourth above-mentioned current path；As shown in fig. 6, being this
The second positive voltage in inventive embodiments establishes control signal generating circuit packet described in the control signal generating circuit of control circuit
It includes:
First NAND gate 107, the first input end of first NAND gate 107 connect the negative pressure and establish completion signal
The second input terminal of Pump_good, that is, signal PRG2_VBL, first NAND gate 107 connect the programming signal PRG2.
Second phase inverter 108, the input terminal of second phase inverter 108 connect the output end of first NAND gate 107.
Second NAND gate 110, the first input end of second NAND gate 110 connect the block signal BULK, and described the
Second input terminal of two NAND gates 110 connects the output end of second phase inverter 108；The output of second phase inverter 108
The signal of end output is signal PRG2VBL；The output end of second NAND gate 110 exports first control signal B_PRG2B.
Third phase inverter 109, the input terminal of the third phase inverter 109 connect the output end of second phase inverter 108,
The output end of the third phase inverter 109 exports second control signal PRG2B.
The first control signal B_PRG2B controls the conducting and disconnection of the 4th current path, second control
Signal PRG2B simultaneously control first current path, second current path and the third current path conducting and
It disconnects.
Preferably, as shown in figure 5, first current path includes the 4th NMOS tube MN4, the 4th NMOS tube MN4
Source electrode ground connection, the drain electrode of the 4th NMOS tube MN4 connects the source electrode of the second NMOS tube MN2, the 4th NMOS tube
The grid of MN4 connects the second control signal PRG2B.
Second current path includes the 5th NMOS tube MN5 and second current path is by the 6th NMOS tube MN6
With the image current of the 5th current path of the 4th PMOS tube MP4 composition；The source electrode of the 5th NMOS tube MN5 is grounded, described
The drain electrode of 5th NMOS tube MN5 connects the source electrode of the second NMOS tube MN2；The grid of the 5th NMOS tube MN5 connects institute
State grid and drain electrode and the drain electrode of the 4th PMOS tube MP4 of the 6th NMOS tube MN6, the source of the 6th NMOS tube MN6
Pole ground connection, the source electrode of the 4th PMOS tube MP4 connect bias current sources IBIAS, the grid connection of the 4th PMOS tube MP4
The second control signal PRG2B；The size of current of 5th current path is the size of the bias current sources IBIAS,
The conducting electric current size of second current path and the conducting electric current size of the 5th current path are proportional, as ratio is
1:3.
The third current path includes the 5th PMOS tube MP5, and the source electrode of the 5th PMOS tube MP5 connects supply voltage
The drain electrode of VDD, the 5th PMOS tube MP5 connect the drain electrode of the second NMOS tube MN2, the grid of the 5th PMOS tube MP5
Pole connects the second control signal PRG2B.
4th current path includes the 6th PMOS tube MP6, and the source electrode of the 6th PMOS tube MP6 connects supply voltage
The drain electrode of VDD, the 6th PMOS tube MP6 connect the drain electrode of the third NMOS tube MN3, the grid of the 6th PMOS tube MP6
Pole connects the first control signal B_PRG2B, the conducting electric current size of the 4th current path and third electric current road
The conducting electric current size of diameter is proportional, if ratio is 1:5.
The ratio value of the conducting electric current of second current path and the conducting electric current of the 5th current path passes through institute
The ratio for stating the channel width-over-length ratio of the 5th NMOS tube MN5 and the channel width-over-length ratio of the 6th NMOS tube MN6 determines.Described 4th
The ratio value of the conducting electric current of current path and the conducting electric current of the third current path passes through the 6th PMOS tube MP6's
The ratio of channel width-over-length ratio and the channel width-over-length ratio of the 5th PMOS tube MP5 determines.
The storage unit of the storage array includes the storage tube 102 and selecting pipe 103, the same storage unit
The source electrode of the storage tube 102 connects the drain electrode of the selecting pipe 103, and the grid with each storage tube 102 of a line all connects
The the first wordline WLS mutually to go together is met, the grid with each selecting pipe 103 of a line all connects the second wordline WL mutually to go together,
The drain electrode of each storage tube 102 of same row all connects the bit line BL of same column, and the source electrode of each selecting pipe 103 is all
It is connected to source line SL.In the embodiment of the present invention, the structure of the storage array uses structure identical with Fig. 1.Similarly, since depositing
Array is stored up by rows and columns, therefore the first wordline and the second wordline also have multirow respectively, every a line all respectively includes one first
In wordline WLS and one second wordline WL, Fig. 1 after WLS plus [x] and after WL plus [x] indicate the corresponding WLS of x-1 row or
WL, x are integers, show that two rows, corresponding x are respectively 0 and 1 in Fig. 1.Similarly, each column of storage array all include one
Two bit line BL are shown in bit line BL, Fig. 1, and add [even] to indicate the corresponding bit line of even column after BL, and [odd] is added to indicate
The corresponding bit line of odd column.
Equally, with the load current Ineg of negative pressure charge pump 105 in a specific example illustratively embodiment of the present invention,
Voltage value shown in table one with reference also to front, under Flash Bulk PRG mode are as follows:
The second all wordline WL voltages are all negative pressure VNEG, as negative pressure VNEG takes -4.3V.
The first all wordline WLS voltages are all positive high voltage VPOS, as positive high voltage VPOS takes 7.2V.
The voltage that each storage tube 102 is connected with the substrate of selecting pipe 103 i.e. underlayer voltage VBPW is negative pressure VNEG.
It defines and is programmed into 1, the voltage of bit line BL [0] is negative pressure VNEG, and even number even indicates 0 here, indicates that the 0th column add
1 can be written after negative pressure VNEG.
Definition is programmed into 0, and the voltage of bit line BL [1] is positive pressure VBL, if positive pressure VBL takes 1.2V, even number odd table here
Show 1,0 can be written after indicating the 1st column plus positive pressure VBL.
Source line SL floating (float).
The embodiment of the present invention optimizes the timing of starting, is established by VNEG module, that is, negative pressure charge pump 105 in VNEG
A signal Pump_good is generated after reaching target potential, the starting of voltage VBL is controlled by Pump_good signal.In signal
When Pump_good is invalid, VBL=0；When signal Pump_good is effective, VBL=1.2V.This timing, which can reduce, to be started
Ineg in journey, is described as follows:
Before voltage VNEG is established, the Ivbl of VBL=0, Ivbl electric current ratio VBL=1.2V are small.Voltage VPOS and
The stage that VNEG starting is established is similar to charge to the capacitor of memory cell array, wherein Ivneg=Ivpos+Ivbl；Due to
Ivbl becomes smaller, therefore Ivneg can become smaller.After voltage VNEG is established, Ivpos becomes smaller, so Ivneg can also become than before
It is small.In this way after voltage VPOS, VNEG and VBL are established, Ivneg ≈ Ivbl.
The present invention has been described in detail through specific embodiments, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (13)
1. a kind of charge pump circuit of nonvolatile memory, it is characterised in that: charge pump circuit includes simultaneously positive pressure charge pump
With negative pressure charge pump；
The positive pressure charge pump provides the first positive voltage and the second positive voltage, and the negative pressure charge pump provides third negative voltage；Institute
The first positive voltage is stated greater than second positive voltage；First positive voltage, second positive voltage and the third negative voltage
All it is supplied to the storage array of nonvolatile memory；The programming electricity for writing 1 of the storage tube of the storage unit of the storage array
Pressure determines that first positive voltage is added on the corresponding storage tube by the difference of first positive voltage and the third negative voltage
Grid, the third negative voltage is added on the bit line of the corresponding storage tube；The storage tube writes 0 program voltage by institute
The difference for stating the first positive voltage and second positive voltage determines that first positive voltage is added on the grid of the corresponding storage tube
Pole, second positive voltage are added on the bit line of the corresponding storage tube；
It include that a negative pressure establishes completion signal generating circuit in the negative pressure charge pump, in opening for the nonvolatile memory
When dynamic, the third negative voltage starts to start, and when the third negative voltage reaches target value, the negative pressure, which is established, completes signal
It is effective that the negative pressure of generation circuit output establishes completion signal；
It include that the second positive voltage establishes control circuit in the positive pressure charge pump, in the starting of the nonvolatile memory,
First positive voltage starts to start and start to target value, and second positive voltage is established the control circuit input negative pressure and built
Vertical to complete signal, before negative pressure foundation completion signal is effective, second positive voltage remains 0V；It is built in the negative pressure
It is vertical complete signal it is effective after, second positive voltage starts to start and start to target value, by by second positive voltage
Starting timing be placed on the third negative voltage establish complete reduce the third negative voltage later in the load of startup stage.
2. the charge pump circuit of nonvolatile memory as described in claim 1, it is characterised in that: the negative pressure, which is established, to be completed
Signal generating circuit includes a voltage comparator circuit, and the voltage comparator circuit compares the first comparison voltage and second with reference to electricity
Proportional and ratio value is the first value in real time for pressure, first comparison voltage and the third negative voltage, and described second with reference to electricity
It presses and the target value of the third negative voltage is proportional and ratio value is also the first value, when the third negative voltage reaches target value
When, the negative pressure of the output end output of the voltage comparator circuit, which is established, completes signal by being switched in vain effectively.
3. the charge pump circuit of nonvolatile memory as claimed in claim 2, it is characterised in that: the voltage comparator circuit
Including the first NMOS tube and the first PMOS tube, grid connection first comparison voltage of first NMOS tube, described first
The source electrode of NMOS tube is grounded, and the grid of first PMOS tube connects second reference voltage, the source of first PMOS tube
Pole connects supply voltage, and the drain electrode of first NMOS tube is connected and defeated in tie point with the drain electrode of the first PMOS pipe
The negative pressure, which is established, out completes signal.
4. the charge pump circuit of nonvolatile memory as claimed in claim 3, it is characterised in that: the negative pressure, which is established, to be completed
Signal generating circuit further includes one first phase inverter, the second PMOS tube and third PMOS tube；
The input terminal of first phase inverter connects the negative pressure and establishes completion signal, the output end output of first phase inverter
The negative pressure establishes the inversion signal for completing signal；
The source electrode of second PMOS tube connects supply voltage, and the grid of second PMOS tube connects first PMOS tube
Grid；
The source electrode of the third PMOS tube connects the drain electrode of second PMOS tube, described in the drain electrode connection of the third PMOS tube
Negative pressure, which is established, completes signal, and the grid of the third PMOS tube connects the negative pressure and establishes the inversion signal for completing signal.
5. the charge pump circuit of nonvolatile memory as claimed in claim 2 or 3 or 4, it is characterised in that: the negative pressure is built
Vertical to complete when signal is 1 to be useful signal, 0 when is invalid signals.
6. the charge pump circuit of nonvolatile memory as described in claim 1, it is characterised in that: second positive voltage is built
Vertical control circuit includes the second NMOS tube, and second NMOS tube connects to form voltage follower, the grid of second NMOS tube
Pole connects the input signal for the second positive voltage that the positive pressure charge pump generates, the source electrode output of second NMOS tube described the
Two positive voltages, include between the source electrode and ground of second NMOS tube by parallel the first current path and the second current path,
Third current path is connected between the drain electrode and supply voltage of second NMOS tube；
When the negative pressure establishes completion invalidating signal, second current path and the third current path are all disconnected, institute
Stating the conducting of the first current path makes the second positive voltage 0V；
When the negative pressure establish complete signal it is effective when, first current path disconnects, second current path and described
Third current path is all connected, the input signal for the second positive voltage that second positive voltage follows the positive pressure charge pump to generate
Change and starts to target value.
7. the charge pump circuit of nonvolatile memory as claimed in claim 6, it is characterised in that: second positive voltage is built
Vertical control circuit further includes third NMOS tube, and the third NMOS tube connects to form voltage follower, the third NMOS tube
Grid connects the input signal for the second positive voltage that the positive pressure charge pump generates, described in the source electrode output of the third NMOS tube
Second positive voltage, the source electrode of the third NMOS tube connect the source electrode of second NMOS tube, in the leakage of the third NMOS tube
The 4th current path is connected between pole and supply voltage；
When the nonvolatile memory is block mode and negative pressure foundation completion signal is effective, the 4th current path
Conducting；When the nonvolatile memory is non-piece of mode, the 4th current path is disconnected.
8. the charge pump circuit of nonvolatile memory as claimed in claim 7, it is characterised in that: non-volatile deposited described
Reservoir is programming mode and the negative pressure is established when completing invalidating signal, second current path and the third current path
It all disconnects, the first current path conducting makes the second positive voltage 0V；It is programming mould in the nonvolatile memory
Formula and the negative pressure establish complete signal it is effective when, first current path disconnects, second current path and described the
Three current paths are all connected, and the input signal for the second positive voltage that second positive voltage follows the positive pressure charge pump to generate becomes
Change and starts to target value；
When the nonvolatile memory is non-programmed mode, second current path, the third current path and institute
It states the 4th current path all to disconnect, the first current path conducting makes the second positive voltage 0V.
9. the charge pump circuit of nonvolatile memory as claimed in claim 8, it is characterised in that: when programming signal is 1
The nonvolatile memory is programming mode, and when the programming signal is 0, the nonvolatile memory is non-programmed mould
Formula；
When block signal is 1, the nonvolatile memory is block mode, the non-volatile memories when the block signal is 0
Device is non-piece of mode；
The negative pressure, which is established, to be completed when signal is 1 to be useful signal, and 0 when is invalid signals.
10. the charge pump circuit of nonvolatile memory as claimed in claim 9, it is characterised in that: second positive voltage
Establishing control circuit includes control signal generating circuit, and the control signal generating circuit includes:
First NAND gate, the first input end of first NAND gate, which connects the negative pressure, to be established and completes signal, described first with
Second input terminal of NOT gate connects the programming signal；
Second phase inverter, the input terminal of second phase inverter connect the output end of first NAND gate；
Second NAND gate, the first input end connection block signal of second NAND gate, the second of second NAND gate
Input terminal connects the output end of second phase inverter；The output end of second NAND gate exports first control signal；
Third phase inverter, the input terminal of the third phase inverter connect the output end of second phase inverter, the third reverse phase
The output end of device exports second control signal；
The first control signal controls the conducting and disconnection of the 4th current path, and the second control signal controls simultaneously
The conducting and disconnection of first current path, second current path and the third current path.
11. the charge pump circuit of nonvolatile memory as claimed in claim 10, it is characterised in that:
First current path includes the 4th NMOS tube, and the source electrode of the 4th NMOS tube is grounded, the 4th NMOS pipe
Drain electrode connects the source electrode of second NMOS tube, and the grid of the 4th NMOS tube connects the second control signal；
Second current path includes the 5th NMOS tube and second current path is by the 6th NMOS tube and the 4th PMOS
The image current of 5th current path of pipe composition；The source electrode of 5th NMOS tube is grounded, the drain electrode of the 5th NMOS tube
Connect the source electrode of second NMOS tube；The grid of 5th NMOS tube connect the 6th NMOS tube grid and drain electrode with
And the drain electrode of the 4th PMOS tube, the source electrode ground connection of the 6th NMOS tube, the source electrode of the 4th PMOS tube connect biasing
The grid of current source, the 4th PMOS tube connects the second control signal；The size of current of 5th current path is
The size of the bias current sources, the electric conduction of the conducting electric current size of second current path and the 5th current path
It is proportional to flow size；
The third current path includes the 5th PMOS tube, and the source electrode of the 5th PMOS tube connects supply voltage, and the described 5th
The drain electrode of PMOS tube connects the drain electrode of second NMOS tube, the grid connection of the 5th PMOS tube the second control letter
Number；
4th current path includes the 6th PMOS tube, and the source electrode of the 6th PMOS tube connects supply voltage, and the described 6th
The drain electrode of PMOS tube connects the drain electrode of the third NMOS tube, the grid connection of the 6th PMOS tube the first control letter
Number, the conducting electric current size of the 4th current path and the conducting electric current size of the third current path are proportional.
12. the charge pump circuit of nonvolatile memory as claimed in claim 11, it is characterised in that: second electric current road
The ratio value of the conducting electric current of diameter and the conducting electric current of the 5th current path is long by the ditch road width of the 5th NMOS tube
Ratio than the channel width-over-length ratio with the 6th NMOS tube determines；
The ratio value of the conducting electric current of the conducting electric current and third current path of 4th current path passes through described the
The ratio of the channel width-over-length ratio of the channel width-over-length ratio of six PMOS tube and the 5th PMOS tube determines.
13. the charge pump circuit of nonvolatile memory as described in claim 1, it is characterised in that: the storage array
Storage unit includes the storage tube and selecting pipe, and the source electrode of the storage tube of the same storage unit connects the selection
The drain electrode of pipe, the grid with each storage tube of a line all connect the first wordline mutually gone together, with each selection of a line
The grid of pipe all connects the second wordline mutually gone together, and the drain electrode of each storage tube of same row all connects institute's rheme of same column
The source electrode of line, each selecting pipe is all connected to source line.
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| CN109994135B (en) * | 2017-12-29 | 2023-03-24 | 紫光同芯微电子有限公司 | Positive and negative pressure charge pump voltage stabilizing circuit |
| KR102523373B1 (en) * | 2018-11-13 | 2023-04-18 | 삼성전기주식회사 | Negative voltage circuit |
| CN111681698B (en) * | 2020-05-25 | 2022-05-20 | 上海华虹宏力半导体制造有限公司 | Positive and negative voltage generating circuit |
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| US5414669A (en) * | 1993-09-10 | 1995-05-09 | Intel Corporation | Method and apparatus for programming and erasing flash EEPROM memory arrays utilizing a charge pump circuit |
| CN102355127B (en) * | 2011-09-28 | 2016-08-03 | 上海华虹宏力半导体制造有限公司 | Charge pump circuit |
| US8811093B2 (en) * | 2012-03-13 | 2014-08-19 | Silicon Storage Technology, Inc. | Non-volatile memory device and a method of operating same |
| CN103904870B (en) * | 2012-12-28 | 2016-12-28 | 北京兆易创新科技股份有限公司 | A kind of charge pump circuit system |
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