CN107154436B - Semiconductor transistor with double gate electrodes and manufacturing method thereof - Google Patents
Semiconductor transistor with double gate electrodes and manufacturing method thereof Download PDFInfo
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- CN107154436B CN107154436B CN201710317833.4A CN201710317833A CN107154436B CN 107154436 B CN107154436 B CN 107154436B CN 201710317833 A CN201710317833 A CN 201710317833A CN 107154436 B CN107154436 B CN 107154436B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 6
- 230000009977 dual effect Effects 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 2
- 238000009413 insulation Methods 0.000 claims 1
- 239000004020 conductor Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
Abstract
The invention discloses a semiconductor transistor with double gate electrodes, which comprises a substrate and a first gate electrode positioned on the substrate; trap regions are arranged on two sides of the first gate electrode, a first gate insulating layer is arranged on the trap regions and the first gate electrode, an oxide layer is arranged on the first gate insulating layer, a drain electrode and a source electrode are respectively arranged on two sides of the oxide layer, a semiconductor layer is arranged on the oxide layer, a second gate insulating layer is arranged on the semiconductor layer, and a second gate electrode is arranged on the second gate insulating layer; and an insulating layer covers the first gate insulating layer, the drain electrode, the source electrode and the second gate electrode, a connecting hole is formed in the insulating layer, and a metal conducting layer is arranged on the inner wall of the connecting hole. The invention has the characteristics of low power consumption, convenient manufacture, simple structure and low cost through the structural design of the semiconductor transistor with the double-gate electrode, and reduces the manufacturing process and the complexity of the semiconductor transistor.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a semiconductor transistor with double gate electrodes and a manufacturing method thereof.
Background
Semiconductor refers to a material having a conductive property between a conductor and an insulator at normal temperature. Semiconductors are used in a wide variety of applications, such as diodes, which are devices made using semiconductors, which refers to a material whose conductivity can be controlled, ranging from insulators to conductors.
The development of semiconductor integrated circuits requires higher and higher low-power devices, and the working principle of the conventional semiconductor device basically uses diffusion and drift as a main carrier transmission mechanism, so that the working current of the device is larger, and the larger power consumption is also caused. As the size of the semiconductor device is smaller and smaller, various leakage currents become larger and larger, and thus the current device research field in the aspect of low power consumption of the semiconductor device mainly focuses on reducing the leakage current of the device.
In addition, the semiconductor transistor has the problems of poor stability, complex manufacturing process, high manufacturing cost, complex structure and the like in the working process, and in order to solve the problems in the semiconductor transistor, a semiconductor transistor with a double gate electrode and a manufacturing method thereof are designed.
Disclosure of Invention
The invention aims to provide a semiconductor transistor with double gate electrodes and a manufacturing method thereof, which solve the problems of high power consumption, complex manufacturing process and high cost of the semiconductor transistor with the double gate electrodes.
The purpose of the invention can be realized by the following technical scheme:
a semiconductor transistor of double gate electrode, including the substrate and first gate electrode on the said substrate;
a trap region is arranged on one side of the first gate electrode, a first gate insulating layer is arranged on the trap region and the first gate electrode, an oxide layer is arranged on the first gate insulating layer, a drain electrode and a source electrode are respectively arranged on two sides of the oxide layer, a semiconductor layer is arranged on the oxide layer, a second gate insulating layer is arranged on the semiconductor layer, and a second gate electrode is arranged on the second gate insulating layer;
an insulating layer covers the first gate insulating layer, the drain electrode, the source electrode and the second gate electrode, and a first connecting hole, a second connecting hole, a third connecting hole and a fourth connecting hole are respectively formed in the positions, corresponding to the first gate insulating layer, the drain electrode, the source electrode and the second gate electrode, of the insulating layer;
and metal conducting layers are respectively arranged on the inner walls of the first connecting hole, the second connecting hole, the third connecting hole and the fourth connecting hole.
Further, the first connecting hole, the second connecting hole, the third connecting hole and the fourth connecting hole are the same in size, and the cross-sectional shape is circular or rectangular.
Further, the cross-sectional dimensions of the first connection hole, the second connection hole, the third connection hole and the fourth connection hole are respectively smaller than the dimensions of the first gate insulating layer, the drain electrode, the source electrode and the second gate electrode.
Furthermore, the thickness of the metal conducting layer is less than or equal to one half of the size of the connecting hole.
A method for manufacturing a semiconductor transistor with double gate electrodes comprises the following steps:
step S1: selecting a substrate, forming a first gate electrode above the substrate, and removing an oxide layer film on the surface of the substrate by an etching method;
step S2: determining the position of a trap region on one side of the first gate electrode by using a photoetching technology, and forming the trap region;
step S3: forming a first gate insulating layer over the trap region and the first gate electrode by a deposition method;
step S4: forming an oxide layer on the first gate insulating layer by a deposition method, and etching the oxide layer;
step S5: forming a drain electrode and a source electrode on both sides of the oxide layer;
step S6: forming a semiconductor layer above the oxide layer, forming a second gate insulating layer above the semiconductor layer, and forming a second gate electrode above the second gate insulating layer;
step S7: an insulating layer covers the first gate insulating layer, the drain electrode, the source electrode and the second gate electrode;
step S8: and the insulating layers above the drain electrode, the source electrode, the first gate electrode and the second gate electrode are respectively provided with a first connecting hole, a second connecting hole, a third connecting hole and a fourth connecting hole, and a metal conducting layer is arranged in the connecting holes.
Further, the drain electrode and the source electrode on both sides of the oxide layer are not in contact.
Further, the first gate insulating layer and the second gate insulating layer both adopt aluminum oxide films.
The invention has the beneficial effects that:
the semiconductor transistor structure of the double-gate electrode is reasonably designed, so that the current passing through the semiconductor transistor is reduced, and the semiconductor transistor structure has the characteristic of low power consumption and has good compatibility with the traditional MOS transistor; the two gate electrodes are respectively arranged on different layers, and the overlapping parts among the source electrode, the gate electrode and the drain electrode are less, so that the response speed of the semiconductor is improved; the semiconductor transistor has the characteristics of convenience in manufacture, simple structure and low cost, greatly reduces the manufacturing process and complexity of the semiconductor transistor with the double-gate electrode and has important significance in the future.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of a semiconductor transistor with dual gate electrodes according to the present invention;
FIG. 2 is a flow chart of a method for fabricating a semiconductor transistor with dual gate electrodes according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, the present invention is a semiconductor transistor with a dual gate electrode, including a substrate 1, a first gate electrode 2 disposed above the substrate 1, a trap region 3 disposed on one side of the first gate electrode 2, a first gate insulating layer 4 disposed above the trap region 3 and the first gate electrode 2, an oxide layer 5 disposed on an upper end of the first gate insulating layer 4, a drain electrode 6 and a source electrode 7 disposed on two sides of the oxide layer 5, a semiconductor layer 8 disposed on the oxide layer 5, a second gate insulating layer 9 disposed on the semiconductor layer 8, and a second gate electrode 10 disposed on the second gate insulating layer 9;
the insulating layer 11 covers the first gate insulating layer 4, the drain electrode 6, the source electrode 7 and the second gate electrode 10, the insulating layer 11 is of a horizontal structure, the insulating layer 11 is respectively provided with a first connecting hole 121, a second connecting hole 122, a third connecting hole 123 and a fourth connecting hole 124, the lower ends of the first connecting hole 121, the second connecting hole 122, the third connecting hole 123 and the fourth connecting hole 124 are respectively connected with the first gate insulating layer 4, the drain electrode 6, the source electrode 7 and the second gate electrode 10, the cross sections of the first connecting hole 121, the second connecting hole 122, the third connecting hole 123 and the fourth connecting hole 124 are of a circular or rectangular structure, and the cross section sizes of the connecting holes are smaller than the size of the corresponding electrodes;
the inner walls of the first connection hole 121, the second connection hole 122, the third connection hole 123 and the fourth connection hole 124 are respectively provided with a metal conductive layer 13, the thickness of the metal conductive layer 13 is less than or equal to one half of the size of the connection holes, and the electrodes of the semiconductor transistor are respectively connected with external circuits by respectively connecting the connection lines with the metal conductive layer 13.
As shown in fig. 2, a method for manufacturing a semiconductor transistor with dual gate electrodes includes the following steps:
step S1: selecting an N-type or P-type substrate 1, forming a first gate electrode 2 above the substrate 1, and removing an oxide layer film on the surface of the substrate 1 by an etching method;
step S2: determining the position of the trap region 3 on one side of the first gate electrode 2 by photoetching technology, forming the trap region 3, and changing the characteristic of the trap region 3 by controlling the concentration of the trap region 3;
step S3: forming a first gate insulating layer 4 over the trap region 3 and the first gate electrode 2 by a deposition method;
step S4: forming an oxide layer 5 on the first gate insulating layer 4 by a deposition method, and etching the oxide layer 5 to partially cover the first gate insulating layer 4 with the oxide layer 5;
step S5: forming a drain electrode 6 and a source electrode 7 on two sides of the oxide layer 5 to ensure that the drain electrode 6 is not in contact with the source electrode 7;
step S6: forming a semiconductor layer 8 above the oxide layer 5, forming a second gate insulating layer 9 above the semiconductor layer 8, and forming a second gate electrode 10 above the second gate insulating layer 9;
step S7: an insulating layer 11 covers the first gate insulating layer 4, the drain electrode 6, the source electrode 7 and the second gate electrode 10;
step S8: a first connection hole 121, a second connection hole 122, a third connection hole 123 and a fourth connection hole 124 are respectively formed in the insulating layer 11 above the drain electrode 6, the source electrode 7, the first gate electrode 2 and the second gate electrode 10, and a metal conductive layer 13 is disposed in the connection holes.
The semiconductor transistor structure of the double-gate electrode is reasonably designed, so that the current passing through the semiconductor transistor is reduced, and the semiconductor transistor structure has the characteristic of low power consumption and has good compatibility with the traditional MOS transistor; the two gate electrodes are respectively arranged on different layers, and the overlapping parts among the source electrode, the gate electrode and the drain electrode are less, so that the response speed of the semiconductor is improved; the semiconductor transistor has the characteristics of convenience in manufacture, simple structure and low cost, greatly reduces the manufacturing process and complexity of the semiconductor transistor with the double-gate electrode and has important significance in the future.
The foregoing is merely exemplary and illustrative of the principles of the present invention and various modifications, additions and substitutions of the specific embodiments described herein may be made by those skilled in the art without departing from the principles of the present invention or exceeding the scope of the claims set forth herein.
Claims (4)
1. A semiconductor transistor with dual gate electrodes, comprising: comprises a substrate (1) and a first gate electrode (2) positioned on the substrate (1);
a trap region (3) is arranged on one side of the first gate electrode (2), a first gate insulating layer (4) is arranged on the trap region (3) and the first gate electrode (2), an oxide layer (5) is arranged on the first gate insulating layer (4), a drain electrode (6) and a source electrode (7) are respectively arranged on two sides of the oxide layer (5), a semiconductor layer (8) is arranged on the oxide layer (5), a second gate insulating layer (9) is arranged on the semiconductor layer (8), and a second gate electrode (10) is arranged on the second gate insulating layer (9);
an insulating layer (11) covers the first gate insulating layer (4), the drain electrode (6), the source electrode (7) and the second gate electrode (10), and a first connecting hole (121), a second connecting hole (122), a third connecting hole (123) and a fourth connecting hole (124) are respectively formed in the positions, corresponding to the first gate insulating layer (4), the drain electrode (6), the source electrode (7) and the second gate electrode (10), on the insulating layer (11);
the inner walls of the first connecting hole (121), the second connecting hole (122), the third connecting hole (123) and the fourth connecting hole (124) are respectively provided with a metal conducting layer (13);
the first connecting hole (121), the second connecting hole (122), the third connecting hole (123) and the fourth connecting hole (124) are the same in size, and the cross section of the first connecting hole is circular or rectangular;
the cross-sectional sizes of the first connecting hole (121), the second connecting hole (122), the third connecting hole (123) and the fourth connecting hole (124) are respectively smaller than the sizes of the first gate insulating layer (4), the drain electrode (6), the source electrode (7) and the second gate electrode (10);
the thickness of the metal conducting layer (13) is less than or equal to one half of the size of the connecting hole.
2. The method of fabricating a semiconductor transistor with dual gate electrodes as claimed in claim 1, comprising the steps of:
step S1: selecting a substrate (1), forming a first gate electrode (2) above the substrate (1), and removing an oxide layer film on the surface of the substrate (1) by an etching method;
step S2: determining the position of a trap region (3) on one side of the first gate electrode (2) through a photoetching technology, and forming the trap region (3);
step S3: forming a first gate insulation layer (4) over the trap region (3) and the first gate electrode (2) by a deposition method;
step S4: forming an oxide layer (5) on the first gate insulating layer (4) by a deposition method, and etching the oxide layer (5);
step S5: forming a drain electrode (6) and a source electrode (7) on both sides of the oxide layer (5);
step S6: forming a semiconductor layer (8) above the oxide layer (5), forming a second gate insulating layer (9) above the semiconductor layer (8), and forming a second gate electrode (10) above the second gate insulating layer (9);
step S7: an insulating layer (11) covers the first gate insulating layer (4), the drain electrode (6), the source electrode (7) and the second gate electrode (10);
step S8: a first connecting hole (121), a second connecting hole (122), a third connecting hole (123) and a fourth connecting hole (124) are formed in the insulating layer (11) above the drain electrode (6), the source electrode (7), the first gate electrode (2) and the second gate electrode (10) respectively, and a metal conducting layer (13) is arranged in the connecting holes.
3. The method of claim 2, wherein the method further comprises: the drain electrode (6) and the source electrode (7) on the two sides of the oxide layer (5) are not in contact.
4. The method of claim 2, wherein the method further comprises: the first gate insulating layer (4) and the second gate insulating layer (10) both adopt aluminum oxide films.
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| CN201710317833.4A CN107154436B (en) | 2017-05-08 | 2017-05-08 | Semiconductor transistor with double gate electrodes and manufacturing method thereof |
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| CN201710317833.4A CN107154436B (en) | 2017-05-08 | 2017-05-08 | Semiconductor transistor with double gate electrodes and manufacturing method thereof |
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| CN107154436B true CN107154436B (en) | 2020-04-03 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465776A (en) * | 2014-12-12 | 2015-03-25 | 西安邮电大学 | Manufacturing method of semiconductor device with double gate electrodes and application of semiconductor device with double gate electrodes |
| CN105264668A (en) * | 2013-05-20 | 2016-01-20 | 株式会社半导体能源研究所 | Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100585107B1 (en) * | 2003-11-13 | 2006-05-30 | 삼성전자주식회사 | Method for manufacturing local SONOS device using self aligning |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105264668A (en) * | 2013-05-20 | 2016-01-20 | 株式会社半导体能源研究所 | Semiconductor device |
| CN104465776A (en) * | 2014-12-12 | 2015-03-25 | 西安邮电大学 | Manufacturing method of semiconductor device with double gate electrodes and application of semiconductor device with double gate electrodes |
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Effective date of registration: 20220623 Address after: 230000 Room 301 and 302, building 4, phase I, mechanical and Electrical Industrial Park, No. 767, Yulan Avenue, high tech Zone, Hefei City, Anhui Province Patentee after: Hefei Huayu Semiconductor Co.,Ltd. Address before: 6 / F, building B, public service and applied technology R & D Center for scientific and technological innovation, Hewu Beng Experimental Zone, 860 Wangjiang West Road, high tech Zone, Hefei City, Anhui Province, 230000 Patentee before: HEFEI HUADA SEMICONDUCTOR Co.,Ltd. |
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Address after: 230000, No. 66 Tiantangzhai Road, High tech Zone, Hefei City, Anhui Province Patentee after: Hefei Huayu Semiconductor Co.,Ltd. Country or region after: China Address before: 230000 Room 301 and 302, building 4, phase I, mechanical and Electrical Industrial Park, No. 767, Yulan Avenue, high tech Zone, Hefei City, Anhui Province Patentee before: Hefei Huayu Semiconductor Co.,Ltd. Country or region before: China |