CN107154276A

CN107154276A - Semiconductor device and memory access control method

Info

Publication number: CN107154276A
Application number: CN201710126513.0A
Authority: CN
Inventors: 坪井幸利; 滨崎博幸
Original assignee: Renesas Electronics Corp
Current assignee: Renesas Electronics Corp
Priority date: 2016-03-02
Filing date: 2017-03-02
Publication date: 2017-09-12
Anticipated expiration: 2037-03-02
Also published as: EP3223157A3; US10379941B2; US20190317854A1; CN107154276B; EP3223157B1; EP3223157A2; US10942802B2; JP6605359B2; US20170255509A1; JP2017156984A

Abstract

The present invention relates to a kind of semiconductor device and memory access control method, it is intended to detects failure of the address signal system in memory access.Included according to the semiconductor device of the present invention：Address conversion circuit, based on being generated for the first address of data storage for error detection code to be stored into the second address in memory；Write circuit, writes data into the first address and error detection code is write into the second address；And reading circuit, the data from the first address are read, reads and comes from two address error detection code, and detect mistake based on data and error detection code.The value of at least one that address conversion circuit passes through the first address of modification, so that the storage location of error detection code is displaced to the storage location of the data, and by invert the value of the position of the defined quantity among other positions or quantity as defined in making position order rearrangement, to generate address as the second address.

Description

Semiconductor device and memory access control method

The cross reference of related application

The Japanese patent application NO.2016-039566 submitted on March 2nd, 2016 including specification, accompanying drawing and summary Disclosure of that is hereby incorporated by reference in their entirety.

Background technology

For example, the present invention relates to a kind of semiconductor device and memory access control method, and be related to data and by The technology of the error detection code storage of data generation in memory.

Patent document 1 is disclosing a kind of memorizer control circuit as an example, as shown in Fig. 4 of patent document 1 in the past 's.The memorizer control circuit includes address/control line control circuit and ECC circuit.When by address and data from CPU send to During memorizer control circuit, ECC circuit generates ECC data from data and is written into the specified address of memory.Work as reading During data, ECC circuit is by the new ECC data of the data creation read from memory, and the ECC numbers that will be read from memory It is compared according to the ECC data with newly creating, and carries out the correction of error detection and data.

However, in the memorizer control circuit, having a problem that, it is used in address/control line control circuit by ground Location is specified in any line into the address signal line of memory, when being worth persistent fault generation, it is difficult to detect that address is wrong By mistake.Because being specified by data and by the ECC data write-in of data creation to the address of memory；Therefore, even if never Meet expected address reading data and ECC data, be compared by the ECC data read and the ECC data that newly creates When, it will not also detect difference.

Herein, in order to solve this problem, the computer system disclosed in patent document 1 respectively specifies that the ground of write-in data Location and the address of write-in ECC data.However, when solving the above problems, the technology and technology disclosed in this specification are complete It is different.

(patent document 1) Japanese patent application discloses No.Hei5 (1993) -88992.

The content of the invention

As described above, the technology disclosed in patent document 1 has a problem, it is difficult to detect address signal system in storage Failure in device access.

By the explanation and accompanying drawing of this specification, other problems and new feature of the invention will become apparent.

According to one embodiment, semiconductor device is used at least one of the first address of data storage by modification Value, so that the storage location of error detection code is displaced to the storage location of data, and by making the regulation among other positions Quantity position value reversion or quantity as defined in making position order, to generate address as storing error detection generation Second address of code.

According to one embodiment, failure of the address signal system in memory access can be detected.

Brief description of the drawings

Fig. 1 is the block diagram for the configuration for showing the cpu system according to embodiment 1；

Fig. 2 is the block diagram for the configuration for showing the I/F change-over circuits according to embodiment 1；

Fig. 3 is the block diagram for the configuration for showing the ADR circuit for reversing according to embodiment 1；

Fig. 4 is the concept map mapped according to the memory of the internal storage of embodiment 1；

Fig. 5 is the concept map for the operation for showing the I/F change-over circuits according to embodiment 1；

Fig. 6 is the concept map for showing the operation when being not carried out ADR reversions；

Fig. 7 is to show the accompanying drawing changed according to value of the address signal of embodiment 1 when stuck-at fault occurs；

Fig. 8 is to show value of the address signal when fixed (stuck-at) failure occurs when being not carried out ADR reversions The accompanying drawing of change；

Fig. 9 is the block diagram for the configuration for showing the I/F change-over circuits according to embodiment 2；

Figure 10 is the block diagram for the configuration for showing the ADR rotation circuits according to embodiment 2；

Figure 11 is the concept map mapped according to the memory of the internal storage of embodiment 2；

Figure 12 is the concept map (the first example) for the operation for showing the I/F change-over circuits according to embodiment 2；

Figure 13 is to show the accompanying drawing (the changed according to value of the address signal of embodiment 2 when stuck-at fault occurs One example)；

Figure 14 is the concept map (the second example) for the operation for showing the I/F change-over circuits according to embodiment 2；

Figure 15 is the concept map (the second example) for showing the operation when performing ADR reversions；

Figure 16 is to show the accompanying drawing (the changed according to value of the address signal of embodiment 2 when stuck-at fault occurs Two examples)；

Figure 17 is the accompanying drawing for showing value change of the address signal when stuck-at fault occurs when performing ADR reversions (the second example)；

Figure 18 is the block diagram for the configuration for showing the ADR rotation circuits according to embodiment 3；

Figure 19 is the concept map mapped according to the memory of the internal storage of embodiment 3；

Figure 20 is to show the accompanying drawing changed according to value of the address signal of embodiment 3 when stuck-at fault occurs；

Figure 21 be show according to value of the address signal of embodiment 3 when another stuck-at fault occurs change it is attached Figure；

Figure 22 is the block diagram for the configuration for showing the I/F change-over circuits according to embodiment 4；

Figure 23 is the block diagram for the configuration for showing the ADR positions order circuit for reversing according to embodiment 4；

Figure 24 is the block diagram for the configuration for showing another ADR order circuit for reversing according to embodiment 4；

Figure 25 is the accompanying drawing for the address bit altered form for showing 2 bit address；

Figure 26 is the accompanying drawing for the address bit altered form for showing 3 bit address；

Figure 27 is the accompanying drawing for the address bit altered form for showing 4 bit address；

Figure 28 is the accompanying drawing for the formula for showing the quantity for calculating address bit altered form；

Figure 29 is the block diagram for the configuration for showing the ADR rotation circuits according to embodiment 5；

Figure 30 is the block diagram for the configuration for showing another ADR rotation circuits according to embodiment 5；

Figure 31 is the concept map mapped according to the memory of the internal storage of embodiment 5；

Figure 32 is the block diagram for the configuration for showing the I/F change-over circuits according to embodiment 6；

Figure 33 is to show to shift the block diagram that ＆ skews set the configuration of circuit according to the ADR of embodiment 6；

Figure 34 is the block diagram for the configuration for showing the ADR displacement ＆ skew setting circuits when N=4 position；

Figure 35 is the concept map mapped according to the memory of the internal storage of embodiment 6；

Figure 36 is to show the accompanying drawing changed according to value of the address signal of embodiment 6 when stuck-at fault occurs；

Figure 37 is the block diagram for the configuration for showing the ADR change-over circuits in I/F change-over circuits according to embodiment 7；

Figure 38 is to show to shift the block diagram that ＆ skews set the configuration of circuit according to the ADR of embodiment 7；

Figure 39 is the concept map mapped according to the memory of the internal storage of embodiment 7；

Figure 40 is to show to shift the block diagram that ＆ skews set the configuration of circuit according to the ADR of embodiment 8；

Figure 41 is the block diagram for the configuration for showing the I/F change-over circuits according to embodiment 9；

Figure 42 is to show the block diagram that the configuration for setting circuit is offset according to the ADR reverse shifts ＆ of embodiment 9；

Figure 43 is to show to shift the block diagram that ＆ skews set the configuration of circuit according to the ADR of embodiment 10；

Figure 44 is the block diagram for the configuration for showing the ADR selection circuits according to embodiment 10；

Figure 45 is the block diagram for the configuration for showing the cpu system according to embodiment 11；

Figure 46 is the block diagram for the configuration for showing the change-over circuit according to embodiment 11；

Figure 47 is the accompanying drawing for explaining the effect of embodiment 11；

Figure 48 is the block diagram for the configuration for showing the I/F change-over circuits according to embodiment 12；

Figure 49 is the concept map mapped according to the memory of the internal storage of embodiment 12；

Figure 50 is the accompanying drawing for showing the change carried out by address conversion to address according to embodiment 12；And

Figure 51 is used as the accompanying drawing of the semiconductor device of the general introduction configuration of embodiment 1 to 12.

Embodiment

Hereinafter, preferred embodiment is explained referring to the drawings.The concrete numerical value shown in the examples below is only profit In the example for understanding embodiment, rather than the limitation to value, unless otherwise expressly provided.Be described below with accompanying drawing, in order to Clarification explaination, is suitably abridged and is write a Chinese character in simplified form to the obvious content of those skilled in the art.

First, the configuration and operation of embodiment 1 are explained referring to the drawings.Reference picture 1, explain according to the CPU of embodiment 1 (in Central Processing Unit) system configuration.As shown in figure 1, cpu system 1 includes CPU 10, control input I/F 11, order output I/F 12nd, I/F change-over circuits 13, internal storage 14, DMAC (DMA controller) 15, other various peripheral circuits 16 and other various I/F 17.

It is CPU 10, control input I/F 11, order output I/F 12, I/F change-over circuits 13, DMAC 15, other various outer Enclose circuit 16 and other various I/F 17 intercouple via system bus.The internal storage 14 is via I/F change-over circuits 13 Coupled with system bus.

Embodiment 1 illustrates the example as the vehicle control syetem in vehicle using cpu system 1.However, showing Example is not limited to this.Cpu system 1 may be mounted in any equipment, and any equipment includes：Input block, the input block For entering data into cpu system 1；And control unit, cpu system 1 is based on the data inputted from input block come to this Control unit is controlled that (equipment includes：For example, transmission mechanical (such as vehicle or motorcycle), construction machinery (such as heavy type Industrial machine) or industrial machinery (such as manufacture machine people)).As long as equipment includes memory and addressable to memory Device (for example, CPU), cpu system 1 can just be mounted in any equipment information processing system (for example, information equipment, Such as personal computer or smart phone).

For example, cpu system 1 is set up in microcontroller (semiconductor device).Then, the cpu system 1 can control car , cooperated with other microcontrollers (" sub- microcomputer " in Fig. 1).

Input block is mounted in the device in vehicle.Input block receives the control of the instruction control unit from user Input.For example, input block is key unit or switch (" SW " in Fig. 1).In response to the input from user, input is single Member transmits the input data for indicating input content to cpu system 1.

Control unit is mounted in the device in vehicle.Control unit is controlled by cpu system 1.For example, control unit is door Or mirror.The input content that cpu system 1 is indicated based on the input data by being received from input block, is used as indicating to generate The order of the control data of the control content of control unit, and the order of generation is transmitted to control unit.In response to from The order of cpu system 1, control unit is operated according to the control content indicated by order.

CPU 10 generates control data based on entering data to from input block.For example, when control data is directed to door When, the generations of CPU 10 indicate that the control data that door is opened and closed is used as control content.For example, when control data is directed to mirror, The control data of the position of the generation instruction regulation mirrors of CPU 10 is used as control content.

Control input I/F 11 is the interface circuit that input block is coupled to system bus.That is, control unit will be entered The input data of row control is inputted to control input I/F 11 from input block.Order output I/F 12 is with being by control unit The interface circuit of bus of uniting coupling.That is, order output I/F 12 to the order that control unit is controlled by for exporting to control Unit processed.

I/F change-over circuits 13 are the interface circuits for coupling internal storage 14 with system bus.In response to CPU will be come from The request of the data of each write-in in 10 and DMAC 15, I/F change-over circuits 13 write data into internal storage 14 In.Request in response to reading data from each in CPU 10 and DMAC 15, I/F change-over circuits 13 are from internal storage 14 read data.When accessing internal storage 14 (by number in response to the request of each in CPU 10 and DMAC 15 Data are read according to write-in internal storage 14 or from internal storage 14) when, I/F change-over circuits 13 are performed for detecting in number According to the processing of the failure in signal system and address signal system.

More specifically, when I/F change-over circuits 13 are write data into internal storage 14, I/F change-over circuits 13 are also The ECC generated by data (improper correction code) is written in internal storage 14.When I/F change-over circuits 13 are from storage inside When device 14 reads data, I/F change-over circuits 13 are from reading data generation ECC, and by that the ECC of generation and will have been written into ECC in internal storage 14 with data is compared to detect failure.In embodiment 1, as will be described later, lead to The address from the address of data storage generation storage ECC is crossed, the failure in data signal system can be not only detected, can be with Detect the failure in address signal system.

Internal storage 14 is the storage circuit of various types of data of being stored with.That is, for example, above-mentioned input data, control Data (order) processed, ECC etc. are stored in internal storage 14.

DMAC 15 realizes the data transfer among coupled to the circuit 10 to 13 of system bus, 16 and 17.For example, DMAC 15 will be transferred to I/F change-over circuits 13 from the input data that input block is inputted to control input I/F 11, and ask The input data of transmission is written in internal storage 14 by I/F change-over circuits 13.For example, DMAC 15 asks I/F change-over circuits 13 from the reading order of internal storage 14, and the order read from I/F change-over circuits 13 is transferred into order output I/F 12.Therefore, by order output to control unit.

Herein, CPU 10 asks I/F change-over circuits 13 to read the input number being stored in by DMAC 15 in internal storage 14 According to, and obtain the input data read by I/F change-over circuits 13.CPU 10 enters data to generation life based on what is got Order, and ask I/F change-over circuits 13 that the order of generation is written in internal storage 14.Therefore, it is stored in storage inside Order in device 14 is transmitted by DMAC 15, as described above.

Cpu system 1 can be used as other various peripheral circuits 16 including any circuit.Other various I/F 17 are to set Other units (such as sub- microcomputer) in vehicle control syetem are coupled to the interface circuit of system bus.

As described above, CPU 10 and DMAC 15 are operated as bus master controller.The conduct of other circuits 11 to 13,16 and 17 Bus slave is operated.

Next, reference picture 2, explains the configuration of the I/F change-over circuits 13 according to embodiment 1.As shown in Fig. 2 I/F is changed Circuit 13 includes I/F controls circuit 110, ADR change-over circuits 120, WDT change-over circuits 130 and RDT change-over circuits 140.Herein, " ADR ", " WDT " and " RDT " is to indicate respectively address, write-in data and the abbreviation title for reading data.

Bus master controller will enable (selection) signal, write-in/reading signal, address signal and write-in via system bus Data output is to I/F change-over circuits 13.I/F change-over circuits 13 will wait # signals via system bus, read data and mistake Notification signal is exported to bus master controller.I/F change-over circuits 13 and internal storage 14 with from clock forming circuit (not shown) The clock signal synchronization operation of input.The " # " for waiting # signals is the symbol for indicating to wait # signals to be low useful signal.

Herein, based on it is assumed hereinafter that to explain example：It is 1 position to enable signal；Write-in/reading signal is 1 position；Address Signal is N number of position (N is regulation positive integer)；It is 8 positions to write data；It is 1 position to wait # signals；It is 8 positions to read data； It is 1 position with fault notification signal.

When writing data into internal storage 14, bus master controller will be asked to write the signal of data, asserted Signal (for example, value is " 1 ") is enabled, write-in/reading signal (for example, value is " 0 ") of data write-in is specified, indicates write-in data The address signal of address and the write-in data output as data to be written to I/F change-over circuits 13.In response to this, I/F turns The address that data write-in is indicated by the address signal in memory 14 internally will be write by changing circuit 13.In this case, I/F Change-over circuit 13 will be also written in internal storage 14 from the ECC of write-in data generation.

When reading data from internal storage 14, bus master controller enables signal (value is " 1 "), specified number by what is asserted The address signal for reading the address of data according to write-in/reading signal (value is " 1 ") of reading and instruction, which is exported to I/F, changes electricity Road 13.In response to this, I/F change-over circuits 13 read the address for being stored in and being indicated by the address signal in memory 14 internally Data, and by the data output read to bus master controller, be used as and read data.In this case, I/F conversions electricity Road 13 reads ECC corresponding with the data from internal storage 14, and ECC and data based on reading are determined in data Whether make a mistake.When detecting the mistake of data by the determination, the output error notification signal of I/F change-over circuits 13 with to Bus master controller notification error.However, in the case of a bit-errors, to the reading data progress to be output to bus master controller Correction.

When bus master access internal storage 14, I/F controls circuit 110 by that will wait a clock cycle should For bus master controller, to make access extend to two clock cycle.Then, I/F controls circuit 110 to be controlled such that ADR Change-over circuit 120, WDT change-over circuits 130 and RDT change-over circuits 140 perform the behaviour on the data in the first clock cycle Make and the operation on the ECC in the second clock cycle.That is, extended by the output for the signal that will be exported by bus master controller To the second clock cycle, I/F control circuits 110 can perform the behaviour on ECC based on the signal in the second clock cycle Make.

I/F control circuits 110 include enabling signal holding circuit 111 and waiting signal generative circuit 112.

When bus master access internal storage 14, enable signal holding circuit 111 and be maintained at for the first clock cycle In the value for enabling signal asserted, and with clock signal synchronization, the value of holding will be used as in the second clock cycle The signal output of output is inverted to waiting signal generative circuit 112.That is, signal is enabled via I/ from what bus master controller was exported Internal storage 14 is input to during F change-over circuits 13, and is also input into I/F control circuits 110.For example, enabling signal Holding circuit 111 is FF (trigger) circuit.

That is, in the first clock cycle, (value is the signal that enables asserted based on going in a previous clock cycle " 0 "), enabling signal holding circuit 111 will export to waiting signal generative circuit as the signal of reversion output (value is " 1 ") 112.Next, in the second clock cycle, opening based on asserting in a previous clock cycle (the first clock cycle) With signal (value is " 1 "), signal holding circuit 111 is enabled using the signal exported as reversion (value is 0) output to waiting signal Generative circuit 112.

Herein, write-in and reading that whether signal designation enabled or disabled data are enabled.When enable data write-in and During reading, assert and enable signal.When disabling the write-in and reading of data, go to assert and enable signal.

When input assertion is when enabling signal, internal storage 14 is based on the write-in/reading inputted from I/F change-over circuits 13 Signal (specify write-in), address signal and write-in data are write data into internal storage 14, as later described 's.On the other hand, when input go to assert when enabling signal, internal storage 14, which is not performed, writes data into internal storage In 14, no matter write-in/reading signal, address signal and the input for waiting pending data.

When input assertion is when enabling signal, internal storage 14 is based on the write-in/reading inputted from I/F change-over circuits 13 Signal (specify and read) and address signal to read data from internal storage 14, as will be described later.On the other hand, when Input go to assert when enabling signal, internal storage 14 does not perform from internal storage 14 and reads data, no matter write-in/reading The input of signal and address signal.

Waiting signal generative circuit 112 will enable signal and electric from signal holding is enabled as what is inputted from bus master controller The signal output of the NAND operating results for the signal that road 111 is inputted is used as wait # signals to bus master controller.For example, waiting letter Number generative circuit 112 is NAND circuit.

That is, in the first clock cycle, waiting signal generative circuit 112 is based on from enabling signal holding circuit 111 That asserts enables signal (for example, value is " 1 ") and signal (for example, value is " 1 "), by the wait # signals asserted (for example, value For " 0 ") export to bus master controller.While the wait # signals that this is asserted are inputted, bus master controller is stopped operation.Connect down Come, in the second clock cycle, waiting signal generative circuit 112 from the holding for enabling signal holding circuit 111 based on asserting Enable signal (for example, value is " 1 ") and signal (for example, value is " 0 "), the wait # signals asserted will be removed (for example, value is " 1 ") export to bus master controller.While in input, this removes the wait # signals asserted, bus master controller is stopped operation.

By this way, when bus master access internal storage 14, by the wait # signals of input assertion by Extend a clock cycle access cycle.Then, access of the bus master controller to internal storage 14 passes through two clock cycle Complete.Therefore, when bus master access internal storage 14, maintenance enable signal, write-in/reading signal, address signal, With two clock cycle of output of write-in data.

# signals are waited to also serve as the operation to ADR change-over circuits 120, WDT change-over circuits 130 and RDT change-over circuits 140 The data switched over /ECC signals.That is, waiting signal generative circuit 112 will wait # signal outputs to ADR change-over circuits 120, Each of WDT change-over circuits 130 and RDT change-over circuits 140, are used as data/ECC signals.

# signals are waited to also serve as the address that indicates the write-in data internally in memory 14 or internally memory 14 In reading data address highest component level value signal.That is, waiting signal generative circuit 112 will wait # signal outputs To internal storage 14, the signal for the highest component level for indicating address is used as.

In the first clock cycle, in order to which the address for writing or reading data is specified to internal storage 14, ADR turns Changing circuit 120 will actually export to internal storage 14 from the address signal that bus master controller is inputted.On the other hand, second In clock cycle, in order to write or read and the ECC of data pair to be written or to be read address is specified to interior Portion's memory 14, ADR change-over circuits 120 indicate write-in or reading based on the address signal inputted from bus master controller to generate The address signal of ECC address is taken, and the address signal of generation is exported to internal storage 14.

ADR change-over circuits 120 include ADR circuit for reversing 121 and selector 122.The address that will be exported from bus master controller Signal is input in ADR circuit for reversing 121.ADR circuit for reversing 121 inverts all of the address of the address signal instruction by inputting Each value of position, and address signal is exported to selector 122.By the address signal from bus master controller and from ADR The address signal of circuit for reversing 121 is input in selector 122.Selector 122 selects the address signal from bus master controller With one in the address signal from ADR circuit for reversing 121, and the address signal of selection is exported to internal storage 14。

When it is the first clock for inputting data/ECC signals (for example, value be " 0 ") from waiting signal generative circuit 112 During the cycle, selector 122 selects the address signal inputted from bus master controller, and the address signal of selection is exported to inside Memory 14.On the other hand, when it is to input data/ECC signals (for example, value is 1) from waiting signal generative circuit 112 During the second clock cycle, selector 122 selects the address signal inputted from ADR circuit for reversing 121, and the address of selection is believed Number output is to internal storage 14.

Therefore, in (N+1) bit address signal in recently entering internal storage 14, lower-order N becomes ADR and turned The N bit address signals that circuit 120 has been exported are changed, and a position of most high-order has become waiting signal generative circuit 112 The data of output/ECC signals.

Then, internal storage 14 is performed to write data into and referred to by (N+1) bit address signal in the first clock cycle The address that shows or from the address reading data.Internal storage 14 is performed ECC write-ins by the (N+ in the second clock cycle 1) address of bit address signal designation or from the address reading data.

In the first clock cycle, in order to write data into internal storage 14, WDT change-over circuits 130 are actually By the write-in data output inputted from bus master controller to internal storage 14.On the other hand, in the second clock cycle, in order to It will be written to the ECC for writing data pair in internal storage 14, WDT change-over circuits 130 are based on from bus master controller input Write-in data to generate ECC, and the ECC of generation is exported to internal storage 14.

WDT change-over circuits 130 include ECC generative circuits 131 and selector 132.By the write-in number from bus master controller According to being input in ECC generative circuits 131.ECC generative circuits 131 generate ECC from the write-in data of input, and by generation ECC is exported to selector 132.

Write-in data from bus master controller and the ECC from ECC generative circuits 131 are input in selector 132. Selector 132 selects one in the write-in data from bus master controller and the ECC from ECC generative circuits 131, and will One of selection is exported to internal storage 14.

When it is the first clock for inputting data/ECC signals (for example, value be " 0 ") from waiting signal generative circuit 112 During the cycle, selector 132 selects the write-in data inputted from bus master controller, and by the write-in data output of selection to inside Memory 14.On the other hand, when it is to input data/ECC signals (for example, value is 1) from waiting signal generative circuit 112 During the second clock cycle, selector 132 selects the ECC inputted from ECC generative circuits 131, and the ECC of selection is exported to interior Portion's memory 14.

Therefore, when write-in/reading signal of data write-in is specified in input, in the first clock cycle, internal storage 14 by the write-in data storage inputted from bus master controller in the address by (N+1) bit address signal designation.In second clock In cycle, the ECC inputted from WDT change-over circuits 130 (precisely, is included virtual bit and ECC number by internal storage 14 According to as will be described later) it is stored in by the address of (N+1) bit address signal designation.It is actual via I/F change-over circuits 13 On the write-in exported from bus master controller/reading signal is inputted to internal storage 14.

On the other hand, when write-in/reading signal of digital independent is specified in input, in the first clock cycle, inside is deposited Reservoir 14 will be stored in the data output of the address by (N+1) bit address signal designation to RDT change-over circuits 140, be used as reading Access evidence.In the second clock cycle, internal storage 14 will be stored in the address by (N+1) bit address signal designation ECC is exported to RDT change-over circuits 140.

When bus master controller reads data from internal storage 14, RDT change-over circuits 140 are based on from internal storage 14 The reading data and ECC of input come determine mistake whether have occurred and that read data in.Number is being read when mistake has not occurred According to it is middle when, RDT change-over circuits 140 are actually by the reading data output inputted from internal storage 14 to bus master controller.Separately On the one hand, when mistake, which has occurred and that, to be read in data, RDT change-over circuits 140 are based on ECC come to from internal storage 14 Mistake in the reading data of input is corrected, and then by the reading data output after correction to bus master controller.

RDT change-over circuits 140 include data holding circuit 141, ECC Check circuit 142 and Error-Correcting Circuit 143.

When bus master access internal storage 14, data holding circuit 141 fetched in the first clock cycle from The reading data of internal storage input, and with clock signal synchronization, in the second clock cycle by the reading data of holding Export to ECC Check circuit 142 and Error-Correcting Circuit 143.For example, data holding circuit 141 is FF circuits.

ECC Check circuit 142 is operated not in the first clock cycle；However, being operated in the second clock cycle, ECC inspections The ECC that circuit 142 is inputted based on the reading data inputted from data holding circuit 141 and from internal storage 14 is looked into, to determine Whether the mistake of data has occurred and that.

That is, in the first clock cycle, when by data/ECC signals (for example, value be " 0 ") from waiting signal generative circuit During 112 input, ECC Check circuit 142 does not perform determination failure.On the other hand, in the second clock cycle, when by data/ECC Signal (for example, value be " 1 ") from waiting signal generative circuit 112 input when, the mistake of the determination data of ECC Check circuit 142 is It is no to have occurred and that.In other words, data/ECC signals are used as the operation for indicating whether to enable or disabling ECC Check circuit 142 Enable signal.

When ECC Check circuit 142 determines that mistake is had occurred and that in any one position of data, ECC Check circuit 142 The error correction signal output of position of error bit will be indicated to Error-Correcting Circuit 143.When ECC Check circuit 142 determines nothing 2 of method correction or multi-bit error be when having occurred and that in data, and ECC Check circuit 142 is by the fault notification signal asserted (for example, value is " 1 ") output is to bus master controller, the signal occurred as notification error.On the other hand, ECC Check circuit is worked as 142 determine can not correct 2 or when multi-bit error is had not occurred in data, and ECC Check circuit 142 will go the mistake asserted Output is to bus master controller for notification signal (for example, value is " 0 ") by mistake, the signal not occurred as notification error.

When mistake is had not occurred in data, Error-Correcting Circuit 143 actually will be in the second clock cycle from number The reading data output inputted according to holding circuit 141 is to bus master controller.On the other hand, when mistake is had occurred and that in data When, the mistake for the reading data that 143 pairs of Error-Correcting Circuit is inputted in the second clock cycle from data holding circuit 141 is carried out Correction, and then by the reading data output after correction to bus master controller.More specifically, Error-Correcting Circuit 143 will be In the readings data inputted from data holding circuit 141 by making in the error correction letter by inputting from ECC Check circuit 142 Number indicate position position at value reversion and obtain data output to bus master controller, be used as the reading after error correction Access evidence.For example, Error-Correcting Circuit 143 includes N XOR (different OR) circuit.

Reference picture 3, below explaination is included in the ADR circuit for reversing 121 in the ADR change-over circuits 120 according to embodiment 1 Configuration.As shown in figure 3, ADR change-over circuits 120 include N section values circuit for reversing 1210.Herein, the ground with N number of is illustrated The example of location signal.

Each in N section values circuit for reversing 1210 is with the position A0 of N bit address signals, A1, A2 ..., in A (N-1) Each correspondence.Each in N section values circuit for reversing 1210 makes the value reversion of the corresponding position of address signal, and exports Value after the reversal.From in N section values circuit for reversing 1210 each output position A ' 0, A ' 1, A ' 2 ..., A ' (N- 1) N bit address signals are collected as, and are output to internal storage 14.Herein, after " A " numeral indicate with The increase of numeral, it is the position of higher order.That is, in N number of position, " 0 " indicates that it is minimum component level, and " N-1 " indicates that it is Highest component level.It is also such for other positions.For example, place value circuit for reversing 1210 is NOT (logic NOT) circuit.

Next, reference picture 4, explains the configuration mapped according to the memory of the internal storage 14 of embodiment 1.Herein, It is that 8 positions, the address width of internal storage 14 are (N+1) individual position, internal storage to the data width of internal storage 14 14 data volume is (8 × 2^(N+1)) individual position, and N=3 example makes explaination.

The half of low order in Fig. 4 is used as the region of storing initial data by internal storage 14, and by the one of high-order Half is used as the region for the ECC that storage is matched with primary data.That is, the region in memory 14 internally is divided into by address The value (A3 in Fig. 4) of highest component level be set to be stored with when " 0 " in address space the regions of data, and divide into Be stored with ECC region when the value of the highest component level of address is set into " 1 ".In embodiment 1, for the data that are stored with The value of low order N (A2 to A0 in Fig. 4) of address, is stored with and the value of low order N of the ECC of data pair address is logical Crossing the operation of the ADR circuit for reversing 121 (part of " ADR reversions " that A2 to A0 value is marked as in Fig. 4) shown in Fig. 3 makes position The value put reversion and obtained.

That is, as shown in figure 4, address AD R-0 (" 0000 ") data (" DATA0 ") and address AD R-F (" 1111 ") ECC (" ECC0 ") matches.Address AD R-1 (" 0001 ") data (" DATA1 ") and address AD R-E (" 1110 ") ECC (" ECC1 ") matches.Address AD R-2 (" 0010 ") data (" DATA2 ") and address AD R-D (" 1101 ") ECC (" ECC2 ") matches.Address AD R-3 (" 0011 ") data (" DATA3 ") and address AD R-C (" 1100 ") ECC (" ECC3 ") matches.Address AD R-4 (" 0100 ") data (" DATA4 ") and address AD R-B (" 1011 ") ECC (" ECC4 ") matches.Address AD R-5 (" 0101 ") data (" DATA5 ") and address AD R-A (" 1010 ") ECC (" ECC5 ") matches.Address AD R-6 (" 0110 ") data (" DATA6 ") and address AD R-9 (" 1001 ") ECC (" ECC6 ") matches.Address AD R-7 (" 0111 ") data (" DATA7 ") and address AD R-8 (" 1000 ") ECC (" ECC7 ") matches.

Herein, part corresponding with " n " of " ADR-n " shown in Fig. 4 is the hexadecimal number notation of address.That is, " ADR- 0 " specifies address to be " 0000 ", and " ADR-F " specifies address to be " 1111 ".

There are 5 positions from the ECC of 8 data generations.Therefore, by the way that virtual bit (for example, value is " 0 ") is added into 3 ECC is changed into 8 data by high-order position, and the ECC is stored in internal storage 14.

Internal storage 14 is configured as described above, and the I/F change-over circuits 13 being correspondingly arranged with internal storage 14 Operation as described above.Therefore, when mistake occurs in any one position of the data in writing internal storage 14, I/F turns The mistake of data can be detected when reading data by changing the RDT change-over circuits 140 of circuit 13.Then, when detecting a bit-errors When, mistake is corrected.When detecting two or multi-bit error, send the wrong uncorrectable error of instruction and notify letter Number.

Therefore, when stuck-at fault (being fixed to 0 or 1) is because treating the WDT change-over circuits 130 from I/F change-over circuits 13 Export (disconnected to the failure of any one or more of lines among 8 signal lines of the write-in data (8) of internal storage 14 Open connection) and when occurring in the data and ECC being mutually paired, value at the position of position corresponding with the signal wire of disconnection becomes Into the value (reverse value) different from initial value.Therefore, when reading the data, value change is detected as in ECC Check circuit certainly A bit-errors or two or more multi-bit error in 142.When stuck-at fault (being fixed to 0 or 1) in I/F because changing electricity Any one among 8 signal lines of the reading data (8) that the RDT change-over circuits 140 on road 13 are inputted from internal storage 14 The failure (disconnecting) of bar or a plurality of line and when occurring, this also sets up.

On the other hand, stuck-at fault (being fixed to 0 or 1) is explained below because treating ADR turns from I/F change-over circuits 13 Change any one or more of among the N signal lines for the address signal (N) that circuit 120 is input in internal storage 14 The failure (disconnecting) of line and situation about occurring.

Reference picture 5, illustrates occur in the failure of fixed 1 (being fixed to 1) in be input to internal storage 14 below Address signal (N) A2 positions in the case of operation.Assuming that internal storage 14 has N=3, as shown in Figure 4.This Place, explaination is made to performing the situation of write-in and reading of data by below scheme.

(1) by data (" DATA5 ") writing address ADR-5 (" 0101 "), and by with the ECC of data pair (" ECC5 ") Writing address ADR-A (" 1010 ").In the accompanying drawings, " DATA5 " and " ECC5 " is indicated in bracket.

(2) again by data (" DATA1 ") writing address ADR-1 (" 0001 "), and by the ECC with data pair (" ECC1 ") writing address ADR-E (" 1110 ").

(3) herein, the failure of fixed 1 occurs in address signal line corresponding with the A2 of address positions.Therefore, access internal The address AD R-0 to ADR-3 and address AD R-8 to ADR-B of memory 14 are impossible.

(4) purpose is to read data (" DATA1 ") and the ECC (" ECC1 ") with data pair, and the data and the ECC exist (2) had been written in.

(4) ' now, in fact, due to the failure of address signal line being had occurred and that in (3), from internal storage 14 Address AD R-5 (" 0101 "), rather than read data from the data that are stored with (" DATA1 ") address AD R-1 (" 0001 ") (“DATA5”).On the other hand, be stored with ECC (" ECC1 ") address AD R-E (" 1110 ") not by the failure shadow of address signal line Ring.Therefore, ECC (" ECC1 ") is normally read.That is, read the data (" DATA5 ") of data that are not written into (2) and not with The ECC (" ECC1 ") of data pair.

(5) result, be included in the ECC Check circuit 142 in RDT change-over circuits 140 is by the fault detect of fixed 1 certainly One bit-errors or two bit-errors or more multi-bit error.By this way, the event in address signal system can also be detected Barrier；Therefore, from the viewpoint of functional safety, embodiment 1 is fine.

In addition, reference picture 6, is illustrated in the situation that the region for storing ECC performs " ADR reversions " (is not deleted in Fig. 2 below The situations of ADR change-over circuits 120 in shown I/F change-over circuits 13) under, perform data according to Fig. 5 identicals mode Write-in and reading when operation.

(1) by data (" DATA5 ") writing address ADR-5 (" 0101 "), and by with the ECC of data pair (" ECC5 ") Writing address ADR-D (" 1101 ").In the accompanying drawings, " DATA5 " and " ECC5 " is indicated in bracket.

(2) again by data (" DATA1 ") writing address ADR-1 (" 0001 "), and by the ECC with data pair (" ECC1 ") writing address ADR-9 (" 1001 ").

(4) ' now, in fact, due to the failure of address signal line being had occurred and that in (3), from internal storage 14 Address AD R-5 (" 0101 "), rather than read data from the data that are stored with (" DATA1 ") address AD R-1 (" 0001 ") (“DATA5”).Be stored with ECC (" ECC1 ") address AD R-9 (" 1001 ") by the fault impact of address signal line.Therefore, from The address AD R-D (" 1101 ") of internal storage 14 reads ECC (" ECC5 ").That is, the data being not written into (2) are read (" DATA5 ") and the ECC (" ECC1 ") with data pair.

(5) therefore, it is included in the ECC Check circuit 142 in RDT change-over circuits 140 and thinks data (" DATA5 ") and ECC (" ECC5 ") is into normal right.Therefore, it is a bit-errors or two by fault detect as long as bit-errors are had not occurred in data Or more multi-bit error is impossible.

Fig. 5 shows in the failure of fixed 1 (being fixed to 1) occur the address signal in be input to internal storage 14 A2 positions in when operation.However, according to embodiment 1, the failure of address signal line can be equally detected, even in fixed 0 Occur when failure (being fixed to 0) occurs in A2 or in the failure of fixed 1 or the failure of fixed 0 in other addresses (tool Body is A1 and A0) in when.

As for the situation of the N=3 shown in Fig. 4, Fig. 7 is form, this table show more than 8 rows (according to from above Serial number be " 0 " to " 7 ") 3 A2 to A0 of low order of address signal value, about 8 differences to " DATA0 " and " ECC0 ", " DATA1 " and " ECC1 " ... and " DATA7 " and " ECC7 ".In the figure 7, it will be deposited by being input to inside when reading data The address that address signal in reservoir 14 is indicated is expressed as " address (data) ", and will be by being input to inside when reading ECC The address that address signal in memory 14 is indicated is expressed as " address (ECC) ".

The form from left to right show a case that following 7 kinds it is different：

(1) there is no situation of the failure in all positions of address；

(2) situation (this is corresponding with the situation shown in Fig. 5) in the A2 positions of address occurs for the failure of fixed 1；

(3) situation in the A2 positions of address occurs for the failure of fixed 0；

(4) situation in the A1 positions of address occurs for the failure of fixed 1；

(5) situation in the A1 positions of address occurs for the failure of fixed 0；

(6) situation in the A0 positions of address occurs for the failure of fixed 1；And

(7) situation in the A0 positions of address occurs for the failure of fixed 0.

Three values (0 or 1) at the position of each are set to A2 to A0 value in sequence.In its value Rule below value at the position for the position for hindering for some reason and changing.

The second row (numbering is 1) of form shown in Fig. 7 is to show to be written into Fig. 5 (2) while being stored with and staying in Data (" DATA1 ") and row with the ECC (" ECC1 ") of data pair address.When failure is had not occurred in all of address When in position, address has (" the 001 ") ADR-1 of low order 3 and low order 3 (" 110 ") ADR-E being shown respectively in Far Left. In form shown in Fig. 7, A2 to A0 these values to being surrounded by solid line.

Herein, when the failure of fixed 1 occurs in A2, address is shown immediately in the right of form, wherein, address The ADR-1 of (data) is influenceed to become different ADR-5 (low order 3 is " 101 ") by failure, and not by fault impact In the case of, the ADR-E (low order 3 is " 1-1 ") of address (ECC) remains ADR-E.In the table, A2 to A0 these Value to failure influence after value by dotted line, also, simultaneously, A2 to A0 these values to failure shadow Surrounded in each in value after sound by solid line by the address (data) of actual access and address (ECC) and in the table Coupled with thick line.Therefore, data (" DATA5 ") and ECC (" ECC1 ") are accessed.That is, the pairing of data and ECC has obviously been collapsed Burst, such as shown in Fig. 5 (4) '.

Equally, as other examples, further right in the table shows that the failure of fixed 1 occurs in A1 Situation in A0 occurs for situation and the failure of fixed 1, wherein, value A2 is shown extremely according to aforesaid way identical mode A0 pair.Data and ECC pairing have obviously been collapsed.

As other examples, it is related in the 7th row (numbering is 6) of the form shown in Fig. 7 while the data that are stored with (" DATA6 ") and the address with the ECC (" ECC6 ") of data pair, equally, shows that the failure of fixed 0 occurs in A2 Situation in A0 occurs for the situation and the failure of fixed 0 that situation, the failure of fixed 0 occur in A1.In any situation Under, data and ECC pairing collapse, as expected.Pass through the form, it is obvious that when stuck-at fault hair When in any one raw in the position of address, failure can be detected certainly.

Fig. 8 is form, and the form (that is, deletes Fig. 2 in the situation not to the region execution " ADR reversions " for the ECC that is stored with The situation of the ADR change-over circuits 120 of shown I/F change-over circuits 13) under, shown by similar mode in the way of Fig. 7 Address (data) and address (ECC) low order 3 A2 to A0 value.The failure of fixed 1, which has occurred and that, is being present in the form The second row (numbering is 1) in left side the second failure example in address A2 positions in situation and the situation shown in Fig. 6 Correspondence.

In this case, being seen in the form as shown in from Fig. 8, when stuck-at fault occurs in the position of address Any one in when, become in the case where being affected data at the address that can not possibly access and ECC to being considered as It is data at another address and ECC to (that is, address becomes to degenerate).Therefore, address signal is detected when reading data The failure of line is impossible.

The example that the value of all of the N bit address signals to being inputted from bus master controller is inverted makes above-mentioned explaination. However, the present invention is not limited to the example.For example, position (any amount of N of the defined quantity by making N bit address signals Position is to one) value invert and obtain effect to a certain degree.The position of defined quantity can be set to from N number of most The position of the defined quantity of high-order position or the position of defined quantity from minimum component level.Can be by the defined quantity Position is set to the continuous position or discontinuous position of N number of.However, as set forth above, it is possible to multiple failures are detected, preferably by making N The reversion of the value of all of bit address signal.

As described above, in embodiment 1, ADR change-over circuits 120 are based on being used to store data in internal storage 14 The first address, come generate for store from data generate error detection code the second address.When request writes data into During the first address, WDT change-over circuits 130 write data into the first address and error detection code are write into the second address.When Request from the first address reading data when, RDT change-over circuits 104 are from the first address reading data, from the second address read error Code is detected, and detects mistake based on data and error detection code.

Herein, I/F controls at least one position of the modification of circuit 110 first address (corresponding with (N+1) bit address) (with (N+ 1) the highest component level correspondence of bit address) value, and the storage location of error detection code is displaced to the storage location of data. ADR change-over circuits 120 are by inverting the value of the position of the defined quantity of other positions (corresponding with low order N), to generate address It is used as the second address.In the examples described above, ADR change-over circuits 120 are by inverting the value of all other position (N number of position), next life The second address is used as into address.

Therefore, when the fixed after ECC generated by data and by data is to being written in internal storage 14 Failure (being fixed to 0 or 1) occur any one in the address signal line for leading to internal storage 14 it is middle when, can read The failure of address signal line is detected when taking write-in data.

This failure to two or a plurality of address signal line is equally effective.The event of the value of influence address can also be detected Barrier, this occurs in ADR change-over circuits 120 to generate and export to be input to the address signal in internal storage 14, and Occur in the address signal process circuit (not shown) in memory 14 internally.

In embodiment 1, bus master controller perform data write-in or reading unit interval (with the clock cycle pair Should) in the write-in or reading that enable data are enabled into signal output to internal storage 14.In response to enabling writing for data The signal that enables from bus master controller output for entering or reading, I/F control circuits 110 export waiting signal with the unit interval The interior operation for suppressing bus master controller, rather than export waiting signal to allow the operation of bus master controller.

In response to the waiting signal for controlling circuit 110 to export from I/F for the operation for suppressing bus master controller, WDT conversion electricity Road 130 writes data into the first address (corresponding with the first clock cycle).Then, in response to allowing the operation of bus master controller The waiting signal that circuit 110 is exported is controlled from I/F, error detection code is write the second address (with the by WDT change-over circuits 130 Two clock cycle correspondence).

In response to the waiting signal for controlling circuit 110 to export from I/F for the operation for suppressing bus master controller, RDT conversion electricity Road 140 then from the first address reading data, and in response to allow bus master controller operation from I/F control circuit 110 The waiting signal of output, RDT change-over circuits 140 detect code from the second address read error.

It therefore, it can maintain the request of write-in or the reading of data by bus master controller, also, simultaneously, using holding The continuous time, error detection code can be written in internal storage 14, or be examined from the read error of internal storage 14 Survey code.Waiting signal can also be shifted, with using simpler configuration come the continuation of the request of the write-in of realizing data and Switching between the write-in of data and the write-in of error detection code.Waiting signal can be further shifted, it is simpler to utilize Configuration come the continuation of request and cutting between the reading of data and the reading of error detection code of the reading of realizing data Change.

In embodiment 1, the waiting signal that will suppress the operation of bus master controller is used as at least one position of the first address Value.To allow the operation of bus master controller waiting signal be used as the first address after modification at least one Value.

Therefore, it can shift waiting signal, with using simpler configuration come the continuation of the request of the write-in of realizing data, With the skew of the storage location of error detection code to the storage location of data.

In embodiment 1, in response to the wait letter for controlling circuit 110 to export from I/F for the operation for suppressing bus master controller Number, RDT change-over circuits 140 keep the data read from internal storage 14.Then, in response to allowing the behaviour of bus master controller The waiting signal for controlling circuit 110 to export from I/F made, RDT change-over circuits 140 are based on the mistake read from internal storage 14 Error detection code detects mistake with the data kept.

It therefore, it can shift waiting signal, to realize the write-in of data or asking for reading using simpler configuration The continuation asked and the change of the operation for error detection.

Next, explaining the configuration and operation of embodiment 2 referring to the drawings.According to the configuration of the cpu system 1 of embodiment 2 and Operation is substantially the same with the configuration and operation of the cpu system 1 according to embodiment 1 shown in Fig. 1.Therefore, eliminate to its Explaination.However, in example 2, it is included in configuration and operation and the root of a part for I/F change-over circuits 13 in cpu system 1 Configuration according to the I/F change-over circuits 13 of embodiment 1 is different with operation.

Next, reference picture 9, explains the configuration of the I/F change-over circuits 13 according to embodiment 2.With the I/ according to embodiment 1 F change-over circuits 13 are compared, and ADR rotation circuits 123 are included according to the I/F change-over circuits 13 of embodiment 2 to replace changing in ADR ADR circuit for reversing 121 in circuit 120.Circuit 110, WDT change-over circuits 130 and RDT is controlled to turn according to the I/F of embodiment 2 Change the configuration of circuit 140 and operate identical with the configuration and operation of the corresponding part according to embodiment 1.

The address signal exported from bus master controller is input in ADR rotation circuits 123.ADR rotation circuits 123 make by All rotations (displacement) of the address that the address signal of input is indicated, and postrotational address signal is exported to selector 122.Therefore, in example 2, selector 122 selects the address signal exported from bus master controller and from ADR rotation circuits One in the address signal of 123 outputs, and the address signal of selection is exported to internal storage 14.

Next, reference picture 10, explains the ADR rotation circuits being included in ADR change-over circuits 120 according to embodiment 2 123 configuration.Herein, the example with the address signal of N number of is illustrated.

As shown in Figure 10, ADR rotation circuits 123 make the address indicated from address signal to anticlockwise (to high-order position direction) One position, to reset the position of each of N bit address signals.That is, ADR rotation circuits 123 make N number of position of address signal to the left A position is displaced, and the highest component level of spilling is moved to minimum component level.

As shown in Figure 10, this be by make N bit address signal wire input phase and in the output stage in ADR rotation circuits What each bit position shift in 123 was realized with coupling.That is, the N bit address signals that will enter into ADR rotation circuits 123 Position A0, A1, A2 ..., each in A (N-1) N bit address signals for being set to treat to export from ADR rotation circuits 123 A ' 1, A ' 2 ..., each in A ' (N-1), A ' 0.In the ADR rotation circuits 123, each position of N bit address signal wires Signal by each reception in N number of buffer 1230, and make the bit position shift of connection destination.

Next, reference picture 11, explains and is mapped according to the memory of the internal storage 14 of embodiment 2.With shown in Fig. 4 According to as the internal storage 14 of embodiment 1, herein, the data width to internal storage 14 is 8 positions, internal storages 14 address width is that (N+1) individual position, the data volume of internal storage 14 are (8 × 2^(N+1)) individual position, and N=3 example does Go out explaination.

In example 2, for the data that are stored with address low order N (A2 to A0 in Figure 11) value, be stored with A kind of arrangement is changed to the value of low order N of the ECC of data pair address, in this arrangement, by shown in Figure 10 Each position is reset in the operations of ADR rotation circuits 123 (part of " ADR reversions " that A2 to A0 value is marked as in Figure 11).

I.e., as shown in figure 11, address AD R-0 (" 0000 ") data (" DATA0 ") are with address AD R-8's (" 1000 ") ECC (" ECC0 ") matches.Address AD R-1 (" 0001 ") data (" DATA1 ") and address AD R-A (" 1010 ") ECC (" ECC1 ") matches.Address AD R-2 (" 0010 ") data (" DATA2 ") and address AD R-C (" 1100 ") ECC (" ECC2 ") matches.Address AD R-3 (" 0011 ") data (" DATA3 ") and address AD R-E (" 1110 ") ECC (" ECC3 ") matches.Address AD R-4 (" 0100 ") data (" DATA4 ") and address AD R-9 (" 1001 ") ECC (" ECC4 ") matches.Address AD R-5 (" 0101 ") data (" DATA5 ") and address AD R-B (" 1011 ") ECC (" ECC5 ") matches.Address AD R-6 (" 0110 ") data (" DATA6 ") and address AD R-D (" 1101 ") ECC (" ECC6 ") matches.Address AD R-7 (" 0111 ") data (" DATA7 ") and address AD R-F (" 1111 ") ECC (" ECC7 ") matches.

In the same manner as in Example 1, by the way that virtual bit (for example, value is " 0 ") is changed into 8 by ECC added to high-order 3 Data, and ECC is stored in internal storage 14.In the same manner as in Example 1, when stuck-at fault (being fixed to 0 or 1) because Believe treating that the WDT change-over circuits 130 from I/F change-over circuits 13 are exported to eight of the write-in data of internal storage 14 (8) The failure (disconnecting) of any one or more of lines among number line and occur mutually form to data and ECC in When, value at the position of position corresponding from the signal wire of disconnection becomes the different value (reverse value) of adult fish initial value.Therefore, reading is worked as Access according to when, certainly by value change is detected as a bit-errors or two or more dislocations in ECC Check circuit 142 By mistake.When stuck-at fault (being fixed to 0 or 1) is because the RDT change-over circuits 140 in I/F change-over circuits 13 are from internal storage 14 The failure (disconnecting) of any one or more of lines among 8 signal lines of the reading data (8) of input and occur When, this is also identical.

On the other hand, stuck-at fault (being fixed to 0 or 1) is explained below because treating WDT turns from I/F change-over circuits 13 Change any one or more of among the N signal lines for the address signal (N) that circuit 130 is input in internal storage 14 The failure (disconnecting) of line and situation about occurring.

Reference picture 12, as Fig. 5 of embodiment 1, illustrates occur treating in the failure of fixed 1 (being fixed to 1) below Operation in the case of being input in the A2 positions of the address signal in internal storage 14 (N).Assuming that internal storage 14 has There is N=3, as shown in figure 11.Herein, the situation of write-in and the reading to performing data by below scheme makes explaination.

(1) by data (" DATA3 ") writing address ADR-3 (" 0011 "), and by with the ECC of data pair (" ECC3 ") Writing address ADR-E (" 1110 ").By data (" DATA5 ") writing address ADR-5 (" 0101 "), and by with data pair ECC (" ECC5 ") writing address ADR-B (" 1011 ").In the accompanying drawings, they are indicated in bracket.

(2) again by data (" DATA1 ") writing address ADR-1 (" 0001 "), and by the ECC with data pair (" ECC1 ") writing address ADR-A (" 1010 ").

(4) ' now, in fact, due to the failure of address signal line being had occurred and that in (3), from internal storage 14 Address AD R-5 (" 0101 "), rather than read data from the data that are stored with (" DATA1 ") address AD R-1 (" 0001 ") (“DATA5”).Read from address AD R-E (" 1110 "), rather than from the ECC that is stored with (" ECC1 ") address AD R-A (" 1010 ") Take ECC (" ECC3 ").That is, the data (" DATA5 ") for the data that reading is not written into (2) and the not ECC with data pair (“ECC3”)。

(5) result, be included in the ECC Check circuit 142 in RDT change-over circuits 140 is by the fault detect of fixed 1 certainly One bit-errors or two bit-errors or more multi-bit error.By this way, the event in address signal system can also be detected Barrier；Therefore, from the viewpoint of functional safety, embodiment 2 is fine.

Figure 12 shows in the failure of fixed 1 (being fixed to 1) occur the address letter in be input to internal storage 14 Number A2 positions in when operation.However, according to embodiment 2, the failure of address signal line can be equally detected, even in fixed Occur when 0 failure (being fixed to 0) occurs in A2 or in the failure of fixed 1 or the failure of fixed 0 in other addresses When in (being specially A1 and A0).

As for the situation of the N=3 shown in Figure 11, Figure 13 is form, this table show more than 8 rows (according to from above Rise serial number be " 0 " to " 7 ") address signal 3 A2 to A0 of low order value, about 8 differences to " DATA0 " with " ECC0 ", " DATA1 " and " ECC1 " ... and " DATA7 " and " ECC7 ".In fig. 13, will be by being inputted when reading data The address indicated to the address signal in internal storage 14 is expressed as " address (data) ", and will be by defeated when reading ECC Enter the address indicated to the address signal in internal storage 14 to be expressed as " address (ECC) ".

(1) there is no situation of the failure in all positions of address；

(2) situation (this is corresponding with the situation shown in Figure 12) in the A2 positions of address occurs for the failure of fixed 1；

(7) situation in the A0 positions of address occurs for the failure of fixed 0.

The second row (numbering is 1) of form shown in Figure 13 is to show to be write in Figure 12 (2) while being stored with and staying in The data (" DATA1 ") entered and the row with the ECC (" ECC1 ") of data pair address.When failure has not occurred the institute in address When having in position, address has low order 3 (" 001 "), the ADR-E low order 3 for the ADR-1 being shown respectively in Far Left (“110”).In the form shown in Figure 13, A2 to A0 these values to being surrounded by solid line.

Herein, when the failure of fixed 1 occurs in A2, address is shown immediately in the right of form, wherein, address The ADR-1 of (data) is influenceed to become different ADR-5 (low order 3 is " 101 ") by failure, and address (ECC) ADR-A is influenceed to become different ADR-E by failure (low order 3 is " 110 ").In the table, in A2 to A0 these values To failure influence after value by dotted line, also, simultaneously, A2 to A0 these values to failure influence Surrounded and use in the table by solid line by the address (data) of actual access and address (ECC) in each in value afterwards Thick line couples.Therefore, data (" DATA5 ") and ECC (" ECC3 ") are accessed.I.e., it is understood that data and ECC pairing have been collapsed Burst, such as shown in Figure 12 (4) '.

Equally, as other examples, further right in the table shows that the failure of fixed 1 occurs in A1 Situation in A0 occurs for situation and the failure of fixed 1, wherein, show A2 to A0 according to aforesaid way identical mode Value pair.Data and ECC pairing have obviously been collapsed.

As other examples, it is related in the 7th row (numbering is 6) of the form shown in Figure 13 while the data that are stored with (" DATA6 ") and the address with the ECC (" ECC6 ") of data pair, equally, shows that the failure of fixed 0 occurs in A2 Situation in A0 occurs for the situation and the failure of fixed 0 that situation, the failure of fixed 0 occur in A1.In any situation Under, data and ECC pairing collapse, as expected.Pass through the form, it is obvious that when stuck-at fault hair When in any one raw in the position of address, failure can be detected certainly.

In addition, in example 2, even if working as in stuck-at fault (being fixed to 0 or 1) because treating from I/F change-over circuits 13 ADR change-over circuits 120 be input to any one in the N signal lines of the address signal in internal storage 14 (N) Failure (disconnecting) and occur after, perform data write-in and reading when, failure can also be detected, such as below will explaination 's.

Reference picture 14, illustrates occur in the failure of fixed 1 (being fixed to 1) in be input to internal storage 14 below Address signal (N) A2 positions in after perform data write-in and reading in the case of operation.Assuming that internal storage 14 have N=3, as shown in figure 11.Herein, the situation of write-in and the reading to performing data by below scheme makes explaination.

(1) by data (" DATA3 ") writing address ADR-3 (" 0011 "), and by with the ECC of data pair (" ECC3 ") Writing address ADR-E (" 1110 ").By data (" DATA5 ") writing address ADR-5 (" 0101 "), and by with data pair ECC (" ECC5 ") writing address ADR-B (" 1011 ").By data (" DATA1 ") writing address ADR-1 (" 0001 "), and will With ECC (" ECC1 ") writing address ADR-A (" 1010 ") of data pair.In the accompanying drawings, they are indicated in bracket.

(2) herein, the failure of fixed 1 occurs in address signal line corresponding with the A2 of address positions.Therefore, access internal The address AD R-0 to ADR-3 and address AD R-8 to ADR-B of memory 14 are impossible.

(3) purpose is again by data (" DATA2 ") writing address ADR-2 (" 0010 "), and will be with data pair ECC (" ECC2 ") writing address ADR-C (" 1100 ").Now, in fact, due to the address signal being had occurred and that in (2) The failure of line, by data (" DATA2 ") writing address ADR-6 (" 0110 "), rather than write-in internal storage 14 address ADR-2(“0010”).On the other hand, ECC (" ECC2 ") is normally written address AD R-C (" 1100 ").

(4) next, it is therefore intended that by data (" DATA6 ") writing address ADR-6 (" 0110 "), and will match somebody with somebody with data To ECC (" ECC6 ") writing address ADR-D (" 1101 ").Now, not by the address signal line being had occurred and that in (2) In the case of fault impact, data (" DATA6 ") and ECC (" ECC6 ") are all write into normal address.

(4) number that address AD R-6 (" 0110 ") is had been written into (3) ' now, is overwritten in by data (" DATA6 ") According to (" DATA2 ").

(5) purpose is to read data (" DATA2 ") and the ECC (" ECC2 ") with data pair, and the data and the ECC exist (3) had been written in.

(5) ' now, in fact, from the address AD R-6 (" 0110 ") of internal storage 14, rather than from being stored with The address AD R-2 (" 0010 ") of data (" DATA2 ") reads data (" DATA6 ").Because in address AD R-6 (" 0110 ") place, once writing data (" DATA2 ") in (3), it is possible in (4) ' middle rewriting data (" DATA6 ").From depositing The address AD R-C (" 1100 ") for containing ECC (" ECC2 ") normally reads ECC (" ECC2 ").Therefore, data (" DATA6 ") are read With the ECC (" ECC2 ") of the pairing collapse with data.

(6) result, be included in the ECC Check circuit 142 in RDT change-over circuits 140 is by the fault detect of fixed 1 certainly One bit-errors or two or multiple bit-errors.

By this way, the failure in address signal system can also be detected；Therefore, come from the viewpoint of functional safety See, embodiment 2 is fine.

Reference picture 15, to store ECC region perform " ADR reversions " embodiment 1 in the case of, to according to Figure 14 Explaination is made in operation when write-in and reading of the identical mode to perform data.

(1) by data (" DATA5 ") writing address ADR-5 (" 0101 "), and by with the ECC of data pair (" ECC5 ") Writing address ADR-A (" 1010 ").By data (" DATA1 ") writing address ADR-1 (" 0001 "), and by with data pair ECC (" ECC1 ") writing address ADR-E (" 1110 ").In the accompanying drawings, they are indicated in bracket.

(3) purpose is again by data (" DATA2 ") writing address ADR-2 (" 0010 "), and will be with data pair ECC (" ECC2 ") writing address ADR-D (" 1101 ").Now, in fact, due to the address signal being had occurred and that in (2) The failure of line, by data (" DATA2 ") writing address ADR-6 (" 0110 "), rather than write-in internal storage 14 address ADR-2(“0010”).On the other hand, ECC (" ECC2 ") is normally written address AD R-D (" 1101 ").

(4) next, it is therefore intended that by data (" DATA6 ") writing address ADR-6 (" 0110 "), and will match somebody with somebody with data To ECC (" ECC6 ") writing address ADR-9 (" 1001 ").Now, in fact, due to the address letter being had occurred and that in (2) The failure of number line, by ECC (" ECC6 ") writing address ADR-D (" 1101 "), rather than write-in internal storage 14 address ADR-9(“1001”).On the other hand, data (" DATA6 ") are normally written address AD R-6 (" 0110 ").

(4) number that address AD R-6 (" 0110 ") is had been written into (3) ' now, is overwritten in by data (" DATA6 ") According to (" DATA2 ").The ECC (" ECC2 ") of writing address ADR-D (" 1101 ") is rewritten by ECC (" ECC6 ").

(5) ' now, in fact, from the address AD R-6 (" 0110 ") of internal storage 14, rather than from being stored with The address AD R-2 (" 0010 ") of data (" DATA2 ") reads data (" DATA6 ").Because in address AD R-6 (" 0110 ") place, once writing data (" DATA2 ") in (3), it is possible in (4) ' middle rewriting data (" DATA6 ").From The stored address AD R-D (" 1101 ") for having ECC (" ECC2 ") reads ECC (" ECC6 ").Because in address AD R-D (" 1101 ") place, once writing ECC (" ECC2 ") in (3), it is possible in (4) ' middle rewriting ECC (" ECC6 ").That is, read (3) data (" DATA6 ") for the data being not written into and the not ECC (" ECC6 ") with data pair.

(6) result, is included in the ECC Check circuit 142 in RDT change-over circuits 140 and thinks data (" DATA6 ") and ECC (" ECC6 ") formation is normal right.Therefore, it is a bit-errors or two by fault detect as long as bit-errors are had not occurred in data Position or more multi-bit error be exactly impossible.

Figure 14 shows in the failure of fixed 1 (being fixed to 1) occur the address letter in be input to internal storage 14 Number A2 positions in when operation.However, according to embodiment 2, the failure of address signal line can be equally detected, even in fixed Occur when 0 failure (being fixed to 0) occurs in A2 or in the failure of fixed 1 or the failure of fixed 0 in other addresses When in (being specially A1 and A0).

As for the situation of the N=3 shown in Figure 11, Figure 16 is form, this table show more than 8 rows (according to from upper Serial number be " 0 " to " 7 ") 3 A2 to A0 of low order of address signal value, about 8 differences to " DATA0 " and " ECC0 ", " DATA1 " and " ECC1 " ... and " DATA7 " and " ECC7 ".In figure 16, will be by being input to inside when reading data The address that address signal in memory 14 is indicated is expressed as " address (data) ", and will be in being input to when reading ECC The address that address signal in portion's memory 14 is indicated is expressed as " address (ECC) ".As Figure 13, the form from left to right shows It has the situation that there occurs 7 kinds of different failures (1) to (7).The failure of fixed 1, which has occurred and that, is being present in the 3rd of the form Situation in the A2 positions of address in the second failure example in the left side in row (numbering is 2) is corresponding with the situation shown in Figure 14.

The third line (numbering is 2) of form shown in Figure 16 is to show to be write in Figure 14 (3) while being stored with and staying in The data (" DATA2 ") entered and the row with the ECC (" ECC2 ") of data pair address.When failure has not occurred the institute in address When having in position, address has the low order 3 (" 010 ") and ADR-C low order 3 for the ADR-2 being shown respectively in Far Left (“100”).In the form shown in Figure 16, A2 to A0 these values to by dotted line.

Herein, when the failure of fixed 1 occurs in A2, address is shown immediately in the right of form, wherein, address The ADR-2 of (data) is influenceed to become different ADR-6 (low order 3 is " 110 ") by failure, and not by fault impact In the case of, the ADR-C (low order 3 is " 100 ") of address (ECC) remains ADR-C.In the table, A2 to A0 these Value to failure influence after value by dotted line, also, simultaneously, A2 to A0 these values to failure shadow Surrounded in each in value after sound by solid line by the address (data) of actual access and address (ECC) and in the table Coupled with thick line.Therefore, data (" DATA6 ") and ECC (" ECC2 ") are accessed.I.e., it is understood that data and ECC pairing are Collapse, shown in such as Figure 14 (5) '.

Except the value by A2 to A0 in the third line on failure influenceed after value in addition to, in the table 1st row, the 5th row and the value by A2 to A0 in the 7th row on failure influenceed after value also by dotted line.So And, the combination to being four class addresses of two in the A2 to A0 shown in this 4 row value：(low order 3 is ADR-6 " 110 ") or ADR-4 (low order 3 is " 100 ") address (data) and ADR-C (low order 3 is " 100 ") or ADR-D The address (ECC) of (low order 3 is " 101 ").Therefore, as shown in Figure 14 (4) ', though when by data and ECC to write-in with Initially to different addresses (data) and address (ECC) when, can also rewrite initially to data and ECC in one；However, Data and ECC will not be rewritten simultaneously.

For the right of identical the third line, as another example, the failure of fixed 1 occur situation in A1 with In the case that the failure of fixed 1 occurs in A0, according to pair with aforesaid way identical mode come the value that shows A2 to A0. In both cases, data and ECC pairing have obviously all been collapsed.Obviously will not also occur while rewriteeing data and ECC.

As other examples, in the 6th row (numbering is 5) of the form shown in Figure 16, it is related to the data that are stored with (" DATA5 ") and with the address of one in the ECC (" ECC5 ") of data pair, equally, show the failure of fixed 0 occur exist Situation in A0 occurs for the situation and the failure of fixed 0 that situation, the failure of fixed 0 in A2 occur in A1. In the case of any one of situation, data and ECC pairing have been collapsed.Will not occur at the same rewrite it is initial to data and ECC.Pass through the form, it is obvious that when stuck-at fault occurs in any one in the position of address, certainly may be used To detect failure.

On the situation for the embodiment 1 that " ADR reversions " is performed to the region for storing ECC, as Figure 16, Figure 17 is table Lattice, this table show A2 to A0 value, are used as address (data) and the low order of address (ECC) 3.The failure of fixed 1 is Be present in situation in the A2 positions of the address in the second failure example of the left in the third line of the table (numbering is 2) with Situation correspondence shown in Figure 15.

Under existing conditions, by the form shown in Figure 17, occur when in stuck-at fault in any position of address Afterwards perform data write-in and reading when, address (data) and address (ECC) to become with initially to difference, but with ground Location (data) is another different to consistent (that is, address becomes to degenerate) with address (ECC's).Therefore, when reading data perhaps not The failure of address signal line can be detected.

In this case, it is obvious that the failure of address signal line can be ignored, because address (data) and ground Two classes of location (ECC) are to that can make to degenerate each other.However, working as the two of address (data) and address (ECC) of the calculating before degeneration During the A2 to A0 of each class of class centering 3 bit address parity, the value of a class becomes " 0 " and another kind of value becomes " 1 ". Therefore, it can by using the fact that distinguish two classes.Even if i.e., it is possible to being designed such as in this case, also affirming Failure can be detected.

For example, 3 be made up of continuous (000 or 111) three address parity values may be used as being affixed to 5 ECC virtual high-order 3.That is, in the A2 to A0 of address (data) 3 bit address, when including odd number " 1 ", generate " 111 " As virtual bit, and when including even number " 1 ", generation " 000 " is used as virtual bit.When reading ECC, ECC Check circuit 142 It is the value of address parity to determine the frequency chance value in the most numerical value of each in 3.Then, depending on determination value whether It is " 0 " or " 1 " that ECC Check circuit 142 is to data and ECC to the fact right and because the failure of address signal line is come The fact that be overwritten in data and the ECC of initial centering simultaneously makes a distinction.By this way, the detection of ECC Check circuit 142 address The failure of signal wire.

More specifically, when using this fault detection method, also in ECC generative circuits 131 and ECC Check circuit 142 The address signal that middle input is inputted from bus master controller.Then, ECC generative circuits 131 are indicated based on the address signal by inputting Address generate virtual bit.ECC Check circuit 142 generates address parity based on the address indicated by the address signal inputted Property, and determine generation address parity whether with from the virtual bit for being attached to be added to the ECC inputted from internal storage 14 The address parity of determination is consistent.Then, when the address parity being compared is inconsistent, ECC Check circuit 142 is definitely Location signal wire breaks down, and the fault notification signal (for example, value is " 1 ") of output notice mistake.

Herein, the value of address parity can be set to one or two by ECC generative circuits 131, but not set It is set to all 3 of virtual bit.Then, ECC Check circuit 142 can determine address parity according to the value of one or two The value of property.In this case, but, although can be with correction data, but when a bit-errors occur and to change address strange During the value of idol, the fault notification signal (for example, value is " 1 ") that uncorrectable error of giving notice occurs.Therefore, as above institute State, the value of address parity is preferably set to all 3 of virtual bit.

The example that all positions of N bit address signals to being inputted from bus master controller are rotated (displacement) makes above-mentioned explain Release.The present invention is not limited to the example.If for example, (any amount of N to 1 of the position of the defined quantity of N bit address signals Position) rotated, then obtain effect to a certain degree.As above-mentioned situation, the position of the defined quantity can be set to High-order position, low-order bit, continuous position or discontinuous position.However, as described above, it is preferred to by making all positions of N bit address signals Rotation, can detect multiple failures.

As described above, in example 2, ADR change-over circuits 120 are by resetting except the first address is (with (N+1) bit address The position of the defined quantity in the position (corresponding with low order N) outside the value of at least one correspondingly), to generate address conduct Second address.In the examples described above, ADR change-over circuits 120 are by resetting in addition to the value of at least one of the first address All positions (N number of position), to generate address as the second address.More specifically, ADR change-over circuits 120 are by making except first All positions (N number of position) outside the value of at least one of address (show in the position of high-order side's upward displacement specified quantity above-mentioned It is 1 position in example), to generate address as the second address.

This failure to two or a plurality of address signal line is equally effective.The event of the value of influence address can also be detected Barrier, this occurs in ADR change-over circuits 120 to generate and export to be input to the address signal in internal storage 14, and Occur in the address signal process circuit in memory 14 internally.

In addition, according to embodiment 2, even if occurring when in stuck-at fault (being fixed to 0 or 1) in address signal line When the write-in and reading of data are performed after in any one, due to rewriteeing both data and ECC, do not ignoring address signal In the case of the failure of line, failure can be also detected certainly.

Next, explaining the configuration and operation of embodiment 3 referring to the drawings.According to the configuration of the cpu system 1 of embodiment 3 and Operation is substantially the same with the configuration and operation of the cpu system 1 according to embodiment 1 shown in Fig. 1.Therefore, eliminate to its Explaination.Electricity is changed according to the I/F of embodiment 2 according to the configuration and operation of the I/F change-over circuits 13 of embodiment 3 and Fig. 9 The configuration and operation on road 13 are substantially the same.Therefore, the explaination to it is eliminated.However, in embodiment 3, being included in I/F and turning The ADR rotation circuits 123 that change in the ADR change-over circuits 120 in circuit 13 with according to the ADR rotation circuits 123 of embodiment 2 not Together.

Next, reference picture 18, explains the configuration of the ADR rotation circuits 123 according to embodiment 3.Herein, illustrating has The example of the address signal of N number of.Hereinafter, in order to the rotation of the address in embodiment 2 and embodiment 3 progress area Point, be in embodiment 3 expressed as the rotation of the position of address " ADR rotations 2 ", and in example 2 by the rotation of the position of address Turn to be expressed as " ADR rotations ".

Make the address indicated from address signal to anticlockwise (to high-order position side according to the ADR rotation circuits 123 of embodiment 2 To) position, to reset the position of each of N bit address signal wires.In contrast, in embodiment 3, rotate address To opposite direction.That is, address is made one to right rotation (to low-order bit direction) according to the ADR rotation circuits 123 of embodiment 3 Position.

As shown in figure 18, this be by make N bit address signal wire input phase and in the output stage in ADR rotation circuits What each bit position shift in 123 was realized with coupling.That is, the N bit address signals that will enter into ADR rotation circuits 123 Each position A0, A1, A2 ..., A (N-1) be set to treat each position of N bit address signals for being exported from ADR rotation circuits 123 A’(N-1)、A’0、A’1、……、A’(N-2).Equally, in the ADR rotation circuits 123, each position of N bit address signal wires Signal by each reception in N number of buffer 1230, and make the bit position shift of connection destination.

Next, reference picture 19, explains the configuration mapped according to the memory of the internal storage 14 of embodiment 3.With figure It is 8 positions to the data width of internal storage 14 herein, interior as the internal storage 14 according to embodiment 2 shown in 11 The address width of portion's memory 14 is that (N+1) individual position, the data volume of internal storage 14 are (8 × 2^(N+1)) individual position, and N=3 Example make explaination.

In embodiment 3, for the data that are stored with address low order N (A2 to A0 in Figure 19) value, be stored with Value with low order N of the ECC of data pair address is by (A2 to the A0 value quilt of ADR rotation circuits 123 shown in Figure 18 Labeled as in Figure 19 " part of ADR rotations 2 ") operation come the value resetting each position and obtain.

I.e., as shown in figure 19, address AD R-0 (" 0000 ") data (" DATA0 ") are with address AD R-8's (" 1000 ") ECC (" ECC0 ") matches.Address AD R-1 (" 0001 ") data (" DATA1 ") and address AD R-C (" 1100 ") ECC (" ECC1 ") matches.Address AD R-2 (" 0010 ") data (" DATA2 ") and address AD R-9 (" 1001 ") ECC (" ECC2 ") matches.Address AD R-3 (" 0011 ") data (" DATA3 ") and address AD R-D (" 1101 ") ECC (" ECC3 ") matches.Address AD R-4 (" 0100 ") data (" DATA4 ") and address AD R-A (" 1010 ") ECC (" ECC4 ") matches.Address AD R-5 (" 0101 ") data (" DATA5 ") and address AD R-E (" 1110 ") ECC (" ECC5 ") matches.Address AD R-6 (" 0110 ") data (" DATA6 ") and address AD R-B (" 1011 ") ECC (" ECC6 ") matches.Address AD R-7 (" 0111 ") data (" DATA7 ") and address AD R-F (" 1111 ") ECC (" ECC7 ") matches.

As embodiment 1 and embodiment 2, by by virtual bit (for example, value be " 0 ") added to high-order 3 by ECC 8 data are changed into, and ECC is stored in internal storage 14.As embodiment 1 and embodiment 2, when reading data When, it can detect certainly because of the failure of any one or more of lines among 8 signal lines of write-in data (8) (disconnecting) and produce value change, be used as the bit-errors or two bit-errors in ECC Check circuit 142.Above-mentioned feelings Condition is also applied for reading the failure (disconnecting) of 8 signal lines of data (8).

As for the situation of the N=3 shown in Figure 19, Figure 20 is form, this table show more than 8 rows (according to from above Rise serial number be " 0 " to " 7 ") address signal 3 A2 to A0 of low order value, about 8 differences to " DATA0 " with " ECC0 ", " DATA1 " and " ECC1 " ... and " DATA7 " and " ECC7 ".In fig. 20, will be by being inputted when reading data The address indicated to the address signal in internal storage 14 is expressed as " address (data) ", and will be by defeated when reading ECC Enter the address indicated to the address signal in internal storage 14 to be expressed as " address (ECC) ".

(1) there is no situation of the failure in all positions of address；

(2) situation in the A2 positions of address occurs for the failure of fixed 1；

(7) situation in the A0 positions of address occurs for the failure of fixed 0.

The second row (numbering is 1) of form shown in Figure 20 be show and meanwhile the data that are stored with (" DATA1 ") and with number According to the row of the ECC (" ECC1 ") of pairing address.When failure is had not occurred in all positions of address, address has most left While the low order for the ADR-1 being shown respectively 3 (" 001 ") and ADR-C low order 3 (" 100 ").In the form shown in Figure 20, A2 to A0 these values to being surrounded by solid line.

Herein, when the failure of fixed 1 occurs in A2, address is shown immediately in the right of form, wherein, address The ADR-1 of (data) is influenceed to become different ADR-5 (low order 3 is " 101 ") by failure, and address (ECC) ADR-C (low order 3 is " 100 ") is not by fault impact.In the table, A2 to A0 these values to failure influence it Value afterwards is by dotted line, also, simultaneously, A2 to A0 these values to failure influence after value in each Middle address (data) and address (ECC) by actual access is surrounded and coupled in the table with thick line by solid line.Therefore, access Data (" DATA5 ") and ECC (" ECC1 ").That is, the pairing of data and ECC has obviously been collapsed.

Equally, as other examples, further right in the table shows that the failure of fixed 1 occurs in A1 Situation in A0 occurs for situation and the failure of fixed 1, wherein, show A2 to A0 according to aforesaid way identical mode Value pair.Obviously, in both cases, data and ECC pairing have all been collapsed.

As other examples, it is related in the 7th row (numbering is 6) of the form shown in Figure 20 while the data that are stored with (" DATA6 ") and the address with the ECC (" ECC6 ") of data pair, equally, shows that the failure of fixed 0 occurs in A2 Situation in A0 occurs for the situation and the failure of fixed 0 that situation, the failure of fixed 0 occur in A1.In situation In the case of any one, data and ECC pairing have been collapsed.Pass through the form, it is obvious that when stuck-at fault hair When in any one raw in the position of address, failure can be detected certainly.

As for the situation of the N=3 shown in Figure 19, Figure 21 is form, this table show more than 8 rows (according to from above Rise serial number be " 0 " to " 7 ") address signal 3 A2 to A0 of low order value, about 8 differences to " DATA0 " with " ECC0 ", " DATA1 " and " ECC1 " ... and " DATA7 " and " ECC7 ".In figure 21, will be by being inputted when reading data The address indicated to the address signal in internal storage 14 is expressed as " address (data) ", and will be by defeated when reading ECC Enter the address indicated to the address signal in internal storage 14 to be expressed as " address (ECC) ".As Figure 20, the form is from a left side Show a case that to there occurs 7 kinds of different failures (1) to (7) to the right side.

The third line (numbering is 2) of form shown in Figure 21 be show and meanwhile the data that are stored with (" DATA2 ") and with number According to the row of the ECC (" ECC2 ") of pairing address.When failure is had not occurred in all positions of address, address is in Far Left The low order 3 (" 010 ") for the ADR-2 being shown respectively and ADR-9 low order 3 (" 001 ").In the form shown in Figure 21, A2 To A0 these values to by dotted line.

Herein, when the failure of fixed 1 occurs in A2, address is shown immediately in the right of form, wherein, address The ADR-2 of (data) is influenceed to become different ADR-6 (low order 3 is " 110 ") by failure, and address (ECC) ADR-9 (low order 3 is " 001 ") is influenceed to become different ADR-D by failure (low order 3 is " 101 ").In the table, A2 to A0 these values to failure influence after value by dotted line, also, simultaneously, in A2 to A0 these values To failure influence after value in each in by the address (data) of actual access and address (ECC) by solid line bag Enclose and coupled in the table with thick line.Therefore, data (" DATA6 ") and ECC (" ECC3 ") are accessed.I.e., it is clear that data with ECC pairing has been collapsed.

Except the value by A2 to A0 in the third line on failure influenceed after value in addition to, in the table 5th row, the 7th row and the value by A2 to A0 in eighth row on failure influenceed after value also by dotted line.So And, the combination to being four class addresses of two in the A2 to A0 shown in this 4 row value：(low order 3 is ADR-6 " 110 ") or ADR-7 (low order 3 is " 111 ") address (data) and ADR-D (low order 3 is " 101 ") or ADR-F The address (ECC) of (low order 3 is " 111 ").Therefore, though when by data and ECC to write-in with initially to different addresses When (data) and address (ECC), can also rewrite it is initial to data and ECC in one；However, data will not be rewritten simultaneously And ECC.

For the right of identical the third line, as other examples, show that the feelings in A1 occur for the failure of fixed 1 Situation in A0 occurs for condition and the failure of fixed 1, wherein, show A2 to A0's according to aforesaid way identical mode Pair of two of value.Obviously, in both cases, data and ECC pairing have all been collapsed.Again, it is clear that will not occur same When rewrite data and ECC.

As other examples, in the 6th row (numbering is 5) of the form shown in Figure 21, it is related to while the data that are stored with (" DATA5 ") and the address with the ECC (" ECC5 ") of data pair, equally, shows that the failure of fixed 0 occurs in A2 Situation in A0 occurs for the situation and the failure of fixed 0 that situation, the failure of fixed 0 occur in A1.In situation In the case of any one, data and ECC pairing have been collapsed.Will not occur at the same rewrite it is initial to data and ECC.Pass through The form, it is obvious that when stuck-at fault occurs in any one in the position of address, can detect certainly Failure.

Equally, in embodiment 3, the rotation of position (N to 1) of the defined quantity of N bit address signals can be made, strictly according to the facts Apply what example 2 was explained.

As described above, in embodiment 3, ADR change-over circuits 120 are by resetting except the first address is (with (N+1) bit address The position of the defined quantity in the position (corresponding with low order N) outside the value of at least one correspondingly), to generate address conduct Second address.In the examples described above, ADR change-over circuits 120 are by resetting in addition to the value of at least one of the first address All positions (N number of position), to generate address as the second address.More specifically, ADR change-over circuits 120 are by making except first All positions (N number of position) outside the value of at least one of address (show in the position of high-order side's upward displacement specified quantity above-mentioned It is 1 position in example), to generate address as the second address.

Therefore, effect same as Example 2 is obtained.That is, when in the ECC generated by data and by data to writing Stuck-at fault (being fixed to 0 or 1) occurs leading to the address signal of internal storage 14 after entering internally memory 14 Any one in line it is middle when, can read write-in data when detect address signal line failure.

In addition, according to embodiment 3, even if occurring when in stuck-at fault (being fixed to 0 or 1) in address signal line When the write-in and reading of data are performed after in any one, due to rewriteeing both data and ECC, do not ignoring address signal In the case of the failure of line, failure can be also detected certainly.

Next, explaining the configuration and operation of embodiment 4 referring to the drawings.According to the configuration of the cpu system 1 of embodiment 4 and Operation is substantially the same with the configuration and operation of the cpu system 1 according to embodiment 1 shown in Fig. 1.Therefore, eliminate to its Explaination.However, in example 4, it is included in configuration and operation and the root of a part for I/F change-over circuits 13 in cpu system 1 Configuration according to the I/F change-over circuits 13 of embodiment 1 is different with operation.

Next, reference picture 22, explains the configuration of the I/F change-over circuits 13 according to embodiment 4.With according to embodiment 1 I/F change-over circuits 13 compare, and include ADR order circuit for reversing 124 to replace according to the I/F change-over circuits 13 of embodiment 4 ADR circuit for reversing 121 in ADR change-over circuits 120.Circuit 110, WDT change-over circuits are controlled according to the I/F of embodiment 4 The configuration and operation of 130 and RDT change-over circuits 140 are identical with the configuration and operation of the corresponding part according to embodiment 1.

The address signal exported from bus master controller is input in ADR order circuit for reversing 124.ADR orders are anti- Shifting circuit 124 makes the reversion of the order of placement of all of the address indicated by the address signal inputted, and it is defeated to invert address Go out to selector 122.Therefore, in example 4, selector 122 selects the address signal exported from bus master controller and from ADR One in the address signal of the output of position order circuit for reversing 124, and the address signal of selection is exported to internal storage 14。

Reference picture 23, explains invert electricity according to the ADR being included in the ADR change-over circuits 120 positions order of embodiment 4 below The configuration on road 124.Herein, the example with the address signal of N number of is illustrated.

In example 2, in order to reset the positions of N bit address signals, address is made one to anticlockwise (to high-order position direction) Individual position, and in embodiment 3, make address to right rotation (to low-order bit direction) position.In contrast, in embodiment 4 In, the position of each position of reordering address signal in upside down orientation, so that the order reversion of position.That is, ADR order inverts electricity Road 124 inverts the order of placement of N number of of address signal.

As shown in figure 23, this be by make N bit address signal wire input phase and the output stage ADR order it is anti- What each bit position shift in shifting circuit 124 was realized with coupling.That is, it will enter into ADR order circuit for reversing 124 Each position A0 of N bit address signals, A1, A2 ..., A (N-2), A (N-1) be set to treat from ADR order circuit for reversing 124 Each A ' (N-1) of the N bit address signals of output, A ' (N-2) ..., A ' 1, A ' 2 and A ' 0.Electricity is inverted in the ADR order In road 124, the signal of each of N bit address signal wires makes connection mesh by each reception in N number of buffer 1240 Ground bit position shift.

However, it is necessary to reset the position of all of N bit address.Therefore, in example 4, it is assumed that N is even number.For example, In the case of N=4, the configuration of ADR order circuit for reversing 124 is as shown in figure 24.

Equally, in example 4, as embodiment 2 and embodiment 3 are explained, it is also preferred that resetting the rule of N bit address signals The position (N number of position into 1 position one) of fixed quantity.

As described above, in example 4, ADR change-over circuits 120 are by resetting except the first address is (with (N+1) bit address The position of the defined quantity in the position (corresponding with low order N) outside the value of at least one correspondingly), to generate address conduct Second address.More specifically, ADR change-over circuits 120 are by resetting the institute in addition to the value of at least one of the first address There is position (N number of position), to generate address as the second address.In the examples described above, ADR change-over circuits 120 are by making except first The order of placement reversion of all positions (N number of position) outside the value of at least one of address, to generate address as the second address.

It is, therefore, apparent that obtaining and embodiment 2 and the identical effect of embodiment 3.Therefore, eliminate to the detailed of its Explaination.

In the embodiment 2, embodiment 3 and embodiment 4 being illustrated above, have in common that, with the ECC's of data pair Circuit (such as ADR rotation circuits 123 or ADR order circuit for reversing 124) is reset by address and changed in address.

In the presence of the various modes of the address rearrangement method for the position of all for resetting N bit address.Here, it is assumed that pattern count Amount is SN (" N " is enter into the quantity of the position of the address signal in above-mentioned I/F change-over circuits 13 in SN).In N=2 feelings Under condition, a pattern (S2=1) shown in Figure 25 is only existed.In the case of N=3, there are two patterns shown in Figure 26 (S3=2).The first mode shown above Figure 26 is corresponding with " the ADR rotations " shown in embodiment 2.The second mould shown in Figure 26 Formula with shown in embodiment 3 " ADR rotations are 2 " corresponding.

In the case of N=4, there are 9 patterns (S4=9) shown in Figure 27.The in the top of a row of left-hand side One pattern is corresponding with " the ADR rotations " shown in embodiment 2, second mode with shown in embodiment 3 " ADR rotations are 2 " corresponding, and 3rd pattern is corresponding with " ADR orders are inverted " in embodiment 4.Herein, three shown in the row of Figure 26 bottom Pattern is two set of the address bit that each two position is rearranged.Therefore, if failure occurs be included in two set simultaneously In one in 2 bit address signal wires in, then there is the constraint that can not perform fault detect.

In general, the quantity for the address rearrangement method of N bit address (N >=3) is provided as the formula 1 shown in Figure 28.

I.e., as shown in figure 27, the rearrangement of the position of the position of the address performed by ADR change-over circuits 120 is not limited in reality Apply " the ADR rotations " explained in example 2 to 4, " ADR rotations 2 " and " ADR orders are inverted ".In following embodiment 5, explaination Pass through " the address rearrangement method of ADR rotations 3 " of Figure 27 most descending centre.

In addition, explaining the configuration and operation of embodiment 5 referring to the drawings.According to the configuration of the cpu system 1 of embodiment 5 and behaviour Make substantially the same with the configuration and operation of the cpu system 1 according to embodiment 1 shown in Fig. 1.Therefore, eliminate and it is explained Release.The I/F change-over circuits according to embodiment 2 according to the configuration and operation of the I/F change-over circuits 13 of embodiment 5 and Fig. 9 13 configuration and operation is substantially the same.Therefore, the explaination to it is eliminated.However, in embodiment 5, being included in I/F conversions The configurations of the ADR rotation circuits 123 in ADR change-over circuits 120 in circuit 13 and operation with according to embodiment 2 and embodiment 3 ADR rotation circuits 123 configuration it is different with operation.

Next, reference picture 29, explains the configuration of the ADR rotation circuits 123 according to embodiment 5.Herein, illustrating has The example of the address signal of N number of.Hereinafter, the rotation of the address according to embodiment 5 is expressed as " ADR rotations 3 ".

Make the address indicated from address signal to anticlockwise (to high-order position side according to the ADR rotation circuits 123 of embodiment 2 To) position, to reset the position of each of N bit address signal wires.In embodiment 3, make address (extremely low to right rotation Component level direction) position.However, in embodiment 5, make address to right rotation (to high-order position direction) two positions.

As shown in figure 29, this be by make N bit address signal wire input phase and in the output stage in ADR rotation circuits What each bit position shift in 123 was realized with coupling.That is, the N bit address signals that will enter into ADR rotation circuits 123 Each position A0, A1, A2 ..., A (N-1) be set to treat each position of N bit address signals for being exported from ADR rotation circuits 123 A’(N-2)、A’(N-1)、A’0、A’1、……、A’(N-3).Equally, in the ADR rotation circuits 123, N bit address signal wires The signal of each by each reception in N number of buffer 1230, and make the bit position shift of connection destination.

Herein, in the case of N=4, figure 30 illustrates configuration.Such as by Figure 30 it will be apparent that in N=4 feelings Under condition, this equates make address to anticlockwise (to low-order bit direction) two positions.This row lucky with the bottom in Figure 27 Centre " ADR rotation 3 " shown in correspondence.

Next, reference picture 31, explains the configuration mapped according to the memory of the internal storage 14 of embodiment 5.Herein, It is that 8 positions, the address width of internal storage 14 are (N+1) individual position, internal storage to the data width of internal storage 14 14 data volume is (8 × 2^(N+1)) individual position, and N=4 example makes explaination.

Left side half in Figure 31 is used as the region of storing initial data by internal storage 14, and the right half is used Make the region for the ECC that storage is matched with primary data.That is, by the region in memory 14 internally divide into by address most The value (A4 in Figure 31) of high-order position is set to be stored with when " 0 " regions of data, and divides into by the most high-order of address The value of position is set to be stored with when " 1 " ECC region.

In embodiment 5, for the value of low order N (A3 to A0 in Figure 31) of the address for the data that are stored with, it is stored with A kind of arrangement is changed to the value of low order N of the ECC of data pair address, in this arrangement, by shown in Figure 30 (in Figure 31, A3 to A0 value is marked as that " part of ADR rotations 3 ", i.e., be shown as in half on the right to ADR rotation circuits 123 A4=1 region) operation reset each position.

I.e., as shown in figure 31, address AD R-00 (" 00000 ") data (" DATA0 ") and address AD R-10 (" 10000 ") ECC (" ECC0 ") match.Address AD R-01 (" 00001 ") data (" DATA1 ") and address AD R-14 (" 10100 ") ECC (" ECC1 ") match.Address AD R-02 (" 00010 ") data (" DATA2 ") and address AD R-18 (" 11000 ") ECC (" ECC2 ") match.Address AD R-03 (" 00011 ") data (" DATA3 ") and address AD R-1C (" 11100 ") ECC (" ECC3 ") match.Address AD R-04 (" 00100 ") data (" DATA4 ") and address AD R-11 (" 10001 ") ECC (" ECC4 ") match.Address AD R-05 (" 00101 ") data (" DATA5 ") and address AD R-15 (" 10101 ") ECC (" ECC5 ") match.Address AD R-06 (" 00110 ") data (" DATA6 ") and address AD R-19 (" 11001 ") ECC (" ECC6 ") match.Address AD R-07 (" 00111 ") data (" DATA7 ") and address AD R-1D (" 11101 ") ECC (" ECC7 ") match.The data (" DATA8 ") in other addresses can be understood according to the mode similar to Figure 31 Each into data (" DATAF ") and progress in each in the ECC (" ECC8 ") to ECC (" ECCF ") of other addresses The corresponding relation of pairing.

In embodiment 2 and embodiment 3, it is assumed that N=3, as shown in Figure 11 and Figure 19, storage is included to internal storage 14 Data and the example of each 8 addresses (3 A2 to A0 of low order of address combination) in correspondence ECC make explaination.With This is on the contrary, in embodiment 5, it is assumed that it is every in data storage and correspondence ECC that N=4, Figure 31 show that internal storage 14 includes The example of 16 addresses (as many as twice) of one.

As embodiment 2 and embodiment 3 are explained, equally, in embodiment 5, it is also preferred that making the regulation of N bit address signals Quantity position (N number of position into 1 position one) rotation.

As described above, in embodiment 5, ADR change-over circuits 120 are by resetting except the first address is (with (N+1) bit address The position of the defined quantity in the position (corresponding with low order N) outside the value of at least one correspondingly), to generate address conduct Second address.In the examples described above, ADR change-over circuits 120 are by resetting in addition to the value of at least one of the first address All positions (N number of position), to generate address as the second address.More specifically, ADR change-over circuits 120 are by making except first All positions (N number of position) outside the value of at least one of address (show in the position of high-order side's upward displacement specified quantity above-mentioned It is 2 positions in example), to generate address as the second address.

It is, therefore, apparent that obtaining and embodiment 2 to the identical effect of embodiment 4.Therefore, eliminate to the detailed of its Explaination.

Next, explaining the configuration and operation of embodiment 6 referring to the drawings.According to the configuration of the cpu system 1 of embodiment 6 and Operation is substantially the same with the configuration and operation of the cpu system 1 according to embodiment 1 shown in Fig. 1.Therefore, eliminate to its Explaination.However, in embodiment 6, it is included in configuration and operation and the root of a part for I/F change-over circuits 13 in cpu system 1 Configuration according to the I/F change-over circuits 13 of embodiment 1 is different with operation.

Next, reference picture 32, explains the configuration of the I/F change-over circuits 13 according to embodiment 6.With according to embodiment 1 I/F change-over circuits 13 compare, and including ADR displacement ＆ skews according to the I/F change-over circuits 13 of embodiment 6 sets circuit 125 come generation For the ADR circuit for reversing 121 in ADR change-over circuits 120.Circuit 110, WDT change-over circuits are controlled according to the I/F of embodiment 6 The configuration and operation of 130 and RDT change-over circuits 140 are identical with the configuration and operation of the corresponding part according to embodiment 1.

The address signal exported from bus master controller and 2 shifted signals are input to ADR displacement ＆ skews circuit is set In 125.ADR displacement ＆ skew setting circuits 125 make defined multiple bit shifts of the address signal of input, by other modifications For the deviant indicated by shifted signal, and amended address signal is exported to selector 122.Therefore, in embodiment 6 In, selector 122 selects the address signal exported from bus master controller and shifts the ground that ＆ skews set circuit 125 to export from ADR One in the signal of location, and the address signal of selection is exported to internal storage 14.

Next, reference picture 33, explains the ADR being included in the ADR change-over circuits 120 displacement ＆ skews according to embodiment 6 The configuration of circuit 125 is set.Herein, pair assume that address signal is N and shifted signal is that the example of M (M=2) is made and explained Release.

As shown in figure 33, shifted according to the ADR of embodiment 6 ＆ skews set shown in circuit 125 and Figure 29 according to embodiment The difference of 5 ADR rotation circuits 123 is that 2 positions indicated by shifted signal are used for high-order 2, instead of using with other Mode is displaced to the low order 2 (A1 and A0) of high-order 2.

That is, ADR displacement ＆ skews set circuit 125 to include skew and set register 1251.2 shifted signals are got back to Skew sets register 1251, is used as deviant.It will be stored in skew and set each in 2 deviants in register 1251 It is individual to set circuit 125 to export from ADR displacement ＆ skews, it is used as the high-order 2 of N bit address signals.

Therefore, the address of the N bit address signal designations in circuit 125 will be set by being input to ADR displacement ＆ skews respectively The A2 of high-order (N-M) position ..., A (N-1) is set to treat to shift the N bit address signals that ＆ skews set circuit 125 to export from ADR The A ' 0 of low order (N-M) position, A ' 1 ..., A ' (N-3).It will be set respectively by being input to ADR displacement ＆ skews in circuit 125 The B (N-2) and B (N-1) for the deviant that shifted signal is indicated are set to treat to shift the N that ＆ skews set circuit 125 to export from ADR The A ' (N-2) and A ' (N-1) of remaining high-order M of bit address signal.

Equally, in ADR displacement ＆ skews set circuit 125, (N-M) bit address signal wire from A2 to A (N-1) The signal of each position makes the bit position shift of connection destination by each reception in (N-M) individual buffer 1250.

Herein, in the case of N=4, ADR displacement ＆ skews are configured as setting circuit 125 as shown in figure 34.That is, divide Not will enter into ADR displacement ＆ skews sets the high-order 2 (A2 and A3) of the address signal in circuit 125 to be set to treat to move from ADR Position ＆ skews set the low order 2 (A ' 0 and A ' 1) of the address signal of the output of circuit 125.ADR displacement ＆ skews are will enter into respectively 2 positions (B2 and B3) of the shifted signal in circuit 125 are set to be set to treat that shifting ＆ skews from ADR sets what circuit 125 was exported The high-order 2 (A ' 2 and A ' 3) of address signal.

Next, reference picture 35, explains the configuration mapped according to the memory of the internal storage 14 of embodiment 6.Herein, It is that 8 positions, the address width of internal storage 14 are (N+1) individual position, internal storage to the data width of internal storage 14 14 data volume is (8 × 2^(N+1)) individual position, and N=4 example makes explaination.

Left side half in Figure 35 is used as the region of storing initial data by internal storage 14, and by the right half A part is used as the region for the ECC that storage is matched with primary data.That is, the region in memory 14 internally is divided into and incited somebody to action The value (A4 in Figure 35) of the highest component level of address is set to be stored with when " 0 " regions of data, and divides into by address The value of highest component level be set to be stored with when " 1 " ECC region.

In embodiment 6, for the value of low order N (A3 to A0 in Figure 35) of the address for the data that are stored with, it is stored with Place value is changed to the value of low order N of the ECC of data pair address, the place value is to shift ＆ by the ADR shown in Figure 34 Skew sets circuit 125, and (A3 to A0 value is marked as the part or on the right of " ADR displacement ＆ skew set " in Figure 35 The A3=1 being shown as in a part for half among A4=1 region and A2=1 region) operation change.That is, show The position B2 and B3 of indicated by shifted signal 2 deviants are come to the example for being set to " 1 ".

I.e., as shown in figure 35, address AD R-00 (" 00000 ") to ADR-03 (" 00011 ") data (" DATA0 " extremely " DATA3 ") matched with address AD R-1C (" 11100 ") ECC (" ECC0 (0,1,2,3) ").Address AD R-04 The data (" DATA4 " to " DATA7 ") of (" 00100 ") to ADR-07 (" 00111 ") and address AD R-1D (" 11101 ") ECC (" ECC1 (4,5,6,7) ") match.Address AD R-08 (" 01000 ") to ADR-0B (" 01011 ") data (" DATA8 " To " DATAB ") matched with address AD R-1E (" 11110 ") ECC (" ECC2 (8,9, A, B) ").Address AD R-0C The data (" DATAC " to " DATAF ") of (" 01100 ") to ADR-0F (" 01011 ") and address AD R-1F (" 11111 ") ECC (" ECC3 (C, D, E, F) ") matches.That is, all 2 positions of deviant are set to " 1 "；Therefore, without using ADR-10 (" 10000 ") to ADR-1B (" 11011 ") 12 addresses.

Herein, in embodiment 1 into embodiment 5,5 ECC are generated by 8 data, and by the way that virtual bit (is worth for 0) It is attached to high-order 3 and is changed to 8 data, is then stored in internal storage 14.However, in embodiment 6,7 Position ECC generate by 32 (four addresses) data, and by virtual bit (value be 0) is attached to a position of most high-order and by 8 data are changed into, are then stored in internal storage 14.

Therefore, in embodiment 6, when 32 data are write in internal storage 14, bus master controller is with every 8 positions Four steps write 32 data, specify continuous address.32 data (" DATA0 " to " DATA3 ") are write for example, working as When entering in internal storage 14, for the first time, bus master controller will indicate address AD R-00 (" 00000 ") address signal and write-in Data (" DATA0 ") are exported to I/F change-over circuits 13.Second, bus master controller will indicate address AD R-01's (" 00001 ") Address signal and write-in data (" DATA1 ") are exported to I/F change-over circuits 13.For the third time, bus master controller will indicate address ADR-02 (" 00010 ") address signal and write-in data (" DATA2 ") is exported to I/F change-over circuits 13.4th time, bus master Address AD R-03 (" 00011 ") address signal will be indicated and write data (" DATA3 ") output to I/F change-over circuits by controlling device 13。

ECC generative circuits 131 will be combined by four sections of write-in data of four write-in inputs, to generate 32 data, and And 32 data based on generation generate ECC.ECC generative circuits 131 are by exporting in last time write-in (the 4th time) The ECC for the generation being related to, the ECC of generation is write in internal storage 14.Therefore, even if for the first time will not be true to third time Definite value writing address ADR-1C (" 11100 "), this is rewritten not when writing for the 4th time also by the ECC by 32 data generations It is determined that value.Therefore, be not in problem.

In embodiment 6, when reading 32 data from internal storage 14, bus master controller is by specifying continuously Location, 32 data are read with four steps of every 8 positions.32 data are read for example, working as from internal storage 14 When (" DATA0 " to " DATA3 "), for the first time, bus master controller will indicate address AD R-00 (" 00000 ") address signal output To I/F change-over circuits 13.Second, bus master controller exports the address signal for indicating address AD R-01 (" 00001 ") to I/F Change-over circuit 13.For the third time, the address signal for indicating address AD R-02 (" 00010 ") is exported to I/F and changed by bus master controller Circuit 13.4th time, bus master controller exports the address signal for indicating address AD R-03 (" 00011 ") to I/F change-over circuits 13。

ECC Check circuit 142 and error detection circuit 143 exist four sections of reading data combinations that input is read by four times Together, and generate 32 data.32 data of the ECC Check circuit 142 based on generation generate ECC, and based on generation The ECC that reads for ECC and the 4th time detect the mistake of 32 data.Then, drawn really according to ECC Check circuit 142 Determine result, Error-Correcting Circuit 143 actually exports 32 data, or, after being corrected to 32 data, by it Output to bus master controller is used as reading data.However, in embodiment 6, will be treated from mistake with four steps of every 8 positions 32 of the output of correcting circuit 143 read data outputs to bus master controller.

As for the situation of the N=4 shown in Figure 35, Figure 36 shows the table of the value of the low order 4 (A3 to A0) of address signal Lattice, it is on four classes pair：" DATA0 " to " DATA3 " and " ECC0 ", " DATA4 " to " DATA7 " and " ECC1 ", " DATA8 " are extremely " DATAB " and " ECC2 " and " DATAC " to " DATAF " and " ECC3 "., will be by being input to when reading data in Figure 36 The address that address signal in internal storage 14 is indicated is expressed as " address (data) ", and will be by being inputted when reading ECC The address indicated to the address signal in internal storage 14 is expressed as " address (ECC) ".

(1) there is no situation of the failure in all positions of address；

(2) situation in the A3 positions of address occurs for the failure of fixed 1；

(3) situation in the A3 positions of address occurs for the failure of fixed 0；

(4) situation in the A2 positions of address occurs for the failure of fixed 1；

(5) situation in the A2 positions of address occurs for the failure of fixed 0；

(6) situation in the A1 positions of address occurs for the failure of fixed 1；And

(7) situation in the A1 positions of address occurs for the failure of fixed 0.

The situation and the failure of fixed 0 that the failure of fixed 1 occurs in the A0 positions of address occur in the A0 positions of address Each situation in situation occurs situation and the failure of fixed 0 in the A1 positions of address with the failure of fixed 1 and occurred on ground Each situation in the case of in the A1 positions of location is similar.Therefore, them are omitted from the table.In sequence by the position of each Four values (0 or 1) at the place of putting are set to A3 to A0 value.Under value at the position for the position for hindering for some reason in its value and changing Rule in face.

The second row (numbering is 4 to 7) of form shown in Figure 36 is to show while the data that are stored with (" DATA4 " extremely " DATA7 ") and row with the ECC (" ECC1 ") of data pair address.When failure is had not occurred in all positions of address, Address has ADR-4 to the ADR-07 low order 4 (" 0100 " to " 0111 ") that is shown respectively in Far Left and ADR-A's is low Rank 4 (" 1101 ").In the form shown in Figure 36, four addresses of address (data) and the individual address of address (ECC) To being surrounded by solid line.

Herein, in the address when the failure of fixed 1 occurs in A3, (low order 4 is address AD R-04 to ADR-07 " 0100 " to " 0111 ") by fault impact become different address AD R-0C to ADR-0F (low order 4 be " 1100 " extremely " 1111 "), and address AD R-1D (low order 4 is " 1101 ") is not by fault impact.In the table, A3 to A0 value pair Failure influence after value by dotted line, also, simultaneously, A3 to A0 these values to failure influence after Value in each in surrounded by the address (data) of actual access and address (ECC) by solid line and use thick line in the table Connection.It is as shown here, access the data (" DATAC " to " DATAF ") of fourth line and the ECC (" ECC2 ") of the second row.That is, show So, data and ECC pairing have been collapsed.

As another example, show a case that the failure of fixed 0 occurs in A3 in the further right of form, its In, according to pair with aforesaid way identical mode come the value that shows A3 to A0.In this case, address AD R-1D (low orders 4 Position is " 1101 ") become different address AD R-15 (low order 4 is " 0101 ") by fault impact, and address is not used in and deposited Store up ECC.It is, therefore, apparent that data and ECC pairing have been collapsed.

As another example, show that the feelings in A1 occur for the failure of fixed 0 in the rightmost of the row of identical second Condition, wherein, according to pair with aforesaid way identical mode come the value that shows A3 to A0.In this case, address AD R- is made 04 to ADR-07 (low order 4 be " 0100 " to " 0111 ") deteriorates to two address ADs R-04 and ADR-05, and (low order 4 is " 0100 " and " 0101 ").Therefore, data (" DATA6 ") and the data being respectively stored at address AD R-06 and ADR-07 are read (" DATA7 ") is impossible.It is, therefore, apparent that data and ECC pairing have been collapsed.

As another example, in the third line of the form shown in Figure 36, it is related to while the data that are stored with (" DATA8 " extremely " DATAB ") and address with the ECC (" ECC2 ") of data pair, equally, show that the failure of fixed 1 occurs in A2 Situation in A1 occurs for the situation and the failure of fixed 1 that situation, the failure of fixed 0 occur in A2.In situation In the case of any one, data and ECC pairing have been collapsed.Pass through the form, it is obvious that when stuck-at fault hair When in any one raw in the position of address, failure can be detected certainly.Illustrate and be both configured to skew (2 positions) The situation of " 1 ".However, in the case that skew to be set to other values " 0 ", it is clear that can also obtain identical with the effect above Effect.Therefore, the detailed explaination to it is eliminated.

In addition, when write-in and reading that data are performed after stuck-at fault occurs in any one of the position of address When, address (data) and address (ECC) to becoming from initial to different pairs.However, this is different to obviously (being counted with address According to) and address (ECC) (that is, the address that will not be degenerated) it is another difference to inconsistent.Therefore, will not occur while rewriteeing data And ECC.Therefore, or even after stuck-at fault occurs in any one in the position of address, it is clear that can also examine certainly Measure failure.

As described above, in embodiment 6, by except the first address (corresponding with (N+1) bit address) at least one Position (corresponding with low order N) outside position is central, makes position from low order in addition to the defined position for offseting bit quantity to low Rank direction shift offsets bit quantity, also, simultaneously, by the bits of offset that amount of displacement (corresponding with M position) will be polarized from high-order It is revised as setting deviant, to generate address as the second address.

Accordingly, it is clear that can obtain and embodiment 2 to the identical effect of embodiment 5.Therefore, eliminate to the detailed of its Explaination.

Next, explaining the configuration and operation of embodiment 7 referring to the drawings.According to the configuration of the cpu system 1 of embodiment 7 and Operation is substantially the same with the configuration and operation of the cpu system 1 according to embodiment 1 shown in Fig. 1.Therefore, eliminate to its Explaination.Electricity is changed according to the I/F of embodiment 6 according to the configuration and operation of the I/F change-over circuits 13 of embodiment 7 and Figure 32 The configuration and operation on road 13 are substantially the same.Therefore, the explaination to it is eliminated.However, being changed according to the I/F of embodiment 7 In circuit 13, the configuration and operation of a part for ADR change-over circuits 120 and matching somebody with somebody for the ADR change-over circuits 120 according to embodiment 6 Put different with operation.Matching somebody with somebody for circuit 110, WDT change-over circuits 130 and RDT change-over circuits 140 is controlled according to the I/F of embodiment 7 Put and operate configuration and operation with the corresponding part according to embodiment 6 identical.

Next, reference picture 37, explains the configuration of the ADR change-over circuits 120 according to embodiment 7.

As shown in figure 37, compared with the ADR change-over circuits 120 according to embodiment 6, electricity is changed according to the ADR of embodiment 7 Road 120 further comprises ADR scopes limiting circuit 126.

ADR scopes limiting circuit 126 limits address (data).The address signal inputted from bus master controller is input to In ADR scopes limiting circuit 126.When not including by the address signal that inputs in data-storable scope is previously determined to be During the address of instruction, ADR scopes limiting circuit 126 is modified to address, so that it can be in the range of, and will be indicated The address signal of amended address exports to selector 122 and ADR displacement ＆ skews and sets circuit 125.On the other hand, when When being previously determined to be data-storable scope and including the address indicated by the address signal that inputs, ADR scopes limitation electricity The address signal for indicating amended address is actually exported to selector 122 and ADR displacement ＆ skews and sets circuit by road 126 125。

Next, reference picture 38, explains and shifts the configuration that ＆ skews set circuit 125 according to the ADR of embodiment 7.Herein, Illustrate the example of N bit address signals.

As shown in figure 38, shifted according to the ADR of embodiment 7 ＆ skews set shown in circuit 125 and Figure 34 according to embodiment 6 ADR displacement ＆ skews set the difference of circuit 125 to be that deleting skew sets register 1251.I.e. according to embodiment 7 It is advance that ADR displacement ＆ skews set circuit 125 to be fixed to each place value of the skew arbitrarily set in embodiment 6 (2 positions) The value (it is assumed herein that being " 1 ") of determination.

Therefore, the address of the N bit address signal designations in circuit 125 will be set by being input to ADR displacement ＆ skews respectively High-order (N-M) position A2 and A3 are set to by treating to shift the ground that ＆ offsets the N bit address signal designations for setting circuit 125 to export from ADR Low order (N-M) position A ' 0 and A'1 of location.The position B2 and B3 (value is " 1 ") that provide deviant are set to respectively to treat to move from ADR Position ＆ skews set remaining high-order M A ' (the N-2)=A ' 2 and A ' (N-1)=A ' 3 of the N bit address signals of the output of circuit 125.

Next, reference picture 39, explains and is mapped according to the memory of the internal storage 14 of embodiment 7.Herein, to inside The data width of memory 14 be 8 positions, internal storage 14 address width be N number of position, the data volume of internal storage 14 It is (8 × 2^N) individual position, and N=4 example makes explaination.That is, in embodiment 7, # signals will not waited to be used as indicating address High-order position signal.

Internal storage 14 uses 12 addresses above Figure 39 as the region of data storage, and uses following four Address is used as the region for storing ECC.That is, internally in the region of memory 14, for N number of position (figure of the address of data storage A3 to A0 in 39) value, the value of N number of of storage and the ECC of data pair address is moved by the ADR shown in Figure 38 Position ＆ skews set circuit 125 (value of the A3 to A0 in Figure 39 be marked as " ADR displacement ＆ skew set " part or Region from four addresses of bottom) operation come the value changed.

I.e., as shown in figure 39, address AD R-0 (" 0000 ") to ADR-3 (" 0011 ") data (" DATA0 " extremely " DATA3 ") matched with address AD R-C (" 1100 ") ECC (" ECC0 (0,1,2,3) ").Address AD R-4 (" 0100 ") is extremely ADR-7 (" 0111 ") data (" DATA4 " to " DATA7 ") and address AD R-D (" 1101 ") ECC (" ECC1 (4,5,6, 7) ") match.Address AD R-8 (" 1000 ") is to the data (" DATA8 " to " DATAB ") of ADR-B (" 1011 ") and address ADR-1E (" 1110 ") ECC (" ECC2 (8,9, A, B) ") matches.Last address AD R-F (" 1111 ") is not used Region.

Therefore, when the address that is indicated by address signal indicates to be stored with ECC address AD R-C (" 1100 ") to ADR-F During one in (" 1111 "), ADR scopes limiting circuit 126 modifies the addressed into the address AD R-0 in the data that are stored with Predetermined address among (" 0000 ") to ADR-B (" 1011 ").

As described above, in embodiment 7, by making the position in addition to the position of defined skew bit quantity from the first address The low order of (corresponding with N bit address) is to low order direction shift offsets bit quantity, also, simultaneously, by will skew bit quantity (with M Individual position correspondence) bits of offset be revised as setting deviant from high-order, to generate address as the second address.

Accordingly, it is clear that can obtain and embodiment 2 to the identical effect of embodiment 6.Therefore, eliminate to the detailed of its Explaination.According to embodiment 7, the region for the address being not used by memory 14 internally can be reduced.

In embodiment 7, include when in the scope for being previously determined to be the scope that the second address can take by bus master During the first address that control device is specified, the address specified by bus master controller is revised as predefining by ADR scopes limiting circuit 126 The address for the address that can be taken for the first address.

Therefore, even if bus master controller specifies storage ECC address and gets out the write-in of data, such as according to implementation As in the configuration of example 7, the address that bus master controller writes the data in addition to ECC the ECC that is stored with is also possible to prevent.

Next, explaining the configuration and operation of embodiment 8 referring to the drawings.According to the configuration of the cpu system 1 of embodiment 8 and Operation is substantially the same with the configuration and operation of the cpu system 1 according to embodiment 1 shown in Fig. 1.Therefore, eliminate to its Explaination.Electricity is changed according to the I/F of embodiment 6 according to the configuration and operation of the I/F change-over circuits 13 of embodiment 8 and Figure 32 The configuration and operation on road 13 are substantially the same.However, in the I/F change-over circuits 13 according to embodiment 8, being included in ADR conversions ADR displacement ＆ skews in circuit 120 set the configuration and operation of a part for circuit 125 with shifting ＆ according to the ADR of embodiment 6 Skew sets the configuration of circuit 125 different with operation.

In embodiment 8, ECC Mode can be switched to two ECC Modes.Under the first ECC Mode, bus master controller Perform and 8 data are write into internal storage 14 and 8 data are read from internal storage 14, and 5 ECC are generated as 8 data and 5 ECC are stored in internal storage 14.Under the second ECC Mode, bus master controller is performed 32 Data write internal storage 14 and read 32 data from internal storage 14, and 7 ECC are generated as into 32 data And 7 ECC are stored in internal storage 14.

According to the ADR of embodiment 8 shift ＆ skew set circuit 125 can by operate switch to shown in Figure 29 according to reality Apply the ADR rotation circuits 123 of example 5 operation or Figure 33 shown according to the ADR of embodiment 6 shift ＆ skew set circuit 125 operation.

That is, according to the ADR change-over circuits 120 of embodiment 8 can " ADR revolves according to setting ECC Mode to switch to operation Turn " or " ADR displacement ＆ skews are set ".

Next, reference picture 40, explains and shifts the configuration that ＆ skews set circuit 125 according to the ADR of embodiment 8.

As shown in figure 40, compared with ＆ skew setting circuits 125 are shifted according to the ADR of embodiment 6, according to embodiment 8 ADR displacement ＆ skews set circuit 125 to further comprise the selector 1252 with the quantity of the position of shifted signal as many.Over the ground Location signal is N and shifted signal is that the example of M (M=2) makes explaination.

It will enter into each in low order M A0 and A1 of the address signal in ADR displacement ＆ skew setting circuits 125 It is input in each selector 1252 in two selectors 1252.It will indicate that being stored in skew is set in register 1251 Each shifted signal in the shifted signal B (N-2) and B (N-1) of 2 deviants is input to every in two selectors 1252 In one selector 1252.

Each selector 1252 in selector 1252 selects low order M of the address signal inputted from bus master controller In A0 and A1 each or from skew set register 1251 input shifted signal B (N-2) and B (N-1) in it is each It is individual, and the signal of selection is exported, it is used as high-order M for the address signal for treating to shift the ＆ skew setting outputs of circuit 125 from ADR A ' (N-2) and A ' (N-1).

The ECC mode signal of specified ECC Mode is input in each selector 1252 in selector 1252.When defeated When entering ECC mode signal (" 0 ") of specified first ECC Mode, each selector 1252 selection address in selector 1252 Each in low order M A0 and A1 of signal.On the other hand, when the ECC mode signal of the second ECC Mode is specified in input When (" 1 "), each in each selector 1252 selection shifted signal B (N-2) and B (N-1) in selector 1252 is inclined Shifting signal.

Will enter into respectively ADR displacement ＆ skew set circuit 125 in address signal high-order (N-M) position A2 ..., A (N-1) each be set to treat from ADR shift the address signal that ＆ skews set circuit 125 to export low order (N-M) position A ' 0, A’1、……、A’(N-3).That is, operation and figure of the operation with the ADR rotation circuits 123 according to embodiment 5 shown in Figure 29 Set the operation of circuit 125 identical according to the ADR of embodiment 6 displacement ＆ skews shown in 33.Equally, set in ADR displacement ＆ skews In circuits 125, each in N number of buffer 1250 has been received by N bit address signal wire A0 to A (N-1) each position Signal after, utilize the signal.

As described above, in embodiment 8, when specifying first mode, ADR displacement ＆ skews set circuit 125 to be removed by making Offset as defined in all positions to relatively low direction displacement outside at least one of first address (corresponding with (N+1) bit address) Bit quantity, to generate address as the second address.When specifying second mode, ADR displacement ＆ skews set circuit 125 to pass through, Among position in addition at least one of the first address, make the position from low order in addition to offseting the position of bit quantity to low Direction shift offsets bit quantity, and by being revised as the bits of offset for being polarized amount of displacement (corresponding with M) from high-order to set Deviant, to generate address as the second address.

Accordingly, under the first ECC Mode, it is clear that optionally obtain and the identical effect of embodiment 5.Therefore, save The detailed explaination to it is omited.Equally, under the second ECC Mode, it is clear that optionally obtain and the identical effect of embodiment 6 Really.Therefore, the detailed explaination to it is eliminated.

Next, explaining the configuration and operation of embodiment 9 referring to the drawings.According to the configuration of the cpu system 1 of embodiment 9 and Operation is substantially the same with the configuration and operation of the cpu system 1 according to embodiment 1 shown in Fig. 1.Therefore, eliminate to its Explaination.Electricity is changed according to the I/F of embodiment 6 according to the configuration and operation of the I/F change-over circuits 13 of embodiment 9 and Figure 32 The configuration and operation on road 13 are substantially the same.However, in the I/F change-over circuits 13 according to embodiment 9, ADR change-over circuits 120 A part configuration and operate it is different from the configuration and operation of the ADR change-over circuits 120 according to embodiment 6.

Next, reference picture 41, explains the configuration of the I/F change-over circuits 13 according to embodiment 9.With according to embodiment 6 I/F change-over circuits 13 compare, and including ADR reverse shifts ＆ skews according to the I/F change-over circuits 13 of embodiment 9 sets circuit 127 To replace the ADR in ADR change-over circuits 120 to shift ＆ skews, circuit 125 is set.Circuit is controlled according to the I/F of embodiment 9 110th, the configuration and operation and the configuration of the corresponding part according to embodiment 6 of WDT change-over circuits 130 and RDT change-over circuits 140 It is identical with operation.

In embodiment 9, ECC Mode can be switched to two ECC Modes.Under the first ECC Mode, bus master controller Perform and 8 data are write into internal storage 14 and 8 data are read from internal storage 14, and 5 ECC are generated as 8 data and 5 ECC are stored in internal storage 14.Under the second ECC Mode, bus master controller is performed 32 Data write internal storage 14 and read 32 data from internal storage 14, and 7 ECC are generated as into 32 data And 7 ECC are stored in internal storage 14.

In the value reversion for making the position in addition to the position of the predetermined quantity from low order, predetermined quantity is displaced to low order Position, and the deviant indicated by shifted signal is set to after the position of the position of the predetermined quantity from high-order, according to implementation The ADR reverse shifts ＆ skews of example 9 set circuit 127 to switch to being inverted according to the ADR of embodiment 1 shown in Fig. 3 by operating The operation of circuit 121 or address signal is exported to the operation of selector 122.Therefore, in embodiment 9, selector 122 In selecting the address signal exported from bus master controller and the address signal for offseting the setting output of circuit 127 from ADR reverse shifts ＆ One, and the address signal of selection is exported to internal storage 14.

That is, according to the ADR change-over circuits 120 of embodiment 9 can " ADR be anti-according to setting ECC Mode to switch to operation Turn " or " ADR displacement ＆ skews are set ".

Next, reference picture 42, explains the configuration for being offset according to the ADR reverse shifts ＆ of embodiment 9 and setting circuit 127.

As shown in figure 42, ADR reverse shifts ＆ skews set circuit 127 to include N section values circuit for reversing 1270, skew and set Put register 1271 and N segment selectors 1272.To address signal be N number of position and shifted signal be M position (M=2) example Make explaination.

Each section in the N sections of place value circuit for reversing 1270 with the position A0 of N bit address signals, A1, A2 ..., A (N-1) In each correspondence.Each section in the N sections of place value circuit for reversing 1270 make address signal corresponding position value reversion, and Value after output reversion.For example, place value circuit for reversing 1270 is NOT circuits.

Herein, by N number of A0 of address signal, A1 ..., each input in A (N-2) and A (N-1) reverse value To N number of A ' 0 of OPADD signal, A ' 1 ..., it is each in the N sections of A ' (N-2) and A ' (N-1) selector 1272 Section.By high-order (N-M) position A2 of address signal, A3 ..., each input in A (N-2) and A (N-1) reverse value is to defeated Go out low order (N-M) position A ' 0 of address signal, A ' 1 ..., in (N-M) section of A ' (N-4) and A ' (N-3) selector 1272 Each section.

M shifted signals are got back into skew register 1271 is set, be used as deviant.It will be stored in skew and deposit be set Each M A ' (N-2) of high-order for being input to OPADD signal and A ' (N-1) choosing in M positions deviant in device 1271 Select in each section in the M sections of device 1272.

Low order (N-M) position A ' 0 of OPADD signal, A ' 1 ..., the choosing of each in A ' (N-4) and A ' (N-3) Select low order (N-M) position A0 of each section in (N-M) section of device 1272 selection and OPADD signal, A1 ..., A (N-4) and High-order (N-M) position A2 of each or address signal in A (N-3) reverse value, A3 ..., A (N-2) and A (N-1) Each in reverse value.

The ECC mode signal of specified ECC Mode is input in each in selector 1272.When input specifies first During ECC mode signal (" 0 ") of ECC Mode, the low order of each section of selecting address signal in (N-M) section of selector 1272 (N-M) position A0, A1 ..., each in A (N-4) and A (N-3) reverse value.On the other hand, when the 2nd ECC is specified in input During ECC mode signal (" 1 ") of pattern, the high-order (N-M) of each section of selecting address signal in (N-M) section of selector 1272 Position A2, A3 ..., each in A (N-2) and A (N-1) reverse value.

It is every in the M selector 1272 of each in M A ' (N-2) of high-order of OPADD signal and A ' (N-1) In the selection of one selector and M A (N-2) of high-order of OPADD signal and A (N-1) reverse value each or it is inclined Each in shifting value B (N-2) and B (N-1).

When ECC mode signal (" 0 ") of the first ECC Mode is specified in input, each selection in M selector 1272 Each in M A (N-2) of high-order of device selecting address signal and A (N-1) reverse value.On the other hand, when input specifies the During ECC mode signal (" 1 ") of two ECC Modes, each selector 1272 selection deviant B (N-2) in selector 1272 With each in B (N-1).

As described above, in embodiment 9, when specifying first mode, ADR reverse shifts ＆ skews set circuit 127 to pass through Make all values reversion of position in addition at least one of the first address (corresponding with N+1), the is used as to generate address Double-address.When specifying second mode, ADR reverse shifts ＆ skews set circuit 127 by making at least one except the first address The value reversion of position outside individual position, by making the position from low order in addition to the position of defined skew bit quantity to low order direction Shift offsets bit quantity, and by the way that the bits of offset that amount of displacement (corresponding with M) is polarized from high-order is changed into setting skew Value, to generate address as the second address.

Accordingly, under the first ECC Mode, it is clear that optionally obtain and the identical effect of embodiment 1.Therefore, save The detailed explaination to it is omited.Equally, under the second ECC Mode, it is clear that optionally obtain and the identical effect of embodiment 6 Really.Therefore, the detailed explaination to it is eliminated.

Next, explaining the configuration and operation of embodiment 10 referring to the drawings.According to the configuration of the cpu system 1 of embodiment 10 It is substantially the same with the configuration and operation of the cpu system 1 according to embodiment 1 shown in Fig. 1 with operating.Therefore, eliminate to it Explaination.The I/F according to embodiment 6 according to the configuration and operation of the I/F change-over circuits 13 of embodiment 10 and Figure 32 turns Change the configuration of circuit 13 and operate substantially the same.However, in the I/F change-over circuits 13 according to embodiment 10, being included in ADR ADR displacement ＆ skews in change-over circuit 120 set configuration and operation and the ADR according to embodiment 6 of a part for circuit 125 Shifting ＆ skews sets the configuration of circuit 125 different with operation.

In embodiment 10, ECC Mode can be switched to two ECC Modes.Under the first ECC Mode, bus master Device, which is performed, to be write internal storage 14 by 8 data and reads 8 data from internal storage 14, and 5 ECC are generated It is stored in for 8 data and by 5 ECC in internal storage 14.Under the second ECC Mode, bus master controller is performed 32 Position data write internal storage 14 and read 32 data from internal storage 14, and 7 ECC are generated as into 32 digits It is stored according to and by 7 ECC in internal storage 14.

According to the ADR of embodiment 10 shift ＆ skew set circuit 125 can by operate switch to shown in Fig. 3 according to reality Apply the ADR circuit for reversing 121 of example 1 operation or Figure 33 shown according to the ADR of embodiment 6 shift ＆ skew set circuit 125 operation.

That is, according to the ADR change-over circuits 120 of embodiment 10 can " ADR be anti-according to setting ECC Mode to switch to operation Turn " or " ADR displacement ＆ skews are set ".

Next, reference picture 43, explains and shifts the configuration that ＆ skews set circuit 125 according to the ADR of embodiment 10.

As shown in figure 43, compared with ＆ skew setting circuits 125 are shifted according to the ADR of embodiment 6, according to embodiment 10 ADR displacement ＆ skews set circuit 125 to further comprise the N sections of ADR selection circuits 1253.It is N to address signal and inclined Shifting signal is that the example of M (M=2) makes explaination.

Via buffer 1250 by N number of A0 of address signal, A1 ..., A (N-2), A (N-1) value each is defeated Enter the N number of A ' 0 to OPADD signal, A ' 1 ..., in the N sections of A ' (N-2) and A ' (N-1) ADR selection circuits 1253 Each section.Via buffer 1250 by high-order (N-M) position A2 of address signal, A3 ..., A (N-2) and A (N-1) value Each input to low order (N-M) position A ' 0 of OPADD signal, A ' 1 ..., A ' (N-4) and A ' (N-3) ADR select electricity Each section in (N-M) section on road 1253.

M shifted signals are got back into skew register 1251 is set, be used as deviant.It will be stored in skew and deposit be set M positions deviant B (N-2) and B (N-1) in device 1251 are input to M A ' (N-2) of high-order and the MA ' (N-1) of OPADD signal In the ADR selection circuits 1253 of each M sections in each section in.

Low order (N-M) position A ' 0 of OPADD signal, A ' 1 ..., the ADR of each in A ' (N-4) and A ' (N-3) Low order (N-M) position A0 of each section in (N-M) section of selection circuit 1253 selection and OPADD signal, A1 ..., A (N- 4) high-order (N-M) position A2 of each or address signal and in A (N-3) reverse value, A3 ..., A (N-2) and A (N- 1) each in value.

The ECC mode signal of specified ECC Mode is input in each in ADR selection circuits 1253.When input refers to During ECC mode signal (" 0 ") of fixed first ECC Mode, each section of selection address in (N-M) section of ADR selection circuits 1253 Low order (N-M) position A0 of signal, A1 ..., each in A (N-4) and A (N-3) value, and export the reversion of selective value Value.The value selected herein is described as " the first value " later.On the other hand, when the ECC Mode letter of the second ECC Mode is specified in input When number (" 1 "), high-order (N-M) position of each section of selection and OPADD signal in (N-M) section of ADR selection circuits 1253 A2, A3 ..., each in A (N-2) and A (N-1) value.The value selected herein is described as " second value " later.

M A ' (N-2) of high-order of OPADD signal and the M sections of the ADR selection circuits 1253 of each in A ' (N-1) In each section of selection and M A (N-2) of high-order of OPADD signal and A (N-1) reverse value in each or it is inclined Each in shifting value B (N-2) and B (N-1).

It is every in the M sections of ADR selection circuits 1253 when ECC mode signal (" 0 ") of the first ECC Mode is specified in input Each in M A (N-2) of high-order of one section of selecting address signal and A (N-1) value, and export the reverse value of selective value. The value selected herein is described as " the first value " later.On the other hand, when the ECC mode signal of the second ECC Mode is specified in input It is each in each section of selection and output offset value B (N-2) and B (N-1) in the M sections of ADR selection circuits 1253 when (" 1 ") It is individual.The value selected herein is described as " second value " later.

Next, reference picture 44, explains the configuration of the ADR selection circuits 1253 according to embodiment 10.

As shown in figure 44, ADR selection circuits 1253 include NOR circuit 12531, AND circuit 12532 and OR circuits 12533。

NOR circuit 12531 regard signal output to OR circuits 12533 as the NOR of the first value and the value of ECC mode signal The operation result of (negative logic addition).AND circuit 12532 regard signal output to OR circuits 12533 as second value and ECC moulds The AND (logic product) of the value of formula signal operation result.The output signal of OR circuits 12533, is inputted as from NOR circuit 12531 Signal and from AND circuit 12532 input signal OR (logical addition) operation result.

As described above, in embodiment 10, when specifying first mode, ADR displacement ＆ skews set circuit 125 by making The all values reversion of position in addition at least one of the first address (corresponding with N+1), to generate address as second Address.When specifying second mode, ADR displacement ＆ skews set circuit 125 to pass through, except at least one position of the first address Outside position among, make from low order the position for not including the position of defined skew bit quantity to low direction shift offsets bit quantity, And by being revised as the bits of offset for being polarized amount of displacement (corresponding with M) from high-order to set deviant, make to generate address For the second address.

Therefore, under the first ECC Mode, it is clear that optionally obtain and the identical effect of embodiment 1.Therefore, save The detailed explaination to it is omited.Equally, under the second ECC Mode, it is clear that optionally obtain and the identical effect of embodiment 6 Really.Therefore, the detailed explaination to it is eliminated.

Next, explaining the configuration and operation of embodiment 11 referring to the drawings.Reference picture 45, is explained according to embodiment 11 The configuration of cpu system 1.As shown in figure 45, with relatively being shown according to what the cpu system 1 of embodiment 1 was carried out shown in Fig. 1, according to The cpu system 1 of embodiment 1 does not include control input I/F 11, order output I/F 12 and I/F change-over circuits 13, but including Hardware accelerator 20, sensor I/F I/F 21, actuator I/F 22, change-over circuit 23, DDR I/F 24 and DDR memory 25。

In embodiment 11, vehicle is provided with the sensor unit as input block.Sensor unit observation vehicle Around and by the sensing data for indicating observed result send to cpu system 1, be used as input data.For example, sensor unit It is radar or camera.

Vehicle is provided with the actuating unit controlled by cpu system 1, is used as control unit.For example, control unit is direction Disk or brake.

In the cpu system 1 according to embodiment 11, CPU 10 has coenocytism.CPU10 is based on coming from sensor unit Sensing data generate control data.For example, when control data is directed to steering wheel, the generation instruction modifications of CPU 10 direction The control data of the steering angle of disk is used as control content.For example, when control data is for brake, the generation instructions of CPU 10 are adjusted The control data of section brake oil pressure is used as control content.

Hardware accelerator 20 is the hardware of coenocytism and addedly performs CPU 10 processing.For example, hardware-accelerated Device 20 is GPU (graphics processing unit) or DSP (digital signal processor).

Sensor I/F 21 is by the interface circuit of sensor unit couples to system bus.That is, sensor list will be come from The sensing data of member is input in sensor I/F 21.Actuator I/F 22 is that actuating unit is coupled into system bus Interface circuit.That is, actuator I/F 22 will be exported to actuating unit for the order for controlling actuating unit.

Change-over circuit 23 is the interface circuit that DDR I/F 24 are coupled to system bus.As described later, with root According to as the I/F change-over circuits 13 of embodiment 1 to 10, the perform detection data signal system of change-over circuit 23 and address signal system Failure processing, when each bus master controller (CPU 10, DMAC 15 and hardware accelerator 20) via system bus in DDR DDR memory 25 is accessed under I/F 24 auxiliary (to write data into DDR memory 25 or read number from DDR memory 25 According to).

More specifically, when writing data into DDR memory 25, the ECC that change-over circuit 23 will also be generated by data It is written in DDR memory 25.When reading data from DDR memory 25, change-over circuit 23 generates ECC from data are read, and And be compared the ECC of the generation and ECC that is written in the DDR memory 25 with data, and therefore detect failure.Together Sample, in embodiment 11, ECC address is stored by being generated from the address of data storage, not only can be with data detection signal system The failure of system, can also detect the failure of address signal system.

DDR I/F 24 are performed from DDR memory 25 according to the packet inputted via change-over circuit 23 from bus master controller Read data or write data into DDR memory 25.That is, in embodiment 11, bus master controller passes through according to packet Form will indicate the data of writing address and indicate the data output for writing data to change-over circuit 23, to perform writing for data Enter.Bus master controller according to block form by will indicate the data output for reading address to change-over circuit 23, to perform data Reading.

DDR memory 25 is the storage circuit for storing Various types of data.That is, DDR memory 25 is stored, for example, above-mentioned sensing Device data, control data (order) and ECC.

Next, reference picture 46, explains the configuration of the change-over circuit 23 according to embodiment 11.As shown in figure 46, electricity is changed Road 23 includes WADR change-over circuits 210, RADR change-over circuits 220, WDT change-over circuits 230 and RDT change-over circuits 240.Herein, " WADR " indicates writing address, and " RADR " indicates to read address." WDT " and " RDT " such as embodiment 1 is explained.

Bus master controller will indicate the packet of writing address via system bus, indicate to read the packet of address and indicate The packet of write-in data is exported to change-over circuit 23.Change-over circuit 23 will indicate packet and the mistake of reading data via system bus Notification signal is exported to bus master controller by mistake.Change-over circuit 23 is based on the clock signal inputted from clock forming circuit (not shown) To operate.

When writing data into DDR memory 25, bus master controller will indicate writing for the address as write-in data Enter the packet of address and indicate that the packet for being used as the write-in data of write-in data is exported to change-over circuit 23.In response to this, change Circuit 23 exports these packets to DDR I/F 24, also, in addition, will indicate to be used as write-in ECC corresponding with write-in data Address ECC addresses packet and indicate that the ECC packet being written in DDR memory 25 is exported to DDR I/F 24.

DDR I/F 24 write the write-in data indicated by the packet from change-over circuit 23 by from change-over circuit 23 Packet indicate DDR memory 25 writing address.DDR I/F 24 are also by by the packet instruction from change-over circuit 23 The ECC addresses for the DDR memory 25 that ECC write-ins are indicated by the packet from change-over circuit 23.

When reading data from DDR memory 25, bus master controller is with will indicating to be used as the reading of the address of reading data The packet of location is exported to change-over circuit 23.In response to this, change-over circuit 23 exports the packet to DDR I/F 24, also, separately Outside, it will indicate to be used as reading the packet output with the ECC addresses as the corresponding ECC of the reading data of data to be read address To DDR I/F 24.

The reading address of DDR I/F 24 from the DDR memory 25 indicated by the packet from change-over circuit 235, which is read, reads Access evidence, and the packet for indicating the reading data read is exported to change-over circuit 23.DDR I/F 24 also from by from Read ECC, and the packet for the ECC that instruction is read in the ECC addresses for the DDR memory 25 that the packet of change-over circuit 23 is indicated Export to change-over circuit 23.

Then, when by using the reading data indicated by the packet from DDR I/F 24 and by from DDR I/F 24 The ECC that indicates of packet, when checking to detect the mistake of data, change-over circuit 23 is by the fault notification signal of notification error Export to bus master controller.

As shown in figure 46, WADR change-over circuits 210 include ADR generative circuits 212 that address buffer 211, ECC specify, Control switching circuit 213 and selector 214.

Address buffer 211 is to export the packet of the instruction writing address from bus master controller to selector 214 simultaneously And then temporarily keep the memory of the packet.

The write-in that the specific ADR generative circuits 212 of ECC are indicated based on the packet by being stored in address buffer 211 Location, to generate the packet for indicating ECC addresses.The operation of ECC addresses is generated with being inverted according to the ADR of embodiment 1 from writing address The operation of circuit 121 is identical.Therefore, the detailed explaination to it is eliminated.The specific ADR generative circuits 212 of ECC divide generation Group is exported to selector 214.It is however to be noted that in embodiment 11,212 pairs of the specific ADR generative circuits of ECC are in embodiment 1 In switched over by the value of highest component level for the address signal for waiting the switching of # signals.

When the packet for indicating writing address is exported to selector 214 from address buffer 211, control switching circuit 213 indicate the selection packet of selector 214.More specifically, control switching circuit 213 extremely selects data/ECC signals (" 0 ") output Select device 214.Complete from address buffer 211 to export the packet for indicating writing address to selector 214, will indicate The packet of ECC addresses from the specific ADR generative circuits 212 of ECC export to selector 214 while, control switching circuit 213 refers to Show the selection packet of selector 214.More specifically, control switching circuit 213 exports data/ECC signals (" 1 ") to selector 214。

When from 213 input datas of control switching circuit/ECC signals (" 0 ") when, selector 214 is selected from address buffer The packet of 211 inputs, and the packet of selection is exported to DDR I/F 24.On the other hand, when defeated from control switching circuit 213 When entering data/ECC signals (" 1 "), selector 214 selects the packet inputted from the specific ADR generative circuits 212 of ECC, and will The packet of selection is exported to DDR I/F 24.

The configuration and operation of RADR change-over circuits 220 are identical with the configuration and operation of WADR change-over circuits 210.Therefore omit Explaination to it.

As shown in figure 46, WDT change-over circuits 230 include data buffer 231, ECC generative circuits 232, switching control electricity Road 233 and selector 234.

Data buffer 231 is to export the packet of the instruction write-in data from bus master controller to selector 234 simultaneously And then temporarily keep the memory of the data.

The write-in data that ECC generative circuits 232 are indicated based on the packet by being stored in data buffer 231, to generate Indicate ECC packet.Operation from write-in data generation ECC is identical with the operation of the ECC generative circuits 131 according to embodiment 1. Therefore, the detailed explaination to it is eliminated.ECC generative circuits 232 export the packet of generation to selector 234.

While by indicating that the packet for writing data is exported to selector 234 from data buffer 231, switching control electricity Road 233 indicates the selection packet of selector 234.More specifically, control switching circuit 233 exports data/ECC signals (" 0 ") extremely Selector 234.Complete from data buffer 231 to export the packet for indicating to write data to selector 234, will refer to Show the packets of ECC addresses from ECC generative circuits 232 export to selector 234 while, control switching circuit 233 indicates selection The selection packet of device 234.More specifically, control switching circuit 233 exports data/ECC signals (" 1 ") to selector 234.

When from 233 input datas of control switching circuit/ECC signals (" 0 ") when, selector 234 is selected from data buffer The packet of 231 inputs, and the packet of selection is exported to DDR I/F 24.On the other hand, when defeated from control switching circuit 233 When entering data/ECC signals (" 1 "), selector 234 selects the packet inputted from ECC generative circuits 232, and dividing selection Group is exported to DDR I/F 24.

RDT change-over circuits 240 include data buffer 241, enable control circuit 242, ECC Check circuit 243 and mistake Correcting circuit 244.

Data buffer 241 is that the packet that the instruction from DDR I/F 24 is read into data is exported to ECC Check circuit 243 and Error-Correcting Circuit 244, and the then memory of temporarily storage packet.The storage of data buffer 241 comes from DDR I/ F 24 instruction ECC packet.

When the packet for indicating ECC is stored in into data buffer 241, enables the control output of circuit 242 and enable signal, with It is determined that whether the mistake of the data indicated by the packet being stored in data buffer 241 occurs.More specifically, enabling control electricity Road 242 enables signal (" 1 ") output to ECC Check circuit 243 by what is asserted.When remaining, enabling control circuit 242 will Go that asserts to enable signal (" 0 ") output to ECC Check circuit 243.For example, later that description is electric by ECC inspections when completing Road 243 carries out timing really, and enabling control circuit 242 will go that asserts to enable signal (" 0 ") output to ECC Check circuit 243.

In response to from enable control circuit 242 assert enable signal (" 1 "), ECC Check circuit 243 is based on by depositing Data and be grouped the ECC indicated by being stored in data buffer 241 that packet of the storage in data buffer 241 is indicated, To determine whether the mistake of data has occurred and that.

When ECC Check circuit 243 determines that mistake is had occurred and that in any one position of data, ECC Check circuit 243 By the error correction signal output of the position of indicating bit to Error-Correcting Circuit 244.When the determination of ECC Check circuit 243 can not school When positive 2 or multi-bit error are had occurred and that in data, ECC Check circuit 243 is by the fault notification signal of notification error Export to bus master controller.

When mistake is had not occurred in data, Error-Correcting Circuit 244 will actually be inputted from data buffer 241 Indicate that the packet of data is exported to bus master controller, be used as reading data.On the other hand, when mistake is had occurred and that in data When, the mistake for the data that 244 pairs of Error-Correcting Circuit is indicated by the packet inputted from data buffer 241 is corrected, and Then by data output to bus master controller.The method of the specific error correction of data and configuration and the mistake according to embodiment 1 The method of correcting circuit 143 is identical with configuration.Therefore, the explaination to it is eliminated.

Herein, in DDR memory 25, pass through and specify column address and row address, it is possible to specify read data address or Person writes the address of data.DDR I/F 24 are by the Address Resolution that will be indicated by packet for column address and row address and with two Individual step transmits the address signal for indicating each address to DDR memory 25, to realize the access to DDR memory 25.Cause This, reduces the quantity of the address signal line between DDR I/F 24 and DDR memory 25.However, for example, working as DDR memory When the quantity of 25 data signal line is 32, the low order 2 of the address indicated by packet is meaningless；Therefore they are not exported To DDR memory 25.

However, when stuck-at fault occur one in address signal line it is middle when, above-mentioned configuration is equal to is consolidated by 2 The address for fault impact of shaping.However, according to embodiment 11,2 or multi-bit error can be detected as described above；Therefore, agree Surely it may also detect that this mistake.

Herein, reference picture 47 explains other effects of embodiment 11.More specifically, as shown in figure 47, DDR I/F 24 are wrapped Include DDR control circuits 310 and cache memory 320.

The packet that DDR controls circuit 310 to read address according to the instruction exported from change-over circuit 23 is stored in DDR to read The data read at address of memory 25.When by data buffer storage to cache memory 320, DDR control circuit 310 from Cache memory 320 reads data, rather than is read from DDR memory 25.Then, DDR controls the generation of circuit 310 to indicate The packet of the data read, as reading data, and the packet of generation is exported to change-over circuit 23.

Cache memory 320 is managed using association scheme is set and including multiple paths.Set when using n roads During association scheme, cache memory 320 includes n region of a variety of data that are stored with.Each in n region uses n Each of the different path address of class is marked.

Association scheme is set using 4 tunnels in Figure 47.Figure 47 shows each in four regions with four class.paths Each class in location (" 00 ", " 01 ", " 10 " and " 11 ") is marked.Here, it is assumed that path address reads address using N High-order 2.

In embodiment 11, RADR change-over circuits 220 make the ECC's of low order N of the reading among (N+1) position of address The place value of address is reversed to read the address of data.Therefore, when the path address for reading data is " 00 ", ECC road is read Footpath address becomes " 11 ".That is, according to embodiment 11, the value that low order is 1 is on the road of the mark and storage ECC in the path of data storage It is different from each other between the mark in footpath.

Therefore, when 1 corresponding signal of low order with path address among address signal line occurs for stuck-at fault When in line, the mark from low order 1 with identical value reads data and ECC.Therefore, data and ECC pairing collapse. As a result, failure is detected by RDT change-over circuits 240.I.e., it is understood that embodiment 11 can be suitably applied to this DDR I/F 24。

To performing basis in by using the configuration according to the packet of embodiment 11 to perform write-in and the reading of data The example of the address conversion of embodiment 1 makes explaination.However, example is not limited to this.By using according to embodiment 11 It is grouped in the configuration of write-in and reading to perform data, it is also preferred that performing the ground of one in other embodiments 2 to 10 Change location.When the quantity of the position of quantity as defined in for making address signal is less than the value reversion of N position or reset, at a high speed Marked with the position of at least one of the position of the defined quantity including address signal in each path of buffer storage 320 Note.

As described above, in embodiment 11, address buffer 211 stores the ground of instruction first received from bus master controller First packet of location.WADR change-over circuits 210 and RADR change-over circuits 220 are based on by being stored in address buffer 211 The first address that one packet is indicated, two address second packet is indicated to generate.WADR change-over circuits 210 will be from bus master The first packet transmission that device is received is sent to DDR I/F 24 to DDR I/F 24, and by the second packet of generation.Therefore, WADR change-over circuits 210, which are performed, to be write data into the first address and error detection code is write into the second address.RADR is changed Circuit 220 sends out the first packet transmission received from bus master controller to DDR I/F 24, and by the second packet of generation Deliver to DDR I/F 24.Therefore, RADR change-over circuits 220 are performed from the first address reading data and read from the second address wrong Error detection code.

Therefore, though when performing the write-in and reading of data according to the form of the packet from bus master controller, The failure of address signal system can be detected.When providing connected reference continuous multiple addresses in order to improve data access efficiency Burst access mode when, preferably export initial value, be used as address corresponding with the scope accessed by burst access Low order multidigit, by it from the specific ADR generative circuits 212 of the ECC of WADR change-over circuits 210 and RADR change-over circuits 220 Address conversion target exclude.Even if in this case, when stuck-at fault occurs in DDR I/F 14 and DDR memory One in address signal line between 25 it is middle when, via with low order multidigit identical address signal line, be broken down into row ground The corresponding higher-order multi-bit sent after location and row address can also be influenceed by stuck-at fault.Accordingly it is also possible to detect this Plant failure.

In embodiment 11, DDR I/F 24 cache the data of DDR memory 25 using association scheme is set Cache memory 320.By making in addition to the value of at least one of the first address (corresponding with (N+1) bit address) Position (corresponding with low order N) among defined quantity position value reversion, to generate address as the second address.It is slow at a high speed The each path for rushing memory is marked with the position of at least one in the position including defined quantity.

It therefore, it can detect that address is believed by shifting the function in DDR I/F 24 cache memory 320 The failure of number system.

Next, explaining the configuration and operation of embodiment 12 referring to the drawings.According to the configuration of the cpu system 1 of embodiment 12 It is substantially the same with the configuration and operation of the cpu system 1 according to embodiment 1 shown in Fig. 1 with operating.Therefore, eliminate to it Explaination.However, in embodiment 12, it is included in the configuration and operation of a part for I/F change-over circuits 13 in cpu system 1 Configuration and operation from the I/F change-over circuits 13 according to embodiment 1 is different.

Next, reference picture 48, explains the configuration of the I/F change-over circuits 13 according to embodiment 12.With according to embodiment 10 I/F change-over circuits 13 compare, according to the I/F change-over circuits 13 of embodiment 12 further comprise ECC Mode control circuit 150。

ECC Mode control circuit 150 includes ECC Mode and sets register 151.ECC Mode set register 151 store with The relevant all kinds of arranges values of ECC Mode.ECC Mode controls circuit 150 to be set according to ECC Mode is stored in register 151 Arranges value, to perform the control to enabling or disabling ECC Mode and the control to switching ECC Mode when enabling ECC Mode.

Herein, register 151 is set for example, following (1)-(4) are set to ECC Mode, is used as arranges value.Herein, exist (2) in-(4), multiple groups be each associated can be set.

(1) enable/disable ECC Mode

(2) ECC Mode

(3) scope (for example, being specified by the start address and end address of scope) of ECC Mode

(4) skew from the region of data storage to the region for storing ECC

When the arranges value for disabling ECC Mode being stored in ECC Mode setting register 151, ECC Mode control circuit 150 suppress in I/F controls circuit 110, ADR change-over circuits 120, WDT change-over circuits 130 and RDT change-over circuits 140 with ECC (is written in internal storage 14, ECC is read from internal storage 14 and determined based on ECC by relevant ECC processing Error in data).

For example, ECC Mode controls circuit 150 that the ECC for going to assert is enabled into signal (" 0 ") output to I/F control circuits 110.When going the ECC asserted to enable signal (" 0 ") from the ECC Mode control input of circuit 150, I/F control circuits 110 suppress The wait # signals (" 0 ") of output assertion in first clock cycle.

On the other hand, when being stored in the arranges value for enabling ECC Mode in ECC Mode setting register 151, ECC moulds Formula control circuit 150 allows to control circuit 110, ADR change-over circuits 120, WDT change-over circuits 130 and RDT change-over circuits in I/F ECC (is written in internal storage 14, reads ECC from internal storage 14 and be based on by the processing relevant with ECC in 140 ECC determines error in data).

For example, ECC Mode controls circuit 150 that the ECC asserted is enabled into signal (" 1 ") output to I/F control circuits 110. When the ECC that the input assertion of circuit 150 is controlled from ECC Mode enables signal (" 1 "), I/F controls circuit 110 in the first clock week The wait # signals (" 0 ") of output assertion in phase.

Also the address signal being input to from bus master controller in ADR change-over circuits 120 is input to ECC Mode control circuit In 150.When enabling ECC Mode, ECC Mode control circuit 150 determines whether the address indicated by address signal is included in (3) ECC Mode in the range of.When the address indicated by address signal is included in the range of ECC Mode, ECC Mode control electricity Road 150 will specify the ECC moulds being arranged on according to associated mode in the range of ECC Mode sets the ECC Mode of register 151 The ECC mode signal of formula is exported to ADR change-over circuits 120.

ECC Mode control circuit 150 by the value of high-order L of the address signal inputted from bus master controller be revised as and by Photograph association mode be arranged on ECC Mode set register 151 ECC Mode in the range of above-mentioned (4) deviant phase Plus value.ECC Mode controls circuit 150 by the signal output of the amended value of instruction to internal storage 14.L signals are used as To be input to the signal of high-order L of (N+L) bit address signal in internal storage 14.

Therefore, as shown in figure 49, can be first as the data being stored in the specific scope in internal storage 14 ECC corresponding with data is stored under ECC Mode, and as the data being stored in other specific scopes, can be in the 2nd ECC ECC corresponding with data is stored under pattern.

Therefore, as shown in figure 50, address is changed.That is, under the first ECC Mode shown in Figure 50 upper part, The value added to high-order L of (N+L) bit address will be offset, and invert the value of low order N.Shown in Figure 50 lower part The second ECC Mode under, will offset added to (N+L) bit address high-order L value.As for the low order value of N, by high-order M Position is revised as being arranged on skew and sets skew in register 1251, and high-order (N-M) position is changed into low in low order (N-M) position The value of direction displacement.

To controlling the showing applied to the I/F change-over circuits according to embodiment 10 of circuit 150 according to the ECC Mode of embodiment 12 Example makes explaination.However, example is not limited to this.Circuit 150 is controlled to can apply to basis according to the ECC Mode of embodiment 12 The I/F change-over circuits 13 of one in embodiment 8 and 9.

Reference picture 51, regard the configuration for explaining semiconductor device 9 as the cpu system 1 according to above-described embodiment 1 to 12 below General introduction configuration.I.e., as shown in figure 51, a part for the characteristic configuration being extracted in the cpu system 1 according to embodiment 1 to 12.

As shown in figure 51, semiconductor device 9 includes address conversion circuit 91, write circuit 92 and reading circuit 93.

Address conversion circuit 91 is used to store based on for storing data in the first address in memory 94 to generate Second address of the error detection code generated by data.Address conversion circuit 91 is corresponding with ADR change-over circuits 120.

When request is write data into the first address, write circuit 92 is write data into the first address while will Error detection code is write in the second address.Write circuit 92 is corresponding with WDT change-over circuits 130.

When request is from the first address reading data, reading circuit 93 is read from the first address reading data from the second address Take error detection code, and mistake is detected based on data and error detection code.Reading circuit 93 and RDT change-over circuits 140 correspondences,

Here, at least one value of the address conversion circuit 91 by the first address of modification, by making error detection generation The storage location of code is offset to the storage location of data, and by inverting the value of the position of the defined quantity among other positions Or reset, to generate address as second address.

As described above, having been based on embodiment specifically to illustrate the present invention completed by the present inventor.However, must not Do not emphasize that the present invention is not limited to above-described embodiment, and can in a variety of ways change in the range of without departing from main points.

In above-described embodiment 1 to 12, it is included in enabling the ECC that single bit error correction and 2 or multi-bit error are detected (error correction code) is used as detecting that the wrong error detection code of data is explained.However, example is not limited In this.It is also preferred that using CRC (Cyclical Redundancy Check) or parity code, being used as error detection code.However, it is more preferred to sharp With the ECC for not only enabling error detection and also enabling error correction, as described above.

In above-mentioned internal storage 14 or DDR I/F 24 address signal process circuit, even in execution in logic In the case of the processing that address is changed between address and physical address, the present embodiment can also be applied.

The quantity and value of the position of above-mentioned various types of signal are not limited to above-mentioned example.For example, enabling signal and error notification letter Number the value asserted can be set to " 0 ", and the value of negative is set to " 1 ".It can be that high state is effectively believed to wait # signals Number.Write-in/reading signal can set the values to write-in being appointed as " 1 ", and set the values to reading being appointed as " 0 ". Wait multiple positions that # signals can be the defined high-order position for specifying address.

Data width, address width and the data volume of above-mentioned internal storage 14 are not limited to above-mentioned example.Deviant Position M quantity is not limited to the example of above-mentioned two position.Deviant is not limited to above-mentioned value.

Claims

1. a kind of semiconductor device, including：

Address conversion circuit, the address conversion circuit is based on for storing data in the first address in memory, next life Into the second address for storing the error detection code generated by the data；

Write circuit, said write circuit writes the data when the data are write first address by request described First address, and the error detection code is write second address by said write circuit；And

Reading circuit, the reading circuit is when request is read and is stored in the data of first address from first ground The data are read in location, and the reading circuit reads the error detection code and based on relevant from second address The data and the relevant error detection code detect mistake,

Wherein, the address conversion circuit is by changing the value of at least one of first address, so that the mistake inspection The storage location for surveying code is displaced to the storage location of the data, and by making the position of the defined quantity among other positions Value reversion or make defined quantity among other positions position order rearrangement, to generate address as second ground Location.

2. semiconductor device according to claim 1,

Wherein, the address conversion circuit is by inverting the value of institute's rheme of the defined quantity, to generate address conduct Second address.

3. semiconductor device according to claim 1,

Wherein, the address conversion circuit by reset it is described as defined in quantity institute's rheme order, to generate address conduct Second address.

4. semiconductor device according to claim 3,

Wherein, the address conversion circuit by make it is described as defined in quantity institute's bit shifts to high-order direction or low order side To generate address as second address.

5. semiconductor device according to claim 3,

Wherein, the address conversion circuit is made by inverting the order of institute's rheme of the defined quantity to generate address For second address.

6. semiconductor device according to claim 1,

Wherein, the address conversion circuit among the position in addition at least one of first address by making from low Institute's rheme that rank plays in addition to institute's rheme of defined skew bit quantity shifts the skew bit quantity to low order direction, and By the way that the bits of offset of the skew bit quantity from high-order is revised as into default deviant, to generate address as described Second address.

7. semiconductor device according to claim 1,

Wherein, the address conversion circuit is by making in first address from low order except defined skew bit quantity Institute's rheme outside institute's rheme shifts the skew bit quantity to low order direction, and by will from high-order the skew digit The bits of offset of amount is revised as default deviant, to generate address as second address.

8. semiconductor device according to claim 7,

Wherein, from the write-in and the reading of the data of data described in bus master requests,

Wherein, first address is specified by the bus master controller, and

Wherein, the semiconductor device further comprises address limiting circuit, when described specified by the bus master controller One address is included in when being confirmed as in advance in the scope that second address allows, and the address limiting circuit will be by described total It is revised as being confirmed as in advance the address for the address that first address allows in the address that line main controller is specified.

9. semiconductor device according to claim 1,

Wherein, when specifying first mode, the address conversion circuit is by making except at least one position of first address Outside institute's rheme to low order direction displacement as defined in skew bit quantity, to generate address as second address, and

Wherein, when specifying second mode, the address conversion circuit passes through except at least one position of first address Outside institute's rheme among, make from low order except it is described skew bit quantity institute's rheme in addition to institute's rheme to low order direction move The position skew bit quantity, and by the way that the bits of offset of the skew bit quantity from high-order is revised as into default skew Value, to generate address as second address.

10. semiconductor device according to claim 1,

Wherein, when specifying first mode, the address conversion circuit is by making except at least one position of first address Outside position value reversion, to generate address as second address, and

Wherein, when specifying second mode, the address conversion circuit makes in addition at least one position of first address Position value reversion, make from low order except it is defined skew bit quantity institute's rheme in addition to institute's rheme to low order direction shift The skew bit quantity, and the bits of offset of the skew bit quantity from high-order is revised as default deviant.

11. semiconductor device according to claim 1,

Wherein, when specifying second mode, the address conversion circuit passes through except at least one position of first address Outside institute's rheme among, make institute's rheme from low order in addition to institute's rheme of defined skew bit quantity to low order direction The skew bit quantity is shifted, and it is default inclined by the way that the bits of offset of the skew bit quantity from high-order is revised as Shifting value, to generate address as second address.

12. semiconductor device according to claim 1,

Wherein, the write-in of the data is asked by the bus master controller,

Wherein, the bus master controller will enable signal output to the memory, for performing the write-in of the data The write-in of the data is enabled during unit interval,

Wherein, the semiconductor device further comprises controlling circuit, and the control circuit is in response to by the bus master controller The described of the write-in for being used to enable the data of output enables signal, to bus master controller output in the unit interval Period is used for the second waiting signal for disabling the operation of the bus master controller, instead of the behaviour for enabling the bus master controller The first waiting signal made, and

Wherein, the data are write first address by said write circuit in response to the output of second waiting signal, And in response to the follow-up output of first waiting signal, the error detection code is write into second address.

13. semiconductor device according to claim 12,

Wherein, the memory by the write-in data storage inputted from said write circuit by defeated from the address conversion circuit The address that the address signal entered is indicated,

Wherein, the address conversion circuit will indicate the ground of first address in response to the output of second waiting signal Location signal output will indicate second ground to the memory, and in response to the follow-up output of first waiting signal The address signal of location is exported to the memory, and

Wherein, said write circuit regard the data as said write data in response to the output of second waiting signal Output is to the memory, and in response to the follow-up output of first waiting signal, using the error detection code as Said write data output is to the memory.

14. semiconductor device according to claim 12,

Wherein, second waiting signal is used as the value of at least one of first address, and

Wherein, first waiting signal is used as the value of at least one of first address after modification.

15. semiconductor device according to claim 1,

Wherein, the reading of the data is by bus master requests,

Wherein, the bus master controller will enable signal output to the memory, for performing the reading of the data The reading of the data is enabled during the unit interval,

Wherein, the semiconductor device further comprises controlling circuit, and the control circuit is in response to from the bus master The described of the reading for being used to enable the data of device enables signal, to bus master controller output in phase unit interval Between be used for disable the bus master controller operation the second waiting signal, instead of the operation for enabling the bus master controller The first waiting signal, and

Wherein, the reading circuit reads the data in response to the output of second waiting signal from first address, And in response to the follow-up output of first waiting signal, the error detection code is read from second address.

16. semiconductor device according to claim 15,

Wherein, the reading circuit is kept from described in memory reading in response to the output of second waiting signal Data, and in response to the follow-up output of first waiting signal, based on the error detection read from the memory Code detects mistake with the data kept.

17. semiconductor device according to claim 1,

Wherein, the first packet of first address is indicated by being received from bus master controller, from the bus master requests The write-in of the data and each in the reading of the data,

Wherein, the semiconductor device further comprises：

Buffer, first packet that the buffer storage is received from the bus master controller；And

Interface circuit, the interface circuit is based on the address indicated by the described first packet, to perform writing for the data Enter the reading with the data,

Wherein, the address conversion circuit is grouped indicate described first based on described first by being stored in the buffer Address, the two address second packet is indicated to generate,

Wherein, said write circuit from first packet that the bus master controller is received by will transmit to the interface Circuit and the second packet generated by the address conversion circuit is transmitted to the interface circuit, will be described to perform Data are written to first address and the error detection code are written into second address, and

Wherein, the reading circuit from first packet that the bus master controller is received by will transmit to the interface Circuit and the second packet generated by the address conversion circuit is transmitted to the interface circuit, to perform from described Read the data and read the error detection code from second address in the first address.

18. semiconductor device according to claim 17,

Wherein, the address conversion circuit is by inverting the value of institute's rheme of defined quantity, to generate address as described Second address,

Wherein, the interface circuit include cache memory, the cache memory by using setting association Scheme caches come the data to the memory, and

Wherein, each path of the cache memory is marked with position, institute's rheme includes institute's rheme of defined quantity In at least one.

19. semiconductor device according to claim 9, further comprises：

Mode control circuit, the mode control circuit, which has to be used to set, indicates the first mode or the second mode Value memory cell, and the mode control circuit is by the first mode being arranged in the memory cell or institute Second mode is stated to specify to the address conversion circuit.

20. a kind of memory access control method, comprises the following steps：

First write step, it is described when request writes data into the first address for storing the data in memory First write step writes the data in first address；

Second write step, second write step is generated based on first address to be generated for storing by the data Error detection code the second address, and by the error detection code write generation second address；

First read step, when request, which is read, is stored in the data in first address, first read step is from institute State the first address and read the data；And

Second read step, second read step generates second address based on first address, from generation The error detection code is read in second address, and based on the relevant data and the relevant error detection generation Code detects mistake,

Wherein, each in second write step and second read step, by changing first address The value of at least one is so that the storage location of the error detection code is displaced to the storage location of the data, and passes through Make the value reversion of institute's rheme of the defined quantity among other positions or make the institute of the defined quantity among other positions The order rearrangement of rheme, to generate address as second address.