JPS58115694A - Information processor - Google Patents

Abstract

PURPOSE:To evade a fixed fault of a control storage without increasing capacity of control storage by adding an address bit replacing circuit which replaces address bits of address supplied to the control storage mutually. CONSTITUTION:The control storage 1 is supplied with write data 10 and a write signal from a write control circuit 4. Read data from the control storage 1 is inputted to a control storage register 2, whose output, i.e. read data 8 is supplied to a parity check circuit 3 for a parity check to output a parity check result signal 9. The result signal 9 is transmitted to a write control circuit. In a mode register 5, a mode signal 16 from the write control circuit 4 is set. A mode signal 15 outputted from the mode register 5 controls the address bit replacing circuit 6 to change, by replacing address bits, the correspondent relation between a readout address 12 and a physical address 14 to the control storage during the operation of a processor, or the relation between a write address 11 and the physical address 14 supplied during writing. The address replacing circuit 6 replaces write data to be written at a fixed fault position until the write data coincides with a fixed fault to evade the fixed fault of the control storage.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device, and particularly to an information processing device including a control memory.

A conventional information processing device includes a write control circuit that outputs a series of addresses and write data corresponding to the addresses, writes and stores the write data according to the addresses, and writes and stores successive data according to the addresses. It is configured to include a control memory for outputting, and an odd-even check circuit that performs an odd-even check on the read data and outputs an odd-even check result signal.

In this way, the conventional information processing device includes a rewritable control memory, performs reading after writing when writing to the control memory, performs an odd-even test on the read data, and outputs an odd-even test result signal. There is.

Here, when the odd-even test result signal is an error, there is a fixed fault in the control memory, so there is a drawback that the device cannot be used due to the fault in the control memory.

In order to solve such fixed failures, it is considered possible to add an error detection and correction circuit to the control memory.
With the addition of V4BS scan code 0, the capacity of the control memory increases, and it becomes necessary to provide a complicated wAb detection and correction circuit, resulting in disadvantages such as an increase in the amount of design, an increase in the amount of hardware, and a rise in manufacturing costs. That will happen. Furthermore, the machine cycle is extended due to the delay time in the error detection and correction circuit, resulting in a disadvantage that the performance of the information processing apparatus is degraded.

That is, the conventional information processing apparatus has a drawback in that it is not easy to avoid fixed failures in control memory.

An object of the present invention is to provide an information processing device that can easily avoid fixed failures.

That is, an object of the present invention is to provide a reliable information processing device that can avoid fixed failures in control memory detected when writing to control memory with the addition of a very small number of circuits.

The information processing device of the present invention outputs an updated mode signal when the odd-even test result signal indicates an error, and outputs a series of @
1 address, a write control circuit that outputs write data corresponding to the first address every time the mode signal is updated, a mode register that stores the mode signal, and the address of the #X1 address. an address bit switching circuit that outputs a second address with bits switched according to the mode signal; and a control that writes and stores the write data according to the second address and outputs read data that is read according to the second address. The device includes a memory, and an odd-even test circuit that performs an odd-even test on the read data and outputs the odd-even test result signal.

In other words, the information processing device of the present invention includes a rewritable control memory, a mode register that holds a mode signal selected from a normal mode and one or more exchange modes;
address bit switching means for mutually switching at least two bits in accordance with a mode signal stored in the mode register; reading means for reading after writing the control memory; and performing an odd-even check on the read value. It is equipped with an odd-even test means and a means for setting a mode signal indicating an exchange mode in the mode register when 1li4shi is detected in the odd-even test, and when initializing the device, reading and reading after writing the control memory is performed. The data is checked for parity and evenness, and when multiple errors are detected by the check, the mode register is updated, a 9-exchange mode is set, and writing to the control memory is performed again from the first address.

That is, the information processing apparatus of the present invention can switch between normal mode and
A mode register that holds a mode signal selected from one or more switching modes and an address bit switching circuit that switches the address bits of the address supplied to the control memory are provided. When writing to , the succeeding data is checked for odd-even after writing, and if a mismatch of 1 bit or an odd number of bits is detected, one of the one or more possible exchange modes is selected. By setting a mode signal indicating the exchange mode in the mode register, the correspondence relationship between the logical control memory address and the physical control memory address that directly depends on the structure of the physical control memory element is set in the mode register. By changing the address bits through the address bit switching circuit controlled by the mode signal set to 1 and writing to the control memory again from the first address), the defect that caused the mismatch during the previous write can be changed. The memory cell is assigned to a logical address different from the previous one, so that data having the same value as the fixed failure value of the wrinkled memory cell is written, thereby avoiding a fixed failure of the control memory.

Next, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a pull diagram showing one embodiment of the present invention.

The control memory 1 is provided with write data 10 and a write signal by the write control circuit 4. The readout data 8 of the control memory 1 is transferred to the control storage register 2, and its output, read data 8, is checked for parity by the parity/parity test circuit 3, and an odd/even test result signal 9 is output.

The odd-even test result signal 9 is transmitted to the write control circuit.

The data register 5 receives the data supplied from the write control circuit 4.
signal 16 is set. A mode signal 15, which is the output of the mode register 5, controls the address bit switching circuit 6, and reads the read address 12 and physical address 14 to the control memory during operation of the processing device, or the write address 11 and physical address 14 given at the time of writing. This is achieved by replacing the address bits. The switching circuit 7 performs switching between the read address 12 during operation of the processing device and the write address 11 to the control storage during initialization.

Next, the operation of the embodiment shown in FIG. 1 will be explained.

First, when O writing to the control memory is started for initialization, the write control circuit 4 that controls writing to the control memory sets the normal mode as an initial value in the mode register 5, and An initial value is set in the write address counter held inside the write control circuit 4.

Next, the external memory 17 storing the write data to the control memory is read out, and the write data lO output from the write control circuit 4 is written to the control memory 1.

The write control circuit 4 updates the write address 11 and the write data 10 every time 111O is written to the control memory 1.

Reading after writing may be performed every time one word is written in the control memory, or after writing all words, the entire number of words may be read in IWI increments.

The read data 8 read after writing is checked by the odd-even check circuit 3, and if an error is detected, the write control circuit 4 sets the initial value of the mode register 5, which is the normal mode, to 1. Then, the other write controls are returned to their initial states, and writing to the control memory 1 is performed again from the first address.

In this second write, the address bit exchange circuit 6 mutually exchanges at least two bits of the ah address bits of address 13 to make address 14, so that when reading after the previous write, The storage bit cell that is erroneous is stored at an address K11ll that is different from the previous one. If the value of the write data to the memory bit cell at this newly divided address matches the fixed fault value, then in the second write to the control memory 1, an odd-even value is applied when reading after writing. If the inspection passes, indicating that the failure has been avoided, the exchange mode for the control memory 1 at this time is saved and the process proceeds to operation of the processing device.

If the odd-even test at the time of writing and reading fails in the second write to control memory 1, the history changes to another exchange mode, the address bits are swapped, and the write to control memory 1 is continued. I'll have to fix it.

If the addresses of the control memory 1 are from 0 to 2-1, it is possible to change the address bits up to n times for all the remaining addresses except for the minimum address 0 and maximum address 2-1. The binary logic value distribution of the data in control memory 1 is
Assuming that O and 1 are equal, by exchanging n address bits, it is possible to avoid failure of one storage bit cell with a probability of 1-1/2, 1 bit! If Ig4 exists at the address of mco rn, all entertainment will be avoided with a probability of (1-1/2).

7~;←-, shown in Figure i: Padresby? 1-1 Pancreatic fly! Figure 1 is a block diagram showing the details of the mode register 5 and the address bit switching circuit 6 in an embodiment having six switching modes for mutually replacing spits. be.

Address 13o consisting of address bits A-A
Of n, the 3 bits of address bits A, A, and A are exchanged with each other to form address bits A', A'.

1 A' becomes part of address 14.

The address bit switching circuit 6 is a 3-bit 6-'vvAY
Mode signal 1 which is the output of mode register 5 at the selector
5 determines the selection position. FIG. 3 is a diagram showing the correspondence between the selection signal S-8S2 and input/output in the address bit switching circuit 6.

The information processing device of the present invention can change the address of a fixed failure location in the control memory by adding an address switching circuit. Since the write data written to the fixed fault location can be replaced until the written data and the fixed fault match, the b! J It has the effect of avoiding a fixed disability letter.

In other words, the information processing device of the present invention does not increase each sound in the control memory by adding an address bit IF circuit that mutually exchanges the address bits of the address supplied to the control memory. This has the advantage that it is possible to avoid the fixed formation W of counterfeit memory without providing a complicated error detection and correction circuit, and to achieve high availability at a low cost.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing one embodiment of the present invention, Figure 2F
FIG. 3 is an explanatory diagram for explaining the input/output relationship in the address bit switching circuit shown in FIG. 2. 1... Control memory, 2... False control memory register, 3... Odd-even check circuit, 4... Convolution control circuit, 5... ...Mode register, 6...
...Address bit switching circuit, 7...°... Address switching circuit, 8... Read data, 9... Odd-even test result signal, 10°°°°°° writing Data, 11...
・Write address, 12...Read address, 13
・・・・・・Address, 14・Old address, 15・
...Mode signal, 16...Mode signal,
17...External memory, A-A...
Address n beep), 8-8...Selection signal. O-fight 2 Leopard 2

Claims (1)

[Claims] An updated mode signal is output when the odd-even test result signal indicates an error, and a series of first addresses and write data corresponding to the first address are output each time the mode signal is updated. an integrated control circuit, a mode register that stores the mode signal, and a second address bit in which the address bits of the first address are exchanged according to the mode signal.
an address bit switching circuit that outputs the address of the address bit, a control memory that writes and stores the write data according to the second address and outputs read data that is read according to the second address, and performs an odd-even test on the read data. and an odd-even test circuit that performs the odd-even test and outputs the odd-even test result signal.