CN107149485B - Medical-based ultrasonic signal processing method and device - Google Patents
Medical-based ultrasonic signal processing method and device Download PDFInfo
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- CN107149485B CN107149485B CN201710422465.XA CN201710422465A CN107149485B CN 107149485 B CN107149485 B CN 107149485B CN 201710422465 A CN201710422465 A CN 201710422465A CN 107149485 B CN107149485 B CN 107149485B
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
- A61B8/00—Diagnosis using ultrasonic, sonic or infrasonic waves
- A61B8/52—Devices using data or image processing specially adapted for diagnosis using ultrasonic, sonic or infrasonic waves
- A61B8/5207—Devices using data or image processing specially adapted for diagnosis using ultrasonic, sonic or infrasonic waves involving processing of raw data to produce diagnostic data, e.g. for generating an image
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- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N29/00—Investigating or analysing materials by the use of ultrasonic, sonic or infrasonic waves; Visualisation of the interior of objects by transmitting ultrasonic or sonic waves through the object
- G01N29/44—Processing the detected response signal, e.g. electronic circuits specially adapted therefor
Abstract
The embodiment of the invention provides a medical-based ultrasonic signal processing method and device. Dividing a second address interval between the first focus and the second focus into a plurality of sub-address intervals; adding the first address intervals and the sub-address intervals with different numbers respectively to obtain a plurality of different third address intervals; and selecting a target third address interval of which the difference between the square of the third address interval and the square of the fourth address interval is smaller than a preset threshold value from the plurality of third address intervals, taking the target third address interval as the address interval between the second focus and the target array element, and adding the address interval between the second focus and the signal generator and the target third address interval to obtain a read address of a signal sent from the signal generator and returned to the target array element through the second focus. And the evolution operation is not required in the whole calculation process, so that the whole calculation process is easy to realize in the FPGA, and the clock resource of the FPGA is saved.
Description
Technical Field
The embodiment of the invention relates to the technical field of medical ultrasound, in particular to a medical-based ultrasonic signal processing method and device.
Background
Currently, in a medical ultrasonic diagnostic system, ultrasonic reflection signals enter a beam forming link after being received by a probe, amplified in an analog mode and sampled in an AD mode. Beam forming is the most critical technology in an ultrasonic diagnostic system, and the quality of beam forming has a great influence on the accuracy and resolution of ultrasonic imaging.
In the medical ultrasonic diagnosis system, signals are sent out from a signal generator and then return to an array element through a focus, for any array element, the time that the signals are sent out from the signal generator and then return to the array element through different focuses is inconsistent, and the same is true for each other array element.
The medical ultrasonic diagnosis system allocates a memory for each array element, and in order to read the signals returned by the same focus from the memories of the array elements, for any focus, the path from the signal generator to the array elements through the focus needs to be calculated, and the path is converted into a read address, and the same is true for each other focus.
For example, assuming that the path through which the signal from the signal generator returns to the array element J through the focus F is as shown in fig. 1, the signal generator is located at the coordinate origin O point, each rectangle located on the X axis is an array element, and the propagation direction of the signal from the signal generator coincides with the Y axis, the path through which the signal from the signal generator returns to the array element J through the focus F is as follows
a is the distance between the array element J and the origin of coordinates, and b is the distance between the focus F and the origin of coordinates. Further, the signal from the signal generator returns to the read address of the array element J through the focus F as
c is the propagation velocity of the signal, fADIs the sampling frequency.
However, in the process of implementing the embodiment of the present invention, the inventor finds that in the process of calculating the read address of the signal sent from the signal generator and returned to the array element J through the focus F, the squaring operation needs to be performed, but the complexity of the squaring operation performed in the FPGA is high, and a lot of clock resources of the FPGA are wasted.
Disclosure of Invention
To overcome the problems in the related art, embodiments of the present invention provide a medical-based ultrasonic signal processing method and apparatus.
According to a first aspect of embodiments of the present invention, there is provided a medical-based ultrasound signal processing method, the method comprising:
acquiring a first address interval which is pre-stored locally and is between a first focus and a target array element;
dividing a second address interval between the first focus and a second focus into a plurality of sub-address intervals;
adding the first address intervals with different numbers of sub-address intervals respectively to obtain a plurality of different third address intervals;
obtaining a square of a fourth address interval between the second focus and the target array element;
selecting a target third address interval, of a plurality of different third address intervals, whose difference between the square and the square of the fourth address interval is smaller than a preset threshold;
and adding the address interval between the second focus and the signal generator and the target third address interval to obtain a read address of a signal sent from the signal generator and returned to the target array element through the second focus.
Wherein the dividing a second address interval between the first focus and the second focus into a plurality of sub-address intervals comprises:
selecting a specified position between a start position and an end position in said second address interval;
determining a portion between a start position and the designated position in the second address interval as a first sub-address interval;
dividing a portion between the designated location and an end location in the second address interval into a plurality of second sub-address intervals.
Wherein the adding the first address interval and the different number of sub-address intervals respectively to obtain a plurality of different third address intervals includes:
adding the first sub-address intervals and second sub-address intervals with different numbers respectively to obtain a plurality of different sub-address interval combinations;
and combining and adding the first address interval and each sub-address interval respectively to obtain a plurality of different third address intervals.
Wherein selecting a target third address interval, among the plurality of different third address intervals, for which a difference between a square of the target third address interval and a square of the target fourth address interval is smaller than a preset threshold value includes:
for each third address interval, calculating the square of the first address interval stored locally in advance; calculating a product between a difference value between the third address interval and the first address interval, the first address interval and a preset numerical value; calculating a square of a difference between the third address interval and the first address interval; summing a square of a difference between the third address interval and the first address interval, a square of the first address interval, and the product to obtain a square of the third address interval;
selecting a square of a third address interval having a smallest difference with a square of the fourth address interval among the obtained squares of the third address interval;
determining the target third address interval according to a square of the selected third address interval.
Wherein the calculating a product between a difference between the third address interval and the first address interval, and a preset value comprises:
and calculating the product of the difference value between the third address interval and the first address interval, the first address interval and a preset numerical value by using a shifting algorithm.
Wherein the selecting a square of a third address interval having a smallest difference with a square of the fourth address interval among the obtained squares of all third address intervals comprises:
sorting the squares of all the obtained third address intervals according to the size sequence;
calculating the average value of the squares of every two adjacent third address intervals after sorting to obtain a plurality of average values arranged according to the size sequence;
respectively forming an average value interval by each two adjacent average values which are sequentially arranged;
selecting an average interval of which the starting endpoint is smaller than the square of the fourth address interval and the ending endpoint is larger than the square of the fourth address interval from the average intervals;
the square of the third address interval lying within the selected average interval is obtained.
According to a second aspect of embodiments of the present invention, there is provided a medical-based ultrasound signal processing apparatus, the apparatus comprising:
the first acquisition module is used for acquiring a first address interval which is stored locally in advance and is between a first focus and a target array element;
a dividing module, configured to divide a second address interval between the first focus and the second focus into a plurality of sub-address intervals;
the first adding module is used for adding the first address intervals and different numbers of sub-address intervals respectively to obtain a plurality of different third address intervals;
a second obtaining module, configured to obtain a square of a fourth address interval between the second focus and the target array element;
a selecting module, configured to select, in a plurality of different third address intervals, a target third address interval in which a difference between a square of the target third address interval and a square of the target fourth address interval is smaller than a preset threshold;
and the second adding module is used for adding the address interval between the second focus and the signal generator and the target third address interval to obtain a read address of a signal sent from the signal generator and returned to the target array element through the second focus.
Wherein the dividing module comprises:
a first selection unit configured to select a specified position between a start position and an end position in the second address interval;
a first determining unit configured to determine a portion between a start position in the second address interval and the designated position as a first sub-address interval;
a dividing unit, configured to divide a portion between the designated position and an end position in the second address interval into a plurality of second sub-address intervals.
Wherein the first adding module comprises:
the first adding unit is used for adding the first sub-address intervals and second sub-address intervals with different numbers respectively to obtain a plurality of different sub-address interval combinations;
and the second adding unit is used for combining and adding the first address interval and each sub-address interval respectively to obtain a plurality of different third address intervals.
Wherein the selection module comprises:
a first calculation unit configured to calculate, for each third address interval, a square of the first address interval stored locally in advance; a second calculation unit, configured to calculate a product between a difference between the third address interval and the first address interval, and a preset value; a third calculation unit for calculating a square of a difference between the third address interval and the first address interval; a summing unit configured to sum a square of a difference between the third address interval and the first address interval, a square of the first address interval, and the product to obtain a square of the third address interval;
a second selection unit configured to select, from among the obtained squares of the third address intervals, a square of a third address interval whose difference with a square of the fourth address interval is smallest;
a second determining unit for determining the target third address interval according to a square of the selected third address interval.
Wherein the second computing unit is specifically configured to: and calculating the product of the difference value between the third address interval and the first address interval, the first address interval and a preset numerical value by using a shifting algorithm.
Wherein the selection unit is configured to include:
the ordering subunit is used for ordering the squares of all the obtained third address intervals according to the order of magnitude;
the calculating subunit is used for calculating the average value of the squares of every two adjacent third address intervals after sorting to obtain a plurality of average values arranged according to the size sequence;
the composition subunit is used for respectively composing the two adjacent average values which are sequentially arranged into an average value interval;
a selecting subunit, configured to select, from the plurality of average value intervals, an average value interval in which a start endpoint is smaller than a square of the fourth address interval and an end endpoint is larger than the square of the fourth address interval;
an obtaining subunit, configured to obtain a square of a third address interval located within the selected average value interval.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
in the embodiment of the invention, a second address interval between a first focus and a second focus is divided into a plurality of sub-address intervals; adding the first address intervals and the sub-address intervals with different numbers respectively to obtain a plurality of different third address intervals; and selecting a target third address interval with the smallest difference between the square of the third address interval and the square of the fourth address interval from the plurality of third address intervals, taking the target third address interval as the address interval between the second focus and the target array element, and adding the address interval between the second focus and the signal generator and the target third address interval to obtain a read address of a signal sent from the signal generator and returned to the target array element through the second focus. And the evolution operation is not required in the whole calculation process, so that the whole calculation process is easy to realize in the FPGA, and the clock resource of the FPGA is saved.
Secondly, in the whole calculation process in the prior art, the path is taken as a unit, the path through which the signal returns to the target array element from the signal generator through the second focus is calculated, then the path is divided by the ratio between the transmission speed and the sampling frequency of the signal, and then the read address through which the signal returns to the target array element from the signal generator through the second focus is obtained.
In the embodiment of the present invention, before calculating the read address of the signal from the signal generator returning to the target array element through the second focus, all the route units are converted into addresses, for example, the distance between each focus and the signal generator is divided by the ratio between the transmission speed and the sampling frequency of the signal to obtain the address interval between each focus and the signal generator, and the distance between each array element and the signal generator is divided by the ratio between the transmission speed and the sampling frequency of the signal to obtain the address interval between each array element and the signal generator. Therefore, in the calculation process, the address calculation can be directly utilized, and then the read address which is sent by the signal generator and returned to the target array element through the second focus is obtained, the division operation for converting the path into the read address is not required in each calculation process, the calculation of the FPGA is facilitated, and the clock resource is saved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of embodiments of the invention.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the embodiments of the invention.
FIG. 1 is a schematic diagram of a scene shown in the prior art;
FIG. 2 is a flow chart illustrating a method of medical-based ultrasound signal processing according to an exemplary embodiment;
FIG. 3 is a flow chart illustrating a method of medical-based ultrasound signal processing according to an exemplary embodiment;
fig. 4 is a block diagram illustrating a medical-based ultrasound information processing apparatus according to an exemplary embodiment.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with embodiments of the invention. Rather, they are merely examples of apparatus and methods consistent with certain aspects of embodiments of the invention, as detailed in the following claims.
Fig. 2 is a flow chart illustrating a method of medical-based ultrasound signal processing, as shown in fig. 2, including the following steps, according to an exemplary embodiment.
In step S101, a first address interval between a first focus and a target array element, which is locally pre-stored, is obtained;
in the embodiment of the invention, a plurality of focuses are distributed on a transmission line of a signal emitted by a signal generator, and the distances between two adjacent focuses at any position are the same. The signal emitted by the signal generator can be a sound wave signal or an electromagnetic wave signal, etc.
The embodiment of the present invention is only exemplified by any two adjacent focuses in the plurality of focuses, but not limited to the scope of the present invention. In an embodiment of the invention, the two adjacent focal points are a first focal point and a second focal point, and the distance between the second focal point and the signal generator is larger than the distance between the first focal point and the signal generator.
In the embodiment of the present invention, each time an address interval between a certain focus and a target array element is obtained through calculation, a focus identifier of the focus and the address interval are combined into a record and stored in a corresponding relationship between the focus identifier and the address interval, which corresponds to the target array element. In general, the address interval between the focus closer to the signal generator and the target array element is calculated first, and then the address interval between the focus closer to the signal generator and the target array element is calculated.
Therefore, in this step, the address interval corresponding to the focus identifier of the first focus may be searched in the above correspondence, and used as the first address interval between the first focus and the target array element.
The focus identifier of the focus may be a number or a name of the focus, which is not limited in this embodiment of the present invention.
The signal generator of the present invention may be an acousto-electric transducer or the like.
In step S102, dividing a second address interval between the first focus and the second focus into a plurality of sub-address intervals;
the second address interval may be divided into a plurality of equally divided sub address intervals, or may be divided into a plurality of unequally divided sub address intervals.
In the embodiment of the present invention, in order to improve the accuracy of the read address of the calculation signal sent from the signal generator and returned to the target array element through the second focus, the number of divided sub-address intervals may be increased as much as possible.
In step S103, adding the first address intervals to different numbers of sub-address intervals, respectively, to obtain a plurality of different third address intervals;
in step S104, a square of a fourth address interval between the second focus and the target array element is obtained;
in the embodiment of the invention, the address interval between each focus and the signal generator is known, and the address interval between each array element and the signal generator is also known. Therefore, in this step, the address interval between the second focus and the signal generator and the address interval between the target array element and the signal generator may be obtained, the square of the address interval between the second focus and the signal generator and the square of the address interval between the target array element and the signal generator may be calculated, and then the square of the address interval between the second focus and the signal generator and the square of the address interval between the target array element and the signal generator may be summed to obtain the square of the fourth address interval between the second focus and the target array element.
In step S105, selecting a target third address interval, of the plurality of different third address intervals, for which a difference between a square of the target third address interval and a square of the target fourth address interval is smaller than a preset threshold;
in the embodiment of the present invention, the squares of each of the third address intervals are respectively calculated, and since any two third address intervals are different, the squares of each of the third address intervals are different, and thus, among the squares of all the third address intervals, there is a square of the third address interval whose difference from the square of the fourth address interval is smaller than the preset threshold. The preset threshold is a value that is set by a technician in advance locally.
Therefore, the step may select a target third address interval with a difference between the square of the third address interval and the square of the fourth address interval smaller than the preset threshold from a plurality of different third address intervals by using the square of the third address interval, which is described in the embodiment shown in fig. 3 below and will not be described in detail herein.
In the embodiment of the present invention, the target third address interval having the smallest difference between the square of the fourth address interval and the square of the fourth address interval may be selected from a plurality of different third address intervals.
In step S106, the address interval between the second focus and the signal generator and the target third address interval are added to obtain a read address of a signal sent from the signal generator via the second focus and returned to the target array element.
In the embodiment of the invention, a second address interval between a first focus and a second focus is divided into a plurality of sub-address intervals; adding the first address intervals and the sub-address intervals with different numbers respectively to obtain a plurality of different third address intervals; and selecting a target third address interval with the smallest difference between the square of the third address interval and the square of the fourth address interval from the plurality of third address intervals, taking the target third address interval as the address interval between the second focus and the target array element, and adding the address interval between the second focus and the signal generator and the target third address interval to obtain a read address of a signal sent from the signal generator and returned to the target array element through the second focus. And the evolution operation is not required in the whole calculation process, so that the whole calculation process is easy to realize in the FPGA, and the clock resource of the FPGA is saved.
Secondly, in the whole calculation process in the prior art, the path is taken as a unit, the path through which the signal returns to the target array element from the signal generator through the second focus is calculated, then the path is divided by the ratio between the transmission speed and the sampling frequency of the signal, and then the read address through which the signal returns to the target array element from the signal generator through the second focus is obtained.
In the embodiment of the present invention, before calculating the read address of the signal from the signal generator returning to the target array element through the second focus, all the route units are converted into addresses, for example, the distance between each focus and the signal generator is divided by the ratio between the transmission speed and the sampling frequency of the signal to obtain the address interval between each focus and the signal generator, and the distance between each array element and the signal generator is divided by the ratio between the transmission speed and the sampling frequency of the signal to obtain the address interval between each array element and the signal generator. Therefore, in the calculation process, the address calculation can be directly utilized, and then the read address which is sent by the signal generator and returned to the target array element through the second focus is obtained, the division operation for converting the path into the read address is not required in each calculation process, the calculation of the FPGA is facilitated, and the clock resource is saved.
In another embodiment of the present invention, in step S102, a designated position is selected between the start position and the end position in the second address interval; for example, a location near or near the midpoint location in the second address interval is selected. Then determining a part between the starting position and the designated position in the second address interval as a first sub-address interval; and dividing a portion between the designated position and the ending position in the second address interval into a plurality of second sub-address intervals.
Accordingly, in step S103, the part of the second address interval between the start position and the designated position may be added to a different number of second sub-address intervals, respectively, to obtain a plurality of different sub-address interval combinations; and the first address interval is combined and added with each sub-address interval respectively to obtain a plurality of different third address intervals.
If the whole second address interval is equally divided into a plurality of sub-address intervals, then the first address interval is respectively added with the second sub-address intervals with different numbers to obtain a plurality of third sub-address intervals.
The third address interval is composed of a part of the second address interval and the sum of the first address interval, and the technician counts for many times in advance, and in the third address interval with the smallest difference value with the fourth address interval, the part of the second address interval is usually larger than half of the second address interval.
That is, the third address interval, which is the sum of less than half of the second address interval and the first address interval in the second address interval, is generally not the third address interval that differs the least from the fourth address interval. However, the process of calculating the third address obtained by adding the part of the second address interval smaller than half of the second address interval to the first address interval consumes more clock resources and time of the FPGA.
Therefore, in order to obtain the target third address interval with the smallest difference value with the fourth address interval and save the clock resource and time of the FPGA, in another embodiment of the present invention, the whole second address interval does not need to be equally divided into a plurality of sub-address intervals. In the embodiment of the present invention, without dividing the sub-address interval in the part of the second address interval between the start position and the designated position, the part of the second address interval between the start position and the designated position may be determined as the first sub-address interval; and dividing a portion between the designated position and the ending position in the second address interval into a plurality of second sub-address intervals. For example, a portion of the second address interval between the specified position and the ending position is divided into a plurality of equally divided sub-address intervals.
Preferably, the designated position is a midpoint position of the second address interval, and the designated position is set as the midpoint position of the second address interval, which is favorable for positioning accuracy of the designated position and real-time calculation rate and calculation accuracy of the receiving delay parameter in beam forming.
Correspondingly, in the process of adding the first address interval with different numbers of sub-address intervals respectively, the part, located between the starting position and the specified position, in the second address interval can be added with different numbers of sub-address intervals respectively to obtain a plurality of different sub-address interval combinations; and the first address interval is combined and added with each sub-address interval respectively to obtain a plurality of different third address intervals.
Each address interval combination is larger than half of the second address interval, so that the calculation process of adding the part smaller than half of the second address interval and the first address interval can be avoided, the target third address interval with the minimum difference value with the fourth address interval can be obtained, and meanwhile clock resources and time of the FPGA can be saved.
For example, assume that the second address interval is m, the selected position is the midpoint position of the second address interval, and the portion of the second address interval between the start position and the midpoint position is
The portion of the second address interval between the midpoint location and the end location is
Means for dividing a portion of the second address interval between the midpoint location and the end location
Equally dividing the address space into 4 parts of sub-address intervals, wherein each part of sub-address interval is
The part of the second address interval between the start position and the middle position is divided into
And 1-part sub-address interval
Adding to obtain sub-address interval combination
The part of the second address interval between the start position and the middle position is divided into
And 2-part sub-address interval
Adding to obtain sub-address interval combination
The part of the second address interval between the start position and the middle position is divided into
And 3-part sub-address interval
Adding to obtain sub-address interval combination
The part of the second address interval between the start position and the middle position is divided into
And 4-part sub-address interval
Adding to obtain sub-address interval combination
In another embodiment of the present invention, referring to fig. 3, step S105 includes:
in step S201, for each third address interval, a square of a locally pre-stored first address interval is calculated; calculating the product of the difference between the third address interval and the first address interval, the first address interval and a preset value; calculating a square of a difference between the third address interval and the first address interval; summing the square of the difference between the third address interval and the first address interval, the square of the first address interval, and the product to obtain the square of the third address interval;
in the embodiment of the present invention, for any one third address interval, the square of the third address interval needs to be calculated, because the third address interval is formed by the difference between the third address interval and the first address interval, when the square of the third address interval is calculated, first, the square of the first address interval needs to be calculated, and because the first address interval is stored locally in advance, the first address interval can be directly obtained locally, and the square of the first address interval is calculated. Secondly, a difference between the third address interval and the first address interval, a product between the first address interval and a preset value, and in the embodiment of the present invention, the difference between the third address interval and the first address interval, the product between the first address interval and the preset value may be calculated through a shift algorithm. Then, it is necessary to calculate the square of the difference between the third address interval and the first address interval, and then sum the square of the first address interval, the product, and the square of the difference between the third address interval and the first address interval to obtain the square of the third address interval.
The above operation is also performed for every other third address interval, so that the square of each third address interval can be obtained.
Wherein, in the embodiment of the present invention, the first focus is connected toThe address interval between the second focuses is obtained by multiplying the distance between the first focus and the second focus by the sampling frequency and dividing by the transmission speed of the signal, and 2 times of the distance between the first focus and the second focus is equal to the ratio of the transmission speed of the signal to the sampling frequency. Thus, the address interval between the first focus and the second focus is equal to
It can be seen that, when the address interval between the first focus and the second focus is split into 2 sub-address intervals of the power of n, where n is a positive integer, when calculating the product between the difference between the third address interval and the first address interval, and the preset value, the product between the difference between the third address interval and the first address interval, and the preset value may be calculated by using a shift algorithm.
In the binary multiplication, the multiplicand needs to be shifted by a corresponding digit to the left, and the dividend needs to be shifted by a corresponding digit to the right in the binary division, so that in the embodiment of the invention, the decimal division can be converted into the binary division, the digit to be shifted to the right is determined according to the divisor, the dividend is shifted to the right by the digit to be shifted, the obtained numerical value is converted into a 10-system number, and the product between the difference value between the third address interval and the first address interval, the first address interval and the preset numerical value is obtained.
For example, let the first address interval be A, the address interval between the first focus and the second focus is set to be A
Split into 4 equal parts, then the squares of the 4 third address intervals are:
wherein in the calculation
In the case of a, a may be converted into a binary number, then shifted by 2 bits to the right, and the obtained binary number may be converted into a 10-ary number.
In the calculation of
In the case of converting a into a binary number, the bit may be shifted to the right by 1 bit, and the obtained binary number may be converted into a 10-ary number.
In the calculation of
In the process, a may be converted into a binary number, then shifted to the right by 2 bits, then the obtained binary number is shifted to the left by 1 bit, and then the finally obtained binary number is converted into a 10-ary number.
In the embodiment of the invention, the difference between the third address interval and the first address interval, the product between the first address interval and the preset numerical value can be calculated through a shift algorithm without using a multiplier to calculate the difference between the third address interval and the first address interval, and the product between the first address interval and the preset numerical value, so that the multiplier resource can be saved, and the cost is reduced.
In step S202, among the squares of the obtained third address intervals, a square of the third address interval whose difference from the square of the fourth address interval is smaller than a preset threshold is selected;
in the prior art, it is required to calculate an absolute value of a difference between a square of each third address interval and a square of the second address interval, and then select a square of the third address interval whose absolute value of the difference from the square of the second address interval is smaller than a preset threshold. However, the method of subtracting, then obtaining the absolute value, and then obtaining the minimum value of the absolute value, which requires the floating-point number subtraction, is difficult to implement in the FPGA, and not only is the algorithm complex, but also a lot of clock resources of the FPGA are consumed.
Therefore, in order to be conveniently realized in the FPGA and save FPGA clock resources, in this step, the squares of all the obtained third address intervals may be sorted according to the order of magnitude; calculating the average value of the squares of every two adjacent third address intervals after sorting to obtain a plurality of average values arranged according to the size sequence; respectively forming an average value interval by each two adjacent average values which are sequentially arranged; selecting an average interval of which the starting endpoint is smaller than the square of the fourth address interval and the ending endpoint is larger than the square of the fourth address interval from the average intervals; the square of the third address interval lying within the selected average interval is obtained.
In the embodiment of the invention, floating point subtraction is not used in the averaging process, and the process of selecting the average interval with the starting end point smaller than the square of the second address interval and the ending end point larger than the square of the second address interval only needs to compare the end points of the average interval of the second address interval, and floating point subtraction is not used, so that compared with the prior art, the embodiment of the invention is more convenient to implement in an FPGA (field programmable gate array), and more clock resources can be saved.
In step S203, a target third address interval is determined according to the square of the selected third address interval.
In the embodiment of the present invention, each time a square of a third address interval is obtained, the third address interval and the square of the third address interval are combined into a record and stored in the correspondence relationship between the address interval and the square of the address interval. Therefore, in this step, an address interval corresponding to the square of the selected third address interval can be searched for in the correspondence relationship between the address interval and the square of the address interval, and is taken as the target third address interval.
Fig. 4 is a block diagram illustrating a medical-based ultrasound signal processing apparatus according to an exemplary embodiment. Referring to fig. 4, the apparatus includes:
the first obtaining module 11 is configured to obtain a first address interval between a first focus and a target array element, where the first address interval is locally pre-stored;
a dividing module 12, configured to divide a second address interval between the first focus and the second focus into a plurality of sub-address intervals;
a first adding module 13, configured to add the first address interval to different numbers of sub-address intervals, respectively, to obtain a plurality of different third address intervals;
a second obtaining module 14, configured to obtain a square of a fourth address interval between the second focus and the target array element;
a selecting module 15, configured to select, in a plurality of different third address intervals, a target third address interval in which a difference between a square of the target third address interval and a square of the target fourth address interval is smaller than a preset threshold;
and a second adding module 16, configured to add the address interval between the second focus and the signal generator and the target third address interval to obtain a read address, where a signal is sent from the signal generator and returned to the target array element through the second focus.
Wherein the dividing module 12 comprises:
a first selection unit configured to select a specified position between a start position and an end position in the second address interval;
a first determining unit configured to determine a portion between a start position in the second address interval and the designated position as a first sub-address interval;
a dividing unit, configured to divide a portion between the designated position and an end position in the second address interval into a plurality of second sub-address intervals.
Wherein the first adding module 13 includes:
the first adding unit is used for adding the first sub-address intervals and second sub-address intervals with different numbers respectively to obtain a plurality of different sub-address interval combinations;
and the second adding unit is used for combining and adding the first address interval and each sub-address interval respectively to obtain a plurality of different third address intervals.
Wherein the selection module 15 comprises:
a first calculation unit configured to calculate, for each third address interval, a square of the first address interval stored locally in advance; a second calculation unit, configured to calculate a product between a difference between the third address interval and the first address interval, and a preset value; a third calculation unit for calculating a square of a difference between the third address interval and the first address interval; a summing unit configured to sum a square of a difference between the third address interval and the first address interval, a square of the first address interval, and the product to obtain a square of the third address interval;
a second selection unit configured to select, from among the obtained squares of the third address intervals, a square of a third address interval whose difference with a square of the fourth address interval is smallest;
a second determining unit for determining the target third address interval according to a square of the selected third address interval.
Wherein the second computing unit is specifically configured to: and calculating the product of the difference value between the third address interval and the first address interval, the first address interval and a preset numerical value by using a shifting algorithm.
Wherein the selection unit is configured to include:
the ordering subunit is used for ordering the squares of all the obtained third address intervals according to the order of magnitude;
the calculating subunit is used for calculating the average value of the squares of every two adjacent third address intervals after sorting to obtain a plurality of average values arranged according to the size sequence;
the composition subunit is used for respectively composing the two adjacent average values which are sequentially arranged into an average value interval;
a selecting subunit, configured to select, from the plurality of average value intervals, an average value interval in which a start endpoint is smaller than a square of the fourth address interval and an end endpoint is larger than the square of the fourth address interval;
an obtaining subunit, configured to obtain a square of a third address interval located within the selected average value interval.
In the embodiment of the invention, a second address interval between a first focus and a second focus is divided into a plurality of sub-address intervals; adding the first address intervals and the sub-address intervals with different numbers respectively to obtain a plurality of different third address intervals; and selecting a target third address interval with the smallest difference between the square of the third address interval and the square of the fourth address interval from the plurality of third address intervals, taking the target third address interval as the address interval between the second focus and the target array element, and adding the address interval between the second focus and the signal generator and the target third address interval to obtain a read address of a signal sent from the signal generator and returned to the target array element through the second focus. And the evolution operation is not required in the whole calculation process, so that the whole calculation process is easy to realize in the FPGA, and the clock resource of the FPGA is saved.
Secondly, in the whole calculation process in the prior art, the path is taken as a unit, the path through which the signal returns to the target array element from the signal generator through the second focus is calculated, then the path is divided by the ratio between the transmission speed and the sampling frequency of the signal, and then the read address through which the signal returns to the target array element from the signal generator through the second focus is obtained.
In the embodiment of the present invention, before calculating the read address of the signal from the signal generator returning to the target array element through the second focus, all the route units are converted into addresses, for example, the distance between each focus and the signal generator is divided by the ratio between the transmission speed and the sampling frequency of the signal to obtain the address interval between each focus and the signal generator, and the distance between each array element and the signal generator is divided by the ratio between the transmission speed and the sampling frequency of the signal to obtain the address interval between each array element and the signal generator. Therefore, in the calculation process, the address calculation can be directly utilized, and then the read address which is sent by the signal generator and returned to the target array element through the second focus is obtained, the division operation for converting the path into the read address is not required in each calculation process, the calculation of the FPGA is facilitated, and the clock resource is saved.
With regard to the apparatus in the above-described embodiment, the specific manner in which each module performs the operation has been described in detail in the embodiment related to the method, and will not be elaborated here.
Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the embodiments of the invention following, in general, the principles of the embodiments of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the embodiments of the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the embodiments of the invention being indicated by the following claims.
It is to be understood that the embodiments of the present invention are not limited to the precise arrangements described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of embodiments of the invention is limited only by the appended claims.
Claims (10)
1. A medical-based ultrasound signal processing method, characterized in that the method comprises:
acquiring a first address interval which is pre-stored locally and is between a first focus and a target array element;
dividing a second address interval between the first focus and a second focus into a plurality of sub-address intervals;
adding the first address intervals with different numbers of sub-address intervals respectively to obtain a plurality of different third address intervals;
obtaining a square of a fourth address interval between the second focus and the target array element;
selecting a target third address interval, of a plurality of different third address intervals, whose difference between the square and the square of the fourth address interval is smaller than a preset threshold;
and adding the address interval between the second focus and the signal generator and the target third address interval to obtain a read address of a signal sent from the signal generator and returned to the target array element through the second focus.
2. The method of claim 1, wherein dividing the second address interval between the first focus and the second focus into a plurality of sub-address intervals comprises:
selecting a specified position between a start position and an end position in said second address interval;
determining a portion between a start position and the designated position in the second address interval as a first sub-address interval;
dividing a portion between the designated location and an end location in the second address interval into a plurality of second sub-address intervals.
3. The method of claim 2, wherein adding the first address interval to different numbers of sub-address intervals to obtain a plurality of different third address intervals comprises:
adding the first sub-address intervals and second sub-address intervals with different numbers respectively to obtain a plurality of different sub-address interval combinations;
and combining and adding the first address interval and each sub-address interval respectively to obtain a plurality of different third address intervals.
4. The method according to claim 1, wherein selecting a target third address interval among the plurality of different third address intervals, wherein a difference between a square of the target third address interval and a square of the target fourth address interval is smaller than a preset threshold value, comprises:
for each third address interval, calculating the square of the first address interval stored locally in advance; calculating a product between a difference value between the third address interval and the first address interval, the first address interval and a preset numerical value; calculating a square of a difference between the third address interval and the first address interval; summing a square of a difference between the third address interval and the first address interval, a square of the first address interval, and the product to obtain a square of the third address interval;
selecting a square of a third address interval having a smallest difference with a square of the fourth address interval among the obtained squares of the third address interval;
determining the target third address interval according to a square of the selected third address interval.
5. The method of claim 4, wherein selecting the square of the third address interval with the smallest difference from the square of the fourth address interval among the squares of all the obtained third address intervals comprises:
sorting the squares of all the obtained third address intervals according to the size sequence;
calculating the average value of the squares of every two adjacent third address intervals after sorting to obtain a plurality of average values arranged according to the size sequence;
respectively forming an average value interval by each two adjacent average values which are sequentially arranged;
selecting an average interval of which the starting endpoint is smaller than the square of the fourth address interval and the ending endpoint is larger than the square of the fourth address interval from the average intervals;
the square of the third address interval lying within the selected average interval is obtained.
6. A medical based ultrasound signal processing apparatus, characterized in that the apparatus comprises:
the first acquisition module is used for acquiring a first address interval which is stored locally in advance and is between a first focus and a target array element;
a dividing module, configured to divide a second address interval between the first focus and the second focus into a plurality of sub-address intervals;
the first adding module is used for adding the first address intervals and different numbers of sub-address intervals respectively to obtain a plurality of different third address intervals;
a second obtaining module, configured to obtain a square of a fourth address interval between the second focus and the target array element;
a selecting module, configured to select, in a plurality of different third address intervals, a target third address interval in which a difference between a square of the target third address interval and a square of the target fourth address interval is smaller than a preset threshold;
and the second adding module is used for adding the address interval between the second focus and the signal generator and the target third address interval to obtain a read address of a signal sent from the signal generator and returned to the target array element through the second focus.
7. The apparatus of claim 6, wherein the partitioning module comprises:
a first selection unit configured to select a specified position between a start position and an end position in the second address interval;
a first determining unit configured to determine a portion between a start position in the second address interval and the designated position as a first sub-address interval;
a dividing unit, configured to divide a portion between the designated position and an end position in the second address interval into a plurality of second sub-address intervals.
8. The apparatus of claim 7, wherein the first summing module comprises:
the first adding unit is used for adding the first sub-address intervals and second sub-address intervals with different numbers respectively to obtain a plurality of different sub-address interval combinations;
and the second adding unit is used for combining and adding the first address interval and each sub-address interval respectively to obtain a plurality of different third address intervals.
9. The apparatus of claim 6, wherein the selection module comprises:
a first calculation unit configured to calculate, for each third address interval, a square of the first address interval stored locally in advance; a second calculation unit, configured to calculate a product between a difference between the third address interval and the first address interval, and a preset value; a third calculation unit for calculating a square of a difference between the third address interval and the first address interval; a summing unit configured to sum a square of a difference between the third address interval and the first address interval, a square of the first address interval, and the product to obtain a square of the third address interval;
a second selection unit configured to select, from among the obtained squares of the third address intervals, a square of a third address interval whose difference with a square of the fourth address interval is smallest;
a second determining unit for determining the target third address interval according to a square of the selected third address interval.
10. The apparatus according to claim 9, wherein the selection unit specifically includes:
the ordering subunit is used for ordering the squares of all the obtained third address intervals according to the order of magnitude;
the calculating subunit is used for calculating the average value of the squares of every two adjacent third address intervals after sorting to obtain a plurality of average values arranged according to the size sequence;
the composition subunit is used for respectively composing the two adjacent average values which are sequentially arranged into an average value interval;
a selecting subunit, configured to select, from the plurality of average value intervals, an average value interval in which a start endpoint is smaller than a square of the fourth address interval and an end endpoint is larger than the square of the fourth address interval;
an obtaining subunit, configured to obtain a square of a third address interval located within the selected average value interval.
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