CN107146784B - Array substrate and embedded touch display panel comprising same - Google Patents
Array substrate and embedded touch display panel comprising same Download PDFInfo
- Publication number
- CN107146784B CN107146784B CN201710335917.0A CN201710335917A CN107146784B CN 107146784 B CN107146784 B CN 107146784B CN 201710335917 A CN201710335917 A CN 201710335917A CN 107146784 B CN107146784 B CN 107146784B
- Authority
- CN
- China
- Prior art keywords
- layer
- conductive pattern
- array substrate
- periphery
- shield ring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/40—OLEDs integrated with touch screens
Landscapes
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
The present disclosure provides an array substrate and an embedded touch display panel including the same. The array substrate comprises a plurality of conductive pattern layers and a shielding ring which is arranged on the same layer as a first conductive pattern layer in the plurality of conductive pattern layers and is positioned on the periphery of the first conductive pattern layer.
Description
Technical Field
The present disclosure relates to the field of display technologies, and more particularly, to an array substrate and an embedded touch display panel including the same.
Background
Organic Light Emitting Displays (AMOLEDs) are one of the hot spots in the research field of flat panel displays, and compared with liquid crystal displays, OLEDs have the advantages of low energy consumption, low production cost, self-luminescence, wide viewing angle, fast response speed, and the like. In-cell touch (in cell touch) technology is increasingly favored because it is compatible with display panel technology. Especially, when the flexible OLED touch panel is applied to a flexible OLED product in the future, the embedded OLED Film Integrated Circuit (FIC) technology will be more advantageous, mainly because the current flexible OLED touch scheme is to directly fabricate a multi-layer touch structure on a Thin Film Encapsulation (TFE) encapsulation structure, which not only increases the difficulty of fabrication, but also increases the fabrication cost.
However, the embedded active matrix organic light emitting diode display has a problem that external noise interferes with internal signals of the panel to affect touch sensitivity.
BRIEF SUMMARY OF THE PRESENT DISCLOSURE
To solve at least one of the above problems, the present disclosure provides an array substrate and an embedded touch display panel including the same.
According to an aspect of the present disclosure, an array substrate is provided, which includes a plurality of conductive pattern layers, and a shield ring disposed on a same layer as a first conductive pattern layer of the plurality of conductive pattern layers and located at a periphery of the first conductive pattern layer.
In one embodiment of the present disclosure, the plurality of conductive pattern layers include a gate pattern layer, a source/drain electrode layer, and a cathode layer and an anode layer of the light emitting display device, and the first conductive pattern layer is one of the cathode layer, the anode layer, the source/drain electrode layer, and the gate pattern layer.
In an embodiment of the present disclosure, the array substrate further includes a shielding ring disposed on the same layer as a second conductive pattern layer of the plurality of conductive pattern layers and located at a periphery of the second conductive pattern layer, and the first conductive pattern layer and the second conductive pattern layer are two selected from a cathode layer, an anode layer, a source/drain electrode layer, and a gate pattern layer.
In one embodiment of the present disclosure, the first and second conductive pattern layers are a cathode layer and an anode layer, respectively, wherein the shield ring located at a periphery of the anode layer and the shield ring located at a periphery of the cathode layer are electrically connected to each other through a through hole formed in the pixel defining layer of the array substrate.
In an embodiment of the present disclosure, the array substrate further includes a shielding ring disposed on the same layer as a third conductive pattern layer of the plurality of conductive pattern layers and located at a periphery of the third conductive pattern layer, and the first conductive pattern layer, the second conductive pattern layer, and the third conductive pattern layer are a cathode layer, an anode layer, and a source/drain electrode layer, respectively, where the shielding ring located at a periphery of the anode layer and the shielding ring located at a periphery of the cathode layer are electrically connected to each other through a through hole formed in a pixel defining layer of the array substrate, and the shielding ring located at a periphery of the anode layer and the shielding ring located at a periphery of the source/drain electrode layer are electrically connected to each other through a through hole formed in a planarization layer.
In one embodiment of the present disclosure, the array substrate further includes a shielding ring disposed in the same layer as and around a fourth conductive pattern layer of the plurality of conductive pattern layers, the first conductive pattern layer, the second conductive pattern layer, the third conductive pattern layer and the fourth conductive pattern layer are a cathode layer, an anode layer, a source/drain electrode layer and a gate pattern layer, respectively, the shielding ring positioned at the periphery of the anode layer and the shielding ring positioned at the periphery of the cathode layer are electrically connected with each other through a through hole formed in a pixel limiting layer of the array substrate, the shielding ring positioned at the periphery of the anode layer and the shielding ring positioned at the periphery of the source/drain electrode layer are electrically connected with each other through a through hole formed in a planarization layer of the array substrate, and the shielding ring positioned at the periphery of the source/drain electrode layer and the shielding ring positioned at the periphery of the gate pattern layer are electrically connected with each other through a through hole formed in a gate insulating layer of the array substrate.
In an embodiment of the present disclosure, the array substrate further includes a shielding ring disposed in the same layer as a second conductive pattern layer of the plurality of conductive pattern layers and located at a periphery of the second conductive pattern layer.
In one embodiment of the present disclosure, the shield ring located at the periphery of the first conductive pattern layer and the shield ring located at the periphery of the second conductive pattern layer are electrically connected to each other.
In one embodiment of the present disclosure, the shield ring is electrically insulated from the first conductive pattern layer by a crossover.
According to another aspect of the present disclosure, there is provided an embedded touch display panel including the array substrate described above.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure. In the drawings:
fig. 1 is a schematic plan view illustrating a shield ring according to an embodiment of the present disclosure;
fig. 2 is a schematic cross-sectional view illustrating an array substrate including a shield ring according to a first embodiment of the present disclosure;
fig. 3 is a schematic cross-sectional view illustrating an array substrate including a shield ring according to a second embodiment of the present disclosure;
fig. 4 is a schematic cross-sectional view illustrating an array substrate including a shield ring according to a third embodiment of the present disclosure;
fig. 5 is a schematic cross-sectional view illustrating an array substrate including a shield ring according to a fourth embodiment of the present disclosure;
fig. 6 is a schematic cross-sectional view illustrating an array substrate including a shield ring according to a fifth embodiment of the present disclosure;
fig. 7 is a partial schematic plan view illustrating a shield ring crossing a gate wiring electrically connected to a touch electrode by means of a crossover according to an embodiment of the present disclosure.
Detailed Description
It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on, connected or bonded to the other element or layer, or intervening elements or layers may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. Like numbers refer to like elements throughout. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Spatially relative terms, such as "lower," "above …," "upper," "below …," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Hereinafter, the present disclosure will be explained in detail with reference to the accompanying drawings.
In general, the array substrate according to the embodiment of the present disclosure includes a plurality of conductive pattern layers, and further includes a shield ring disposed on the same layer as a first conductive pattern layer of the plurality of conductive pattern layers and located at a periphery of the first conductive pattern layer.
In addition, the shield ring may be disposed in a peripheral region of the array substrate. The plurality of conductive pattern layers may include a gate pattern layer, a source/drain electrode layer, and a cathode layer and an anode layer of the light emitting display device, and the first conductive pattern layer is one of the cathode layer, the anode layer, the source/drain electrode layer, and the gate pattern layer.
Optionally, the array substrate further includes a shielding ring disposed in the same layer as the second conductive pattern layer of the plurality of conductive pattern layers and located at the periphery of the second conductive pattern layer. In some cases, the shield ring needs to be electrically insulated from the first conductive pattern layer by means of a crossover.
For example, referring to fig. 1, the shield ring 200 is disposed in a peripheral region of the array substrate, i.e., in a non-display region (i.e., a peripheral region) of the array substrate. The light emitting display device included in the array substrate includes the cathode electrode 109 serving as a touch electrode, and the shield ring 200 is disposed around the touch electrode 109 to effectively shield interference of external noise with signals inside the substrate, thereby improving touch sensitivity.
In one embodiment, shield ring 200 may be electrically connected to an integrated circuit chip (IC chip) and the IC chip may provide a ground signal to shield ring 200.
In addition, the cathode 109 of the light emitting display device may be connected to an external gate wiring.
The plurality of conductive pattern layers described herein may include a gate pattern layer, a source/drain electrode layer, and a cathode layer and an anode layer of the light emitting display device, and the first conductive pattern layer described herein is one of the cathode layer, the anode layer, the source/drain electrode layer, and the gate pattern layer.
In one embodiment, the array substrate further includes a shielding ring disposed on the same layer as and at the periphery of a second conductive pattern layer of the plurality of conductive pattern layers, and the first conductive pattern layer and the second conductive pattern layer are two selected from a cathode layer, an anode layer, a source/drain electrode layer, and a gate pattern layer.
In one embodiment, the first and second conductive pattern layers are a cathode layer and an anode layer, respectively, wherein the shield ring at the periphery of the anode layer and the shield ring at the periphery of the cathode layer are electrically connected to each other through a through hole formed in the pixel defining layer of the array substrate.
In one embodiment, the array substrate further includes a shielding ring disposed on the same layer as and around a third conductive pattern layer of the plurality of conductive pattern layers, and the first conductive pattern layer, the second conductive pattern layer, and the third conductive pattern layer are a cathode layer, an anode layer, and a source/drain electrode layer, respectively.
In this case, the shield ring at the periphery of the anode layer and the shield ring at the periphery of the cathode layer are electrically connected to each other through the through hole formed in the pixel defining layer of the array substrate, and the shield ring at the periphery of the anode layer and the shield ring at the periphery of the source/drain electrode layer are electrically connected to each other through the through hole formed in the planarization layer.
In one embodiment, the array substrate further includes a shielding ring disposed on the same layer as a fourth conductive pattern layer of the plurality of conductive pattern layers and located at the periphery of the fourth conductive pattern layer, and the first conductive pattern layer, the second conductive pattern layer, the third conductive pattern layer, and the fourth conductive pattern layer are a cathode layer, an anode layer, a source/drain electrode layer, and a gate pattern layer, respectively.
In this case, the shield ring located at the periphery of the anode layer and the shield ring located at the periphery of the cathode layer are electrically connected to each other through the through hole formed in the pixel defining layer of the array substrate, the shield ring located at the periphery of the anode layer and the shield ring located at the periphery of the source/drain electrode layer are electrically connected to each other through the through hole formed in the planarization layer of the array substrate, and the shield ring located at the periphery of the source/drain electrode layer and the shield ring located at the periphery of the gate pattern layer are electrically connected to each other through the through hole formed in the gate insulating layer of the array substrate.
In one embodiment, the array substrate further includes a shielding ring disposed in the same layer as a second conductive pattern layer of the plurality of conductive pattern layers and located at the periphery of the second conductive pattern layer.
In this case, the shield ring located at the periphery of the first conductive pattern layer and the shield ring located at the periphery of the second conductive pattern layer are electrically connected to each other.
The shield ring may be electrically insulated from the first conductive pattern layer by a crossover, as necessary.
A specific structure of the shield ring of the embodiment of the present disclosure will be described in detail below with reference to fig. 2 to 6.
Fig. 2 is a schematic cross-sectional view illustrating an array substrate including a shield ring according to a first embodiment of the present disclosure.
Referring to fig. 2, the array substrate 100 according to an embodiment of the present disclosure mainly includes a base substrate 101, a gate pattern layer 102 sequentially formed on the base substrate 101, a gate insulating layer 103 covering the gate pattern layer 102, an active pattern layer 104 formed on the gate insulating layer 103, a source electrode layer 105S and a drain electrode layer 105D (i.e., source/drain electrode layers 105S \105D) respectively contacting the active pattern layer 104 and partially covering the gate insulating layer 103, and a planarization layer 106. The array substrate 100 further includes a light emitting display device formed on the planarization layer 106, wherein the light emitting display device includes a cathode layer 109 serving as a touch electrode, an anode layer 107, and an organic light emitting layer 108 disposed between the cathode layer 109 and the anode layer 107, and an encapsulation layer 110. In addition, a pixel defining layer PDL is disposed between the cathode layer 109 and the anode layer 107.
In the embodiment shown in fig. 2, the shielding ring 200 is disposed in the peripheral region of the array substrate 100 and is formed around the cathode 109. Only the shield ring 200 disposed in the left region of the array substrate 100 is shown in the cross-sectional view of fig. 2, as shown in fig. 1.
In the present embodiment, the shield ring 200 is formed in the same layer as the cathode layer 109 and is electrically insulated from the cathode layer 109.
In one embodiment, the shield ring 200 and the cathode layer 109, which are electrically insulated from each other, may be formed by depositing an electrode material layer on the pixel defining layer PDL and the organic light emitting layer 108, and then by performing, for example, a patterning process on the electrode material layer.
If the shield ring 200 meets the external lead of the cathode layer 109 on the same layer, the shield ring 200 may cross over the external lead of the cathode layer 109 by means of a crossover, i.e., the shield ring 200 may cross over by means of other conductive patterns located on different layers (e.g., a gate metal pattern on the gate insulating layer 103, or an anode metal pattern on the planarization layer 106, etc.). Accordingly, the shield ring 200 can be electrically insulated from the cathode layer 109.
Fig. 3 is a schematic cross-sectional view illustrating an array substrate including a shield ring according to a second embodiment of the present disclosure.
Referring to fig. 3, in the present embodiment, an array substrate 100-1 according to the present embodiment has a similar configuration to the array substrate 100 of the first embodiment except that an arrangement of a shield ring 200-1 is different from that of the shield ring 200 of the first embodiment, and the difference therebetween will be mainly described below.
In the present embodiment, the shield ring 200-1 is not formed in the same layer as the cathode layer 109, but is formed in the same layer as the anode layer 107 and is electrically insulated from the anode layer 107. The shield ring 200-1 is formed around the anode layer 107 in the peripheral region of the array substrate 100-1.
Similarly, in one embodiment, the shield ring 200-1 and the anode layer 107 may be formed to be electrically insulated from each other by depositing a layer of electrode material on the planarization layer 106, and then by subjecting the layer of electrode material to, for example, a patterning process.
The shield ring 200-1 may also be electrically isolated from the anode layer 107 by similar bridging, if desired.
In addition, the array substrate may include both the shield ring 200 formed in the same layer as the cathode layer 109 and electrically insulated from the cathode layer 109 and the shield ring 200-1 formed in the same layer as the anode layer 107 and electrically insulated from the anode layer 107. In this case, the shield ring 200 may be electrically connected to the shield ring 200-1 through a via hole formed in the pixel defining layer PDL. Therefore, the interference of the clock signal and the parasitic signal to the touch signal can be better shielded.
Fig. 4 is a schematic cross-sectional view illustrating an array substrate including a shield ring according to a third embodiment of the present disclosure.
Referring to fig. 4, in the present embodiment, an array substrate 100-2 according to the present embodiment has a similar configuration to the array substrate 100 of the first embodiment except that an arrangement of a shield ring 200-2 is different from that of the shield ring 200 of the first embodiment, and the difference therebetween will be mainly described below.
In the present embodiment, the shield ring 200-2 is not formed in the same layer as the cathode layer 109, but is formed in the same layer as the source electrode 105S and the drain electrode 105D and is electrically insulated from the source electrode 105S and the drain electrode 105D. The shield ring 200-2 is formed around the source electrode 105S and the drain electrode 105D in the peripheral region of the array substrate 100-2.
Similarly, in one embodiment, the shield ring 200-2 and the source electrode 105S and the drain electrode 105D may be formed to be electrically insulated from each other by depositing a metal material layer on the gate insulating layer 103 and then by performing, for example, a patterning process on the metal material layer.
The shield ring 200-2 can also be electrically insulated from the source electrode 105S and the drain electrode 105D by a similar bridge connection manner, if necessary.
Fig. 5 is a schematic cross-sectional view illustrating an array substrate including a shield ring according to a fourth embodiment of the present disclosure.
Referring to fig. 5, the array substrate 100-3 according to the present embodiment has a similar configuration to the array substrate 100 of the first embodiment except for a shield ring, and differences therebetween will be mainly described below.
In the present embodiment, the shield ring includes a shield ring 200 formed in the same layer as the cathode layer 109 and electrically insulated from the cathode layer 109, a shield ring 200-1 formed in the same layer as the anode layer 107 and electrically insulated from the anode layer 107, and a shield ring 200-2 formed in the same layer as the source electrode 105S and the drain electrode 105D and electrically insulated from the source electrode 105S and the drain electrode 105D.
As shown in fig. 5, the shield ring 200 may be electrically connected to the shield ring 200-1 through a via H1 formed in the pixel defining layer PDL, and the shield ring 200-1 may be electrically connected to the shield ring 200-2 through a via H2 formed in the planarization layer 106. Accordingly, the shield ring 200-1, and the shield ring 200-2 are electrically connected.
Further, the formation methods of the shield ring 200, the shield ring 200-1, and the shield ring 200-2 may be similar to those described in the above embodiments, respectively.
Of course, it is understood that the shield ring 200, the shield ring 200-1 and the shield ring 200-2 may not be electrically connected to each other. Alternatively, two of the shield ring 200, the shield ring 200-1, and the shield ring 200-2 are electrically connected. For example, the shield ring 200 is electrically connected to the shield ring 200-1, or the shield ring 200-1 and the shield ring 200-2 are electrically connected.
Fig. 6 is a schematic cross-sectional view illustrating an array substrate including a shield ring according to a fifth embodiment of the present disclosure.
The array substrate 100-4 according to the present embodiment has a similar configuration to the array substrate 100 of the first embodiment except for the shield ring, and the difference therebetween will be mainly described below.
In the present embodiment, the shield ring includes a shield ring 200 formed in the same layer as the cathode layer 109 and electrically insulated from the cathode layer 109, a shield ring 200-1 formed in the same layer as the anode layer 107 and electrically insulated from the anode layer 107, a shield ring 200-2 formed in the same layer as the source electrode 105S and the drain electrode 105D and electrically insulated from the source electrode 105S and the drain electrode 105D, and a shield ring 200-3 formed in the same layer as the gate pattern layer 102 and electrically insulated from the gate pattern layer 102.
As shown in fig. 6, the shield ring 200 may be electrically connected to the shield ring 200-1 through a via H1 formed in the pixel defining layer PDL, the shield ring 200-1 may be electrically connected to the shield ring 200-2 through a via H2 formed in the planarization layer 106, and the shield ring 200-2 may be electrically connected to the shield ring 200-3 through a via H3 formed in the gate insulating layer 103. In this case, the shield ring 200-1, the shield ring 200-2, and the shield ring 200-3 can be electrically connected.
Also, the shield ring 200-1, the shield ring 200-2, and the shield ring 200-3 may not be electrically connected to each other. Alternatively, adjacent two of the shield rings 200, 200-1, 200-2, and 200-3 may be electrically connected.
An array substrate including a shield ring according to some embodiments of the present disclosure is illustrated in fig. 2 to 6, however, according to the present disclosure, the array substrate of the present disclosure is not limited only to the examples shown in fig. 2 to 6.
Fig. 7 is a partial schematic plan view illustrating a shield ring crossing a gate wiring electrically connected to a touch electrode by means of a crossover so as to be electrically insulated from the gate wiring according to an embodiment of the present disclosure.
In fig. 7, the cathode layer 109 of the light emitting display device is connected downward through the hollowed-out region T1 of the pixel defining layer PDL to be electrically connected to the underlying lateral anode metal layer (e.g., ITO/Ag/ITO layer), and then electrically connected to the gate wiring 400 formed on the substrate base plate 101 through the via hole T2 formed in the planarization layer 106 and the via hole T3 formed in the gate insulating layer 103.
In this case, for example, the shield ring 200-3 formed in the same layer as the gate pattern layer 102 and electrically insulated from the gate pattern layer 102 will encounter the gate wiring 400 when making a ring connection, and at this time, in order to achieve electrical insulation from the gate wiring 400, the shield ring 200-3 may be electrically connected in a closed ring by a jumper CL located in a different layer via a via T3 formed in the gate insulating layer 103.
In one embodiment, the jumper line CL may be a part of a source-drain electrode layer (which is electrically insulated from the source electrode 105S and the drain electrode 105D) formed on the gate insulating layer 103, or a part of an anode layer (which is electrically insulated from the anode layer 107) formed on the planarization layer 106. However, in the present disclosure, the type of the jumper line CL is not limited thereto as long as the shield ring can be electrically insulated from the conductive layers of the same layer (e.g., the cathode layer 109, the anode layer 107, the source electrode 105S and the drain electrode 105D, or the gate pattern layer 102, etc.).
In addition, embodiments of the present disclosure also provide an embedded touch display panel including the array substrate described above.
Since the shielding rings are arranged around the corresponding conductive pattern layers in the peripheral region of the array substrate, interference of clock signals and parasitic signals to touch signals can be effectively shielded, and thus touch sensitivity is improved.
The foregoing description of specific exemplary embodiments of the present disclosure has been presented with reference to the accompanying drawings. These exemplary embodiments are not intended to be exhaustive or to limit the disclosure to the precise forms disclosed, and obviously many modifications and variations are possible to those skilled in the art in light of the above teachings. Accordingly, the scope of the present disclosure is not intended to be limited to the foregoing embodiments, but is intended to be defined by the claims and their equivalents.
Claims (6)
1. An array substrate comprises a plurality of conductive pattern layers and a shielding ring which is arranged in the same layer with a first conductive pattern layer in the plurality of conductive pattern layers and is positioned at the periphery of the first conductive pattern layer,
the first conductive pattern is a cathode layer serving as a touch electrode, and the cathode layer is insulated from the shielding ring;
the array substrate further comprises a shielding ring which is arranged on the same layer as a second conductive pattern layer in the plurality of conductive pattern layers and is positioned on the periphery of the second conductive pattern layer, the second conductive pattern layer is an anode layer, and the shielding ring positioned on the periphery of the anode layer and the shielding ring positioned on the periphery of the cathode layer are electrically connected with each other through a through hole formed in a pixel limiting layer of the array substrate.
2. The array substrate of claim 1, wherein the plurality of conductive pattern layers comprise a gate pattern layer, a source/drain electrode layer, and a cathode layer and an anode layer of a light emitting display device.
3. The array substrate of claim 1, wherein the array substrate further comprises a shielding ring disposed in the same layer as and at the periphery of a third conductive pattern layer of the plurality of conductive pattern layers, the second and third conductive pattern layers being an anode layer and a source/drain electrode layer, respectively,
wherein the shielding ring at the periphery of the anode layer and the shielding ring at the periphery of the cathode layer are electrically connected with each other through a through hole formed in the pixel defining layer of the array substrate, and the shielding ring at the periphery of the anode layer and the shielding ring at the periphery of the source/drain electrode layer are electrically connected with each other through a through hole formed in the planarization layer.
4. The array substrate of claim 3, wherein the array substrate further comprises a shielding ring disposed in the same layer as a fourth conductive pattern layer of the plurality of conductive pattern layers and located at the periphery of the fourth conductive pattern layer, the second conductive pattern layer, the third conductive pattern layer and the fourth conductive pattern layer are respectively an anode layer, a source/drain electrode layer and a gate pattern layer,
the shielding ring positioned at the periphery of the anode layer and the shielding ring positioned at the periphery of the cathode layer are electrically connected with each other through a through hole formed in a pixel limiting layer of the array substrate, the shielding ring positioned at the periphery of the anode layer and the shielding ring positioned at the periphery of the source/drain electrode layer are electrically connected with each other through a through hole formed in a planarization layer of the array substrate, and the shielding ring positioned at the periphery of the source/drain electrode layer and the shielding ring positioned at the periphery of the gate pattern layer are electrically connected with each other through a through hole formed in a gate insulating layer of the array substrate.
5. The array substrate of claim 1, wherein the shield ring is electrically insulated from the first conductive pattern layer by a crossover.
6. An embedded touch display panel comprising the array substrate of claim 1.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710335917.0A CN107146784B (en) | 2017-05-12 | 2017-05-12 | Array substrate and embedded touch display panel comprising same |
| PCT/CN2018/072083 WO2018205671A1 (en) | 2017-05-12 | 2018-01-10 | Array substrate and embedded touch display panel comprising same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710335917.0A CN107146784B (en) | 2017-05-12 | 2017-05-12 | Array substrate and embedded touch display panel comprising same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107146784A CN107146784A (en) | 2017-09-08 |
| CN107146784B true CN107146784B (en) | 2021-01-26 |
Family
ID=59778533
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710335917.0A Active CN107146784B (en) | 2017-05-12 | 2017-05-12 | Array substrate and embedded touch display panel comprising same |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN107146784B (en) |
| WO (1) | WO2018205671A1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107146784B (en) * | 2017-05-12 | 2021-01-26 | 京东方科技集团股份有限公司 | Array substrate and embedded touch display panel comprising same |
| CN108520883B (en) * | 2018-04-12 | 2021-12-21 | 武汉华星光电半导体显示技术有限公司 | OLED touch display panel and manufacturing method thereof |
| CN109378335B (en) | 2018-11-22 | 2021-01-15 | 武汉华星光电半导体显示技术有限公司 | Display panel |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102841716A (en) * | 2012-08-21 | 2012-12-26 | 北京京东方光电科技有限公司 | Capacitance-type embedded touch screen and display device |
| CN103926727A (en) * | 2013-12-24 | 2014-07-16 | 上海天马微电子有限公司 | Touch display panel and display device |
| CN104143561A (en) * | 2013-05-09 | 2014-11-12 | 三星显示有限公司 | Organic light emitting diode display |
| CN104749846A (en) * | 2015-04-17 | 2015-07-01 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof and display panel |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5638205B2 (en) * | 2009-06-16 | 2014-12-10 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| CN104793804B (en) * | 2015-05-12 | 2017-12-15 | 京东方科技集团股份有限公司 | Touch base plate, display device and its manufacture method and driving method |
| CN107146784B (en) * | 2017-05-12 | 2021-01-26 | 京东方科技集团股份有限公司 | Array substrate and embedded touch display panel comprising same |
-
2017
- 2017-05-12 CN CN201710335917.0A patent/CN107146784B/en active Active
-
2018
- 2018-01-10 WO PCT/CN2018/072083 patent/WO2018205671A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102841716A (en) * | 2012-08-21 | 2012-12-26 | 北京京东方光电科技有限公司 | Capacitance-type embedded touch screen and display device |
| CN104143561A (en) * | 2013-05-09 | 2014-11-12 | 三星显示有限公司 | Organic light emitting diode display |
| CN103926727A (en) * | 2013-12-24 | 2014-07-16 | 上海天马微电子有限公司 | Touch display panel and display device |
| CN104749846A (en) * | 2015-04-17 | 2015-07-01 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof and display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107146784A (en) | 2017-09-08 |
| WO2018205671A1 (en) | 2018-11-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109103231B (en) | Display substrate, manufacturing method thereof and display device | |
| US20210232250A1 (en) | Display device including touch screen function | |
| US10528166B2 (en) | Flexible display device and method of manufacturing the same | |
| CN107342370B (en) | Display panel and display device | |
| KR101437205B1 (en) | Display with in-cell touch sensor | |
| US10705367B2 (en) | Touch display panel having touch line formed on the same layer as the gate line | |
| US10761660B2 (en) | Touch display device having touch display panel capable of preventing short circuit of adjacent tough lines | |
| EP3321785B1 (en) | Embedded touch screen and organic light-emitting diode display device | |
| US10261640B2 (en) | Embedded touch panel and display device | |
| US9825112B2 (en) | Array substrate, display panel and display device | |
| CN108984012B (en) | Display device | |
| US10466820B2 (en) | OLED array substrate, manufacturing method thereof and touch display device | |
| CN107025028B (en) | Self-capacitance touch screen and display device with same | |
| US8901549B2 (en) | Organic light emitting diode touch display panel | |
| CN108336116B (en) | OLED array substrate, preparation method thereof and display device | |
| CN107146784B (en) | Array substrate and embedded touch display panel comprising same | |
| US10275106B2 (en) | Display device and method of fabricating the same | |
| KR20130045795A (en) | Touch device and fabrication method thereof | |
| CN108389883B (en) | Touch display substrate, manufacturing method thereof and display device | |
| CN105138163A (en) | Organic electroluminescent touch display panel and preparation method thereof as well as display device | |
| KR20120062178A (en) | Organic light emitting diodde desplay device | |
| US20240045541A1 (en) | Display panel, display device and method for fabricating the display panel | |
| CN104978066A (en) | Touch panel and display apparatus | |
| CN109742118B (en) | Display panel, array substrate and preparation method thereof | |
| CN108807461B (en) | Organic light emitting display panel and method of manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |