CN107146784A - Array base palte and the built-in touch display panel including it - Google Patents
Array base palte and the built-in touch display panel including it Download PDFInfo
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- CN107146784A CN107146784A CN201710335917.0A CN201710335917A CN107146784A CN 107146784 A CN107146784 A CN 107146784A CN 201710335917 A CN201710335917 A CN 201710335917A CN 107146784 A CN107146784 A CN 107146784A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/40—OLEDs integrated with touch screens
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Abstract
Present disclose provides a kind of array base palte and a kind of built-in touch display panel including the array base palte.The array base palte includes multiple conductive pattern layers, in addition to is set with the first conductive pattern layer in the multiple conductive pattern layer with layer and positioned at the shading ring on the first conductive pattern layer periphery.
Description
Technical field
This disclosure relates to display technology field, and relate more specifically to a kind of array base palte and a kind of including the array base palte
Built-in touch display panel.
Background technology
OLED (AMOLED) is one of focus of current flat-panel monitor research field, with liquid crystal display
Compare, OLED has the advantages that low low energy consumption, production cost, self-luminous, wide viewing angle and fast response time, at present, OLED is
Start to replace traditional LCD display in display fields such as mobile phone, PDA, digital cameras.Embedded touch (in cell
Touch) technology can with display panel process compatible, so increasingly being favored.Especially future is applied to flexible OLED
During product, embedded OLED film integrated circuits (FIC) technology will more possess advantage, be primarily due to current flexible OLED and touch
It is all the touch structure that multilayer is directly made on thin-film package (TFE) encapsulating structure to touch scheme, and this both adds making
Difficulty, while also increasing cost of manufacture.
However, for embedded active matrix organic light emitting diode display, there is outside noise interference panel
Internal signal and cause the problem of touch-control sensitivity is affected.
Disclosure
For at least one in solving the above problems, include the array present disclose provides a kind of array base palte and one kind
The built-in touch display panel of substrate.
According to the one side of the disclosure there is provided a kind of array base palte, it includes multiple conductive pattern layers, in addition to institute
The first conductive pattern layer in multiple conductive pattern layers is stated to set with layer and positioned at the shading ring on the first conductive pattern layer periphery.
In one embodiment of the disclosure, the multiple conductive pattern layer include gate pattern layer, source/drain electrode layer with
And the cathode layer and anode layer of light-emitting display device, the first conductive pattern layer be cathode layer, anode layer, source drain electrode layer and grid
One in pole figure pattern layer.
In one embodiment of the disclosure, the array base palte also includes and second in the multiple conductive pattern layer
Conductive pattern layer is set with layer and positioned at the shading ring on the second conductive pattern layer periphery, the first conductive pattern layer and the second conductive pattern
Pattern layer be from cathode layer, anode layer, source select two in drain electrode layer and gate pattern layer.
In one embodiment of the disclosure, the first conductive pattern layer and the second conductive pattern layer are cathode layer and sun respectively
Pole layer, wherein, the shading ring positioned at anode layer periphery and the shading ring positioned at cathode layer periphery are by forming in array base palte
Through hole in pixel confining layers is electrically connected to each other.
In one embodiment of the disclosure, the array base palte also includes and the 3rd in the multiple conductive pattern layer
Conductive pattern layer is set with layer and positioned at the shading ring on the 3rd conductive pattern layer periphery, the first conductive pattern layer, second are led
Electrograph pattern layer and the 3rd conductive pattern layer are cathode layer, anode layer and Yuan drain electrode layers respectively, wherein, positioned at anode layer periphery
Shading ring and shading ring positioned at cathode layer periphery it is electric each other by forming the through hole in the pixel confining layers of array base palte
Connection, positioned at anode layer periphery shading ring and positioned at source drain electrode layer periphery shading ring by being formed in planarization layer
Through hole be electrically connected to each other.
In one embodiment of the disclosure, the array base palte also includes and the 4th in the multiple conductive pattern layer
Conductive pattern layer is set with layer and positioned at the shading ring on the 4th conductive pattern layer periphery, the first conductive pattern layer, the second conductive pattern
Pattern layer, the 3rd conductive pattern layer and the 4th conductive pattern layer be respectively cathode layer, anode layer, source drain electrode layer and gate pattern
Layer, wherein, the shading ring positioned at anode layer periphery and the shading ring positioned at cathode layer periphery are by forming the picture in array base palte
Through hole in plain confining layers is electrically connected to each other, positioned at anode layer periphery shading ring and positioned at source drain electrode layer periphery shielding
Ring is electrically connected to each other by forming the through hole in the planarization layer of array base palte, positioned at source drain electrode layer periphery shading ring
It is electrically connected to each other with the shading ring positioned at gate pattern layer periphery by forming the through hole in the gate insulator of array base palte.
The array base palte described in one embodiment of the disclosure also includes and second in the multiple conductive pattern layer
Conductive pattern layer is set with layer and positioned at the shading ring on the second conductive pattern layer periphery.
In one embodiment of the disclosure, positioned at the shading ring on the first conductive pattern layer periphery and positioned at described
The shading ring on two conductive pattern layer peripheries is electrically connected to each other.
In one embodiment of the disclosure, shading ring is electrically insulated by cross-over mode and the first conductive pattern layer.
According to another aspect of the present disclosure there is provided a kind of built-in touch display panel, the built-in touch is shown
Panel includes array base palte described above.
Brief description of the drawings
Including accompanying drawing to provide further understanding of the disclosure, accompanying drawing is incorporated herein and constitutes one of the application
Point, accompanying drawing shows embodiment of the disclosure, and is used for the principle of explaining the disclosure together with the description.In the accompanying drawings：
Fig. 1 is the floor map for showing shading ring in accordance with an embodiment of the present disclosure；
Fig. 2 is the schematic cross sectional views for showing the array base palte including shading ring according to first embodiment of the present disclosure；
Fig. 3 is the schematic cross sectional views for showing the array base palte including shading ring according to second embodiment of the present disclosure；
Fig. 4 is the schematic cross sectional views for showing the array base palte including shading ring according to third embodiment of the present disclosure；
Fig. 5 is the schematic cross sectional views for showing the array base palte including shading ring according to fourth embodiment of the present disclosure；
Fig. 6 is the schematic cross sectional views for showing the array base palte including shading ring according to fifth embodiment of the present disclosure；
Fig. 7 is to show that shading ring in accordance with an embodiment of the present disclosure is electrically connected by cross-over mode across with touch control electrode
The partial schematic plan view of grid wiring.
Embodiment
It will be appreciated that when element or layer be referred to as another element or layer " on " or " being connected to " another element or layer
When, the element or layer can directly on another element or layer, be directly connected to or be bonded directly to another element or layer, or
Can also there are intermediary element or intermediate layer.On the contrary, when element be referred to as " direct " another element or layer " on " it is or " direct
Be connected to " another element or layer when, in the absence of intermediary element or intermediate layer.Like number indicates same element all the time.Such as
It is used herein, term "and/or" includes any combination of the project listed by one or more correlations and all combinations.
For the ease of description, space relative terms can be used herein, such as " under ", " ... top ", " on ", " ... under
Side " etc. describes an element as illustrated in the drawing or feature and other elements or the relation of feature.It will be appreciated that space phase
Term is intended to comprising the different azimuth of device in use or operation in addition to the orientation being described in the drawings.
As used herein, unless the context clearly indicates otherwise, otherwise singulative is " one (kind) " and " described
(being somebody's turn to do) " is also intended to include plural form.It will be further understood that term "comprising" and/or " comprising " ought be used in this manual
When, illustrate there is the feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of one or more
Further feature, entirety, step, operation, element, component and/or their group.
Hereinafter, the disclosure is explained in detail with reference to the accompanying drawings.
Generally say, according to the array base palte of the embodiment of the present disclosure include multiple conductive pattern layers, in addition to it is described many
The first conductive pattern layer in individual conductive pattern layer is set with layer and positioned at the shading ring on the first conductive pattern layer periphery.
In addition, shading ring can be arranged in the neighboring area of array base palte.Multiple conductive pattern layers can include grid
The cathode layer and anode layer of patterned layer, source/drain electrode layer and light-emitting display device, the first conductive pattern layer are cathode layer, sun
Pole layer, source drain electrode layer and gate pattern layer in one.
Alternatively, array base palte also include with the second conductive pattern layer in the multiple conductive pattern layer with layer set and
Shading ring positioned at the second conductive pattern layer periphery.In some cases, shading ring needs conductive by cross-over mode and first
Patterned layer is electrically insulated.
For example, referring to Fig. 1, shading ring 200 is arranged in the neighboring area of array base palte, that is, is arranged on the non-of array base palte
In viewing area (that is, outer peripheral areas).The light-emitting display device being included in array base palte includes the negative electrode as touch control electrode
109, and shading ring 200 is set around touch electrode 109, and substrate internal signal is done with effectively shielding outside noise
Disturb, so as to improve touch-control sensitivity.
In one embodiment, shading ring 200 can be electrically connected with IC chip (IC chip), and IC chip can be with
Ground signalling is provided to shading ring 200.
In addition, the negative electrode 109 of light-emitting display device may be coupled to external grid lead.
Multiple conductive pattern layers as described herein can include gate pattern layer, source/drain electrode layer and active display
The cathode layer and anode layer of part, the first conductive pattern layer as described herein be cathode layer, anode layer, source drain electrode layer and grid
One in patterned layer.
In one embodiment, array base palte also includes same with the second conductive pattern layer in the multiple conductive pattern layer
Layer is set and positioned at the shading ring on the second conductive pattern layer periphery, the first conductive pattern layer and the second conductive pattern layer are from negative electrode
Layer, anode layer, source select two in drain electrode layer and gate pattern layer.
In one embodiment, the first conductive pattern layer and the second conductive pattern layer are cathode layer and anode layer respectively, its
In, the shading ring positioned at anode layer periphery and the shading ring positioned at cathode layer periphery are limited by the pixel formed in array base palte
Through hole in layer is electrically connected to each other.
In one embodiment, array base palte also includes same with the 3rd conductive pattern layer in the multiple conductive pattern layer
Layer is set and positioned at the shading ring on the 3rd conductive pattern layer periphery, the first conductive pattern layer, the second conductive pattern layer and the 3rd are led
Electrograph pattern layer is cathode layer, anode layer and Yuan drain electrode layers respectively.
In the case, the shading ring positioned at anode layer periphery and the shading ring positioned at cathode layer periphery are by forming in battle array
Through hole in the pixel confining layers of row substrate is electrically connected to each other, positioned at anode layer periphery shading ring and positioned at source drain electrode layer
The shading ring on periphery is electrically connected to each other by the through hole formed in planarization layer.
In one embodiment, array base palte also includes same with the 4th conductive pattern layer in the multiple conductive pattern layer
Layer is set and positioned at the shading ring on the 4th conductive pattern layer periphery, the first conductive pattern layer, the second conductive pattern layer, the 3rd conduction
Patterned layer and the 4th conductive pattern layer be respectively cathode layer, anode layer, source drain electrode layer and gate pattern layer.
In the case, the shading ring positioned at anode layer periphery and the shading ring positioned at cathode layer periphery are by forming in battle array
Through hole in the pixel confining layers of row substrate is electrically connected to each other, positioned at anode layer periphery shading ring and positioned at source drain electrode layer
The shading ring on periphery is electrically connected to each other by forming the through hole in the planarization layer of array base palte, positioned at source drain electrode layer week
The shading ring on side and positioned at gate pattern layer periphery shading ring by forming the through hole in the gate insulator of array base palte
It is electrically connected to each other.
In one embodiment, array base palte also includes same with the second conductive pattern layer in the multiple conductive pattern layer
Layer is set and positioned at the shading ring on the second conductive pattern layer periphery.
In the case, positioned at the shading ring and the screen positioned at the second conductive pattern layer periphery on the first conductive pattern layer periphery
Ring is covered to be electrically connected to each other.
As needed, shading ring can be electrically insulated by cross-over mode and the first conductive pattern layer.
Describe the concrete structure of the shading ring of the embodiment of the present disclosure in detail below with reference to Fig. 2 to Fig. 6.
Fig. 2 is the schematic cross sectional views for showing the array base palte including shading ring according to first embodiment of the present disclosure.
Reference picture 2, underlay substrate 101 is mainly included according to the array base palte 100 of the embodiment of the present disclosure, lining is sequentially formed at
Gate pattern layer 102, the gate insulator 103 of cover grid pole figure pattern layer 102, formation on substrate 101 is in gate insulator
On 103 active patterns layer 104, respectively with active patterns layer 104 contact and partly covering gate insulator 103 source electrode
Layer 105S and drain electrode layer 105D (that is, source drain electrode layer 105S 105D) and planarization layer 106.Array base palte 100 is also wrapped
The light-emitting display device to be formed on planarization layer 106 and encapsulated layer 110 are included, wherein, light-emitting display device includes being used as touching
Control cathode layer 109, anode layer 107 and the organic luminous layer 108 being arranged between cathode layer 109 and anode layer 107 of electrode.
In addition, pixel confining layers PDL is arranged between cathode layer 109 and anode layer 107.
In the embodiment shown in Figure 2, shading ring 200 is arranged in the neighboring area of array base palte 100, and around negative electrode
109 and formed.The shading ring 200 being arranged in the left field of array base palte 100 is illustrate only in the sectional view in fig. 2, such as
It is illustrated in fig. 1.
In the present embodiment, shading ring 200 is formed with layer with cathode layer 109 and is electrically insulated with cathode layer 109.
In one embodiment, the deposition of electrode material on pixel confining layers PDL and organic luminous layer 108 can be passed through
Layer, then forms the shading ring 200 and cathode layer that are electrically insulated from each other by carrying out such as Patternized technique to electrode material layer
109。
If the external lead wire of shading ring 200 and cathode layer 109 meets on the same layer, shading ring 200 can pass through
External lead wire of the cross-over mode across cathode layer 109, i.e. shading ring 200 can pass through other conductive patterns on different layers
Case (gate metallic pattern such as, on gate insulator 103 or the anode metal pattern on planarization layer 106 etc.) is entered
Row bridging.Therefore, shading ring 200 can be electrically insulated with cathode layer 109.
Fig. 3 is the schematic cross sectional views for showing the array base palte including shading ring according to second embodiment of the present disclosure.
Reference picture 3, in the present embodiment, except shading ring 200-1 set-up mode is different from the shielding of first embodiment
Outside the set-up mode of ring 200, the array base palte 100 with first embodiment is had according to the array base palte 100-1 of the present embodiment
Similar construction, will mainly describe the difference of the two below.
In the present embodiment, shading ring 200-1 is not formed with cathode layer 109 with layer, but with anode layer 107 with layer
Formed and be electrically insulated with anode layer 107.Shading ring 200-1 is that anode layer 107 is surrounded in array base palte 100-1 neighboring area
Formed by.
Similarly, in one embodiment, can then it be passed through by the deposition of electrode material layer on planarization layer 106
Electrode material layer is carried out such as Patternized technique to form the shading ring 200-1 and anode layer 107 that are electrically insulated from each other.
If necessary, shading ring 200-1 can also realize the electric insulation with anode layer 107 by similar cross-over mode.
In addition, array base palte can include the shading ring for being formed and being electrically insulated with cathode layer 109 with layer with cathode layer 109
200 and with anode layer 107 formed with layer and with anode layer 107 be electrically insulated shading ring 200-1 both.In the case,
Optionally, shading ring 200 can be electrically connected by forming the through hole in pixel confining layers PDL with shading ring 200-1.
Therefore, it is possible to preferably shield the interference of clock signal and parasitic signal to touching signals.
Fig. 4 is the schematic cross sectional views for showing the array base palte including shading ring according to third embodiment of the present disclosure.
Reference picture 4, in the present embodiment, except shading ring 200-2 set-up mode is different from the shielding of first embodiment
Outside the set-up mode of ring 200, the array base palte 100 with first embodiment is had according to the array base palte 100-2 of the present embodiment
Similar construction, will mainly describe the difference of the two below.
In the present embodiment, shading ring 200-2 is not formed with cathode layer 109 with layer, but with source electrode 105S and leakage
Electrode 105D is formed with layer and is electrically insulated with source electrode 105S and drain electrode 105D.Shading ring 200-2 is in array base palte
Around formed by source electrode 105S and drain electrode 105D in 100-2 neighboring area.
Similarly, in one embodiment, deposited metal material layer, Ran Houtong on gate insulator 103 can be passed through
Cross and metal material layer is carried out such as Patternized technique to form the shading ring 200-2 being electrically insulated from each other and source electrode 105S and leakage
Electrode 105D.
If necessary, shading ring 200-2 can also be realized and source electrode 105S and drain electrode by similar cross-over mode
105D electric insulation.
Fig. 5 is the schematic cross sectional views for showing the array base palte including shading ring according to fourth embodiment of the present disclosure.
Reference picture 5, in addition to shading ring, has and first embodiment according to the array base palte 100-3 of the present embodiment
The similar construction of array base palte 100, will mainly describe the difference of the two below.
In the present embodiment, shading ring includes the shielding for being formed and being electrically insulated with cathode layer 109 with layer with cathode layer 109
Ring 200, with anode layer 107 formed with layer and with anode layer 107 be electrically insulated shading ring 200-1 and with source electrode 105S and
The shading ring 200-2 that drain electrode 105D is formed with layer and is electrically insulated with source electrode 105S and drain electrode 105D.
As shown in figure 5, shading ring 200 can be by forming the through hole H1 in pixel confining layers PDL and shading ring 200-1
Electrical connection, and shading ring 200-1 can be electrically connected by the through hole H2 formed in planarization layer 106 with shading ring 200-2.Cause
This, shading ring 200, shading ring 200-1 and shading ring 200-2 this three realization electrical connections.
In addition, the forming method of shading ring 200, shading ring 200-1 and shading ring 200-2 can respectively with superincumbent reality
The method applied described in example is similar.
It is, of course, understood that shading ring 200, shading ring 200-1 and shading ring 200-2 can not also be electrically connected each other
Connect.Or, two in shading ring 200, shading ring 200-1 and shading ring 200-2 are realized electrical connection.Such as, shading ring 200 with
Shading ring 200-1 realizes that electrical connection is realized in electrical connection, or shading ring 200-1 and shading ring 200-2.
Fig. 6 is the schematic cross sectional views for showing the array base palte including shading ring according to fifth embodiment of the present disclosure.
In addition to shading ring, the array base palte with first embodiment is had according to the array base palte 100-4 of the present embodiment
100 similar constructions, will mainly describe the difference of the two below.
In the present embodiment, shading ring includes the shielding for being formed and being electrically insulated with cathode layer 109 with layer with cathode layer 109
Ring 200 and anode layer 107 are formed and the shading ring 200-1 being electrically insulated with anode layer 107 and source electrode 105S and leakage with layer
Electrode 105D formed with layer and with source electrode 105S and drain electrode 105D the shading ring 200-2 being electrically insulated and with grid figure
The shading ring 200-3 that pattern layer 102 is formed with layer and is electrically insulated with gate pattern layer 102.
As shown in fig. 6, shading ring 200 can be by forming the through hole H1 in pixel confining layers PDL and shading ring 200-1
Electrical connection, shading ring 200-1 can be electrically connected by the through hole H2 formed in planarization layer 106 with shading ring 200-2, and
Shading ring 200-2 can be electrically connected by the through hole H3 formed in gate insulator 103 with shading ring 200-3.In this feelings
Under condition, shading ring 200, shading ring 200-1, shading ring 200-2 and shading ring 200-3 can realize electrical connection.
Equally, shading ring 200, shading ring 200-1, shading ring 200-2 and shading ring 200-3 can not also be electrically connected each other
Connect.Or, adjacent two shading ring in shading ring 200, shading ring 200-1, shading ring 200-2 and shading ring 200-3 can
To realize electrical connection.
Had been illustrated in Fig. 2 into Fig. 6 includes the array base palte of shading ring according to some embodiments of the present disclosure, so
And according to content of this disclosure, the array base palte of the disclosure is not restricted in Fig. 2 to the example shown in Fig. 6.
Fig. 7 is to show that shading ring in accordance with an embodiment of the present disclosure is electrically connected by cross-over mode across with touch control electrode
Partial schematic plan view of the grid wiring to be electrically insulated with grid wiring.
In the figure 7, the cathode layer 109 of light-emitting display device is connected downwards by pixel confining layers PDL void region T1,
So as to which the horizontal anode metal layer (for example, ITO/Ag/ITO layers) with lower section is electrically connected, then by being formed in planarization layer
The via T3 of via T2 and formation in gate insulator 103 in 106 is with forming the grid wiring on underlay substrate 101
400 electrical connections.
In the case, for example, the screen for being formed and being electrically insulated with gate pattern layer 102 with layer with gate pattern layer 102
Grid wiring 400 will be run into when carrying out ring connection by covering ring 200-3, now in order to realize the electric insulation with grid wiring 400, be shielded
Covering ring 200-3 can be closed via the via T3 formed in gate insulator 103 by the jumper CL positioned at different layers
The electrical connection of cyclization.
In one embodiment, jumper CL can be formed in part source-drain electrode layer (its on gate insulator 103
It is electrically insulated with source electrode 105S and drain electrode 105D), or segment anode layer (itself and the sun being formed on planarization layer 106
Pole layer 107 is electrically insulated).However, in the disclosure, jumper CL type not limited to this, as long as shading ring and same layer can be made
Conductive layer (such as, cathode layer 109, anode layer 107, source electrode 105S and drain electrode 105D or gate pattern layer 102 etc.)
Realize electric insulation.
In addition, embodiment of the disclosure additionally provides a kind of built-in touch display panel, it includes battle array described above
Row substrate.
Due to being provided with shading ring around corresponding conductive pattern layer in the neighboring area of array base palte, so can have
The interference of the shielding of effect ground clock signal and parasitic signal to touching signals, therefore improve touch-control sensitivity.
The description before certain exemplary embodiments of this disclosure is given for accompanying drawing.These exemplary realities
Apply that example is not intended to exhaustive or the disclosure is confined to disclosed precise forms, and it is evident that in the above
Under the enlightenment of teaching, those of ordinary skill in the art can make many modifications and variations.Therefore, the scope of the present disclosure and unawareness
Figure is confined to foregoing embodiment, but is intended to being limited by claim and their equivalent.
Claims (10)
1. a kind of array base palte, including multiple conductive pattern layers, in addition to it is first conductive in the multiple conductive pattern layer
Patterned layer is set with layer and positioned at the shading ring on the first conductive pattern layer periphery.
2. array base palte according to claim 1, wherein, the multiple conductive pattern layer includes gate pattern layer, source/drain
The cathode layer and anode layer of electrode layer and light-emitting display device, the first conductive pattern layer be cathode layer, anode layer, source electric leakage
One in pole layer and gate pattern layer.
3. array base palte according to claim 2, wherein, the array base palte also includes and the multiple conductive pattern layer
In the second conductive pattern layer set with layer and positioned at the shading ring on the second conductive pattern layer periphery, the first conductive pattern layer and the
Two conductive pattern layers be from cathode layer, anode layer, source select two in drain electrode layer and gate pattern layer.
4. array base palte according to claim 3, wherein, the first conductive pattern layer and the second conductive pattern layer are cloudy respectively
Pole layer and anode layer,
Wherein, the shading ring positioned at anode layer periphery and the shading ring positioned at cathode layer periphery are by forming the picture in array base palte
Through hole in plain confining layers is electrically connected to each other.
5. array base palte according to claim 3, wherein, the array base palte also includes and the multiple conductive pattern layer
In the 3rd conductive pattern layer with layer set and positioned at the 3rd conductive pattern layer periphery shading ring, the first conductive pattern
Layer, the second conductive pattern layer and the 3rd conductive pattern layer be respectively cathode layer, anode layer and source drain electrode layer,
Wherein, the shading ring positioned at anode layer periphery and the shading ring positioned at cathode layer periphery are by forming the picture in array base palte
Through hole in plain confining layers is electrically connected to each other, positioned at anode layer periphery shading ring and positioned at source drain electrode layer periphery shielding
Ring is electrically connected to each other by the through hole formed in planarization layer.
6. array base palte according to claim 5, wherein, the array base palte also includes and the multiple conductive pattern layer
In the 4th conductive pattern layer set with layer and positioned at the shading ring on the 4th conductive pattern layer periphery, the first conductive pattern layer, the
Two conductive pattern layers, the 3rd conductive pattern layer and the 4th conductive pattern layer be respectively cathode layer, anode layer, source drain electrode layer and
Gate pattern layer,
Wherein, the shading ring positioned at anode layer periphery and the shading ring positioned at cathode layer periphery are by forming the picture in array base palte
Through hole in plain confining layers is electrically connected to each other, positioned at anode layer periphery shading ring and positioned at source drain electrode layer periphery shielding
Ring is electrically connected to each other by forming the through hole in the planarization layer of array base palte, positioned at source drain electrode layer periphery shading ring
It is electrically connected to each other with the shading ring positioned at gate pattern layer periphery by forming the through hole in the gate insulator of array base palte.
7. array base palte according to claim 2, wherein, the array base palte also includes and the multiple conductive pattern layer
In the second conductive pattern layer with layer set and positioned at the second conductive pattern layer periphery shading ring.
8. array base palte according to claim 7, wherein, shading ring and position positioned at the first conductive pattern layer periphery
Shading ring in the second conductive pattern layer periphery is electrically connected to each other.
9. array base palte according to claim 1, wherein, the shading ring passes through cross-over mode and first conductive pattern
Pattern layer is electrically insulated.
10. a kind of built-in touch display panel, it includes array base palte according to claim 1.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710335917.0A CN107146784B (en) | 2017-05-12 | 2017-05-12 | Array substrate and embedded touch display panel comprising same |
| PCT/CN2018/072083 WO2018205671A1 (en) | 2017-05-12 | 2018-01-10 | Array substrate and embedded touch display panel comprising same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710335917.0A CN107146784B (en) | 2017-05-12 | 2017-05-12 | Array substrate and embedded touch display panel comprising same |
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| CN107146784A true CN107146784A (en) | 2017-09-08 |
| CN107146784B CN107146784B (en) | 2021-01-26 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108520883A (en) * | 2018-04-12 | 2018-09-11 | 武汉华星光电半导体显示技术有限公司 | OLED touch-control display panels and preparation method thereof |
| WO2018205671A1 (en) * | 2017-05-12 | 2018-11-15 | 京东方科技集团股份有限公司 | Array substrate and embedded touch display panel comprising same |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109378335B (en) | 2018-11-22 | 2021-01-15 | 武汉华星光电半导体显示技术有限公司 | Display panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107146784B (en) * | 2017-05-12 | 2021-01-26 | 京东方科技集团股份有限公司 | Array substrate and embedded touch display panel comprising same |
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2017
- 2017-05-12 CN CN201710335917.0A patent/CN107146784B/en active Active
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| US20100314727A1 (en) * | 2009-06-16 | 2010-12-16 | Nec Electronics Corporation | Semiconductor device |
| CN102841716A (en) * | 2012-08-21 | 2012-12-26 | 北京京东方光电科技有限公司 | Capacitance-type embedded touch screen and display device |
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| WO2018205671A1 (en) * | 2017-05-12 | 2018-11-15 | 京东方科技集团股份有限公司 | Array substrate and embedded touch display panel comprising same |
| CN108520883A (en) * | 2018-04-12 | 2018-09-11 | 武汉华星光电半导体显示技术有限公司 | OLED touch-control display panels and preparation method thereof |
| CN108520883B (en) * | 2018-04-12 | 2021-12-21 | 武汉华星光电半导体显示技术有限公司 | OLED touch display panel and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
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| CN107146784B (en) | 2021-01-26 |
| WO2018205671A1 (en) | 2018-11-15 |
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