CN107134248B

CN107134248B - Source electrode driving circuit, voltage control method of output signal of source electrode driving circuit and display device

Info

Publication number: CN107134248B
Application number: CN201710537782.6A
Authority: CN
Inventors: 刘志友; 许益祯
Original assignee: BOE Technology Group Co Ltd; Chongqing BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chongqing BOE Optoelectronics Technology Co Ltd
Priority date: 2017-07-04
Filing date: 2017-07-04
Publication date: 2020-11-06
Anticipated expiration: 2037-07-04
Also published as: CN107134248A

Abstract

The invention discloses a source electrode driving circuit, a voltage control method of an output signal of the source electrode driving circuit and a display device, and belongs to the technical field of display. The voltage control method of the output signal of the source electrode driving circuit comprises the following steps: detecting whether the level of a polarity control signal sent by a time-measuring controller jumps or not; when the level of the polarity control signal jumps, if the voltage of the output signal is a gamma reference voltage with positive polarity, increasing the voltage of the output signal; and when the level of the polarity control signal jumps, if the voltage of the output signal is the gamma reference voltage with negative polarity, reducing the voltage of the output signal. The method provided by the invention can improve the charging efficiency and reduce the charging time.

Description

Source electrode driving circuit, voltage control method of output signal of source electrode driving circuit and display device

Technical Field

The invention relates to the technical field of display, in particular to a source electrode driving circuit, a voltage control method of an output signal of the source electrode driving circuit and a display device.

Background

A display device may generally include a display panel and a driving circuit for driving the display panel. The driving circuit may include a Timing Controller (TCON), a gate driving circuit, and a source driving circuit.

In the related art, the source driving circuit may convert a digital signal input by the TCON into an analog signal corresponding to a gray-scale voltage according to a gamma reference voltage and output the analog signal to each pixel unit of the display panel. At present, in order to improve the display effect of the display device, the display panel is generally driven by frame inversion, that is, the polarity of the voltage stored in each pixel unit of the display panel is opposite in the period of two adjacent frames. In the frame inversion driving method, the timing controller may output a polarity control signal to the source driving circuit, and the source driving circuit may adjust the polarity of the analog signal output to the display panel according to the level of the polarity control signal.

However, when the source driver circuit outputs the analog signal to the display panel, the pixel unit far from the source driver circuit is charged for a long time due to a certain impedance of the data signal line, and thus the charging efficiency is low.

Disclosure of Invention

In order to solve the problems of long charging time and low charging efficiency when a source electrode driving circuit charges a pixel unit in the related art, the invention provides a source electrode driving circuit, a voltage control method of an output signal of the source electrode driving circuit and a display device. The technical scheme is as follows:

in a first aspect, a method for controlling a voltage of an output signal of a source driving circuit is provided, and the method is applied to the source driving circuit and comprises the following steps:

detecting whether the level of a polarity control signal sent by a time-measuring controller jumps or not;

when the level of the polarity control signal jumps, if the voltage of the output signal is a gamma reference voltage with positive polarity, increasing the voltage of the output signal;

and when the level of the polarity control signal jumps, if the voltage of the output signal is the gamma reference voltage with negative polarity, reducing the voltage of the output signal.

Optionally, after increasing the voltage of the output signal, the method further comprises:

restoring the voltage of the output signal to the positive polarity gamma reference voltage after a first period of time;

after reducing the voltage of the output signal, the method further comprises:

restoring the voltage of the output signal to the negative polarity gamma reference voltage after a second period of time;

wherein the first time period and the second time period are both less than a time period in which the polarity control signal is held at any level in each cycle.

Optionally, if the voltage of the output signal is a positive gamma reference voltage, increasing the voltage of the output signal includes:

increasing the voltage of the output signal from the positive polarity gamma reference voltage GAM1 to a first target voltage GAM11, the first target voltage GAM11 satisfying:

GAM11 is GAM1+1/2(AVDD-GAM1), where AVDD is a reference voltage of the gamma reference voltage.

Optionally, if the voltage of the output signal is a negative gamma reference voltage, reducing the voltage of the output signal includes:

reducing the voltage of the output signal from the negative polarity gamma reference voltage GAM2 to a second target voltage GAM22, the second target voltage GAM22 satisfying:

GAM22 is GAM2+1/2(GND + GAM2), where GND is ground voltage.

In a second aspect, there is provided a source driving circuit including: the device comprises a detection module and an output module;

the input end of the detection module is connected with the time schedule controller, the output end of the detection module is connected with the output module, and the detection module is used for detecting whether the level of the polarity control signal sent by the time schedule controller jumps or not;

the output module is used for: when the level of the polarity control signal jumps, if the voltage of the output signal is a gamma reference voltage with positive polarity, increasing the voltage of the output signal; and when the level of the polarity control signal jumps, if the voltage of the output signal is the gamma reference voltage with negative polarity, reducing the voltage of the output signal.

Optionally, the detection module includes: at least one logic gate; the output module includes: the control submodule, the first output submodule and the second output submodule;

the at least one logic gate is used for outputting an indication signal at a first level to the control submodule when the level of the polarity control signal jumps, and outputting an indication signal at a second level to the control submodule when the level of the polarity control signal does not jump;

the control submodule is used for starting the first output submodule when the indication signal is at a second level, and the voltage of the output signal output by the first output submodule is gamma reference voltage;

the control submodule is further configured to start the second output submodule when the indication signal is at the first level, and the second output submodule is configured to increase the voltage of the output signal when the voltage of the output signal is a positive gamma reference voltage; and reducing the voltage of the output signal when the voltage of the output signal is a negative gamma reference voltage.

Optionally, the at least one logic gate includes: the first AND gate is connected with the first output end of the first output end;

the two input ends of the OR gate and the two input ends of the NAND gate are respectively connected with the time sequence controller;

the first input end of the or gate is used for receiving a polarity control signal, the second input end of the or gate is used for receiving a delay signal of the polarity control signal, and the output end of the or gate is connected with the first input end of the first and gate;

the first input end of the NAND gate is used for receiving the polarity control signal, the second input end of the NAND gate is used for receiving the delay signal of the polarity control signal, and the output end of the NAND gate is connected with the second input end of the first AND gate;

the output end of the first AND gate is connected with the first input end of the second AND gate, the second input end of the second AND gate is connected with a reference level, the output end of the second AND gate is connected with the control submodule, and the reference level is a first level.

GAM22 is GAM2+1/2(GND + GAM2), where GND is ground voltage.

In a third aspect, there is provided a display device including: a source driver circuit as claimed in the second aspect.

The technical scheme provided by the invention has the beneficial effects that:

the invention provides a source electrode driving circuit, a voltage control method of an output signal of the source electrode driving circuit and a display device, wherein when the level jump of a polarity control signal is detected, the source electrode driving circuit starts to charge each pixel unit in a display panel; if the voltage polarity of the output signal is negative at this time, the source driving circuit can reduce the voltage of the output signal, so that the absolute value of the voltage of the output signal can be improved, the charging efficiency can be improved, and the charging time length can be reduced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present invention;

FIG. 2 is a flowchart of a method for controlling the output signal voltage of a source driver circuit according to an embodiment of the present invention;

fig. 3 is a schematic diagram illustrating a correspondence relationship between voltages of a control signal and an output signal according to an embodiment of the present invention;

FIG. 4 is a timing diagram of a polarity control signal and an output signal according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a source driving circuit according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of a detection module according to an embodiment of the present invention;

fig. 7 is a schematic diagram of a corresponding relationship among voltages of a control signal, an indication signal and an output signal according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present invention, and as can be seen from fig. 1, the display device may generally include a display panel 10, a timing controller 20, a gate driving circuit 30, and a source driving circuit 40. Wherein the timing controller 20 is respectively connected to the gate driving circuit 30 and the source driving circuit 40 for controlling the operation states of the gate driving circuit 30 and the source driving circuit 40. The gate driving circuit 30 is respectively connected to each row of pixel units in the display panel 10, and is configured to scan a plurality of rows of pixel units in the display panel 10 line by line. The source driving circuit 40 is respectively connected to each row of pixel units of the display panel, and is configured to output analog signals to the plurality of rows of pixel units to charge the plurality of rows of pixel units.

Specifically, the timing controller 20 can output a polarity control signal to the source driving circuit 40, and the source driving circuit 40 can adjust the polarity of the analog signal output to the display panel 10 according to the level of the polarity control signal, so as to implement the frame inversion driving of the display panel 10. That is, when the level of the polarity control signal is transited, the polarity of the analog signal output from the source driving circuit 40 is also transited.

Fig. 2 is a flowchart of a method for controlling a voltage of an output signal of a source driving circuit according to an embodiment of the present invention, where the method can be applied to the source driving circuit 40 shown in fig. 1, and referring to fig. 2, the method specifically includes:

and step 101, detecting whether the level of the polarity control signal sent by the time schedule controller jumps or not.

When the source driving circuit detects that the level of the polarity control signal jumps, step 102 may be executed; when it is detected that the level of the polarity control signal has not transitioned, step 101 may be continuously performed, that is, the level of the polarity control signal is continuously detected.

Step 102, detecting the voltage polarity of the output signal.

When the source driving circuit detects that the level of the polarity control signal jumps, it can be determined that the gate driving circuit starts scanning the display panel for a new frame. In order to improve the charging efficiency of the output signal of the source driving circuit, the voltage polarity of the current output signal may be detected first.

In the embodiment of the present invention, the voltage of the output signal output from the source driving circuit is a gamma reference voltage determined according to the control signal output from the timing controller. Specifically, the source driving circuit may be configured with a plurality of gamma reference voltages having different voltage values in advance, the timing controller may output a control signal to the source driving circuit before each frame scanning, and the source driving circuit may select one of the plurality of gamma reference voltages as a voltage of the output signal according to the control signal.

For example, assume that, as shown in fig. 3, the source driving circuit is configured with 8 gamma reference voltages with different voltage values in advance: gam1 to gam8, wherein gam1 to gam4 are positive polarity voltages, and gam5 to gam8 are negative polarity voltages. The control signal output by the timing controller may include three control bits: d1, D2, and D3, wherein each control bit may take the value of 0 or 1. The source driving circuit may determine one voltage from the 8 gamma reference voltages as a voltage of the output signal according to values of the three control bits. For example, in fig. 3, when the control bit D3 takes 0, gam1 to gam4 are turned on, gam5 to gam8 are turned off, and when the control bit D3 takes 1, gam1 to gam4 are turned off, and gam5 to gam8 are turned off; when the control bit D2 takes 0, gam1, gam2, gam5 and gam6 are turned on, gam3 and gam4, and gam7 and gam8 are turned off; when the control bit D1 takes 0, gam1, gam3, gam5 and gam7 are turned on, gam2 and gam4, and gam6 and gam8 are turned off. Therefore, by controlling the values of the three control bits, it can be ensured that only one gamma reference voltage is gated. In the example shown in fig. 3, the three control bits D1, D2 and D3 in the control signal output by the timing controller are all 0, so that the gam1 is gated, and the voltage OUT of the output signal output by the source driving circuit at this time is the positive gamma reference voltage gam 1.

Step 103, if the voltage of the output signal is the positive gamma reference voltage, increasing the voltage of the output signal. Step 105 is performed.

When the voltage of the output signal is the positive gamma reference voltage, in order to improve the charging efficiency and reduce the charging time period, the voltage of the output signal may be increased from the positive gamma reference voltage GAM1 to the first target voltage GAM 11. The first target voltage GAM11 may satisfy:

GAM11 is GAM1+1/2(AVDD-GAM1), where AVDD is a reference voltage of the gamma reference voltage. The gamma reference voltages with different voltage values, which are configured in advance in the source driving circuit, are calculated according to the reference voltage AVDD, and the reference voltage AVDD is larger than any gamma reference voltage.

For example, as shown in fig. 4, assuming that at time t1, the polarity control signal pol (t) transitions from a negative level to a positive level (i.e., the polarity control signal is a rising edge), and the voltage polarity of the output signal OUT is a positive gamma voltage GAM1, the source driving circuit may increase the voltage value thereof from GAM1 to the first target voltage GAM 11.

And 104, if the voltage of the output signal is the gamma reference voltage with the negative polarity, reducing the voltage of the output signal. Step 106 is performed.

When the voltage of the output signal is the gamma reference voltage of the negative polarity, in order to improve the charging efficiency and reduce the charging time period, the voltage of the output signal may be reduced from the gamma reference voltage of the negative polarity GAM2 to the second target voltage GAM 22. When the voltage polarity of the output signal is negative, the voltage value is reduced, namely the absolute value of the voltage is improved, so that the charging efficiency can be improved, and the charging time length is reduced.

In the embodiment of the present invention, the adjusted second target voltage GAM22 may satisfy:

GAM22 is GAM2+1/2(GND + GAM2), where GND is the ground voltage, and the voltage value of GND may be 0, for example.

For example, as shown in fig. 4, assuming that at time t2, the polarity control signal pol (t) transitions from a positive level to a negative level (i.e., the polarity control signal is a falling edge), and the voltage polarity of the output signal OUT is the gamma voltage GAM2 with a negative polarity, the source driving circuit may decrease the voltage value thereof from GAM2 to the second target voltage GAM 22.

Step 105, after the first period of time, restoring the voltage of the output signal to the positive gamma reference voltage.

In the embodiment of the present invention, referring to fig. 1, during the scanning process of each frame, the gate driving circuit 30 generally scans the display panel 10 from the end far away from the source driving circuit 40 along the direction close to the source driving circuit 40 (for example, the X direction in fig. 1). That is, the source driving circuit 40 charges the pixel units at the far end first during each frame scanning process. Since the impedance of the line is large when charging the remote pixel unit, the absolute value of the charging voltage can be increased first. After the first period of time has elapsed, when the gate driving circuit 30 scans the near-end pixel cell, since the impedance when the near-end pixel cell is charged is small, the voltage of the output signal can be restored to the original positive polarity gamma reference voltage to reduce the driving power consumption.

For example, as shown in fig. 4, after the source driving circuit increases the voltage of the output signal to the first target voltage GAM11, the voltage thereof may be restored to the original positive gamma reference voltage GAM1 after the first time period t1' has elapsed.

And 106, after the second time period, restoring the voltage of the output signal to the gamma reference voltage with the negative polarity.

Accordingly, in order to reduce power consumption, the source driving circuit may restore the voltage of the output signal to the original negative gamma reference voltage after a second period of time after adjusting the voltage to the second target voltage.

For example, as shown in fig. 4, after the source driving circuit reduces the voltage of the output signal to the second target voltage GAM22, the voltage thereof may be restored to the original gamma reference voltage GAM2 of negative polarity after the second time period t2' has elapsed.

It should be noted that, as can also be seen from fig. 4, the first time period and the second time period are both less than the duration of the polarity control signal being maintained at any level in each cycle. Since the level of the polarity control signal pol (t) is transited once every other frame, and the duration of keeping the low level and the high level equal is the duration of one frame, the first period and the second period may be equal in the embodiment of the present invention.

It should be noted that, in practical applications, the gate driving circuit 30 may also start scanning the display panel 10 from the end close to the source driving circuit 40 (for example, scanning in the direction opposite to X in fig. 1). For the case that the gate driving circuit 30 scans from the near end to the far end, the source driving circuit 40 may start timing after the level of the polarity control signal jumps, and after a preset time period (the preset time period should be less than the duration of any level maintained by the polarity control signal in each period) elapses, because the gate driving circuit 30 scans the far end pixel unit, the impedance when charging the far end pixel unit is large, and therefore if the voltage polarity of the output signal is positive, the source driving circuit 40 may increase the voltage of the output signal; if the voltage polarity of the output signal is negative, the source driver circuit 40 can reduce the voltage of the output signal, thereby effectively improving the charging efficiency. When the level of the polarity control signal jumps again, the source driving circuit 40 may restore the voltage of the output signal and restart the timing.

It should be noted that, the order of the steps of the voltage control method for the output signal of the source driving circuit provided in the embodiment of the present invention may be appropriately adjusted. Any method that can be easily conceived by those skilled in the art within the technical scope of the present disclosure is covered by the protection scope of the present disclosure, and thus, the detailed description thereof is omitted.

In summary, the embodiments of the present invention provide a voltage control method for an output signal of a source driving circuit, where the source driving circuit starts to charge each pixel unit in a display panel when a level of a polarity control signal jumps, and if a voltage polarity of the output signal is positive, the source driving circuit can increase a voltage of the output signal, so as to improve a charging efficiency and reduce a charging duration; if the voltage polarity of the output signal is negative at this time, the source driving circuit can reduce the voltage of the output signal, so that the absolute value of the voltage of the output signal can be improved, the charging efficiency can be improved, and the charging time can be shortened.

Fig. 5 is a schematic structural diagram of a source driving circuit according to an embodiment of the present invention, and referring to fig. 5, the source driving circuit 40 may include: a detection module 401 and an output module 402.

The input end of the detection module 401 is connected to the timing controller 20, the output end is connected to the output module 402, and the detection module 401 is configured to detect whether a level of a polarity control signal sent by the timing controller 20 jumps.

The output module 402 is configured to: when the level of the polarity control signal jumps, if the voltage of the output signal is a gamma reference voltage with positive polarity, the voltage of the output signal is increased; when the level of the polarity control signal jumps, if the voltage of the output signal is a gamma reference voltage with negative polarity, the voltage of the output signal is reduced.

With continued reference to FIG. 5, the detection module 401 may include at least one logic gate (not shown in FIG. 5); the output module 402 may include: a control submodule 4021, a first output submodule 4022, and a second output submodule 4023.

The at least one logic gate is configured to output an indication signal at a first level to the control sub-module 4021 when a level of the polarity control signal transitions, and output an indication signal at a second level to the control sub-module 4021 when the level of the polarity control signal does not transition. The first level may be a high level relative to the second level.

The control sub-module 4021 is configured to start the first output sub-module 4022 when the indication signal is at a second level, and a voltage of an output signal output by the first output sub-module 4022 is a gamma reference voltage.

The control sub-module 4021 is further configured to start the second output sub-module 4023 when the indication signal is at a first level, and the second output sub-module 4023 is configured to increase the voltage of the output signal when the voltage of the output signal is a positive gamma reference voltage; and reducing the voltage of the output signal when the voltage of the output signal is a negative gamma reference voltage.

Specifically, when the voltage of the output signal is the positive gamma reference voltage, the second output submodule 4023 may increase the voltage of the output signal from the positive gamma reference voltage GAM1 to the first target voltage GAM11, and the first target voltage GAM11 may satisfy:

When the voltage of the output signal is the negative gamma reference voltage, the second output sub-module 4023 may decrease the voltage of the output signal from the negative gamma reference voltage GAM2 to a second target voltage GAM22, where the second target voltage GAM22 may satisfy:

GAM22 is GAM2+1/2(GND + GAM2), where GND is ground voltage.

Fig. 6 is a schematic structural diagram of a detection module according to an embodiment of the present invention, and referring to fig. 6, at least one logic gate in the detection module 401 may include: an or gate R1, a nand gate R2, a first and gate R3, and a second and gate R4.

Two input ends of the or gate R1 and two input ends a and B of the nand gate R2 are respectively connected to a timing controller.

The or gate R1 has a first input terminal a for receiving a polarity control signal POL (t), a second input terminal B for receiving a delay signal POL (t-1) of the polarity control signal POL, and an output terminal of the or gate R1 connected to the first input terminal of the first and gate R3.

The nand gate R2 has a first input terminal a for receiving the polarity control signal POL (t), a second input terminal B for receiving the delay signal POL (t-1) of the polarity control signal POL, and an output terminal of the nand gate R2 connected to the second input terminal of the first and gate R3.

In the embodiment of the present invention, a latch may be provided in the timing controller, and the delayed signal POL (t-1) of the polarity control signal may be output after the timing controller latches the output polarity control signal POL (t) through the latch.

The output terminal of the first and gate R3 is connected to the first input terminal of the second and gate R4, the second input terminal C of the second and gate R4 is connected to the reference level, and the output terminal O of the second and gate R4 is connected to the control submodule 4021, and is configured to output an indication signal to the control submodule 4021.

As can be seen from fig. 6, the detection module 401 may include a total of three inputs: A. b and C, wherein the reference level to which the input terminal C is connected may be the first level. The truth table for the three inputs and outputs O can be shown in table 1:

TABLE 1

A	B	C	O
					0	0	0	0
0	0	1	0
				0	1	0	0
0	1	1	1
				1	0	0	0
1	0	1	1
				1	1	0	0
1	1	1	0

In table 1, 0 indicates low level and 1 indicates high level. As can be seen from table 1, when the levels of the input terminal a and the input terminal B are opposite and the reference level connected to the input terminal C is a high level, the output terminal O outputs a high level. That is, when the level of the polarity control signal is opposite to the level of the delay signal thereof (i.e., the level transition of the polarity control signal), the detection module 401 may output the indication signal at the first level; otherwise, the detection module 401 outputs the indication signal at the second level.

For example, referring to fig. 4, at time t1, the polarity control signal POL (t) is at a high level, the delayed signal POL (t-1) of the polarity control signal is at a low level, the levels of the two are opposite, and the voltage of the output signal is the positive gamma reference voltage GAM1, so that the source driving circuit may further increase the voltage of the output signal; at time t2, the polarity control signal POL (t) is at a low level, the delay signal POL (t-1) of the polarity control signal is at a high level, the levels of the two are opposite, and the voltage of the output signal is the gamma reference voltage GAM2 of negative polarity, so that the source driver circuit can further reduce the voltage of the output signal.

Fig. 7 is a schematic diagram of a corresponding relationship among voltages of a control signal, an indication signal and an output signal according to an embodiment of the present invention. In the embodiment of the present invention, the source driving circuit may be further configured with an offset voltage output terminal V ' in advance, and when the voltage of the output signal is the positive gamma reference voltage GAM1, the output offset voltage V ' may be a positive voltage, for example, the offset voltage V ' may satisfy: v' ═ 1/2(AVDD-GAM 1); when the voltage of the output signal is the gamma reference voltage GAM2 with negative polarity, the output offset voltage V' may be a negative voltage, for example, which may satisfy: v' ═ 1/2(GND + GAM 2).

As can be seen from fig. 7, when the indication signal output by the output terminal O of the detection module 401 is at the first level (i.e., O is 1), the offset voltage output terminal V 'is gated, and the voltage of the output signal OUT of the source driving circuit is the sum of the gamma reference voltage and the offset voltage V'. For example, in fig. 7, the gamma reference voltage of the output signal is gam1, and the voltage of the adjusted output signal OUT may be: gam1+ V ═ gam1+1/2(AVDD-gam 1).

When the indication signal output by the output terminal O of the detection module 401 is at the second level (i.e., O is 0), the offset voltage output terminal V' is turned off, and the voltage of the output signal OUT of the source driving circuit is the gamma reference voltage.

In summary, the embodiments of the present invention provide a source driving circuit, when a level of a polarity control signal jumps, the source driving circuit starts to charge each pixel unit in a display panel, and if a voltage polarity of an output signal is positive, the source driving circuit can increase a voltage of the output signal, so as to improve a charging efficiency and reduce a charging duration; if the voltage polarity of the output signal is negative at this time, the source driving circuit can reduce the voltage of the output signal, so that the absolute value of the voltage of the output signal can be improved, the charging efficiency can be improved, and the charging time can be shortened.

Referring to fig. 1, an embodiment of the present invention provides a display device, which may include a source driving circuit as shown in fig. 5, and the source driving circuit may include a detection module as shown in fig. 6. The display device may be: the display device comprises any product or component with a display function, such as a liquid crystal panel, electronic paper, an OLED panel, an AMOLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the circuits and the modules described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims

1. A voltage control method of an output signal of a source driving circuit is applied to the source driving circuit, and the method comprises the following steps:

if the pixel units are sequentially charged from one end far away from the source electrode driving circuit to one end close to the source electrode driving circuit, when the level of the polarity control signal jumps to perform scanning of a new frame, if the voltage of the output signal is a gamma reference voltage with positive polarity, the voltage of the output signal is increased;

and if the pixel units are sequentially charged from one end far away from the source electrode driving circuit to one end close to the source electrode driving circuit, when the level of the polarity control signal jumps to perform scanning of a new frame, if the voltage of the output signal is a gamma reference voltage with negative polarity, the voltage of the output signal is reduced.

2. The method of claim 1, wherein after increasing the voltage of the output signal, the method further comprises:

after reducing the voltage of the output signal, the method further comprises:

3. The method of claim 1 or 2, wherein increasing the voltage of the output signal if the voltage of the output signal is a positive gamma reference voltage comprises:

4. The method according to claim 1 or 2, wherein the reducing the voltage of the output signal if the voltage of the output signal is a negative gamma reference voltage comprises:

GAM22 is GAM2+1/2(GND + GAM2), where GND is ground voltage.

5. The method of claim 1, further comprising:

if the pixel units are sequentially charged from one end close to the source electrode driving circuit to one end far away from the source electrode driving circuit, after the level of the polarity control signal jumps and a preset time period elapses, if the voltage of the output signal is a positive gamma reference voltage, the voltage of the output signal is increased, and if the voltage of the output signal is a negative gamma reference voltage, the voltage of the output signal is decreased; the preset time period is less than the duration of the polarity control signal keeping any level in each period.

6. A source driving circuit, comprising: the device comprises a detection module and an output module;

the output module is used for: if the pixel units are sequentially charged from one end far away from the source electrode driving circuit to one end close to the source electrode driving circuit, when the level of the polarity control signal jumps to perform scanning of a new frame, if the voltage of the output signal is a gamma reference voltage with positive polarity, the voltage of the output signal is increased; and if the pixel units are sequentially charged from one end far away from the source electrode driving circuit to one end close to the source electrode driving circuit, when the level of the polarity control signal jumps to perform scanning of a new frame, if the voltage of the output signal is a gamma reference voltage with negative polarity, the voltage of the output signal is reduced.

7. The source driver circuit of claim 6, wherein the detection module comprises: at least one logic gate; the output module includes: the control submodule, the first output submodule and the second output submodule;

8. The source driver circuit of claim 7, wherein the at least one logic gate comprises: the first AND gate is connected with the first output end of the first output end;

9. The source driver circuit of any of claims 6 to 8, wherein increasing the voltage of the output signal if the voltage of the output signal is a positive polarity gamma reference voltage comprises:

10. The source driver circuit of any of claims 6 to 8, wherein the reducing the voltage of the output signal if the voltage of the output signal is a negative gamma reference voltage comprises:

GAM22 is GAM2+1/2(GND + GAM2), where GND is ground voltage.

11. A display device, characterized in that the display device comprises: a source driver circuit as claimed in any one of claims 6 to 10.