CN107134247A

CN107134247A - A kind of gate driving circuit

Info

Publication number: CN107134247A
Application number: CN201710407705.9A
Authority: CN
Inventors: 金慧俊
Original assignee: Shanghai AVIC Optoelectronics Co Ltd
Current assignee: Shanghai AVIC Optoelectronics Co Ltd
Priority date: 2017-06-02
Filing date: 2017-06-02
Publication date: 2017-09-05

Abstract

The embodiment of the invention discloses a kind of gate driving circuit, in the display stage, the low potential of first control module and the second control module in response to second voltage end, disconnect between control tertiary voltage end and the first output end, in the touch-control stage, the high potential of first control module and the second control module in response to second voltage end, control to connect between tertiary voltage end and the first output end, so as to by setting the first control module and the second control module in each scanning element, the first output end is set to maintain low potential using the first control module in the touch-control stage, the second output end is set to maintain low potential using the second control module simultaneously, Capacitance Coupled effect in touch-control display panel so as to weaken gate driving circuit application between each gate line and touch control electrode, improve touch control detection precision, and increased cabling is shorter, line width is smaller, take frame area smaller, be conducive to the realization of narrow frame.

Description

A kind of gate driving circuit

Technical field

The present invention relates to display actuation techniques field, more particularly to a kind of gate driving circuit.

Background technology

With the development of Display Technique, increasing display panel is integrated with touch controllable function, and its touch-control principle is divided into mutually Capacitance touching control technology and self-capacitance touch technology, wherein, the self-capacitance touch technology is due to compared to mutual capacitance touch technology One layer of touch control electrode is only needed, the lightening development of display panel is more suitable for.

Current self-capacitance touch-control display panel by the common electrode layer in the display panel by being divided into multiple public Electrode unit, by the way of timesharing drives, by the public electrode it is unit multiplexed be touch control electrode unit, further to reduce The thickness of the display panel, meanwhile, production efficiency is also improved, production cost is reduced.

Specifically, keeping it, it is necessary to the current potential of each gate line in touch-control display panel is dragged down in the touch control detection stage Low level, to weaken the effect of the Capacitance Coupled between each gate line and touch control electrode, improves touch control detection precision.In this regard, existing The gate driving circuit of touch-control display panel, generally using extra increase coordination electrode line to be electrically connected to, each gate line is corresponding to be swept The mode of the output end of unit is retouched, to realize that the touch control detection stage current potential of each gate line is dragged down, still, due to touch-control display surface In plate, the quantity of gate line is more so that the electricity of the corresponding scanning element of part of grid pole line is electrically connected in gate driving circuit Connection line length is longer, and width is larger, so as to cause the rim area area of touch-control display panel larger, is unfavorable for the reality of narrow frame It is existing.

The content of the invention

In order to solve the above technical problems, the embodiments of the invention provide a kind of gate driving circuit, including the grid to reduce The frame area of the touch-control display panel of pole drive circuit, so as to be conducive to the realization of narrow frame.

To solve the above problems, the embodiments of the invention provide following technical scheme：

A kind of gate driving circuit, the gate driving circuit includes n grade scanning elements, and the n grades of scanning element is the One-level scanning element is to n-th grade of scanning element, and n is the integer not less than 2；Wherein, include per one-level scanning element：First son is swept Retouch unit, the second sub- scanning element, first voltage end, second voltage end, tertiary voltage end；

Wherein, the described first sub- scanning element includes：First control end, the second control end, the first input module, on first Draw node, it is the first pull-up control module, the first pull-down node, the first drop-down control module, the first drop-down generation module, first defeated Go out module, the first output end, the first signal end, the first clock signal terminal, the first control module；

The second sub- scanning element includes：3rd control end, the 4th control end, the second input module, the second pull-up section Point, the second pull-up control module, the second pull-down node, the second drop-down control module, the second drop-down generation module, the second output mould Block, the second output end, secondary signal end, second clock signal end, the second control module；

Wherein, first input module and controls the first voltage end in response to the current potential of first control end With the on-state between first pull-up node, and control the tertiary voltage end respectively with first pull-down node With the on-state of second pull-down node, and in response to the current potential of the second control end, and second voltage end and institute are controlled The on-state of the first pull-up node is stated, wherein, the level at the first voltage end and the second voltage end is opposite；

Described first pulls up current potential of the control module in response to first pull-up node, and controls the tertiary voltage end Respectively with the on-state of first pull-down node, the first drop-down generation module and the second drop-down generation module；

Described first pulls down current potential of the control module in response to first pull-down node, and controls the tertiary voltage end Respectively with first pull-up node, first output module, first output end, second pull-up node, described The on-state of second output module, second output end；

It is described first drop-down generation module in response to first signal end current potential, and control first signal end with The on-state of first pull-down node, wherein, in the described first pull-up control module in response to first pull-up node Current potential, and control the tertiary voltage end respectively with first pull-down node, the first drop-down generation module and described the When two drop-down generation modules are connected, the current potential of first pull-down node and the second pull-down node is the electricity at the tertiary voltage end Position；

First output module and controls first clock signal terminal in response to the current potential of first pull-up node With the on-state of first output end；

First control module in response to the second voltage end current potential, and control the tertiary voltage end with it is described The on-state of first output end；

Second input module in response to the 3rd control end current potential, and control the first voltage end with it is described The on-state of second pull-up node, and in response to the current potential of the 4th control end, and control second voltage end and described second The on-state of pull-up node；

Described second pulls up current potential of the control module in response to second pull-up node, and controls the tertiary voltage end Respectively with the on-state of second pull-down node, the second drop-down generation module and the first drop-down generation module；

Described second pulls down current potential of the control module in response to second pull-down node, and controls the tertiary voltage end Respectively with second pull-up node, second output module, second output end, first pull-up node, described The on-state of first output module, first output end；

It is described second drop-down generation module in response to the secondary signal end current potential, and control the secondary signal end with The on-state of second pull-down node, wherein, in the described second pull-up control module in response to second pull-up node Current potential, and control the tertiary voltage end respectively with second pull-down node, the second drop-down generation module and described When first drop-down generation module is connected, the current potential of second pull-down node and the first pull-down node is the tertiary voltage end Current potential；

Second output module and controls the second clock signal end in response to the current potential of second pull-up node With the on-state of second output end；

Second control module in response to the second voltage end current potential, and control the tertiary voltage end with it is described The on-state of second output end；

Wherein, in the display stage, first control module is controlled described in response to the low potential at the second voltage end Disconnect between tertiary voltage end and first output end, in the touch-control stage, first control module is in response to described The high potential of two voltage ends, controls to connect between the tertiary voltage end and first output end；

In the display stage, second control module is in response to the low potential at the second voltage end, control the described 3rd Disconnect between voltage end and second output end, in the touch-control stage, second control module is in response to the described second electricity The high potential of pressure side, controls to connect between the tertiary voltage end and second output end.

It is preferred that, the tertiary voltage end includes the first sub- voltage end and the second sub- voltage end, wherein, the second son electricity The voltage of pressure side is less than or equal to the voltage of the described first sub- voltage end.

It is preferred that in first control module includes：27th transistor, the grid of the 27th transistor The second voltage end is electrically connected to, first end is electrically connected to the described first sub- voltage end, and the second end is electrically connected to described first Output end；

Second control module includes：28th transistor, the grid of the 28th transistor is electrically connected to The second voltage end, first end electrically connects the first sub- voltage end, and the second end is electrically connected to second output end.

It is preferred that, the first drop-down control module includes：5th transistor, the 6th transistor, the 14th transistor and 16th transistor；

The grid of 5th transistor is electrically connected to first pull-down node, and first end is electrically connected to second son Voltage end, the second end is electrically connected to first pull-up node；

The grid of 6th transistor is electrically connected to first pull-down node, and first end is electrically connected to first son Voltage end, the second end is electrically connected to first output end；

The grid of 14th transistor is electrically connected to first pull-down node, and first end is electrically connected to described first Sub- voltage end, the second end is electrically connected to second output end；

The grid of 16th transistor is electrically connected to first pull-down node, and first end is electrically connected to described second Sub- voltage end, the second end is electrically connected to second pull-up node；

The second drop-down control module includes：7th transistor, the 8th transistor, the 17th transistor and the 18th are brilliant Body pipe；

The grid of 7th transistor is electrically connected to second pull-down node, and first end is electrically connected to second son Voltage end, the second end is electrically connected to first pull-up node；

The grid of 8th transistor is electrically connected to second pull-down node, and first end is electrically connected to first son Voltage end, the second end is electrically connected to first output end；

The grid of 17th transistor is electrically connected to second pull-down node, and first end is electrically connected to described first Sub- voltage end, the second end is electrically connected to second output end；

The grid of 18th transistor is electrically connected to second pull-down node, and first end is electrically connected to described second Sub- voltage end, the second end is electrically connected to second pull-up node.

It is preferred that, the first sub- scanning element also includes：First cascade output end and the first cascade output module；

The first cascade output module controls first clock to believe in response to the current potential of first pull-up node Number end with described first cascade output end on-state；

And, the second sub- scanning element also includes：Second cascade output end and the second cascade output module；

Described second cascades current potential of the output module in response to second pull-up node, and controls the second clock to believe Number end with described second cascade output end on-state.

It is preferred that, the first drop-down control module also includes：31st transistor and the 35th transistor；

The grid of 31st transistor is electrically connected to first pull-down node, and first end is electrically connected to described Two sub- voltage ends, the second end is electrically connected to the first cascade output end；

The grid of 35th transistor is electrically connected to first pull-down node, and first end is electrically connected to described Two sub- voltage ends, the second end is electrically connected to the second cascade output end；

The second drop-down control module also includes：30th two-transistor and the 34th transistor；

The grid of 30th two-transistor is electrically connected to second pull-down node, and first end is electrically connected to described Two sub- voltage ends, the second end is electrically connected to the first cascade output end；

The grid of 35th transistor is electrically connected to second pull-down node, and first end is electrically connected to described Two sub- voltage ends, the second end is electrically connected to the second cascade output end.

It is preferred that, the first cascade output module includes the 33rd transistor, the grid of the 33rd transistor Pole is electrically connected to first pull-up node, and the first end of the 33rd transistor is electrically connected to first clock signal End, the second end is electrically connected to the first cascade output end；

The second cascade output module includes the 36th transistor, and the grid of the 36th transistor is electrically connected To second pull-up node, the first end of the 36th transistor is electrically connected to the second clock signal end, second End is electrically connected to the second cascade output end.

It is preferred that, described also to include reset signal end per one-level scanning element, the first sub- scanning element also includes the Three control modules, the second sub- scanning element also includes the 4th control module；

3rd control module and controls the described second sub- voltage end and institute in response to the current potential at the reset signal end State the on-state of the first pull-up node；

4th control module and controls the described second sub- voltage end and institute in response to the current potential at the reset signal end State the on-state of the second pull-up node.

It is preferred that, the 3rd control module includes the 29th transistor, the grid electricity of the 29th transistor The reset signal end is connected to, the first end of the 29th transistor is electrically connected to the described second sub- voltage end, second End is electrically connected to first pull-up node；

And, the 4th control module includes the 30th transistor, and the grid of the 30th transistor is electrically connected to The reset signal end, the first end of the 30th transistor is electrically connected to the described second sub- voltage end, the electrical connection of the second end To second pull-up node.

It is preferred that, first input module includes the first transistor, second transistor, third transistor and the 23rd Transistor；

The grid of the first transistor is electrically connected to first control end, and the first end of the first transistor is electrically connected The first voltage end is connected to, the second end is electrically connected to first pull-up node；

The grid of the second transistor is electrically connected to second control end, the second transistor first end electrical connection To the second voltage end, the second end is electrically connected to first pull-up node；

The grid of the third transistor is electrically connected to first control end, and the first end of the third transistor is electrically connected The described second sub- voltage end is connected to, the second end is electrically connected to first pull-down node；

The grid of 23rd transistor is electrically connected to first control end, the of the 23rd transistor One end is electrically connected to the described second sub- voltage end, and the second end is electrically connected to second pull-down node；

And, second input module includes the 25th transistor and the 26th transistor；

The grid of 25th transistor is electrically connected to the 3rd control end, the 25th transistor first Voltage end, the second end is electrically connected to second pull-up node；

The grid of 26th transistor is electrically connected to the 4th control end, the 26th transistor First end is electrically connected to the second voltage end, and the second end is electrically connected to second pull-up node.

It is preferred that, the first pull-up control module includes：4th transistor, the 13rd transistor and the 22nd crystal Pipe；

The grid of 4th transistor is electrically connected to first pull-up node, the first end electricity of the 4th transistor The described second sub- voltage end is connected to, the second end is electrically connected to first pull-down node；

The grid of 13rd transistor is electrically connected to first pull-up node, the first of the 13rd transistor End is electrically connected to the described second sub- voltage end, and the second end is electrically connected to the first drop-down generation module；

The grid of 20th two-transistor is electrically connected to first pull-up node, the 20th two-transistor First end is electrically connected to the described second sub- voltage end, and the second end is electrically connected to the second drop-down generation module；

And, the second pull-up control module includes：Tenth two-transistor, the 20th transistor and the 21st crystal Pipe；

The grid of tenth two-transistor is electrically connected to second pull-up node, the first of the tenth two-transistor End is electrically connected to the described second sub- voltage end, and the second end is electrically connected to first time generation module；

The grid of 20th transistor is electrically connected to second pull-up node, the first of the 20th transistor End is electrically connected to the described second sub- voltage end, and the second end is electrically connected to the second drop-down generation module；

The grid of 21st transistor is electrically connected to second pull-up node, the 21st transistor First end is electrically connected to the described second sub- voltage end, and the second end is electrically connected to second pull-down node.

It is preferred that, the first drop-down generation module includes：Tenth transistor and the 11st transistor；

The grid and first end of tenth transistor are electrically connected to first signal end, the tenth transistor Second end is electrically connected to the second end of the tenth two-transistor and the second end of the 13rd transistor simultaneously；

The grid of 11st transistor is electrically connected to the second end of the tenth transistor, and first end electrical connection is described First signal end, the second end electrically connects first pull-down node；

And, the second drop-down generation module includes：24th transistor and the 19th transistor；

The grid and first end of 24th transistor are electrically connected to the secondary signal end, the described 24th Second end of transistor be electrically connected to simultaneously the 20th two-transistor the second end and the 20th transistor second End；

The grid of 19th transistor is electrically connected to the second end of the 24th transistor, first end electrical connection The secondary signal end, the second end electrically connects second pull-down node.

It is preferred that, the breadth length ratio of the 13rd transistor and the tenth two-transistor is all higher than the width of the tenth transistor Long ratio, the breadth length ratio of the 20th transistor and the 20th two-transistor is more than the breadth length ratio of the 24th transistor.

It is preferred that, first output module includes the 9th transistor and the first bootstrap capacitor, second output module Including the 15th transistor and the second bootstrap capacitor；

The grid of 9th transistor and the first pole plate of first bootstrap capacitor are electrically connected on described first Node is drawn, the first end of the 9th transistor is electrically connected to first clock signal terminal, the second of the 9th transistor Second pole plate of end and first bootstrap capacitor is electrically connected to first output end；

The grid of 15th transistor and the first pole plate of second bootstrap capacitor are electrically connected to described second Pull-up node, the first end of the 15th transistor is electrically connected to the second clock signal end, the 15th transistor The second end and the second pole plate of second bootstrap capacitor be electrically connected to second output end.

It is preferred that, it is i-stage scanning element and i+1 level scanning element to define scanning element described in adjacent two-stage, and i is not Positive integer more than n；

First output end of the i-stage scanning element is connected with the first control end of i+1 level scanning element, institute The first output end for stating i+1 level scanning element is connected with the second control end of the i-stage scanning element；

Second output end of the i-stage scanning element is connected with the 3rd control end of i+1 level scanning element, institute The second output end for stating i+1 level scanning element is connected with the 4th control end of the i-stage scanning element；

And, the first clock signal terminal of scanning element described in odd level is same signal end and second clock signal end For same signal end, the first clock signal terminal of scanning element described in even level is same signal end and second clock signal end For same signal end.

It is preferred that, when the described first sub- scanning element also includes the first cascade output end, the second sub- scanning element also includes During the second cascade output end, the first cascade output end of the i-stage scanning element and the first of i+1 level scanning element Control end is connected, the second control end of the first cascade output end and the i-stage scanning element of the i+1 level scanning element It is connected；Second cascade output end of the i-stage scanning element is connected with the 3rd control end of i+1 level scanning element, Second cascade output end of the i+1 level scanning element is connected with the 4th control end of the i-stage scanning element.

The invention also discloses a kind of gate driving circuit, the gate driving circuit includes n grades of scanning elements, the n Level scanning element is first order scanning element to n-th grade of scanning element, and n is the integer not less than 2；Wherein, scanned per one-level single Member includes：First sub- scanning element, the second sub- scanning element, first voltage end, second voltage end, tertiary voltage end, control section Point；

The first sub- scanning element includes：First control end, the second control end, the first input module, the first pull-up section Point, the first pull-up control module, the first pull-down node, the first drop-down control module, the first drop-down generation module, the first output mould Block, the first output end, the first signal end, the first clock signal terminal, the first control module, the 5th control module；

The second sub- scanning element includes：3rd control end, the 4th control end, the second input module, the second pull-up section Point, the second pull-up control module, the second pull-down node, the second drop-down control module, the second drop-down generation module, the second output mould Block, the second output end, secondary signal end, second clock signal end, the second control module, the 6th control module；

Wherein, first input module and controls the first voltage end in response to the current potential of first control end With the on-state between first pull-up node, and the control first voltage end and the connection shape of the control node State, and in response to the current potential of the second control end, and the on-state at second voltage end and first pull-up node is controlled, its In, the level at the first voltage end and the second voltage end is opposite；

Described first pulls down current potential of the control module in response to first pull-down node, and controls the tertiary voltage end Respectively with the control node, first pull-up node, first output module, first output end, described second Pull-up node, second output module, the on-state of second output end；

5th control module and controls the tertiary voltage end and described the in response to the current potential of the control node The on-state of one pull-down node；

Second input module in response to the 3rd control end current potential, and control the first voltage end with it is described The on-state of second pull-up node, and in response to the current potential of the 4th control end, and control second voltage end and described second The on-state of pull-up node and the control node；

Described second pulls down current potential of the control module in response to second pull-down node, and controls the tertiary voltage end Respectively with the control node, the second pull-up node, second output module, second output end, first pull-up Node, first output module, the on-state of first output end；

6th control module and controls the tertiary voltage end and described the in response to the current potential of the control node The on-state of two pull-down nodes；

It is preferred that, first control module includes：27th transistor, the grid electricity of the 27th transistor The second voltage end is connected to, first end is electrically connected to the described first sub- voltage end, and it is defeated that the second end is electrically connected to described first Go out end；

It is preferred that, the 5th control module includes the 39th transistor, the grid electricity of the 39th transistor The control node is connected to, first end is electrically connected to the described second sub- voltage end, and the second end is electrically connected to first pull-up Node；

And, the 6th control module includes the 40th transistor, and the grid of the 40th transistor is electrically connected to The control node, first end is electrically connected to the described second sub- voltage end, and the second end is electrically connected to second pull-up node.

It is preferred that, the first drop-down control module includes：5th transistor, the 6th transistor, the 14th crystal Pipe, the 16th transistor and the 41st transistor；

The grid of 41st transistor is electrically connected to first pull-down node, and first end is electrically connected to described Two sub- voltage ends, the second end is electrically connected to the control node；

The second drop-down control module includes：7th transistor, the 8th transistor, the 17th transistor, the 18th crystalline substance Body pipe and the 40th two-transistor；

The grid of 18th transistor is electrically connected to second pull-down node, and first end is electrically connected to described second Sub- voltage end, the second end is electrically connected to second pull-up node；

The grid of 40th two-transistor is electrically connected to second pull-down node, and first end is electrically connected to described Two sub- voltage ends, the second end is electrically connected to the control node.

It is preferred that, the first sub- scanning element also includes the 7th control module, and the second sub- scanning element also includes 8th control module；

7th control module and controls the described second sub- voltage end and institute in response to the current potential of first output end State the on-state of control node；

8th control module and controls the described second sub- voltage end and institute in response to the current potential of second output end State the on-state of control node.

It is preferred that, the 7th control module includes the 43rd transistor, the grid electricity of the 43rd transistor First output end is connected to, first end is electrically connected to the described second sub- voltage end, and the second end is electrically connected to the control section Point；

And, the 8th control module includes the 44th transistor, and the grid of the 44th transistor is electrically connected Second output end is connected to, first end is electrically connected to the described second sub- voltage end, and the second end is electrically connected to the control node.

It is preferred that, first input module includes the first transistor, second transistor and the 37th transistor；

The grid of the first transistor is electrically connected to first control end, and first end is electrically connected to the first voltage End, the second end is electrically connected to first pull-up node；

The grid of the second transistor is electrically connected to second control end, and first end is electrically connected to the second voltage End, the second end is electrically connected to first pull-up node；

The grid of 37th transistor is electrically connected to first control end, and first end is electrically connected to described first Voltage end, the second end is electrically connected to the control node；

And, second input module includes the 25th transistor, the 26th transistor and the 38th crystal Pipe；

The grid of 25th transistor is electrically connected to the 3rd control end, and first voltage end, the second end is electrically connected It is connected to second pull-up node；

The grid of 26th transistor is electrically connected to the 4th control end, and first end is electrically connected to described second Voltage end, the second end is electrically connected to second pull-up node；

The grid of 38th transistor is electrically connected to the 4th control end, and first end is electrically connected to described second Voltage end, the second end is electrically connected to the control node.

The gate driving circuit that the embodiment of the present invention is provided, sets the first control module and second in each scanning element Control module, and the first control module and the second control module are both responsive to the current potential at second voltage end, in display stage, second Voltage end is to disconnect between low potential, therefore tertiary voltage end and the first output end and the second output end, normal to realize Display function.

But in the touch-control stage, second voltage end is high potential, the first control module and the second control module, is both responsive to this The high potential at second voltage end, controls tertiary voltage end to be connected with the first output end and the second output end respectively, i.e., by the 3rd electricity The low potential of pressure side is passed to, so that the first output end and the second output end maintain low potential, so as to weaken the raster data model Capacitance Coupled effect in the touch-control display panel of circuit application between each gate line and touch control electrode, improves touch control detection essence Degree；And increased circuit is simple, and cabling is shorter, and line width is smaller, occupancy frame area is smaller, is conducive to the reality of narrow frame It is existing.

Brief description of the drawings

In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing There is the accompanying drawing used required in technology description to be briefly described, it should be apparent that, drawings in the following description are only this Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with Other accompanying drawings are obtained according to these accompanying drawings.

The structural representation of scanning element in the gate driving circuit that Fig. 1 is provided by one embodiment of the invention；

The sequential of second voltage end input signal in the gate driving circuit that Fig. 2 is provided by one embodiment of the invention Figure；

Fig. 3 is a kind of concrete structure schematic diagram of scanning element in gate driving circuit shown in Fig. 1；

Fig. 4 is the leakage current Ids of a thin film transistor (TFT) with the change curve of the voltage difference Vgs between its grid and drain electrode Schematic diagram；

The structural representation of scanning element in the gate driving circuit that Fig. 5 is provided for another embodiment of the invention；

Fig. 6 is a kind of concrete structure schematic diagram of scanning element in gate driving circuit shown in Fig. 5；

The structural representation of scanning element in the gate driving circuit that Fig. 7 is provided for another embodiment of the invention；

Fig. 8 is a kind of concrete structure schematic diagram of scanning element in gate driving circuit shown in Fig. 7；

The structural representation of scanning element in the gate driving circuit that Fig. 9 is provided for another embodiment of the invention；

The structural representation of each scanning element cascade in the gate driving circuit that Figure 10 is provided by one embodiment of the invention Figure；

The structure of each scanning element cascade is shown in the gate driving circuit that Figure 11 is provided by another embodiment of the present invention It is intended to；

The structural representation of scanning element in the gate driving circuit that Figure 12 is provided for another embodiment of the invention；

Figure 13 is a kind of concrete structure schematic diagram of scanning element in gate driving circuit shown in Figure 12；

The structural representation of scanning element in the gate driving circuit that Figure 14 is provided for further embodiment of the present invention；

The structural representation of scanning element in the gate driving circuit that Figure 15 is provided for another embodiment of the invention；

The structural representation of scanning element in the gate driving circuit that Figure 16 is provided for further embodiment of the present invention；

Figure 17 is a kind of concrete structure schematic diagram of scanning element in gate driving circuit shown in Figure 16.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made Embodiment, belongs to the scope of protection of the invention.

Many details are elaborated in the following description to facilitate a thorough understanding of the present invention, still the present invention can be with It is different from other manner described here using other to implement, those skilled in the art can be without prejudice to intension of the present invention In the case of do similar popularization, therefore the present invention is not limited by following public specific embodiment.

The embodiments of the invention provide a kind of gate driving circuit, the gate driving circuit includes n grades of scanning elements, institute It is first order scanning element to n-th grade of scanning element to state n grades of scanning elements, and n is the integer not less than 2；As shown in figure 1, each Level scanning element includes：First sub- scanning element, the second sub- scanning element, first voltage end FW, second voltage end BW, the 3rd electricity Pressure side VGL；Wherein, the described first sub- scanning element includes：First control end SET1, the second control end RESET1, the first input Module 101, the first pull-up node P1, the first pull-up control module 102, the first pull-down node Q1, the first drop-down control module 103rd, the first drop-down generation module 104, the first output module 105, the first output end Gout1, the first signal end V1, the first clock Signal end CK1, the first control module 106；The second sub- scanning element includes：3rd control end SET2, the 4th control end RESET2, the second input module 201, the second pull-up node P2, the second pull-up control module 202, the second pull-down node Q2, second Pull down the drop-down of control module 203, second generation module 204, the second output module 205, the second output end Gout2, secondary signal Hold V2, second clock signal end CK2, the second control module 206.

In embodiments of the present invention, the first input module 101 and is controlled in response to the current potential of the first control end SET1 On-state between the first voltage end FW and the first pull-up node P1, and control the tertiary voltage end VGL difference With the first pull-down node Q1 and the second pull-down node Q2 on-state, and in response to the second control end RESET1 current potential, And control second voltage end BW and the first pull-up node P1 on-state.Wherein, first voltage end FW and second voltage end BW Level on the contrary, so that being connected between the first pull-up node P1 when first voltage end FW and second voltage end BW are different, That is when being connected between first voltage end FW and the first pull-up node P1, do not connect between second voltage end BW and the first pull-up node P1 It is logical, when being connected between second voltage end BW and the first pull-up node P1, between first voltage end FW and the first pull-up node P1 Disconnect, also, first voltage end FW and the first pull-up node P1 connection when and second voltage end BW and the first pull-up node P1 During connection, the first pull-up node P1 is varying level.

Below using first voltage end FW as high level, second voltage end BW is low level, and tertiary voltage end VGL is low level Exemplified by, the first sub- scanning element provided the embodiment of the present invention is described.

Specifically, when the first control end SET1 is high level, when the second control end RESET1 is low level, first voltage Connection between FW and the first pull-up node P1 is held, first voltage end FW signal is transmitted to the first pull-up node P1, by first Draw node P1 current potential to draw high, and connected between tertiary voltage end VGL and the first pull-down node Q1, tertiary voltage end VGL letter Number transmit to the first pull-down node Q1, the first pull-down node Q1 current potential is dragged down.When the first control end SET1 is low level, the Two control end RESET1 be high level when, between first voltage end FW and the first pull-up node P1 end, tertiary voltage end VGL with End between first pull-down node Q1, in the display stage, second voltage end BW low level signal is transmitted to the first pull-up node P1, the first pull-up node P1 current potential is dragged down.

Also, when the first control end SET1 signal is high level, tertiary voltage end VGL and the second pull-down node Q2 it Between connect, tertiary voltage end VGL signal transmits to the second pull-down node Q2, the second pull-down node Q2 current potential dragged down.When First control end SET1 is low level, when the second control end RESET1 is high level, tertiary voltage end VGL and the second pull-down node End between Q2.

Continue as shown in figure 1, the first pull-up control module 102 and controls the in response to the first pull-up node P1 current potential Three voltage end VGL give birth to the first pull-down node Q1, the first drop-down generation module 104 and second drop-down respectively Into the on-state of module 204.When the first pull-up node P1 is high level, the first pull-down node Q1 and tertiary voltage end VGL Between connect, tertiary voltage end VGL signal transmits to the first pull-down node Q1, the first pull-down node Q1 current potential dragged down； Connected between the drop-down generation modules 104 of tertiary voltage end VGL and first, control first pulls down the output of the no signal of generation module 104； Connected between the drop-down generation modules 204 of tertiary voltage end VGL and second, control second pulls down the output of the no signal of generation module 204. When the first pull-up node P1 is low level, do not controlled between the first pull-down node Q1 and tertiary voltage end VGL by the first pull-up Molding block 102 is connected, and the drop-downs of tertiary voltage end VGL and first generation module 104, the drop-downs of tertiary voltage end VGL and second are generated Also do not connected between module 204 by the first pull-up control module 102, the first 102 pair first of pull-up control module drop-down generation The signal output of the drop-down generation module 204 of module 104 and second does not play control action.

First pulls down current potential of the control module 103 in response to the first pull-down node Q1, and controls tertiary voltage end VGL to distinguish With the first pull-up node P1, the first output module 105, the first output end Gout1, the second pull-up node P2, the second output module 205th, the second output end Gout2 on-state.

Specifically, when the first pull-down node Q1 is high potential, tertiary voltage end VGL and the first pull-up node P1 are indirectly It is logical, tertiary voltage end VGL signal is transmitted to the first pull-up node P1, the first pull-up node P1 current potential dragged down, and ties up Low potential is held, and then makes and disconnecting between the first clock signal terminal CK1 and the first output module 105；And tertiary voltage end VGL distinguishes Connected between the first output module 105 and the first output end Gout1, tertiary voltage end VGL signal is transmitted to first defeated Go out and hold Gout1, and exported through the first output end Gout1；Connected between tertiary voltage end VGL and the second pull-up node P2, by the Three voltage end VGL signal is transmitted to the second pull-up node P2, the second pull-up node P2 current potential is dragged down, and maintain low electricity Position, and then make and disconnecting between second clock signal end CK2 and the second output module 205；And tertiary voltage end VGL is respectively with second Connected between the output end Gout2 of output module 205 and second, tertiary voltage end VGL signal is transmitted to the second output end Gout2, and exported through the second output end Gout2.

When the first pull-down node Q1 is low potential, not by the between tertiary voltage end VGL and the first pull-up node P1 One drop-down control module 103 is connected, and between tertiary voltage end VGL and the first output module 105 and the first output end Gout1 not Connected by the first drop-down control module 103；Meanwhile, do not pass through first between tertiary voltage end VGL and the second pull-up node P2 Drop-down control module 103 is connected, and obstructed between tertiary voltage end VGL and the second output module 205 and the second output end Gout2 The first drop-down control module 103 is crossed to connect.

When disconnecting between the drop-down generation modules 104 of tertiary voltage end VGL and first, the first drop-down generation module 104 In response to the first signal end V1 current potential, and control the first signal end V1 and the first pull-down node Q1 on-state.

In the first pull-up control module 102 in response to the first pull-up node P1 high potentials, and control tertiary voltage end VGL points When not connected with the first pull-down node Q1, the first drop-down drop-down generation module 204 of generation module 104 and second, the first drop-down section Point Q1 and the second pull-down node Q2 current potential are tertiary voltage end VGL current potential.

On the premise of disconnecting between the drop-down generation modules 104 of tertiary voltage end VGL and first, as the first signal end V1 When being connected between the first pull-down node Q1, the first signal end V1 signals exported are transmitted to the first pull-down node Q1, so that Control first pulls down the work of control module 103；When being connected between the drop-down generation modules 104 of tertiary voltage end VGL and first, First pulls down generation module 104, and in response to tertiary voltage end VGL signal, no signal is exported.

First output module 105 and controls the first clock signal terminal CK1 and the in response to the first pull-up node P1 current potential One output end Gout1 on-state.When the first pull-up node P1 is high level, during the first output module 105 control first Connected between clock signal end CK1 and the first output end Gout1, the first clock signal terminal CK1 signal is transmitted to the first output Gout1 is held, and is exported through the first output end Gout1.

First control module 106 in response to second voltage end BW current potential, and control tertiary voltage end VGL and first export Hold Gout1 on-state.

In embodiments of the present invention, as shown in Fig. 2 in the display stage, BW second voltages end BW perseverances in second voltage end are the One level signal H1, i.e., permanent is low potential, and the first control module 106 is in response to second voltage end BW low potential, control the 3rd Disconnect between voltage end VGL and the first output end Gout1, the setting to ensure the first control module 106 do not interfere with this Driving work of the one sub- scanning element in the display stage.In the touch-control stage, second voltage end BW is adjusted to second electrical level signal H2, That is second voltage end BW is adjusted to high potential, and the first control module 106 is in response to second voltage end BW high potential, control the 3rd Connected between voltage end VGL and the first output end Gout1, tertiary voltage end VGL low potential is transmitted to the first output end Gout1, to continue to drag down the first output end Gout1 current potential, so that the touch-control display surface applied in the gate driving circuit In plate, the Capacitance Coupled weakened between each gate line and touch control electrode is acted on, and improves touch control detection precision.

It should be noted that touch control electrode can be multiplexed by the public electrode of display panel, common electrode layer is divided into multiple public affairs Common-battery pole unit, it is by the way of timesharing drives, the public electrode is unit multiplexed for touch control electrode unit.

As can be seen here, the gate driving circuit that the embodiment of the present invention is provided, sets first to control in each scanning element Module 106, makes the first output end Gout1 maintain low potential, increased circuit letter in the touch-control stage using the first control module 106 It is single, and cabling is shorter, line width is smaller, and occupancy frame area is smaller, is conducive to the realization of narrow frame.

Second sub- scanning element is similar with the structure of the first sub- scanning element, specifically, in the second sub- scanning element：

Second input module 201 and is controlled on first voltage end FW and second in response to the 3rd control end SET2 current potential The on-state between node P2 is drawn, and in response to the 4th control end RESET2 current potential, and control second voltage end BW and the On-state between two pull-up node P2.Wherein, when the 3rd control end SET2 and the 4th control end RESET2 signal is different For high level, so that when being connected between first voltage end FW and the second pull-up node P2, on second voltage end BW and second Draw and disconnect between node P2, when being connected between second voltage end BW and the second pull-up node P2, first voltage end FW and the Disconnect between one pull-up node P1, and first voltage end FW and second voltage end BW level signal on the contrary, so that During one voltage end FW and the second pull-up node P2 connections and when second voltage end BW and the second pull-up node P2 is connected, the second pull-up Node P2 is varying level；

Continue with using first voltage end FW as high level, second voltage end BW is low level, tertiary voltage end VGL is low Exemplified by level, the second sub- scanning element provided the embodiment of the present invention is described.

Specifically, when the 3rd control end SET2 is high level, and the 4th control end RESET2 is low level, first voltage end Connected between FW and the second pull-up node P2, first voltage end FW signal is transmitted to the second pull-up node P2, by the second pull-up Node P2 current potential is drawn high；When the 3rd control end SET2 is low level, and the 4th control end RESET2 is high level, second voltage Connection between BW and the second pull-up node P2 is held, in the display stage, second voltage end BW low level signal is transmitted on second Node P2 is drawn, the second pull-up node P2 current potential is dragged down.

Second pull-up control module 202 and controls tertiary voltage end VGL and the in response to the second pull-up node P2 current potential On-state between on-state between two pull-down node Q2, the drop-down generation modules 204 of tertiary voltage end VGL and second, And the on-state of the drop-down generation modules 104 of tertiary voltage end VGL and first.When the second pull-up node P2 signal is high electricity Usually, connected between tertiary voltage end VGL and the second pull-down node Q2, tertiary voltage end VGL signal is transmitted to the second drop-down Node Q2, the second pull-down node Q2 current potential is dragged down；Connected between the drop-down generation modules 204 of tertiary voltage end VGL and second, Tertiary voltage end VGL signal is transmitted to the second drop-down generation module 204, and the second drop-down generation module 204 is in response to the 3rd electricity Pressure side VGL signal and no signal is exported；Connected between the drop-down generation modules 104 of tertiary voltage end VGL and first, control first Pull down the output of the no signal of generation module 104.When the second pull-up node P2 is low level, the second pull-down node Q2 and tertiary voltage Do not connected between the VGL of end by the second pull-up control module 202, tertiary voltage end VGL pulls down generation module 104, the with first Also do not connected between the drop-down generation modules 204 of three voltage end VGL and second by the second pull-up control module 202, the second pull-up The signal output of 202 pair of first drop-down drop-down generation module 204 of generation module 104 and second of control module does not play control action.

Second pulls down current potential of the control module 203 in response to the second pull-down node Q2, and controls tertiary voltage end VGL to distinguish With the second pull-up node P2, the second output module 205, the second output end Gout2, the first pull-up node P1, the first output module 105th, the first output end Gout1 on-state.

Specifically, when the second pull-down node Q2 is high potential, tertiary voltage end VGL and the second pull-up node P2 are indirectly It is logical, tertiary voltage end VGL signal is transmitted to the second pull-up node P2, the second pull-up node P2 current potential dragged down, and ties up Low potential is held, and then makes and disconnecting between second clock signal end CK2 and the second output module 205；And tertiary voltage end VGL distinguishes Connected between the second output module 205 and the second output end Gout2, tertiary voltage end VGL signal is transmitted to second defeated Go out and hold Gout2, and exported through the second output end Gout2, to maintain the second output end Gout2 low potential；And tertiary voltage end Connected between VGL and the first pull-up node P1, tertiary voltage end VGL signal is transmitted to the first pull-up node P1, by first Pull-up node P1 current potential is dragged down, and maintains low potential, and then is made between the first clock signal terminal CK1 and the first output module 105 Disconnect；And tertiary voltage end VGL is connected between the first output module 105 and the first output end Gout1 respectively, by the 3rd electricity Pressure side VGL signal is transmitted to the first output end Gout1, and is exported through the first output end Gout1.

When the first pull-down node Q1 is low potential, not by the between tertiary voltage end VGL and the first pull-up node P1 Two drop-down control modules 203 are connected, and between tertiary voltage end VGL and the first output module 105 and the first output end Gout1 not Connected by the second drop-down control module 203；Meanwhile, do not pass through second between tertiary voltage end VGL and the second pull-up node P2 Drop-down control module 203 is connected, and obstructed between tertiary voltage end VGL and the second output module 205 and the second output end Gout2 The second drop-down control module 203 is crossed to connect.

When disconnecting between the drop-down generation modules 204 of tertiary voltage end VGL and second, the second drop-down generation module 204 In response to secondary signal end V2 current potential, and control secondary signal end V2 and the second pull-down node Q2 on-state.

In high potential of the second pull-up control module 202 in response to the second pull-up node P2, and control tertiary voltage end VGL When being connected respectively with the second pull-down node Q2, the second drop-down drop-down generation module 104 of generation module 204 and first, the first drop-down Node Q1 and the second pull-down node Q2 current potential are tertiary voltage end VGL current potential.

On the premise of disconnecting between the drop-down generation modules 204 of tertiary voltage end VGL and second, as secondary signal end V2 When being connected between the second pull-down node Q2, the V2 signals exported in secondary signal end are transmitted to the second pull-down node Q2, so that Control second pulls down the work of control module 204；When being connected between the drop-down generation modules 204 of tertiary voltage end VGL and second, Second pulls down generation module 204, and in response to tertiary voltage end VGL signal, no signal is exported.

Second output module 205 and controls second clock signal end CK2 and in response to the second pull-up node P2 current potential Two output end Gout2 on-state.When the second pull-up node P2 is high level, during the second output module 205 control second Connected between clock signal end CK2 and the second output end Gout2, second clock signal end CK2 signal is transmitted to the second output Gout2 is held, and is exported through the second output end Gout2.

Second control module 206 in response to second voltage end BW current potential, and control tertiary voltage end VGL and second export Hold Gout2 on-state.

In embodiments of the present invention, as shown in Fig. 2 in the display stage, BW perseverances in second voltage end are the first level signal H1, That is second voltage end BW perseverances are low potential, and the second control module 206 is in response to second voltage end BW low potential, the electricity of control the 3rd Disconnect between pressure side VGL and the second output end Gout2, the setting to ensure the second control module 206 do not interfere with this second Driving work of the sub- scanning element in the display stage.In the touch-control stage, second voltage end BW is adjusted to second electrical level signal H2, i.e., Second voltage end BW is adjusted to high potential in the touch-control stage, the second control module 206 in response to second voltage end BW high potential, Control to connect between tertiary voltage end VGL and the second output end Gout2, tertiary voltage end VGL low potential is transmitted to second Output end Gout2, to continue to drag down the second output end Gout2 current potential, so that the touch-control applied in the gate driving circuit In display panel, the Capacitance Coupled weakened between each gate line and touch control electrode is acted on, and improves touch control detection precision.

As can be seen here, the gate driving circuit that the embodiment of the present invention is provided, sets second to control in each scanning element Module 206, makes the second output end Gout2 maintain low potential, increased circuit letter in the touch-control stage using the second control module 206 It is single, and cabling is shorter, line width is smaller, and occupancy frame area is smaller, is conducive to the realization of narrow frame.

In embodiments of the present invention, when second voltage end BW is high potential, just into the touch control detection stage, that is to say, that When needing to carry out n times touch control detection within the time scanned in a frame display picture, it need to only be scanned in a frame display picture In time, second voltage end BW current potential is adjusted to high potential n times, wherein, N is the positive integer not less than 1.

It should be noted that connected with high potential in above-described embodiment, low potential disconnect exemplified by scanning element What operation principle was illustrated, but the present invention this is not limited, specifically depend on the circumstances.

On the basis of above-described embodiment, in one embodiment of the invention, tertiary voltage end VGL includes the first son electricity The sub- voltage end VGL2 of pressure side VGL1 and second, wherein, the second sub- voltage end VGL2 voltage is less than or equal to the first sub- voltage end VGL1 voltage.It should be noted that when the second sub- voltage end VGL2 voltage is equal to the first sub- voltage end VGL1 voltage, The second sub- sub- voltage end VGL1 of voltage end VGL2 and first can be merged into a voltage end.

As shown in figure 3, the concrete structure schematic diagram for the scanning element that Fig. 3 is provided by one embodiment of the invention, below Being specifically described for provided scanning element is provided with reference to Fig. 3 to the present invention.

With reference to Fig. 1 and Fig. 3, in embodiments of the present invention, the first input module 101 includes：The first transistor M1, the second crystalline substance Body pipe M2, third transistor M3 and the 23rd transistor M23.

The first transistor M1 grid electrically connects the first control end SET1, first end electrical connection first voltage end FW, and second The first pull-up node P1 of end electrical connection, when the first control end SET1 is high level, the first transistor M1 conductings, first voltage end FW signal is transmitted to the first pull-up node P1, and the first pull-up node P1 current potential is drawn high.

Second transistor M2 grid electrically connects the second control end RESET1, and first end is electrically connected to second voltage end BW, Second end is electrically connected to the first pull-up node P1, when the second control end RESET1 is high level, second transistor M2 conductings, Display stage, second voltage end BW signal is transmitted to the first pull-up node P1, and the first pull-up node P1 current potential is dragged down.

Third transistor M3 grid electrically connects the first control end SET1, and first end is electrically connected to the second sub- voltage end VGL2, the second end is electrically connected to the first pull-down node Q1, and when the first control end SET1 is high level, third transistor M3 is led Logical, the second sub- voltage end VGL2 voltage is transmitted to the first pull-down node Q1, and the first pull-down node Q1 current potential is dragged down.

23rd transistor M23 grid electrically connects the first control end SET1, and first end electrically connects the second sub- voltage end VGL2, the second end is electrically connected to the second pull-down node Q2, and when the first control end SET1 signal is high level, the 23rd is brilliant Body pipe M23 is turned on, and the second sub- voltage end VGL2 signal is transmitted to the second pull-down node Q2, by the second pull-down node Q2 current potential Drag down.

Second input module 201 includes：25th transistor M25 and the 26th transistor M26, wherein, the 20th Five transistor M25 grid electrically connects the 3rd control end SET2, and first end is electrically connected to first voltage end FW, the electrical connection of the second end To the second pull-up node P2, when the 3rd control end SET2 is high level, the 25th transistor M25 conductings, first voltage end FW signal is transmitted to the second pull-up node P2, and the second pull-up node P2 current potential is drawn high.26th transistor M26 grid Pole electrically connects the 4th control end RESET2, and first end is electrically connected to second voltage end BW, and the second end is electrically connected to the second pull-up section Point P2, when the 4th control end RESET2 is high level, the 26th transistor M26 conductings, second voltage end BW signal is passed The second pull-up node P2 is transported to, the second pull-up node P2 current potential is dragged down.

It should be noted that in embodiments of the present invention, each crystal in the first input module 101, the second input module 201 The conductivity type of pipe is identical, i.e. the first transistor M1, second transistor M2, third transistor M3, the 23rd transistor M23, 25th transistor M25 and the 26th transistor M26 conductivity type is identical, and the present invention with the first input module 101, Exemplified by each transistor is N-type transistor in second input module 201, its operation principle is illustrated.But the present invention is to this Do not limit, each transistor is also in other embodiments of the invention, in the first input module 101, the second input module 201 It can be P-type transistor, specifically depend on the circumstances.

For the ease of description, below to when each module is described in scanning element, each transistor is brilliant as N-type using in the module Illustrated exemplified by body pipe.

Continue as shown in figure 3, the first pull-up control module 102 includes the 4th transistor M4, the 13rd transistor M13 and the 20 two-transistor M22.

Wherein, the 4th transistor M4 grid is electrically connected to the first pull-up node P1, and first end electrically connects the second sub- voltage VGL2 is held, the second end electrically connects the first pull-down node Q1, when the first pull-up node P1 signal is high level, the 4th transistor M4 is turned on, and the second sub- voltage end VGL2 signal transmits to the first pull-down node Q1, the first pull-down node Q1 current potential is dragged down.

13rd transistor M13 grid electrically connects the first pull-up node P1, and first end electrically connects the second sub- voltage end VGL2, the second end is electrically connected to the first drop-down generation module 104, when the first pull-up node P1 signal is high level, and the tenth Three transistor M13 are turned on, and the second sub- voltage end VGL2 signal is transmitted to the first drop-down generation module 104, and control first is pulled down The no signal of generation module 104 is exported.

20th two-transistor M22 grid is electrically connected to the first pull-up node P1, and first end is electrically connected to the second son electricity Pressure side VGL2, the second end is electrically connected to the second drop-down generation module 204.When the first pull-up node P1 is high level, the second son Voltage end VGL2 signal is transmitted to the second drop-down generation module 204, and control second pulls down the output of the no signal of generation module 204.

When the first pull-up node P1 signal is low level, the 4th transistor M4, the 13rd transistor M13 and the 20th Two-transistor M22 ends, and is not connected between the second sub- voltage end VGL2 and the first pull-down node Q1 by the 4th transistor M4, the Do not connected between the drop-down generation modules 104 of two sub- voltage end VGL2 and first by the 13rd transistor M13, the second sub- voltage end Do not connected between the drop-down generation modules 204 of VGL2 and second by the 20th two-transistor M22.

Second pull-up control module 202 includes the tenth two-transistor M12, the 20th transistor M20 and the 21st crystal Pipe M21.

Wherein, the tenth two-transistor M12 grid electrically connects the second pull-up node P2, and first end is electrically connected to the second son electricity Pressure side VGL2, the second end is electrically connected to the first drop-down generation module 104, when the second pull-up node P2 signal is high level, Tenth two-transistor M12 is turned on, and is connected between the drop-down generation modules 104 of the second sub- voltage end VGL2 and first, under control first Draw the output of the no signal of generation module 104.

20th transistor M20 grid electrically connects the second pull-up node P2, and first end electrically connects the second sub- voltage end VGL2, the second end is electrically connected to the second drop-down generation module 204, when the second pull-up node P2 signal is high level, and second Ten transistor M20 are turned on, and the second sub- voltage end VGL2 signal is transmitted to the second drop-down generation module 204, and control second is pulled down The no signal of generation module 204 is exported.

21st transistor M21 grid electrically connects the second pull-up node P2, and first end electrically connects the second sub- voltage end VGL2, the second end electrically connects the second pull-down node Q2, when the second pull-up node P2 is high level, the 21st transistor M21 Conducting, the second sub- voltage end VGL2 signal transmits to the second pull-down node Q2, the second pull-down node Q2 current potential is dragged down.

First drop-down generation module 104 includes the tenth transistor M10 and the 11st transistor M11.Wherein, the tenth transistor M10 grid and first end is electrically connected to the first signal end V1, and the second end electrically connects first and pulls up the He of control module 102 simultaneously Second pull-up control module 202, specifically, the tenth transistor M10 the second end is electrically connected to the tenth two-transistor M12's simultaneously Second end and the 13rd transistor M13 the second end.11st transistor M11 grid electrically connects the of the tenth transistor M10 Two ends, first end electrically connects the first signal end V1, and the second end electrically connects the first pull-down node Q1.

On the premise of disconnecting between the drop-down generation modules 104 of the second sub- voltage end VGL2 and first, when the first signal When to hold V1 be high level, the tenth transistor M10 and the 11st transistor M11 conductings, the first signal end V1 signal are transmitted to the One pull-down node Q1；When first signal end V1 is low level, the tenth transistor M10 and the 11st transistor M11 end, under first Draw the output of the no signal of generation module 104.

It should be noted that in embodiments of the present invention, the 13rd transistor M13 and the tenth two-transistor M12 width are long Than the breadth length ratio more than the tenth transistor M10, to cause compared to the tenth transistor M10, the 13rd transistor M13 and the 12nd Transistor M12 has priority control to the 11st transistor M11.

Accordingly, the second drop-down generation module 204 includes the 19th transistor M19 and the 24th transistor M24.Its In, the 24th transistor M24 grid and first end are electrically connected to secondary signal end V2, and the second end electrically connects first simultaneously The pull-up control module 202 of control module 102 and second is pulled up, specifically, the 24th transistor M24 the second end is electrically connected simultaneously It is connected to the 20th two-transistor M22 the second end and the 20th transistor M20 the second end.19th transistor M19 grid The 24th transistor M24 the second end is electrically connected, first end is electrically connected to secondary signal end V2, and the second end is electrically connected to second Pull-down node Q2.

On the premise of disconnecting between the drop-down generation modules 204 of the second sub- voltage end VGL2 and second, work as secondary signal When the signal for holding V2 is high level, the 19th transistor M19 and the 24th transistor M24 conductings, secondary signal end V2 and the Connected between two pull-down node Q2, secondary signal end V2 signal is transmitted to the second pull-down node Q2.

It should be noted that in embodiments of the present invention, the 20th two-transistor M22 and the 20th transistor M20 width The long breadth length ratio than more than the 24th transistor M24, to cause compared to the 24th transistor M24, the 22nd crystal Pipe M22 and the 20th transistor M20 have priority control to the 19th transistor M19.

On the basis of any of the above-described embodiment, in one embodiment of the invention, the first sub- scanning element has one Individual output end, the signal of output end output is used to provide scanning signal to its corresponding gate line, and is used as next stage first The trigger signal of sub- scanning element；Second sub- scanning element has an output end, and the signal of output end output is used for it Corresponding gate line provides scanning signal, and is used as the trigger signal of the sub- scanning element of next stage second.

On the basis of above-described embodiment, in one embodiment of the invention, continue as shown in figure 3, the first drop-down control Molding block 103 includes the 5th transistor M5, the 6th transistor M6, the 14th transistor M14 and the 16th transistor M16.

Wherein, the 5th transistor M5 grid electrically connects the first pull-down node Q1, and first end electrically connects the second sub- voltage end VGL2, the second end electrically connects the first pull-up node P1.When the first pull-down node Q1 is high level, the 5th transistor M5 conductings, Second sub- voltage end VGL2 signal is transmitted to the first pull-up node P1, and the first pull-up node P1 current potential is dragged down.

6th transistor M6 grid electrically connects the first pull-down node Q1, and first end electrically connects the first sub- voltage end VGL1, Second end electrically connects the first output end Gout1.When the first pull-down node Q1 is high level, the 6th transistor M6 conductings, first Sub- voltage end VGL1 signal is transmitted to the first output end Gout1, is exported through the first output end Gout1.

16th transistor M16 grid is electrically connected to the first pull-down node Q1, and first end is electrically connected to the second sub- voltage VGL2 is held, the second end is electrically connected to the second pull-up node P2.When the first pull-down node Q1 is high level, the 16th transistor M16 is turned on, and the second sub- voltage end VGL2 signal is transmitted to the second pull-up node P2, and the second pull-up node P2 current potential is drawn It is low.

14th transistor M14 grid is electrically connected to the first pull-down node Q1, and first end is electrically connected to the first sub- voltage VGL1 is held, the second end is electrically connected to the second output end Gout2；When the first pull-down node Q1 is high level, the 14th transistor M14 is turned on, and the first sub- voltage end VGL1 signal is transmitted to the second output end Gout2, is exported through the second output end Gout2.

Second drop-down control module 203 includes：7th transistor M7, the 8th transistor M8, the 18th transistor M18 and 17 transistor M17.

Wherein, the 7th transistor M7 grid is electrically connected to the second pull-down node Q2, and first end is electrically connected to the second son electricity Pressure side VGL2, the second end is electrically connected to the first pull-up node P1.When the second pull-down node Q2 is high level, the 7th transistor M7 Conducting, the second sub- voltage end VGL2 signal transmits to the first pull-up node P1, the first pull-up node P1 current potential is dragged down.

8th transistor M8 grid is electrically connected to the second pull-down node Q2, and first end is electrically connected to the first sub- voltage end VGL1, the second end electrically connects the first output end Gout1.When the second pull-down node Q2 is high level, the 8th transistor M8 conductings, First sub- voltage end VGL1 signal is transmitted to the first output end Gout1, is exported through the first output end Gout1.

18th transistor M18 grid electrically connects the second pull-down node Q2, and first end electrically connects the second sub- voltage end VGL2, the second end electrically connects the second pull-up node P2.When the second pull-down node Q2 is high level, the 18th transistor M18 is led Logical, the second sub- voltage end VGL2 signal is transmitted to the second pull-up node P2, and the second pull-up node P2 current potential is dragged down.

17th transistor M17 grid electrically connects the second pull-down node Q2, and first end electrically connects the first sub- voltage end VGL1, the second end electrically connects the second output end Gout2.When the second pull-down node Q2 is high level, the 17th transistor M17 is led Logical, the first sub- voltage end VGL1 signal is transmitted to the second output end Gout2, is exported through the second output end Gout2.

Continue as shown in figure 3, the first output module 105 includes：9th transistor M9 and the first bootstrap capacitor C1.9th is brilliant Body pipe M9 grid electrically connects the first pull-up node P1, and first end electrically connects the first clock signal terminal CK1, the second end electrical connection the One output end Gout1；First bootstrap capacitor C1 the first pole plate electrically connects the first pull-up node P1, the second pole plate electrical connection first Output end Gout1.When the first pull-up node P1 is high level, the first bootstrap capacitor C1 is charged, and the 9th transistor M9 is turned on, and the first clock signal terminal CK1 signal is transmitted to the first output end Gout1, is exported through the first output end Gout1.

It should be noted that in embodiments of the present invention, when the first pull-up node P1 is low level, the first pull-down node Q1 During for high level, the 9th transistor M9 grid is electrically connected to the second sub- voltage end VGL2, the second end by the 5th transistor M5 First sub- voltage end VGL1 is electrically connected to by the 6th transistor M6, therefore, when the second sub- sub- voltages of voltage end VGL2 and first When holding VGL1 voltages identical, the voltage difference between the 9th transistor M9 grid g and the second end (drain d) is zero, when second When sub- voltage end VGL2 voltage is less than the first sub- voltage end VGL1 voltage, the 9th transistor M9 grid g and the second end are (i.e. Voltage difference between drain electrode d) is less than zero.

As shown in figure 4, Fig. 4 shows the leakage current Ids of a thin film transistor (TFT) with the voltage between its grid and drain electrode Poor Vgs change curve schematic diagram, as can be seen from Figure 4, the voltage difference Vgs between the grid g and drain electrode d of a transistor are smaller, The leakage current Ids of the transistor is smaller, therefore, in embodiments of the present invention, when the second sub- voltage end VGL2 voltage is less than the During one sub- voltage end VGL1 voltage, the 9th transistor M9 leakage current can be effectively reduced, it is to avoid the 9th transistor M9 is beaten by mistake Open, improve the stability of the scanning element and the gate driving circuit including the scanning element.

Similarly, with continued reference to Fig. 3, the second output module 205 includes：15th transistor M15 and the second bootstrap capacitor C2. 15th transistor M15 grid electrically connects the second pull-up node P2, first end electrical connection second clock signal end CK2, and second The second output end Gout2 of end electrical connection；Second the first pole plates of bootstrap capacitor C2 electrically connect the second pull-up node P2, the second pole plate electricity Connect the second output end Gout2.When the second pull-up node P2 is high level, the second bootstrap capacitor C2 is charged, and the 15 transistor M15 are turned on, and second clock signal end CK2 signal is transmitted to the second output end Gout2, through the second output end Gout2 is exported.

It should be noted that in embodiments of the present invention, when the second pull-up node P2 is low level, the second pull-down node Q2 During for high level, the 15th transistor M15 grid is electrically connected to the second sub- voltage end VGL2 by the 18th transistor M18, Second end is electrically connected to the first sub- voltage end VGL1 by the 17th transistor M17, therefore, as the second sub- voltage end VGL2 and When one sub- voltage end VGL1 voltages are identical, the voltage difference between the 15th transistor M15 grid and the second end (drain d) is Zero, when the second sub- voltage end VGL2 voltage is less than the first sub- voltage end VGL1 voltage, the 15th transistor M15 grid And the second voltage difference between end (drain d) is less than zero.As shown in Figure 4, the electricity between the grid of transistor and drain electrode Pressure difference is smaller, and the leakage current of the transistor is smaller, therefore, in embodiments of the present invention, when the second sub- voltage end VGL2 voltage During voltage end VGL1 less than first voltage, the 15th transistor M15 leakage current can be effectively reduced, it is to avoid the 15th is brilliant Body pipe M15 is opened by mistake, improves the stability of the scanning element and the gate driving circuit including the scanning element.

Continue as shown in figure 3, first control module 106 includes the 27th transistor M27, the described 27th is brilliant Body pipe M27 grid is electrically connected to second voltage end BW, and first end is electrically connected to the first sub- voltage end VGL1, the electrical connection of the second end To the first output end Gout1.

As shown in Fig. 2 in the display stage, BW second voltages end BW perseverances in second voltage end are the first level signal H1, i.e., permanent For low potential, the 27th transistor M27 is in response to second voltage end BW low potential, the first sub- voltage end VGL1 of control and the Disconnect between one output end Gout1, the setting to ensure the 27th transistor M27 does not interfere with the first sub- scanning element In the driving work in display stage.In the touch-control stage, second voltage end BW is adjusted to second electrical level signal H2, i.e. second voltage end BW is adjusted to high potential, and the 27th transistor M27 controls the first sub- voltage end in response to second voltage end BW high potential Connected between VGL1 and the first output end Gout1, the first sub- voltage end VGL1 low potential is transmitted to the first output end Gout1, to continue to drag down the first output end Gout1 current potential, so that the touch-control display surface applied in the gate driving circuit In plate, the Capacitance Coupled weakened between each gate line and touch control electrode is acted on, and improves touch control detection precision.

Second control module 206 includes the 28th transistor M28, and the 28th transistor M28 grid is electrically connected Second voltage end BW is connected to, first end is electrically connected to the first sub- voltage end VGL1, and the second end is electrically connected to the second output end Gout2。

As shown in Fig. 2 in the display stage, BW second voltages end BW perseverances in second voltage end are the first level signal H1, i.e., permanent For low potential, the 28th transistor M28 is in response to second voltage end BW low potential, the first sub- voltage end VGL1 of control and the Disconnect between two output end Gout2, the setting to ensure the 28th transistor M28 does not interfere with the second sub- scanning element In the driving work in display stage.In the touch-control stage, second voltage end BW is adjusted to second electrical level signal H2, i.e. second voltage end BW is adjusted to high potential, and the 28th transistor M28 controls the first sub- voltage end in response to second voltage end BW high potential Connected between VGL1 and the second output end Gout2, the first sub- voltage end VGL1 low potential is transmitted to the second output end Gout2, to continue to drag down the second output end Gout2 current potential, so that the touch-control display surface applied in the gate driving circuit In plate, the Capacitance Coupled weakened between each gate line and touch control electrode is acted on, and improves touch control detection precision.

The gate driving circuit that the embodiment of the present invention is provided, sets the 27th transistor M27 in each scanning element With the 28th transistor M28, the first output end Gout1 is set to maintain low electricity using the 27th transistor M27 in the touch-control stage Position, and make the second output end Gout2 maintain low potential using the 28th transistor M28, increased circuit is simple, and cabling compared with Short, line width is smaller, and occupancy frame area is smaller, is conducive to the realization of narrow frame.

On the basis of any of the above-described embodiment, in another embodiment of the present invention, as shown in figure 5, being swept per one-level Retouching unit also includes reset signal end RST, and the first sub- scanning element also includes：3rd control module 107, the 3rd control mould Block 107 controls the connection shape between tertiary voltage end VGL and the first pull-up node P1 in response to reset signal end RST signal State.When reset signal end RST signal is high level, connected between tertiary voltage end VGL and the first pull-up node P1, the 3rd Voltage end VGL signal is transmitted to the first pull-up node P1, the first pull-up node P1 current potential is dragged down, so that on first Node P1 current potential is drawn quickly to drag down.

Similarly, the second sub- scanning element also includes the 4th control module 207, and the 4th control module 207 is believed in response to resetting Number end RST signal, control tertiary voltage end VGL and the second pull-up node P2 between on-state.As reset signal end RST Signal when being high level, connected between tertiary voltage end VGL and the second pull-up node P2, tertiary voltage end VGL signal is passed The second pull-up node P2 is transported to, the second pull-up node P2 current potential is dragged down, so that the second pull-up node P2 current potentials are quick Drag down.

Specifically, as shown in fig. 6, the 3rd control module 107 includes：29th transistor M29, the 29th transistor M29 grid electrical connection reset signal end RST, first end is electrically connected to the second sub- voltage end VGL2, and the second end is electrically connected to the One pull-up node P1, when reset signal end RST signal is high level, the 29th transistor M29 conductings, the second sub- voltage End VGL2 signal is transmitted to the first pull-up node P1, and the first pull-up node P1 current potential is quickly dragged down, and improves scanning element With the stability of the gate driving circuit including the scanning element.

Similarly, the 4th control module 207 includes：30th transistor M30, the 30th transistor M30 grid electrical connection Reset signal end RST, first end electrically connects the second sub- voltage end VGL2, and the second end electrically connects the second pull-up node P2, works as reset When signal end RST signal is high level, the 30th transistor M30 conductings, the second sub- voltage end VGL2 signal is transmitted to the Two pull-up node P2, the second pull-up node P2 current potential is quickly dragged down, and improves scanning element and the grid including the scanning element The stability of pole drive circuit.

As shown in fig. 7, Fig. 7 shows the circuit structure signal for the scanning element that another embodiment of the present invention is provided Figure.On the basis of the scanning circuit shown in Fig. 1 and Fig. 3, in the embodiment of the present invention, the first sub- scanning element also includes：First The cascade output modules 108 of cascaded-output end Gout1 ' and first.Wherein, the first cascade output module 108 is in response to the first pull-up Node P1 current potential and control the first clock signal terminal CK1 and first to cascade output end Gout1 ' on-state.First output End Gout1 signal is used to provide scanning signal, the letter of the first cascade output end Gout1 ' outputs for the gate line of its electrical connection Number as the sub- scanning element of next stage first trigger signal.

Second sub- scanning element also includes：Second cascade output end Gout2 ' and the second cascade output module 206.Wherein, Second cascade output module 206 controls second clock signal end CK2 and the second level in response to the second pull-up node P2 current potential Join output end Gout2 ' on-state.The signal of second output end Gout2 outputs is used to provide for the gate line of its electrical connection Scanning signal, the signal of the second cascade output end Gout2 ' outputs is used to believe as the triggering of the sub- scanning element of next stage second Number.

Specifically, as shown in figure 8, on the basis of the scanning circuit shown in Fig. 3, first pulls down in control module 103 newly Two transistors are increased, specifically, the first drop-down control module 103 also includes：31st transistor M31 and the 35th is brilliant Body pipe M35.

31st transistor M31 grid electrically connects the first pull-down node Q1, and first end electrically connects the second sub- voltage end VGL2, the second end electrical connection first cascades output end Gout1 ', when the first pull-down node Q1 is high level, the 31st crystal Pipe M31 is turned on, and the second sub- voltage end VGL2 signal is transmitted to the first cascade output end Gout1 ', and output end is cascaded by first Gout1 ' is dragged down, and the second sub- voltage end VGL2 signal is exported into sub to next stage first through the first cascade output end Gout1 ' Scanning element.

It should be noted that when the first pull-down node Q1 is high level, the 31st transistor M31 conductings, the second son Voltage end VGL2 signal exports the first control end to the sub- scanning element of next stage first through the first cascade output end Gout1 ' SET1, so that the first transistor M1 of the sub- scanning element of next stage first control end electrically connects the second sub- voltage end VGL2, and the first transistor M1 of the sub- scanning element of next stage first the second end electrically connects the first pull-up node P1, when first Pull-up node P1 is low level, and when the first pull-down node Q1 is high level, the first pull-up node P1 is pulled low to the second sub- voltage Hold VGL2 voltage.

Now, between the first transistor M1 of the sub- scanning element of next stage first grid (grid) and the second end (drain electrode) Voltage difference be zero.And it can be seen from Fig. 4, the voltage difference between the grid of transistor and drain electrode is smaller, the transistor Leakage current is smaller, therefore, in embodiments of the present invention, and the second sub- voltage end VGL2 voltage is less than the first sub- voltage end VGL1's Voltage, while effectively the 9th transistor M9 of reduction leakage current, sets the second sub- voltage end VGL2 signal through the first order Connection output end Gout1 ' exports the first control end SET1 to the sub- scanning element of next stage first, helps to reduce next stage first The first transistor M1 of sub- scanning element leakage current, so as to avoid the first transistor M1 of the sub- scanning element of next stage first from missing Open, influence the first pull-up node P1 current potential, so as to influence the scanning element and the raster data model electricity including the scanning element The stability on road.

35th transistor M35 grid is electrically connected to the first pull-down node Q1, and first end is electrically connected to the second son electricity Pressure side VGL2, the second end is electrically connected to the second cascade output end Gout2 '.When the first pull-down node Q1 is high level, the 30th Five transistor M35 are turned on, and the second sub- voltage end VGL2 signal is transmitted to the second cascade output end Gout2 ', defeated through the second cascade Go out to hold Gout2 ' to export to the second of next stage scanning element the sub- scanning element.

Similarly, list is scanned when the second sub- voltage end VGL2 signal is transferred to next stage through the second cascade output end Gout2 ' 3rd control end SET2 of the second sub- scanning element of member, so that the 25th crystal of the sub- scanning element of next stage second Pipe M25 control end the second sub- voltage end VGL2 of electrical connection, and the 25th transistor M25 of the sub- scanning element of next stage first The second end electrically connect the second pull-up node P2, when the second pull-up node P2 be low level, the second pull-down node Q2 be high level When, the second pull-up node P2 is pulled low to the second sub- voltage end VGL2 voltage.

Now, the 25th transistor M25 of the sub- scanning element of next stage second grid (grid) and (leakage of the second end Pole) between voltage difference be zero.And it can be seen from Fig. 4, the voltage difference between the grid of transistor and drain electrode is smaller, the crystalline substance The leakage current of body pipe is smaller, therefore, in embodiments of the present invention, and the second sub- voltage end VGL2 voltage is less than the first sub- voltage end VGL1 voltage, while effectively the 15th transistor M15 of reduction leakage current, sets the second sub- voltage end VGL2 signal The 3rd control end SET2 to the sub- scanning element of next stage second is exported through the second cascade output end Gout2 ', is contributed under reduction 25th transistor M25 of the sub- scanning element of one-level second leakage current, so as to avoid next stage and sub- scanning element 25th transistor M25 is opened by mistake, the second pull-up node P2 current potential is influenceed, so as to influence the scanning element and be swept including this Retouch the stability of the gate driving circuit of unit.

Likewise, two transistors have also been increased newly in the second drop-down control module 203, specifically, the second drop-down control mould Block 203 also includes：30th two-transistor M32 and the 34th transistor M34.

30th two-transistor M32 grid is electrically connected to the second pull-down node Q2, and first end is electrically connected to the second son electricity Pressure side VGL2, the second end is electrically connected to the first cascade output end Gout1 ', when the second pull-down node Q2 signal is high level, 30th two-transistor M32 is turned on, and the second sub- voltage end VGL2 signal is transmitted to the first cascade output end Gout1 ', through first Cascaded-output end Gout1 ' is transferred to the sub- scanning element of the first order first.

34th transistor M34 grid electrically connects the second pull-down node Q2, and first end electrically connects the second sub- voltage end VGL2, the second end electrical connection second cascades output end Gout2 ', when the second pull-down node Q2 is high level, the 34th crystal Pipe M34 is turned on, and the second sub- voltage end VGL2 signal is transmitted to the second cascade output end Gout2 ', through the second cascade output end Gout2 ', which is exported, gives next stage second sub- scanning element.

Continue as shown in figure 8, the first cascade output module 108 includes the 33rd transistor M33, the 33rd transistor M33 grid electrically connects the first pull-up node P1, and first end electrically connects the first clock signal terminal CK1, the second end electrical connection first Cascaded-output end Gout1 '；When the first pull-up node P1 is high level, the 33rd transistor M33 conductings, the first clock letter Number end CK1 signal is transmitted to the first cascade output end Gout1 ', is exported through the first cascade output end Gout1 ' to next stage the One sub- scanning element, is used as the trigger signal of the sub- scanning element of next stage first.

Second cascade output module 208 includes the 36th transistor M36, and the 36th transistor M36 grid is electrically connected The second pull-up node P2 is connected to, first end is electrically connected to second clock signal end CK2, and the second end is electrically connected to the second cascaded-output Hold Gout2 '；When the first pull-up node P1 is high level, the 36th transistor M36 conductings, second clock signal end CK2's Signal is transmitted to the second cascade output end Gout2 ', exports single to the son scanning of next stage first through the second cascade output end Gout2 ' Member, is used as the trigger signal of the sub- scanning element of next stage first.

As shown in figure 9, being the circuit diagram of the scanning element shown in an alternative embodiment of the invention, the embodiment is in Fig. 8 On the basis of shown scanning circuit, reset signal end RST is added.Specifically, the circuit of the scanning element shown in Fig. 9, be In the circuit of scanning element shown in Fig. 8, add the reset signal end RST shown in Fig. 6, and the 29th transistor M29 and 30th transistor M30, using when reset signal end RST is high level, by the 29th transistor M29 conducting, is realized The purpose for quickly being dragged down the first pull-up node P1 current potentials by the second sub- voltage end VGL2, also, pass through the 30th transistor M30 Conducting, realize the purpose that is quickly dragged down the second pull-up node P2 current potentials by the second sub- voltage end VGL2, it is single to improve scanning The stability of gate driving circuit first and including the scanning element.

This increased partial circuit can be retouched with specific reference to Fig. 5 is related in the scanning circuit embodiment shown in Fig. 6 in Fig. 9 State and understood.Specifically, referring in the scanning circuit embodiment shown in Fig. 5 on reset signal end RST, the 3rd control mould The associated description of the control module 207 of block 107 and the 4th.Further, in physical circuit, the scanning shown in Fig. 6 is referred to Description in circuit embodiments on reset signal end RST, and the 29th transistor M29 and the 30th transistor M30, this This is repeated no more in embodiment.

As shown in Figure 10, the structural representation for the gate driving circuit that one embodiment of the invention is provided is shown. On the basis of any of the above-described embodiment, in one embodiment of the invention, define adjacent two-stage scan unit and scanned for i-stage Unit and i+1 level scanning element, i is no more than n positive integer.

Wherein, the first output end Gout1 of i-stage scanning element and the first control end SET1 of i+1 level scanning element It is connected, i+1 level the first output end Gout1 of scanning element is connected with the second control end RESET1 of i-stage scanning element；

Second output end Gout2 of i-stage scanning element is connected with the 3rd control end SET2 of i+1 level scanning element, Second output end Gout2 of i+1 level scanning element is connected with the 4th control end RESET2 of i-stage scanning element；

And, the first clock signal terminal CK1 of odd level scanning element is same signal end and second clock signal end CK2 is same signal end, and the first clock signal terminal CK1 of even level scanning element is same signal end and second clock signal End CK2 is same signal end.

As shown in figure 11, Figure 11 shows the structural representation for the gate driving circuit that another embodiment of the present invention is provided Figure, on the basis of above-described embodiment, in embodiments of the present invention, in addition to the first cascade output end Gout1 ' and the second cascade Output end Gout2 '.

First cascade output end Gout1 ' of i-stage scanning element and the first control end SET1 of i+1 level scanning element It is connected, the first cascade output end Gout1 ' and the second control end RESET1 phases of i-stage scanning element of i+1 level scanning element Even；

Second cascade output end Gout2 ' of i-stage scanning element and the 3rd control end SET2 of i+1 level scanning element It is connected, the second cascade output end Gout2 ' and the 4th control end RESET2 phases of i-stage scanning element of i+1 level scanning element Even.

It should be noted that the gate driving circuit that the embodiment of the present invention is provided, the first control of first order scanning element End SET1 and the 3rd control end SET2 processed provide initial control signal by outer signal.First signal end and secondary signal The signal of end output is frame reverse signal；That is, after the scanned frame picture of gate driving circuit, the first signal end and second The signal of signal end output is each anti-phase.

To sum up, the gate driving circuit that the embodiment of the present invention is provided, sets the first control module in each scanning element With the second control module, the first output end is set to maintain low potential using the first control module in the touch-control stage, while utilizing second Control module makes the second output end maintain low potential, so as to weaken each grid in the touch-control display panel that the gate driving circuit is applied Capacitance Coupled effect between polar curve and touch control electrode, improves touch control detection precision, and increased cabling is shorter, line width compared with Small, occupancy frame area is smaller, is conducive to the realization of narrow frame.

In addition, as shown in figure 12, the embodiment of the present invention additionally provides another gate driving circuit, the gate driving circuit Including n grades of scanning elements, the n grades of scanning element is first order scanning element to n-th grade of scanning element, and n is whole not less than 2 Number；Include per one-level scanning element：First sub- scanning element, the second sub- scanning element, first voltage end FW, second voltage end BW, tertiary voltage end VGL, control node M；

The first sub- scanning element includes：First control end SET1, the second control end RESET1, the first input module 101st, the first pull-up node P1, the first pull-up control module 102, the first pull-down node Q1, the first drop-down control module 103, the One drop-down generation module 104, the first output module 105, the first output end Gout1, the first signal end V1, the first clock signal terminal CK1, the first control module 106, the 5th control module 109；

The second sub- scanning element includes：3rd control end SET2, the 4th control end RESET2, the second input module 201st, the second pull-up node P2, the second pull-up control module 202, the second pull-down node Q2, the second drop-down control module 203, the Two drop-down generation modules 204, the second output module 205, the second output end Gout2, secondary signal end V2, second clock signal end CK2, the second control module 206, the 6th control module 209.

In the present invention is implemented, the first input module 101 and controls institute in response to the current potential of the first control end SET1 State the on-state between first voltage end and the first pull-up node P1, and control the first voltage end FW with it is described Control node M on-state, and in response to the second control end RESET1 current potential, and control second voltage end BW with it is described First pull-up node P1 on-state.Wherein, the first voltage end FW and the second voltage end BW level are opposite；The It is high level when one control end SET1 and the second control end RESET1 signal are different, so that first voltage end FW and first When being connected between pull-up node P1, disconnect between second voltage end BW and the first pull-up node P1, when second voltage end BW with When being connected between the first pull-up node P1, disconnect between first voltage end FW and the first pull-up node P1, and first voltage end FW and the level of second voltage end BW output signals are on the contrary, so that when first voltage end FW and the first pull-up node P1 is connected When being connected with second voltage end BW and the first pull-up node P1, the first pull-up node P1 is varying level.

Specifically, when the first control end SET1 is high level, when the second control end RESET1 is low level, first voltage Connection between FW and the first pull-up node P1 is held, is connected between first voltage end FW and control node M, first voltage end FW letter Number transmit to the first pull-up node P1 and control node M, the first pull-up node P1 and control node M current potential is drawn high.When One control end SET1 is low level, when the second control end RESET1 is high level, first voltage end FW and the first pull-up node P1 Between end, end between first voltage end FW and control node M, second voltage end BW signal transmitted to the first pull-up node P1, the first pull-up node P1 current potential is dragged down.

Continue as shown in figure 12, the first pull-up control module 102 and controls the in response to the first pull-up node P1 current potential Three voltage end VGL give birth to the first pull-down node Q1, the first drop-down generation module 104 and second drop-down respectively Into the on-state of module 204.

When the first pull-up node P1 is high level, connected between the first pull-down node Q1 and tertiary voltage end VGL, the 3rd Voltage end VGL signal is transmitted to the first pull-down node Q1, and the first pull-down node Q1 current potential is dragged down；Tertiary voltage end VGL Connected between the first drop-down generation module 104, control first pulls down the output of the no signal of generation module 104；Tertiary voltage end VGL Connected between the second drop-down generation module 204, control second pulls down the output of the no signal of generation module 204.When the first pull-up section When point P1 is low level, do not connect between the first pull-down node Q1 and tertiary voltage end VGL by the first pull-up control module 102 It is logical, between the drop-downs of tertiary voltage end VGL and first generation module 104, the drop-down generation modules 204 of tertiary voltage end VGL and second Also do not connected by the first pull-up control module 102, the first 102 pair first of control module of pull-up drop-down generation module 104 and the The signal output of two drop-down generation modules 204 does not play control action.

First pulls down current potential of the control module 103 in response to the first pull-down node Q1, and controls tertiary voltage end VGL to distinguish With control node M, the first pull-up node P1, the first output module 105, the first output end Gout1, the second pull-up node P2, The on-state of two output modules 205, the second output end Gout2.

Specifically, when the first pull-down node Q1 is high potential, connected between tertiary voltage end VGL and control node M, will Tertiary voltage end VGL signal is transmitted to control node M, control node M current potential is dragged down, and maintain low potential；3rd electricity Connected between pressure side VGL and the first pull-up node P1, tertiary voltage end VGL signal is transmitted to the first pull-up node P1, will First pull-up node P1 current potential is dragged down, and maintains low potential, and then makes the first clock signal terminal CK1 and the first output module Disconnect between 105；, will and tertiary voltage end VGL is connected between the first output module 105 and the first output end Gout1 respectively Tertiary voltage end VGL signal is transmitted to the first output end Gout1, and is exported through the first output end Gout1；Tertiary voltage end Connected between VGL and the second pull-up node P2, tertiary voltage end VGL signal is transmitted to the second pull-up node P2, by second Pull-up node P2 current potential is dragged down, and maintains low potential, and then is made between second clock signal end CK2 and the second output module 205 Disconnect；And tertiary voltage end VGL is connected between the second output module 205 and the second output end Gout2 respectively, by the 3rd electricity Pressure side VGL signal is transmitted to the second output end Gout2, and is exported through the second output end Gout2.

When the first pull-down node Q1 is low potential, not by the between tertiary voltage end VGL and the first pull-up node P1 One drop-down control module 103 is connected, and between tertiary voltage end VGL and the first output module 105 and the first output end Gout1 not Connected by the first drop-down control module 103；Meanwhile, do not pass through first between tertiary voltage end VGL and the second pull-up node P2 Drop-down control module 103 is connected, and obstructed between tertiary voltage end VGL and the second output module 205 and the second output end Gout2 Cross the first drop-down control module 103 to connect, do not pass through the first drop-down control module between tertiary voltage end VGL and control node M 103 connect.

5th control module 109 and is controlled under the tertiary voltage end VGL and first in response to control node M current potential Draw node Q1 on-state.When the control node M is high level, tertiary voltage end VGL connects with the first pull-down node Q1 It is logical, the first pull-down node Q1 current potential is dragged down.

Second input module 201 and is controlled on first voltage end FW and second in response to the 3rd control end SET2 current potential The on-state between node P2 is drawn, and in response to the 4th control end RESET2 current potential, and control second voltage end BW and the On-state between on-state between two pull-up node P2, and control second voltage end BW and control node M.Its In, it is high level when the 3rd control end SET2 and the 4th control end RESET2 signal are different, so that first voltage end FW When being connected between the second pull-up node P2, disconnect between second voltage end BW and the second pull-up node P2, work as second voltage When being connected between the BW and the second pull-up node P2 of end, disconnect between first voltage end FW and the first pull-up node P1, and first Voltage end FW and second voltage end BW level signal are on the contrary, so that first voltage end FW and the second pull-up node P2 is connected When and second voltage end BW and the second pull-up node P2 connection when, the second pull-up node P2 be varying level.

Specifically, when the 3rd control end SET2 is high level, and the 4th control end RESET2 is low level, first voltage end Connected between FW and the second pull-up node P2, first voltage end FW signal is transmitted to the second pull-up node P2, by the second pull-up Node P2 current potential is drawn high；When the 3rd control end SET2 is low level, and the 4th control end RESET2 is high level, second voltage Connection between BW and the second pull-up node P2 is held, second voltage end BW signal is transmitted to the second pull-up node P2, by second Draw node P2 current potential to drag down, connected between second voltage end BW and control node M, second voltage end BW signal is transmitted to control Node M processed, control node M current potential is dragged down.

Second pulls down current potential of the control module 203 in response to the second pull-down node Q2, and controls tertiary voltage end VGL to distinguish With control node M, the second pull-up node P2, the second output module 205, the second output end Gout2, the first pull-up node P1, The on-state of one output module 105, the first output end Gout1.

Specifically, when the second pull-down node Q2 is high potential, being connected between tertiary voltage end VGL and control node M, by the Three voltage end VGL signal is transmitted to control node M, control node M current potential is dragged down, and maintain low potential；And the 3rd electricity Connected between pressure side VGL and the second pull-up node P2, tertiary voltage end VGL signal is transmitted to the second pull-up node P2, will Second pull-up node P2 current potential is dragged down, and maintains low potential, and then makes second clock signal end CK2 and the second output module Disconnect between 205；, will and tertiary voltage end VGL is connected between the second output module 205 and the second output end Gout2 respectively Tertiary voltage end VGL signal is transmitted to the second output end Gout2, and is exported through the second output end Gout2, to remain second defeated Go out to hold Gout2 low potential；And connected between tertiary voltage end VGL and the first pull-up node P1, by tertiary voltage end VGL letter Number transmit to the first pull-up node P1, the first pull-up node P1 current potential is dragged down, and maintain low potential, and then make the first clock Disconnect between signal end CK1 and the first output module 105；And tertiary voltage end VGL respectively with the first output module 105 and first Connected between output end Gout1, tertiary voltage end VGL signal is transmitted to the first output end Gout1, and through the first output end Gout1 is exported.

When the first pull-down node Q1 is low potential, tertiary voltage end VGL and control node M is not controlled by the second drop-down Module 203 is connected, and is not connected between tertiary voltage end VGL and the first pull-up node P1 by the second drop-down control module 203, And do not pass through the second drop-down control module between tertiary voltage end VGL and the first output module 105 and the first output end Gout1 203 connect；Meanwhile, do not connected between tertiary voltage end VGL and the second pull-up node P2 by the second drop-down control module 203, And do not pass through the second drop-down control module between tertiary voltage end VGL and the second output module 205 and the second output end Gout2 203 connect.

6th control module 209 and is controlled under the tertiary voltage end VGL and second in response to control node M current potential Draw node Q2 on-state.When the control node M is high level, tertiary voltage end VGL connects with the second pull-down node Q2 It is logical, the second pull-down node Q2 current potential is dragged down.

It should be noted that because in the embodiment of the present invention, first in the first sub- scanning element pulls up control module 102nd, the first drop-down generation module 104, the first pull-up node P1, the first pull-down node Q1, the first signal end V1, the first clock letter Number end CK1 and the first output module 105, the first control module 106, the first control end SET1, the second control end RESET1；Second The the second pull-up drop-down of control module 202, second generation module 204 in sub- scanning element, the second pull-up node P2, the second drop-down Node Q2, the 3rd control end SET2, the 4th control end RESET2, secondary signal end V2, second clock signal end CK2 and second are defeated Go out module 205, the second control module 206 identical with the gate driving circuit that above example is provided, the present invention to this no longer Repetition is repeated.The raster data model that the gate driving circuit only provided below the embodiment of the present invention is provided with a upper embodiment The different piece of circuit is described.

Specifically, as shown in figure 13, in embodiments of the present invention, the first input module 101 includes：The first transistor M1, Second transistor M2 and the 37th transistor M37.

37th transistor M37 control end electrically connects the first control end SET1, and first end is electrically connected to first voltage FW is held, the second end is electrically connected to control node M, when the first control end SET1 is high level, the 37th transistor M37 is led Logical, first voltage end FW voltage is transmitted to control node M, and control node M current potential is drawn high.

Second input module 201 includes the 25th transistor M25, the 26th transistor M26 and the 38th crystal Pipe M38.

Wherein, the 25th transistor M25 grid electrically connects the 3rd control end SET2, and first end is electrically connected to the first electricity Pressure side FW, the second end is electrically connected to the second pull-up node P2, when the 3rd control end SET2 is high level, the 25th transistor M25 is turned on, and first voltage end FW signal transmits to the second pull-up node P2, the second pull-up node P2 current potential is drawn high.

26th transistor M26 grid electrically connects the 4th control end RESET2, and first end is electrically connected to second voltage BW is held, the second end is electrically connected to the second pull-up node P2, when the 4th control end RESET2 is high level, the 26th transistor M26 is turned on, and second voltage end BW signal transmits to the second pull-up node P2, the second pull-up node P2 current potential is dragged down.

38th transistor M38 grid electrically connects the 4th control end RESET2, and first end is electrically connected to second voltage BW is held, the second end is electrically connected to control node M, when the 4th control end RESET2 is high level, the 38th transistor M38 is led Logical, second voltage end BW signal is transmitted to control node M, and control node M current potential is dragged down.

First drop-down control module 103 includes the 5th transistor M5, the 6th transistor M6, the 14th transistor M14 and the 16 transistor M16 and the 41st transistor M41.Wherein, in Figure 13 the 5th transistor M5, the 6th transistor M6, 14 transistor M14 and the 16th transistor M16 connected mode and the connected mode of the transistor of same names in Fig. 3 also phase Together, with specific reference to the description of above example, repeat no more here.

Specifically, the 41st transistor M41 grid is electrically connected to the first pull-down node Q1, first end electrical connection second Sub- voltage end VGL2, the second end is electrically connected to control node M, when the first pull-down node Q1 is high level, the 41st crystal Pipe M41 is turned on, and the second sub- voltage end VGL2 signal transmits to control node M, control node M current potential is dragged down.

Second drop-down control module 203 includes：7th transistor M7, the 8th transistor M8, the 18th transistor M18, 17 transistor M17 and the 40th two-transistor M42.Wherein, in Figure 13 the 7th transistor M7, the 8th transistor M8, the tenth The connected mode of the transistor of same names is also identical in eight transistor M18, the 17th transistor M17 connected mode and Fig. 3, With specific reference to the description of above example, repeat no more here.

Specifically, the 40th two-transistor M42 grid electrically connects the second pull-down node Q2, of first end electrical connection second Voltage end VGL2, the second end electrical connection control node M, when the second pull-down node Q2 is high level, the 40th two-transistor M42 Conducting, the second sub- voltage end VGL2 signal transmits to control node M, control node M current potential is dragged down.

5th control module 109 includes the 39th transistor M39, the grid of the 39th transistor M39 The control node M is electrically connected to, first end is electrically connected to the described second sub- voltage end VGL2, and the second end is electrically connected to described One pull-down node Q1, when the control node M is high level, the 39th transistor M39 conductings, the second sub- voltage end VGL2 signal is transmitted to the first pull-down node Q1, and the first pull-down node Q1 current potential is dragged down.

6th control module 209 includes the 40th transistor M40, and the grid of the 40th transistor M40 is electrically connected The control node M is connected to, first end is electrically connected to the second sub- voltage end VGL2, and the second end is electrically connected to the second drop-down section Point Q2, when the control node M is high level, the 40th transistor M40 conductings, the signal of the second sub- voltage end VGL2 Transmit to the second pull-down node Q2, the second pull-down node Q2 current potential is dragged down.

On the basis of above-described embodiment, in one embodiment of the invention, the first sub- scanning element also includes 7th control module, the 7th control module and controls the described second sub- voltage in response to the first output end Gout1 current potential Hold VGL2 and control node M on-state.The second sub- scanning element also includes the 8th control module, the 8th control module In response to the current potential of the second output end Gout2, and control connecing for the described second sub- voltage end VGL2 and control node M Logical state.

Specifically, as shown in figure 14, the 7th control module includes the 43rd transistor M43, the described 43rd Transistor M43 grid is electrically connected to the first output end Gout1, and first end is electrically connected to the described second sub- voltage end VGL2, the second end is electrically connected to the control node M, when the first output end Gout1 is high level, the 43rd crystal Pipe M43 is turned on, and the signal of the second sub- voltage end transmits to the control node M, the current potential of the control node M is dragged down.

8th control module includes the 44th transistor M44, and the grid of the 44th transistor M44 is electrically connected The second output end Gout2 is connected to, first end is electrically connected to the described second sub- voltage end VGL2, and the second end is electrically connected to described Control node M, when the second output end Gout2 is high level, the 44th transistor M44 conductings, the second son electricity Pressure side VGL2 signal is transmitted to the control node M, and control node M current potential is dragged down.

On the basis of any of the above-described embodiment, in one embodiment of the invention, the scanning element also includes multiple Position signal end RST, the first sub- scanning element also includes：3rd control module, the 3rd control module resets in response to described Signal end RST current potential, and control the described second sub- voltage end VGL2 and the first pull-up node P1 on-state.When multiple When position signal end RST signal is high level, connected between the second sub- voltage end VGL2 and the first pull-up node P1, the second son electricity Pressure side VGL2 signal is transmitted to the first pull-up node P1, the first pull-up node P1 current potential is dragged down, so that on first Node P1 current potential is drawn quickly to drag down.

Similarly, the second sub- scanning element also includes the 4th control module, and the 4th control module is in response to reset signal end RST Signal, control the second sub- voltage end VGL2 and the second pull-up node P2 between on-state.When reset signal end RST letter Number be high level when, between the second sub- voltage end VGL2 and the second pull-up node P2 connect, the second sub- voltage end VGL2 signal Transmit to the second pull-up node P2, the second pull-up node P2 current potential is dragged down, so that the second pull-up node P2 current potentials are fast Speed is dragged down.

Specifically, as shown in figure 15, the 3rd control module includes：29th transistor M29, the 29th transistor M29 grid electrical connection reset signal end RST, first end is electrically connected to the second sub- voltage end VGL2, and the second end is electrically connected to the One pull-up node P1, when reset signal end RST signal is high level, the 29th transistor M29 conductings, the second sub- voltage End VGL2 signal is transmitted to the first pull-up node P1, and the first pull-up node P1 current potential is quickly dragged down, and improves scanning element With the stability of the gate driving circuit including the scanning element.

Similarly, the 4th control module includes：30th transistor M30, the 30th transistor M30 grid electrical connection reset Signal end RST, first end electrically connects the second sub- voltage end VGL2, and the second end electrically connects the second pull-up node P2, works as reset signal When the signal for holding RST is high level, the 30th transistor M30 conductings, the second sub- voltage end VGL2 signal is transmitted on second Node P2 is drawn, the second pull-up node P2 current potential is quickly dragged down, scanning element is improved and the grid including the scanning element drives The stability of dynamic circuit.

In summary, the gate driving circuit that the embodiment of the present invention is provided, sets first to control in each scanning element Module and the second control module, make the first output end maintain low potential, utilize simultaneously in the touch-control stage using the first control module Second control module makes the second output end maintain low potential, so that in weakening the touch-control display panel that the gate driving circuit is applied Capacitance Coupled effect between each gate line and touch control electrode, improves touch control detection precision, and increased cabling is shorter, line width Smaller, occupancy frame area is smaller, is conducive to the realization of narrow frame.

On the basis of a upper embodiment, scanning element disclosed in another embodiment of the present invention also add cascaded-output end With cascaded-output module.Specifically, on the basis of Figure 15, in the embodiment of the present invention, as shown in figure 16, the first sub- scanning element Also include：First cascade output end Gout1 ' and the first cascade output module 108.Wherein, the first cascade output module 108 is responded The cascade output ends of the first clock signal terminal CK1 and first Gout1 ' connection shape is controlled in the first pull-up node P1 current potential State.First output end Gout1 signal is used to provide scanning signal, the first cascade output end for the gate line of its electrical connection Gout1 ' output signal as the sub- scanning element of next stage first trigger signal.

Specifically, as shown in figure 17, on the basis of the scanning circuit shown in Figure 15, in the first drop-down control module 103 Two transistors are increased newly, specifically, the first drop-down control module 103 also includes：31st transistor M31 and the 35th Transistor M35.Second drop-down control module 203 has also increased two transistors newly, specifically, the second drop-down control module 203 is also Including：30th two-transistor M32 and the 34th transistor M34.

Continue as shown in figure 17, the first cascade output module 108 includes the 33rd transistor M33, the second cascaded-output Module 208 includes the 36th transistor M36.

Specifically, the 31st transistor M31, the 35th transistor M35, the 30th two-transistor M32, the 34th Transistor M34, the 33rd transistor M33, the 36th transistor M36 connected mode and working method, are referred to Fig. 8 The description of middle scanning element, the functional module of same names, the transistor of same names, its connected mode and working method, work Make mutually reference between principle all same, embodiment, repeat no more here.

Various pieces are described by the way of progressive in this specification, and what each some importance illustrated is and other parts Difference, between various pieces identical similar portion mutually referring to.

The foregoing description of the disclosed embodiments, enables professional and technical personnel in the field to realize or using the present invention. A variety of modifications to these embodiments will be apparent for those skilled in the art, as defined herein General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, it is of the invention Embodiment illustrated herein is not intended to be limited to, and is to fit to consistent with principles disclosed herein and features of novelty Most wide scope.

Claims

1. a kind of gate driving circuit, it is characterised in that the gate driving circuit includes n grades of scanning elements, the n grades of scanning Unit is first order scanning element to n-th grade of scanning element, and n is the integer not less than 2；Wherein, include per one-level scanning element： First sub- scanning element, the second sub- scanning element, first voltage end, second voltage end, tertiary voltage end；

Wherein, the described first sub- scanning element includes：First control end, the second control end, the first input module, the first pull-up section Point, the first pull-up control module, the first pull-down node, the first drop-down control module, the first drop-down generation module, the first output mould Block, the first output end, the first signal end, the first clock signal terminal, the first control module；

The second sub- scanning element includes：3rd control end, the 4th control end, the second input module, the second pull-up node, Two pull-up control modules, the second pull-down node, the second drop-down control module, the second drop-down generation module, the second output module, the Two output ends, secondary signal end, second clock signal end, the second control module；

Wherein, first input module and controls the first voltage end and institute in response to the current potential of first control end State the on-state between the first pull-up node, and control the tertiary voltage end respectively with first pull-down node and institute The on-state of the second pull-down node is stated, and in response to the current potential of the second control end, and control second voltage end and described the The on-state of one pull-up node, wherein, the level at the first voltage end and the second voltage end is opposite；

Described first pulls up current potential of the control module in response to first pull-up node, and controls the tertiary voltage end to distinguish With the on-state of first pull-down node, the first drop-down generation module and the second drop-down generation module；

Described first pulls down current potential of the control module in response to first pull-down node, and controls the tertiary voltage end to distinguish With first pull-up node, first output module, first output end, second pull-up node, described second The on-state of output module, second output end；

It is described first drop-down generation module in response to first signal end current potential, and control first signal end with it is described The on-state of first pull-down node, wherein, in the described first pull-up control module in response to the first pull-up node current potential, And control the tertiary voltage end to be pulled down respectively with first pull-down node, described first under generation module and described second When drawing generation module connection, the current potential of first pull-down node and the second pull-down node is the current potential at the tertiary voltage end；

First output module and controls first clock signal terminal and institute in response to the current potential of first pull-up node State the on-state of the first output end；

First control module and controls the tertiary voltage end and described first in response to the current potential at the second voltage end The on-state of output end；

Second input module and controls the first voltage end and described second in response to the current potential of the 3rd control end The on-state of pull-up node, and in response to the current potential of the 4th control end, and control second voltage end to be pulled up with described second The on-state of node；

Described second pulls up current potential of the control module in response to second pull-up node, and controls the tertiary voltage end to distinguish With the on-state of second pull-down node, the second drop-down generation module and the first drop-down generation module；

Described second pulls down current potential of the control module in response to second pull-down node, and controls the tertiary voltage end to distinguish With second pull-up node, second output module, second output end, first pull-up node, described first The on-state of output module, first output end；

It is described second drop-down generation module in response to the secondary signal end current potential, and control the secondary signal end with it is described The on-state of second pull-down node, wherein, in electricity of the described second pull-up control module in response to second pull-up node Position, and control the tertiary voltage end to pull down generation module and described first with second pull-down node, described second respectively When pulling down generation module connection, the current potential of second pull-down node and the first pull-down node is the electricity at the tertiary voltage end Position；

Second output module and controls the second clock signal end and institute in response to the current potential of second pull-up node State the on-state of the second output end；

Second control module and controls the tertiary voltage end and described second in response to the current potential at the second voltage end The on-state of output end；

Wherein, in the display stage, first control module is in response to the low potential at the second voltage end, control the described 3rd Disconnect between voltage end and first output end, in the touch-control stage, first control module is in response to the described second electricity The high potential of pressure side, controls to connect between the tertiary voltage end and first output end；

In the display stage, second control module controls the tertiary voltage in response to the low potential at the second voltage end Disconnect between end and second output end, in the touch-control stage, second control module is in response to the second voltage end High potential, control to connect between the tertiary voltage end and second output end.

2. gate driving circuit according to claim 1, it is characterised in that the tertiary voltage end includes the first sub- voltage End and the second sub- voltage end, wherein, the voltage of the second sub- voltage end is less than or equal to the voltage of the described first sub- voltage end.

3. gate driving circuit according to claim 2, it is characterised in that first control module includes：20th Seven transistors, the grid of the 27th transistor is electrically connected to the second voltage end, and first end is electrically connected to described One sub- voltage end, the second end is electrically connected to first output end；

Second control module includes：28th transistor, the grid of the 28th transistor is electrically connected to described Second voltage end, first end electrically connects the first sub- voltage end, and the second end is electrically connected to second output end.

4. gate driving circuit according to claim 3, it is characterised in that the first drop-down control module includes：The Five transistors, the 6th transistor, the 14th transistor and the 16th transistor；

The grid of 5th transistor is electrically connected to first pull-down node, and first end is electrically connected to the described second sub- voltage End, the second end is electrically connected to first pull-up node；

The grid of 6th transistor is electrically connected to first pull-down node, and first end is electrically connected to the described first sub- voltage End, the second end is electrically connected to first output end；

The grid of 14th transistor is electrically connected to first pull-down node, and first end is electrically connected to the first son electricity Pressure side, the second end is electrically connected to second output end；

The grid of 16th transistor is electrically connected to first pull-down node, and first end is electrically connected to the second son electricity Pressure side, the second end is electrically connected to second pull-up node；

The second drop-down control module includes：7th transistor, the 8th transistor, the 17th transistor and the 18th crystal Pipe；

The grid of 7th transistor is electrically connected to second pull-down node, and first end is electrically connected to the described second sub- voltage End, the second end is electrically connected to first pull-up node；

The grid of 8th transistor is electrically connected to second pull-down node, and first end is electrically connected to the described first sub- voltage End, the second end is electrically connected to first output end；

The grid of 17th transistor is electrically connected to second pull-down node, and first end is electrically connected to the first son electricity Pressure side, the second end is electrically connected to second output end；

The grid of 18th transistor is electrically connected to second pull-down node, and first end is electrically connected to the second son electricity Pressure side, the second end is electrically connected to second pull-up node.

5. gate driving circuit according to claim 4, it is characterised in that the first sub- scanning element also includes：The One cascade output end and the first cascade output module；

The first cascade output module controls first clock signal terminal in response to the current potential of first pull-up node With the on-state of the described first cascade output end；

Described second cascades current potential of the output module in response to second pull-up node, and controls the second clock signal end With the on-state of the described second cascade output end.

6. gate driving circuit according to claim 5, it is characterised in that the first drop-down control module also includes： 31st transistor and the 35th transistor；

The grid of 31st transistor is electrically connected to first pull-down node, and first end is electrically connected to second son Voltage end, the second end is electrically connected to the first cascade output end；

The grid of 35th transistor is electrically connected to first pull-down node, and first end is electrically connected to second son Voltage end, the second end is electrically connected to the second cascade output end；

The grid of 30th two-transistor is electrically connected to second pull-down node, and first end is electrically connected to second son Voltage end, the second end is electrically connected to the first cascade output end；

The grid of 35th transistor is electrically connected to second pull-down node, and first end is electrically connected to second son Voltage end, the second end is electrically connected to the second cascade output end.

7. gate driving circuit according to claim 6, it is characterised in that the first cascade output module includes the 3rd 13 transistors, the grid of the 33rd transistor is electrically connected to first pull-up node, the 33rd crystal The first end of pipe is electrically connected to first clock signal terminal, and the second end is electrically connected to the first cascade output end；

The second cascade output module includes the 36th transistor, and the grid of the 36th transistor is electrically connected to institute The second pull-up node is stated, the first end of the 36th transistor is electrically connected to the second clock signal end, the second end electricity It is connected to the second cascade output end.

8. gate driving circuit according to claim 3, it is characterised in that described also to include resetting per one-level scanning element Signal end, the first sub- scanning element also includes the 3rd control module, and the second sub- scanning element also includes the 4th control Module；

3rd control module and controls the described second sub- voltage end and described the in response to the current potential at the reset signal end The on-state of one pull-up node；

4th control module and controls the described second sub- voltage end and described the in response to the current potential at the reset signal end The on-state of two pull-up nodes.

9. gate driving circuit according to claim 8, it is characterised in that the 3rd control module includes the 29th Transistor, the grid of the 29th transistor is electrically connected to the reset signal end, the of the 29th transistor One end is electrically connected to the described second sub- voltage end, and the second end is electrically connected to first pull-up node；

And, the 4th control module includes the 30th transistor, and the grid of the 30th transistor is electrically connected to described Reset signal end, the first end of the 30th transistor is electrically connected to the described second sub- voltage end, and the second end is electrically connected to institute State the second pull-up node.

10. the gate driving circuit according to claim any one of 1-9, it is characterised in that the first input module bag Include the first transistor, second transistor, third transistor and the 23rd transistor；

The grid of the first transistor is electrically connected to first control end, and the first end of the first transistor is electrically connected to The first voltage end, the second end is electrically connected to first pull-up node；

The grid of the second transistor is electrically connected to second control end, and the second transistor first end is electrically connected to institute Second voltage end is stated, the second end is electrically connected to first pull-up node；

The grid of the third transistor is electrically connected to first control end, and the first end of the third transistor is electrically connected to The second sub- voltage end, the second end is electrically connected to first pull-down node；

The grid of 23rd transistor is electrically connected to first control end, the first end of the 23rd transistor The described second sub- voltage end is electrically connected to, the second end is electrically connected to second pull-down node；

The grid of 26th transistor is electrically connected to the 4th control end, the first of the 26th transistor End is electrically connected to the second voltage end, and the second end is electrically connected to second pull-up node.

11. gate driving circuit according to claim 10, it is characterised in that the first pull-up control module includes： 4th transistor, the 13rd transistor and the 20th two-transistor；

The grid of 4th transistor is electrically connected to first pull-up node, the first end electrical connection of the 4th transistor To the described second sub- voltage end, the second end is electrically connected to first pull-down node；

The grid of 13rd transistor is electrically connected to first pull-up node, the first end electricity of the 13rd transistor The described second sub- voltage end is connected to, the second end is electrically connected to the first drop-down generation module；

The grid of 20th two-transistor is electrically connected to first pull-up node, the first of the 20th two-transistor End is electrically connected to the described second sub- voltage end, and the second end is electrically connected to the second drop-down generation module；

And, the second pull-up control module includes：Tenth two-transistor, the 20th transistor and the 21st transistor；

The grid of tenth two-transistor is electrically connected to second pull-up node, the first end electricity of the tenth two-transistor The described second sub- voltage end is connected to, the second end is electrically connected to first time generation module；

The grid of 20th transistor is electrically connected to second pull-up node, the first end electricity of the 20th transistor The described second sub- voltage end is connected to, the second end is electrically connected to the second drop-down generation module；

The grid of 21st transistor is electrically connected to second pull-up node, the first of the 21st transistor End is electrically connected to the described second sub- voltage end, and the second end is electrically connected to second pull-down node.

12. gate driving circuit according to claim 11, it is characterised in that the first drop-down generation module includes： Tenth transistor and the 11st transistor；

The grid and first end of tenth transistor are electrically connected to first signal end, the second of the tenth transistor End is electrically connected to the second end of the tenth two-transistor and the second end of the 13rd transistor simultaneously；

The grid of 11st transistor is electrically connected to the second end of the tenth transistor, first end electrical connection described first Signal end, the second end electrically connects first pull-down node；

The grid and first end of 24th transistor are electrically connected to the secondary signal end, the 24th crystal Second end of pipe is electrically connected to the second end of the 20th two-transistor and the second end of the 20th transistor simultaneously；

The grid of 19th transistor is electrically connected to the second end of the 24th transistor, and first end electrical connection is described Secondary signal end, the second end electrically connects second pull-down node.

13. gate driving circuit according to claim 12, it is characterised in that the 13rd transistor and the 12nd crystalline substance The breadth length ratio of body pipe is all higher than the breadth length ratio of the tenth transistor, the width of the 20th transistor and the 20th two-transistor The long breadth length ratio than more than the 24th transistor.

14. gate driving circuit according to claim 13, it is characterised in that it is brilliant that first output module includes the 9th Body pipe and the first bootstrap capacitor, second output module include the 15th transistor and the second bootstrap capacitor；

The grid of 9th transistor and the first pole plate of first bootstrap capacitor are electrically connected to the first pull-up section Point, the first end of the 9th transistor is electrically connected to first clock signal terminal, the second end of the 9th transistor and Second pole plate of first bootstrap capacitor is electrically connected to first output end；

The grid of 15th transistor and the first pole plate of second bootstrap capacitor are electrically connected to second pull-up Node, the first end of the 15th transistor is electrically connected to the second clock signal end, the of the 15th transistor Second pole plate of two ends and second bootstrap capacitor is electrically connected to second output end.

15. gate driving circuit according to claim 1, it is characterised in that scanning element described in defining adjacent two-stage is I-stage scanning element and i+1 level scanning element, i is no more than n positive integer；

First control end of the first output end of the i-stage scanning element and the i+1 level scanning element is connected, and described the First output end of i+1 grades of scanning elements is connected with the second control end of the i-stage scanning element；

3rd control end of the second output end of the i-stage scanning element and the i+1 level scanning element is connected, and described the Second output end of i+1 grades of scanning elements is connected with the 4th control end of the i-stage scanning element；

And, the first clock signal terminal of scanning element described in odd level is same signal end and second clock signal end is same One signal end, the first clock signal terminal of scanning element described in even level is same signal end and second clock signal end is same One signal end.

16. gate driving circuit according to claim 15, it is characterised in that when the described first sub- scanning element also includes First cascade output end, when the second sub- scanning element also includes the second cascade output end, the first order of the i-stage scanning element Connection output end is connected with the first control end of i+1 level scanning element, and the first cascade of the i+1 level scanning element is defeated Go out end with the second control end of the i-stage scanning element to be connected；Second cascade output end of the i-stage scanning element and institute The 3rd control end for stating i+1 level scanning element is connected, the second cascade output end of i+1 level scanning element and described the 4th control end of i grades of scanning elements is connected.

17. a kind of gate driving circuit, it is characterised in that the gate driving circuit includes n grades of scanning elements, and described n grades is swept It is first order scanning element to n-th grade of scanning element to retouch unit, and n is the integer not less than 2；Wherein, per one-level scanning element bag Include：First sub- scanning element, the second sub- scanning element, first voltage end, second voltage end, tertiary voltage end, control node；

The first sub- scanning element includes：First control end, the second control end, the first input module, the first pull-up node, One pull-up control module, the first pull-down node, the first drop-down control module, the first drop-down generation module, the first output module, the One output end, the first signal end, the first clock signal terminal, the first control module, the 5th control module；

The second sub- scanning element includes：3rd control end, the 4th control end, the second input module, the second pull-up node, Two pull-up control modules, the second pull-down node, the second drop-down control module, the second drop-down generation module, the second output module, the Two output ends, secondary signal end, second clock signal end, the second control module, the 6th control module；

Wherein, first input module and controls the first voltage end and institute in response to the current potential of first control end The on-state between the first pull-up node, and the control first voltage end and the on-state of the control node are stated, And in response to the current potential of the second control end, and the on-state at second voltage end and first pull-up node is controlled, wherein, The level at the first voltage end and the second voltage end is opposite；

Described first pulls down current potential of the control module in response to first pull-down node, and controls the tertiary voltage end to distinguish With the control node, first pull-up node, first output module, first output end, second pull-up Node, second output module, the on-state of second output end；

5th control module and is controlled under the tertiary voltage end and described first in response to the current potential of the control node Draw the on-state of node；

Second input module and controls the first voltage end and described second in response to the current potential of the 3rd control end The on-state of pull-up node, and in response to the current potential of the 4th control end, and control second voltage end to be pulled up with described second The on-state of node and the control node；

Described second pulls down current potential of the control module in response to second pull-down node, and controls the tertiary voltage end to distinguish With the control node, the second pull-up node, second output module, second output end, first pull-up node, The on-state of first output module, first output end；

6th control module and is controlled under the tertiary voltage end and described second in response to the current potential of the control node Draw the on-state of node；

18. gate driving circuit according to claim 17, it is characterised in that the tertiary voltage end includes the first son electricity Pressure side and the second sub- voltage end, wherein, the voltage of the second sub- voltage end is less than or equal to the electricity of the described first sub- voltage end Pressure.

19. gate driving circuit according to claim 18, it is characterised in that first control module includes：Second 17 transistors, the grid of the 27th transistor is electrically connected to the second voltage end, and first end is electrically connected to described First sub- voltage end, the second end is electrically connected to first output end；

20. gate driving circuit according to claim 19, it is characterised in that the 5th control module includes the 30th Nine transistors, the grid of the 39th transistor is electrically connected to the control node, and first end is electrically connected to described second Sub- voltage end, the second end is electrically connected to first pull-up node；

And, the 6th control module includes the 40th transistor, and the grid of the 40th transistor is electrically connected to described Control node, first end is electrically connected to the described second sub- voltage end, and the second end is electrically connected to second pull-up node.

21. gate driving circuit according to claim 20, it is characterised in that the first drop-down control module bag Include：5th transistor, the 6th transistor, the 14th transistor, the 16th transistor and the 41st transistor；

The grid of 41st transistor is electrically connected to first pull-down node, and first end is electrically connected to second son Voltage end, the second end is electrically connected to the control node；

The second drop-down control module includes：7th transistor, the 8th transistor, the 17th transistor, the 18th transistor With the 40th two-transistor；

The grid of 18th transistor is electrically connected to second pull-down node, and first end is electrically connected to the second son electricity Pressure side, the second end is electrically connected to second pull-up node；

The grid of 40th two-transistor is electrically connected to second pull-down node, and first end is electrically connected to second son Voltage end, the second end is electrically connected to the control node.

22. gate driving circuit according to claim 21, it is characterised in that the first sub- scanning element also includes： First cascade output end and the first cascade output module；

23. gate driving circuit according to claim 22, it is characterised in that the first drop-down control module is also wrapped Include：31st transistor and the 35th transistor；

24. gate driving circuit according to claim 23, it is characterised in that the first cascade output module includes the 33 transistors, the grid of the 33rd transistor is electrically connected to first pull-up node, and the described 33rd is brilliant The first end of body pipe is electrically connected to first clock signal terminal, and the second end is electrically connected to the first cascade output end；

25. gate driving circuit according to claim 19, it is characterised in that described also to include again per one-level scanning element Position signal end, the first sub- scanning element also includes the 3rd control module, and the second sub- scanning element also includes the 4th control Molding block；

26. gate driving circuit according to claim 25, it is characterised in that the 3rd control module includes the 20th Nine transistors, the grid of the 29th transistor is electrically connected to the reset signal end, the 29th transistor First end is electrically connected to the described second sub- voltage end, and the second end is electrically connected to first pull-up node；

27. gate driving circuit according to claim 19, it is characterised in that the first sub- scanning element also includes the Seven control modules, the second sub- scanning element also includes the 8th control module；

7th control module and controls the described second sub- voltage end and the control in response to the current potential of first output end The on-state of node processed；

8th control module and controls the described second sub- voltage end and the control in response to the current potential of second output end The on-state of node processed.

28. gate driving circuit according to claim 27, it is characterised in that the 7th control module includes the 40th Three transistors, the grid of the 43rd transistor is electrically connected to first output end, and first end is electrically connected to described Two sub- voltage ends, the second end is electrically connected to the control node；

And, the 8th control module includes the 44th transistor, and the grid of the 44th transistor is electrically connected to Second output end, first end is electrically connected to the described second sub- voltage end, and the second end is electrically connected to the control node.

29. the gate driving circuit according to claim any one of 17-28, it is characterised in that first input module Including the first transistor, second transistor and the 37th transistor；

The grid of the first transistor is electrically connected to first control end, and first end is electrically connected to the first voltage end, Second end is electrically connected to first pull-up node；

The grid of the second transistor is electrically connected to second control end, and first end is electrically connected to the second voltage end, Second end is electrically connected to first pull-up node；

The grid of 37th transistor is electrically connected to first control end, and first end is electrically connected to the first voltage End, the second end is electrically connected to the control node；

And, second input module includes the 25th transistor, the 26th transistor and the 38th transistor；

The grid of 25th transistor is electrically connected to the 3rd control end, and first voltage end, the second end is electrically connected to Second pull-up node；

The grid of 26th transistor is electrically connected to the 4th control end, and first end is electrically connected to the second voltage End, the second end is electrically connected to second pull-up node；

The grid of 38th transistor is electrically connected to the 4th control end, and first end is electrically connected to the second voltage End, the second end is electrically connected to the control node.

30. gate driving circuit according to claim 29, it is characterised in that the first pull-up control module includes： 4th transistor, the 13rd transistor and the 20th two-transistor；

31. gate driving circuit according to claim 30, it is characterised in that the first drop-down generation module includes： Tenth transistor and the 11st transistor；

32. gate driving circuit according to claim 31, it is characterised in that the 13rd transistor and the 12nd crystalline substance The breadth length ratio of body pipe is all higher than the breadth length ratio of the tenth transistor, the width of the 20th transistor and the 20th two-transistor The long breadth length ratio than more than the 24th transistor.

33. gate driving circuit according to claim 32, it is characterised in that it is brilliant that first output module includes the 9th Body pipe and the first bootstrap capacitor, second output module include the 15th transistor and the second bootstrap capacitor；