CN107132811B

CN107132811B - Signal acquisition processing device, method and system

Info

Publication number: CN107132811B
Application number: CN201710510964.4A
Authority: CN
Inventors: 南钢洋; 赵扬; 王启武; 郭锐; 张振振; 巨阳
Original assignee: Laser Institute of Shandong Academy of Science
Current assignee: Laser Institute of Shandong Academy of Science
Priority date: 2017-06-28
Filing date: 2017-06-28
Publication date: 2023-07-14
Anticipated expiration: 2037-06-28
Also published as: CN107132811A

Abstract

The invention provides a signal acquisition processing device, a signal acquisition processing method and a signal acquisition processing system, and belongs to signal acquisition processing devices. The signal acquisition processing device comprises: the system comprises a processing module, a programmable control module, a conversion module and at least two paths of signal acquisition modules, wherein each path of signal acquisition module is coupled with the conversion module, the programmable control module is respectively coupled with the conversion module and the processing module, and the processing module is used for being coupled with terminal equipment. The data signal is acquired by at least two paths of signal acquisition modules, and the programmable control module and the processing module are matched to work, so that the sampling rate of data acquisition and processing is effectively improved.

Description

Signal acquisition processing device, method and system

Technical Field

The invention relates to the technical field of power electronic equipment, in particular to a signal acquisition processing device, a signal acquisition processing method and a signal acquisition processing system.

Background

With the development of science and technology, the power electronic equipment is improved by the development of the great extent, and the data acquisition and processing technology is widely applied.

In the existing data acquisition and processing technology, the acquisition and processing of data can be realized through PCI bus technology, DSP technology, FPGA technology or ARM technology. However, in the above-described technique, although the acquisition processing of data can be realized, the sampling rate is low, and is generally within 50 MSPS. With the improvement of the operation performance of the equipment, the data volume required by the operation of the equipment is also larger and larger, and the sampling rate within 50MSPS gradually cannot meet the actual requirement.

Therefore, how to effectively increase the sampling rate of the data acquisition process is a great problem in the industry.

Disclosure of Invention

Accordingly, the present invention is directed to a signal acquisition and processing device, method and system for improving the above-mentioned drawbacks.

Embodiments of the present invention are achieved by:

in a first aspect, an embodiment of the present invention provides a signal acquisition processing apparatus, which is applied to a signal acquisition processing system, where the signal acquisition processing system includes: the terminal equipment, the signal acquisition processing device includes: the system comprises a processing module, a programmable control module, a conversion module and at least two signal acquisition modules. Each path of signal acquisition module is coupled with the conversion module, the programmable control module is respectively coupled with the conversion module and the processing module, and the processing module is used for being coupled with the terminal equipment. The programmable control module is used for controlling the conversion module to acquire the data signals acquired by each path of signal acquisition module and sending the data signals acquired by the conversion module to the processing module according to a preset rate. The processing module is used for generating acquisition data according to the data signals and sending the acquisition data to the terminal equipment according to the preset rate.

In a second aspect, an embodiment of the present invention provides a signal acquisition processing method, which is applied to the signal acquisition processing device. The method comprises the following steps: the programmable control module controls the conversion module to acquire data signals acquired by each path of signal acquisition module, and sends the data signals acquired by the conversion module to the processing module at a preset rate; and the processing module generates acquisition data according to the data signals and sends the acquisition data to the terminal equipment according to a preset rate.

In a third aspect, an embodiment of the present invention provides a signal acquisition processing system, including: the system comprises terminal equipment and the signal acquisition and processing device, wherein the signal acquisition and processing device is coupled with the terminal equipment.

The embodiment of the invention has the beneficial effects that:

the data signals are acquired through at least two paths of signal acquisition modules and output to the conversion module, and the conversion module can efficiently acquire the data signals. The conversion module can send the data signals after analog-to-digital conversion to the programmable control module according to a preset rate through the control of the programmable control module to enable the programmable control module to send the data signals to the processing module according to the preset rate, so that the processing module generates acquisition data according to the data signals and sends the acquisition data to the terminal equipment according to the preset rate. Therefore, the sampling rate of data acquisition and processing is effectively improved through the acquisition of data signals by at least two paths of signal acquisition modules and the cooperation of the programmable control module and the processing module.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the embodiments of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims thereof as well as the appended drawings.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. The above and other objects, features and advantages of the present invention will become more apparent from the accompanying drawings. Like reference numerals refer to like parts throughout the several views of the drawings. The drawings are not intended to be drawn to scale, with emphasis instead being placed upon illustrating the principles of the invention.

Fig. 1 shows a block diagram of a signal acquisition processing system according to an embodiment of the present invention;

Fig. 2 shows a block diagram of a signal acquisition processing device according to an embodiment of the present invention;

fig. 3 shows a circuit diagram of a filtering unit in a signal acquisition processing device according to an embodiment of the present invention;

fig. 4 shows a circuit diagram of a signal acquisition module and a clamp protection circuit in a signal acquisition processing device according to an embodiment of the present invention;

fig. 5 shows a circuit diagram of a first clamp power supply circuit in a signal acquisition processing device according to an embodiment of the present invention;

fig. 6 shows a circuit diagram of a second clamp power supply circuit in a signal acquisition processing device according to an embodiment of the present invention;

fig. 7 shows a circuit diagram of a common mode reference voltage module in a signal acquisition processing device according to an embodiment of the present invention;

fig. 8 shows a circuit diagram of a conversion module in a signal acquisition processing device according to an embodiment of the present invention;

fig. 9 shows a circuit diagram of a clock signal unit in a signal acquisition processing device according to an embodiment of the present invention;

fig. 10 shows a circuit diagram of a power supply unit in a signal acquisition processing device according to an embodiment of the present invention;

fig. 11 shows a circuit diagram of a temperature detection module in a signal acquisition processing device according to an embodiment of the present invention;

Fig. 12 shows a flowchart of a signal acquisition processing method according to an embodiment of the present invention.

Icon: 10-a signal acquisition and processing system; 11-terminal equipment; 100-a signal acquisition and processing device; 110-a power module; a 111-filtering unit; 112-a step-down unit; 120-a signal acquisition module; 121-a first signal acquisition module; 122-a second signal acquisition module; 130-a clamp protection module; 131-a first clamp supply circuit; 132-a second clamp supply circuit; 133-clamp protection circuitry; 140-a common mode reference voltage module; a 150-conversion module; 151-a radio frequency transformation unit; a 152-converting unit; 160-a programmable control module; 161-a clock signal unit; 162-a power supply unit; 163-array of programmable logic gates; 170-a temperature detection module; 180-a processing module; 181-a processing unit; 182-communication unit.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Furthermore, the terms "first," "second," and the like, are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.

Referring to fig. 1, an embodiment of the present invention provides a signal acquisition processing system 10, where the signal acquisition processing system 10 includes: a terminal device 11 and a signal acquisition processing device 100.

The signal acquisition processing device 100 is configured to perform high-efficiency and high-speed acquisition on a data signal through at least two acquisition channels, and generate acquisition data from the acquired data signal through analog-to-digital conversion and according to the data signal after the analog-to-digital conversion. The signal acquisition processing device 100 stores or transmits the generated acquisition data to the terminal device 11 through coupling with the terminal device 11.

The terminal device 11 may be a personal computer (personal computer, PC), tablet computer, smart phone, personal digital assistant (personal digital assistant, PDA), or the like. In this embodiment, the terminal device 11 acquires the acquired data sent by the signal acquisition processing device 100, and the terminal device 11 can implement program operation according to the acquired data, or store and display the acquired data.

Referring to fig. 2, an embodiment of the present invention provides a signal acquisition and processing apparatus 100, where the signal acquisition and processing apparatus 100 includes: the device comprises a power module 110, at least two signal acquisition modules 120, a clamp protection module 130, a common mode reference voltage module 140, a conversion module 150, a programmable control module 160, a temperature detection module 170 and a processing module 180.

The power module 110 is configured to perform voltage stabilization and voltage reduction on electric energy obtained from an external power supply through a voltage stabilizing chip for multiple times, so as to output electric energy adapting to voltage values of each module to each coupled module, so as to ensure normal operation of each module.

Each signal acquisition module 120 is configured to acquire a data signal, amplify the acquired data signal, and output the amplified data signal to the conversion module 150.

The clamping protection module 130 is configured to clamp the voltage of the data signal output by each signal acquisition module 120 to a preset voltage range, so as to protect the conversion module 150 from working normally.

The common mode reference voltage module 140 is configured to amplify the reference electrical signal obtained by the conversion module 150 into a preset reference voltage signal, and load the preset reference voltage signal to the reference voltage end of each signal acquisition module 120 respectively, so as to ensure the normal operation of each signal acquisition module 120.

The conversion module 150 is configured to output the data signals obtained by each signal acquisition module 120 to the programmable control module 160 at a preset rate after analog-to-digital conversion according to the control of the programmable control module 160.

The programmable control module 160 is configured to control the conversion module 150 to obtain the data signal collected by each signal collection module 120, and send the data signal obtained by the conversion module 150 to the processing module 180 at a preset rate.

The temperature detection module 170 is configured to obtain a temperature signal when the signal acquisition processing apparatus 100 is in operation, and send the obtained temperature signal to the processing module 180.

The processing module 180 is configured to generate collected data according to the data signal, revise the collected data generated according to the data signal according to the acquired temperature signal, and send the revised collected data to the terminal device 11 at a preset rate.

Referring to fig. 2 and 3, the power module 110 includes: a filter unit 111 and a step-down unit 112; the filtering unit 111 is coupled to the external power source, the voltage step-down unit 112, the common mode reference voltage module 140 and each signal acquisition module 120, and the voltage step-down unit 112 is coupled to the clamp protection module 130, the conversion module 150, the programmable control module 160, the temperature detection module 170 and the processing module 180, respectively.

In this embodiment, the filtering unit 111 is configured to obtain electric energy of an external power source, filter the electric energy by a pi-type filtering circuit, and step down and output the electric energy to the step-down unit 112, the common mode reference voltage module 140 and each signal acquisition module 120.

Specifically, in the filtering unit 111:

the first power strip P1 is configured to obtain electric energy of an external power source. The 4 pins of the first socket P1 are coupled to one end of the first capacitor C1 and one end of the first FUSE1, respectively. The other end of the first capacitor C1 is grounded to both the 2 pins and the 3 pins of the first row of pins P1. The other end of the first FUSE1 is coupled to one end of the first inductor L1. The other end of the first inductor L1 is coupled to one end of the second capacitor C2, one end of the third capacitor C3 and one end of the fourth capacitor C4, respectively, and the other end of the second capacitor C2, the other end of the third capacitor C3 and the other end of the fourth capacitor C4 are grounded. The anode terminal of the first diode D1 and the anode terminal of the second diode D2 are both coupled to the other end of the fourth capacitor C4, and are provided with a connection terminal A1. The cathode end of the first diode D1 is provided with a connecting terminal A2, and the cathode end of the second diode D2 is provided with a connecting terminal A3. The 1 pin of the first row socket P1 is coupled to one end of the fifth capacitor C5 and one end of the second FUSE2, respectively. The other end of the fifth capacitor C5 is grounded, and the other end of the second FUSE2 is coupled to one end of the second inductor L2. The other end of the second inductor L2 is coupled to one end of the sixth capacitor C6, one end of the seventh capacitor C7 and one end of the eighth capacitor C8, respectively, and the other end of the sixth capacitor C6, the other end of the seventh capacitor C7 and the other end of the eighth capacitor C8 are grounded. One end of the first resistor R1 is coupled to the other end of the eighth capacitor C8, and a connection terminal A4 is provided, the other end of the first resistor R1 is coupled to the cathode end of the first light emitting diode D3, and the anode end of the first light emitting diode D3 is grounded.

Through the coupling relation, the 4 pins of the first row of power strip P1 acquire and output 5V voltage signals. The first inductor L1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 form a first pi-type filter circuit to decouple the 5V voltage signal and reduce ripple noise in the 5V voltage signal. The decoupled 5V voltage signal is output to the common mode reference voltage module 140 and each signal acquisition module 120 through the connection terminal A1. Further, the voltage of the 5V voltage signal is reduced to 4.3V by the rated on-voltage of the first diode D1 and the second diode D2, and is outputted to the voltage reducing unit 112 through both the connection terminal A2 and the connection terminal A3. The 4.3V voltage signal output by the connection terminal A2 is independently used for supplying power for a microprocessor in the sampling control device. The 1 pin of the first row of socket P1 acquires and outputs a voltage signal of-5V. The second inductor L1, the sixth capacitor C6, the seventh capacitor C7 and the eighth capacitor C8 constitute a second pi-type filter circuit to decouple the-5V voltage signal and reduce ripple noise in the-5V voltage signal. The decoupled-5V voltage signal is also output to the common mode reference voltage module 140 and each signal acquisition module 120 via connection terminal A4.

The voltage step-down unit 112 is configured to step down the voltage signal obtained by the filtering unit 111 multiple times to output voltage signals with different voltage values to the clamp protection module 130, the common mode reference voltage module 140, the conversion module 150, the programmable control module 160, and the processing module 180, respectively. As one way, the voltage reducing unit 112 may be a plurality of voltage reducing and stabilizing chips, for example: type 7805. The output terminal VOUT of each buck regulator chip may be coupled to the input terminal VIN of an adjacent buck regulator chip. The step-down unit 112 performs multi-step voltage reduction on the obtained 4.3V voltage signal through a plurality of step-down voltage stabilizing chips. Alternatively, the voltage decreasing unit 112 sequentially decreases the 4.3V voltage signal to 3.3V, 2.5V, 1.8V, and 1.2V. The step-down unit 112 separately outputs a 3.3V voltage signal to the processing module 180 to power the processing module 180. The step-down unit 112 separately outputs the other 3.3V voltage signal and the 1.2V voltage signal to the programmable control module 160 to supply power to the programmable control module 160. In addition, the step-down unit 112 outputs a 1.8V voltage signal to the clamp protection module 130 and the conversion module 150 to ensure the normal operation of the clamp protection module 130 and the conversion module 150.

Referring to fig. 2 and 4, the at least two signal acquisition modules 120 are two signal acquisition modules, which are a first signal acquisition module 121 and a second signal acquisition module 122, respectively. The power supply end of the first signal acquisition module 121 and the power supply end of the second signal acquisition module 122 are both coupled to the power supply module 110, the output end of the first signal acquisition module 121 and the output end of the second signal acquisition module 122 are both coupled to the conversion module 150, and the output end of the first signal acquisition module 121 and the output end of the second signal acquisition module 122 are both coupled.

In the embodiment of the present invention, the first signal acquisition module 121 is configured to acquire a data signal, and amplify and output the acquired data signal to the conversion module 150.

Specifically, in the first signal acquisition module 121:

the 1 pin and the 2 pin of the first acquisition signal interface SMA1 are both coupled with the equipotential points, and the 3 pin of the first acquisition signal interface SMA1 are also both coupled with the equipotential points. One end of the second resistor R2 is coupled with the 5 pin of the first acquisition signal interface SMA1, and the other end of the second resistor R2 is coupled with one end of the third resistor R3 and one end of the ninth capacitor C9 respectively. The other end of the third resistor R3 is coupled to the equipotential point, and the other end of the ninth capacitor C9 is coupled to one end of the fourth resistor R4. The other end of the fourth resistor R4 is respectively coupled with one end of the fifth resistor R5 and the +IN pin of the first differential amplifier U1, wherein the first differential amplifier U1 is of an ADA4938-1 type. The other end of the fifth resistor R5 is coupled to the-FB pin of the first differential amplifier U1. Further, one end of the sixth resistor R6 is coupled to the equipotential point, and the other end of the sixth resistor R6 is coupled to one end of the seventh resistor R7 and one end of the tenth capacitor C10, respectively. The other end of the seventh resistor R7 is coupled to the equipotential point, and the other end of the tenth capacitor C10 is coupled to one end of the eighth resistor R8. The other end of the eighth resistor R8 is coupled to one end of the ninth resistor R9 and the +fb pin of the first differential amplifier U1, respectively. The other end of the ninth resistor R9 is coupled to the-IN pin of the first differential amplifier U1.

The EPAD pin of the first differential amplifier U1 is coupled to the equipotential point, and the VS 1-pin, the VS 2-pin, the VS 3-pin and the VS 4-pin of the first differential amplifier U1 are all coupled to the connection terminal B1. The +VS1 pin, +VS2 pin, +VS3 pin, +VS4 pin, and PD pin of the first differential amplifier U1 are coupled to the connection terminal B2. The reference voltage end VCOM of the first differential amplifier U1 is coupled to the connection terminal B3. The forward output terminal out+ of the first differential amplifier U1 is coupled to one end of the tenth resistor R10, and the other end of the tenth resistor R10 is coupled to one end of the eleventh resistor R11 and one end of the eleventh capacitor C11, respectively. The other end of the eleventh capacitor C11 is grounded, and the other end of the eleventh resistor R11 is coupled to the connection terminal B4. The reverse output OUT-of the first differential amplifier U1 is coupled to one end of a twelfth resistor R12, and the other end of the twelfth resistor R12 is coupled to one end of a thirteenth resistor R13 and one end of a twelfth capacitor C12, respectively. The other end of the twelfth capacitor C12 is grounded, and the other end of the thirteenth resistor R13 is coupled to the connection terminal B5.

Through the above coupling relationship, the first signal acquisition module 121 acquires a data signal through the first acquisition signal interface SMA1, outputs the data signal through the 5 pin of the first acquisition signal interface SMA1, and inputs the data signal to the +in pin and the-FB pin of the first differential amplifier U1. The first differential amplifier U1 acquires a voltage signal of-5V through the connection terminal B1, acquires a voltage signal of 5V through the connection terminal B2, and acquires a preset reference voltage through the connection terminal B3 to perform normal operation. The first differential amplifier U1 differentially amplifies the acquired data signal. The first differential amplifier U1 outputs the one-way data signal after differential amplification to the connection terminal B4 through the forward output terminal out+ to output the data signal to the conversion module 150 through the connection terminal B4. The first differential amplifier U1 also outputs the other data signal after differential amplification to the connection terminal B5 through the reverse output terminal OUT-, so that the data signal is also output to the conversion module 150 through the connection terminal B5.

In the embodiment of the present invention, the second signal acquisition module 122 is configured to acquire a data signal, and also amplify and output the acquired data signal to the conversion module 150.

Specifically, in the second signal acquisition module 122:

the 1 pin and the 2 pin of the second acquisition signal interface SMA2 are both coupled with the equipotential point, and the 3 pin of the second acquisition signal interface SMA1 are both coupled with the equipotential point. One end of the fourteenth resistor R14 is coupled with the 5 pin of the second acquisition signal interface SMA1, and the other end of the fourteenth resistor R14 is coupled with one end of the fifteenth resistor R15 and one end of the thirteenth capacitor C13 respectively. The other end of the fifteenth resistor R15 is coupled to the equipotential point, and the other end of the thirteenth capacitor C13 is coupled to one end of the sixteenth resistor R16. The other end of the sixteenth resistor R16 is respectively coupled with one end of the seventeenth resistor R17 and the +in pin of the second differential amplifier U2, wherein the second differential amplifier U2 is also of the ADA4938-1 type. The other end of the seventeenth resistor R17 is coupled to the-FB pin of the second differential amplifier U2. Further, one end of the eighteenth resistor R18 is coupled to the equipotential point, and the other end of the eighteenth resistor R18 is coupled to one end of the nineteenth resistor R19 and one end of the fourteenth capacitor C14, respectively. The other end of the nineteenth resistor R19 is coupled to the equipotential point, and the other end of the fourteenth capacitor C14 is coupled to one end of the twentieth resistor R20. The other end of the twenty-first resistor R20 is coupled to one end of the twenty-first resistor R21 and the +fb pin of the second differential amplifier U2, respectively. The other end of the twenty-first resistor R21 is coupled to the-IN pin of the second differential amplifier U2.

The EPAD pin of the second differential amplifier U2 is coupled to the equipotential point, and the VS 1-pin, the VS 2-pin, the VS 3-pin and the VS 4-pin of the second differential amplifier U2 are all coupled to the connection terminal C1. The +VS1 pin, +VS2 pin, +VS3 pin, +VS4 pin and PD pin of the second differential amplifier U2 are coupled to the connection terminal C2. The reference voltage end VCOM of the second differential amplifier U2 is coupled to the connection terminal C3. The forward output terminal out+ of the second differential amplifier U2 is coupled to one end of the twenty-second resistor R22, and the other end of the twenty-second resistor R22 is coupled to one end of the twenty-third resistor R23 and one end of the fifteenth capacitor C15, respectively. The other end of the fifteenth capacitor C15 is grounded, and the other end of the twenty-third resistor R23 is coupled to the connection terminal C4. The inverted output OUT-of the second differential amplifier U2 is coupled to one end of a twenty-fourth resistor R24, and the other end of the twenty-fourth resistor R24 is coupled to one end of a twenty-fifth resistor R25 and one end of a sixteenth capacitor C16, respectively. The other end of the sixteenth capacitor C16 is grounded, and the other end of the twenty-fifth resistor R25 is coupled to the connection terminal C5.

Through the above coupling relationship, the second signal acquisition module 122 acquires a data signal through the second acquisition signal interface SMA2, outputs the data signal through the 5 pin of the second acquisition signal interface SMA1, and inputs the data signal to the +in pin and the-FB pin of the second differential amplifier U2. The second differential amplifier U2 acquires a voltage signal of-5V through the connection terminal C1, acquires a voltage signal of 5V through the connection terminal C2, and acquires a preset reference voltage through the connection terminal C3 to perform normal operation. The second differential amplifier U2 differentially amplifies the acquired data signal. The second differential amplifier U2 outputs the one-way data signal after differential amplification to the connection terminal C4 through the forward output terminal out+ to output the data signal to the conversion module 150 through the connection terminal C4. The second differential amplifier U2 also outputs the other data signal after differential amplification to the connection terminal C5 through the reverse output terminal OUT-, so that the data signal is also output to the conversion module 150 through the connection terminal C5.

Referring to fig. 2 and 4, the clamp protection module 130 includes: a first clamp supply circuit 131, a second clamp supply circuit 132, and a clamp protection circuit 133. Wherein, the input terminal of the clamp protection module 130 is coupled to the power module 110, that is, the input terminal of the first clamp power supply circuit 131 and the input terminal of the second clamp power supply circuit 132 are both coupled to the power module 110. The output of the first clamp supply 131 and the output of the second clamp supply 132 are both coupled to a clamp protection circuit 133. The output end of the clamping protection module 130 is coupled to the output end of the first signal acquisition module 121 and the output end of the second signal acquisition module 122, respectively, that is, the clamping protection circuit 133 is coupled to the output end of the first signal acquisition module 121 and the output end of the second signal acquisition module 122, respectively.

As shown in fig. 2, 4 and 5, in the embodiment of the present invention, the first clamp power supply circuit 131 is configured to step down the voltage signal acquired by the power module 110 to a first preset voltage signal, and load the first preset voltage signal to the clamp protection circuit 133.

Specifically, in the first clamp power supply circuit 131:

one end of the seventeenth capacitor C17, one end of the eighteenth capacitor C18, and one end of the first inductor L1 are coupled to the connection terminal D1. The other end of the seventeenth capacitor C17 and the other end of the eighteenth capacitor C18 are both coupled to the equipotential point. The IN1 pin, the IN2 pin and the SHDN pin of the first low dropout linear regulator U3 (Low Dropout regulator, LDO) are all coupled to one end of the first inductor L1, and the other end of the first inductor L1 is coupled to the SW pin of the first low dropout linear regulator U3. The GND1 pin and the GND2 pin of the first low dropout linear regulator U3 are also both coupled to the equipotential point. The BST pin of the first low dropout linear regulator U3 is coupled to one end of a nineteenth capacitor C19. The PG pin of the first low dropout linear regulator U3 is coupled with one end of a twenty-sixth resistor R26, and the other end of the twenty-sixth resistor R26 is respectively coupled with the OUT1 pin and the OUT2 pin of the first low dropout linear regulator U3. One end of the twenty-seventh resistor R27 is coupled to the OUT1 pin and the OUT2 pin of the first low dropout linear regulator U3, respectively, and is provided with a connection terminal D2. One end of the twenty-eighth resistor R28 is coupled to the ADJ pin of the first low dropout linear regulator U3 and the other end of the twenty-seventh resistor R27, respectively. One end of the twentieth capacitor C20 and one end of the twenty-first capacitor C21 are both coupled to the connection terminal D2, and the other end of the nineteenth capacitor C19, the other end of the twentieth capacitor C20, and the other end of the twenty-first capacitor C21 are both coupled to the equipotential point.

Through the above coupling relationship, the connection terminal D1 acquires the 1.8V voltage signal output from the power module 110, and inputs the 1.8V voltage signal to the IN1 pin and the IN2 pin of the first low dropout linear regulator U3. The first low dropout linear regulator U3 performs voltage regulation output on a 1.8V voltage signal, divides the voltage by the twenty-seventh resistor R27 and the twenty-eighth resistor R28, filters the voltage by a capacitor, and outputs a voltage signal of a first preset voltage signal formed by the voltage division to the clamp protection circuit 133 through the connection terminal D2. Wherein the first preset voltage signal is 0.7V. In addition, the first low dropout linear regulator U3 has a small temperature drift coefficient and high working stability, and the voltage ripple of the output first preset voltage signal is small.

As shown in fig. 2, 4 and 6, in the embodiment of the present invention, the second clamp power supply circuit 132 is configured to step down the voltage signal acquired by the power module 110 to a second preset voltage signal, and load the second preset voltage signal to the clamp protection circuit 133.

Specifically, in the second clamp power supply circuit 132:

one end of the twenty-second capacitor C22, one end of the twenty-third capacitor C23, and one end of the second inductor L2 are coupled to the connection terminal E1. The other end of the twenty-second capacitor C22 and the other end of the twenty-third capacitor C23 are both coupled to the isoelectric point. The IN1 pin, the IN2 pin and the SHDN pin of the second low dropout linear regulator U4 are all coupled to one end of the second inductor L2, and the other end of the second inductor L2 is coupled to the SW pin of the second low dropout linear regulator U4. The GND1 pin and the GND2 pin of the second low dropout linear regulator U4 are also both coupled to the equipotential point. The BST pin of the second low dropout linear regulator U4 is coupled to one end of the twenty-fourth capacitor C24. The PG pin of the second low dropout linear regulator U4 is coupled with one end of a twenty-ninth resistor R29, and the other end of the twenty-ninth resistor R29 is respectively coupled with the OUT1 pin and the OUT2 pin of the second low dropout linear regulator U4. One end of the thirty-first resistor R30 is coupled to the OUT1 pin and the OUT2 pin of the second low dropout linear regulator U4, respectively, and is provided with a connection terminal E2. One end of the thirty-first resistor R31 is coupled to the ADJ pin of the second low dropout linear regulator U4 and the other end of the thirty-first resistor R30, respectively. One end of the twenty-fifth capacitor C25 and one end of the twenty-sixth capacitor C26 are both coupled to the connection terminal E2, and the other end of the twenty-fourth capacitor C24, the other end of the twenty-fifth capacitor C25 and the other end of the twenty-sixth capacitor C26 are both coupled to the equipotential points.

Through the above coupling relationship, the connection terminal E1 acquires the 1.8V voltage signal output from the power module 110, and inputs the 1.8V voltage signal to the IN1 pin and the IN2 pin of the second low dropout linear regulator U4. The second low dropout linear regulator U4 performs voltage regulation output on the 1.8V voltage signal, divides the voltage by the thirty-first resistor R30 and the thirty-first resistor R31, filters the voltage by a capacitor, and outputs a voltage signal of a second preset voltage signal formed by the voltage division to the clamp protection circuit 133 through the connection terminal E2. Wherein the second preset voltage signal is 1V. In addition, the second low dropout linear regulator U4 has a small temperature drift coefficient and high working stability, and the voltage ripple of the output second preset voltage signal is small.

As shown in fig. 2 and fig. 4, in the embodiment of the present invention, the clamping protection circuit 133 is configured to clamp both the voltage of the data signal output by the first signal acquisition module 121 and the voltage of the data signal output by the second signal acquisition module 122 to be within a preset voltage range according to the first preset voltage signal and the second preset voltage signal.

Specifically, in the clamp protection circuit 133:

the anode terminal of the first clamping diode D4 is coupled to one terminal of the thirty-second resistor R32, and the other terminal of the thirty-second resistor R32 is coupled to the connection terminal F1. The anode terminal of the second clamping diode D5 is coupled to one terminal of the thirty-third resistor R33, and the other terminal of the thirty-third resistor R33 is coupled to the connection terminal F2. The anode terminal of the third clamping diode D6 is coupled to one terminal of the thirty-fourth resistor R34, and the other terminal of the thirty-fourth resistor R34 is coupled to the connection terminal F2. The anode terminal of the fourth clamping diode D7 is coupled to one terminal of the thirty-fifth resistor R35, and the other terminal of the thirty-fifth resistor R35 is coupled to the connection terminal F3. The connection terminal F1, the connection terminal F2, and the connection terminal F3 are each coupled to the output end of the first clamp power supply circuit 131. The cathode terminal of the fifth clamp diode D8 is coupled to one end of the thirty-sixth resistor R36, and the other end of the thirty-sixth resistor R36 is coupled to the connection terminal F4. The cathode terminal of the sixth clamp diode D9 is coupled to one end of the thirty-seventh resistor R37, and the other end of the thirty-seventh resistor R37 is coupled to the connection terminal F5. The cathode terminal of the seventh clamp diode D10 is coupled to one end of the thirty-eighth resistor R38, and the other end of the thirty-eighth resistor R38 is coupled to the connection terminal F5. The cathode terminal of the eighth clamp diode D11 is coupled to one end of the thirty-ninth resistor R39, and the other end of the thirty-ninth resistor R39 is coupled to the connection terminal F6. The connection terminal F4, the connection terminal F5, and the connection terminal F6 are all coupled to the output end of the second clamp power supply circuit 132.

In addition, the cathode terminal of the first clamping diode D4 and the anode terminal of the fifth clamping diode D8 are both coupled to the forward output terminal out+ of the first differential amplifier U1 in the first signal acquisition module 121, and the cathode terminal of the first clamping diode D4 and the anode terminal of the fifth clamping diode D8 are both also coupled to one end of the twenty-seventh capacitor C27. The cathode terminal of the second clamping diode D5 and the anode terminal of the sixth clamping diode D9 are both coupled to the reverse output terminal OUT-of the first differential amplifier U1 in the first signal acquisition module 121, and the cathode terminal of the second clamping diode D5 and the anode terminal of the sixth clamping diode D9 are both also coupled to the other end of the twenty-seventh capacitor C27. The cathode terminal of the third clamping diode D6 and the anode terminal of the seventh clamping diode D10 are both coupled to the positive output terminal out+ of the second differential amplifier U2 in the second signal acquisition module 122, and the cathode terminal of the third clamping diode D6 and the anode terminal of the seventh clamping diode D10 are both also coupled to one end of the twenty-eighth capacitor C28. The cathode terminal of the fourth clamping diode D7 and the anode terminal of the eighth clamping diode D11 are both coupled to the reverse output terminal OUT-of the second differential amplifier U2 in the second signal acquisition module 122, and the cathode terminal of the fourth clamping diode D7 and the anode terminal of the eighth clamping diode D11 are both also coupled to the other end of the twenty-eighth capacitor C28.

Through the above coupling relationship, the first clamping diode D4 and the fifth clamping diode D8 are a first group to cooperate to form a clamping effect to control the voltage of the data signal output by the positive output terminal out+ of the first differential amplifier U1. The second clamping diode D5 and the sixth clamping diode D9 are a second group to cooperate to form a clamping function to control the voltage of the data signal output by the inverted output terminal OUT-of the first differential amplifier U1. The third clamping diode D6 and the seventh clamping diode D10 are a third group to cooperate to form a clamping function to control the voltage of the data signal output by the positive output terminal out+ of the second differential amplifier U2. The fourth clamping diode D7 and the eighth clamping diode D11 are a fourth group to cooperate to form a clamping function to control the voltage of the data signal output by the inverted output terminal OUT-of the second differential amplifier U2.

The operation principle of each of the four groups is the same, and the first group formed by the first clamp diode D4 and the fifth clamp diode D8 is described as an example. The preset voltage range of the data signal output by the first differential amplifier U1 is 0.4V-1.3V, and the normal operation of the conversion module 150 can be ensured. When the data signal is within the preset voltage range, the 0.7V voltage obtained through the connection terminal F1 and the 1.0V voltage obtained through the connection terminal F4 make both the first clamp diode D4 and the fifth clamp diode D8 in the off state. When the voltage of the data signal fluctuates to be smaller than the preset voltage range, the first clamping diode D4 is turned on, and the fifth clamping diode D8 is still turned off. The first clamping diode D4 is turned on such that the voltage of the data signal is pulled up to clamp the voltage of the data signal to within a preset voltage range. When the voltage of the data signal fluctuates to be greater than the preset voltage range, the first clamp diode D4 remains turned off and the fifth clamp diode D8 turns on. The fifth clamping diode D8 is turned on such that the voltage of the data signal is pulled down to clamp the voltage of the data signal within a preset voltage range.

Referring to fig. 2, 4 and 7, the common mode reference voltage module 140 is coupled to the power module 110, an input end of the common mode reference voltage module 140 is coupled to the conversion module 150, and an output end of the common mode reference voltage module 140 is coupled to the reference voltage end of the first signal acquisition module 121 and the reference voltage end of the signal acquisition module 120, respectively.

Specifically, in the common mode reference voltage module 140:

one end of the forty-resistance R40 and one end of the twenty-ninth capacitance C29 are both coupled to the connection terminal H1. The other end of the twenty-ninth capacitor C29 is coupled to the equipotential point, and the other end of the fortieth resistor R40 is coupled to the positive input terminal +inb of the common mode reference voltage chip U5, where the common mode reference voltage chip U5 may be LTC1051 type. The V+ pin of the common mode reference voltage chip U5 is coupled with the connecting terminal H2, one end of the thirty-first capacitor C30 and one end of the thirty-first capacitor C31 are both coupled with the connecting terminal H2, and the other end of the thirty-first capacitor C30 and the other end of the thirty-first capacitor C31 are both coupled with the equipotential point. The V-pin of the common mode reference voltage chip U5 is coupled with the connecting terminal H3, one end of the thirty-second capacitor C32 and one end of the thirty-third capacitor C33 are both coupled with the connecting terminal H3, and the other end of the thirty-second capacitor C32 and the other end of the thirty-third capacitor C33 are both coupled with the equipotential point. The inverting input-INB of the common-mode reference voltage chip U5 is coupled to one end of a forty-first resistor R41, and the other end of the forty-first resistor R41 is coupled to the output OUTB of the common-mode reference voltage chip U5. The output terminal OUTB of the common-mode reference voltage chip U5 is further coupled to one end of a third inductor L3, and the other end of the third inductor L3 is coupled to one end of a thirty-fourth capacitor C34, one end of a thirty-fifth capacitor C35, one end of a thirty-sixth capacitor C36, and a connection terminal H4, respectively. The other end of the thirty-fourth capacitor C34, the other end of the thirty-fifth capacitor C35 and the other end of the thirty-sixth capacitor C36 are all coupled to the equipotential points.

Through the coupling relation, the 5V voltage signal output by the power module 110 is obtained through the connecting terminal H2, and the-5V voltage signal output by the power module 110 is obtained through the connecting terminal H3, so that the normal operation of the common mode reference voltage chip U5 is ensured. The reference electric signal output from the conversion module 150 is acquired through the connection terminal H1. The common mode reference voltage chip U5 amplifies the reference electric signal into a preset reference voltage signal, and outputs the reference voltage signal to the reference voltage terminal of the first signal acquisition module 121 and the reference voltage terminal of the second signal acquisition module 122 through the connection terminal H4, respectively.

Referring to fig. 2 and 4, the conversion module 150 includes: a radio frequency transforming unit 151 and a converting unit 152. The rf transforming unit 151 and the converting unit 152 are coupled, each signal collecting module 120 is coupled to the converting unit 152, and the converting unit 152 and the rf transforming unit 151 are coupled to the programmable control module 160.

As shown in fig. 2, 4, 7 and 8, in the present embodiment, the rf transforming unit 151 is configured to obtain a clock signal of the programmable control module 160, and output the clock signal to the converting unit 152 through electromagnetic coupling, so as to ensure the normal operation of the converting unit 152.

Specifically, in the radio frequency transforming unit 151:

one end of the thirty-seventh capacitor C37 and one end of the forty-second resistor R42 are both coupled to the connection terminal G1. The other end of the forty-two resistor R42 is grounded, and the other end of the thirty-seventh capacitor C37 is coupled to one end of the forty-three resistor R43. The other end of the forty-third resistor R43 is coupled with the PRI-DOT pin of the radio frequency transformer U6, wherein the radio frequency transformer U6 is of the model ADT1-1WT. The PRI pin of the radio frequency transformer U6 is grounded, the SEC-CT pin of the radio frequency transformer U6 is coupled with one end of the thirty-eighth capacitor C38, and the other end of the thirty-eighth capacitor C38 is also grounded. The SEC-DOT pin of radio frequency transformer U6 is coupled to one end of thirty-ninth capacitor C39. The other end of the thirty-ninth capacitor C39 is coupled to the anode terminal of the ninth clamp diode D12 and the cathode terminal of the tenth clamp diode D13, respectively. The SEC pin of the radio frequency transformer U6 is coupled to one end of the forty-capacitor C40. The cathode terminal of the ninth clamp diode D12 and the anode terminal of the tenth clamp diode D13 are both coupled to the other end of the forty capacitor C40. In addition, the other end of the thirty-ninth capacitance C39 and the other end of the fortieth capacitance C40 are also coupled to the conversion module 150.

Through the coupling relationship, the clock signal output by the programmable control module 160 is obtained through the coupling between the connection terminal G1 and the programmable control module 160, where the clock signal is a differential clock signal. The clock signal is filtered by RC to remove the DC component in the signal, and then input to the primary winding of the RF transformer U6. The radio frequency transformer U6 outputs the clock signal through the electromagnetic coupling relation of the primary winding and the secondary winding, and meanwhile, the electrical isolation is ensured. The clock signal output by the rf transformer U6 is clamped within 0.7V by the clamping circuit formed by the two clamping diodes, so as to ensure stable output of the clock signal to the conversion module 150.

In this embodiment, the conversion unit 152 is configured to perform analog-to-digital conversion on each path of the acquired data signal according to the clock signal and the control of the programmable control module 160, and then output the data signal to the programmable control module 160 of the programmable control module 160 through the data bus.

Specifically, in the conversion unit 152:

the CLK-pin of the analog-to-digital conversion chip U7 is coupled with the other end of the forty capacitor C40, and the CLK+ pin is coupled with the other end of the thirty-ninth capacitor C39, wherein the model of the analog-to-digital conversion chip U7 is AD9268 type. The VINB+ pin of the analog-digital conversion chip U7 is provided with a connecting terminal G2 of a coupling connecting terminal B4, a connecting terminal G3 provided with a coupling connecting terminal B5, a connecting terminal G4 provided with a coupling connecting terminal C5 and a connecting terminal G5 provided with a coupling connecting terminal C4. VCM of the analog-to-digital conversion chip U7 is provided with a connection terminal G6 coupled to the connection terminal H1. The RBIAS pin of the analog-to-digital conversion chip U7 is coupled to one end of the forty-fourth resistor R44, the SENSE pin of the analog-to-digital conversion chip U7 is coupled to one end of the forty-fifth resistor R45, and the VREF pin of the analog-to-digital conversion chip U7 is coupled to one end of the forty-first capacitor C41 and one end of the forty-second capacitor C42, respectively. The other end of the forty-four resistor R44, the other end of the forty-five resistor R45, the other end of the forty-first capacitor C41, and the other end of the forty-second capacitor C42 are all coupled to the equipotential points. The ACDD1 pin, the ACDD2 pin, the ACDD3 pin, the ACDD4 pin, the ACDD5 pin, the ACDD6 pin, the ACDD7 pin and the ACDD8 pin of the analog-to-digital conversion chip U7 are all coupled with the connecting terminal G7. The PDWN pin of the analog-to-digital conversion chip U7 is provided with a connection terminal G8 and is coupled to one end of the forty-six resistor R46. The OEB pin of the analog-to-digital conversion chip U7 is provided with a connection terminal G9 and is coupled to one end of a forty-seventh resistor R47. The CSB pin of the analog-to-digital conversion chip U7 is provided with a connecting terminal G10 and is coupled with one end of a forty-eight resistor R48, and the other end of the forty-eight resistor R48 is coupled with the ACDD8 pin of the analog-to-digital conversion chip U7. The SCLK/DFS pin of the analog-to-digital conversion chip U7 is provided with a connection terminal G11 and is coupled with one end of a forty-nine resistor R49. The SDIO/DCS pin of the analog-to-digital conversion chip U7 is provided with a connecting terminal G12 and is coupled with one end of a fifty-th resistor R50, and the other end of the fifty-th resistor R50 is coupled with the ACDD7 pin of the analog-to-digital conversion chip U7. The ORA pin of the analog-to-digital conversion chip U7 is provided with a connection terminal G13 and is coupled to one end of the fifty-first resistor R51. The other end of the forty-sixth resistor R46, the other end of the forty-seventh resistor R47, and the other end of the forty-ninth resistor R49 are all grounded. The SYNC pin of the analog-to-digital conversion chip U7 is provided with a connection terminal G14, and the DRVDD1 pin, the DRVDD2 pin, the DRVDD3 pin and the DRVDD4 pin of the analog-to-digital conversion chip U7 are all coupled to the connection terminal G15.

In addition, the DB0 pin of the analog-to-digital conversion chip U7 is coupled with the 8.1 pin of the first pin header wiring RM 0. The DB1 pin of the analog-to-digital conversion chip U7 is coupled with the 7.1 pin of the first pin connection flat cable RM 0. The DB2 pin of the analog-to-digital conversion chip U7 is coupled with the 6.1 pin of the first pin connection flat cable RM 0. The DB3 pin of the analog-to-digital conversion chip U7 is coupled with the 5.1 pin of the first pin connection flat cable RM 0. The DB4 pin of the analog-to-digital conversion chip U7 is coupled with the 4.1 pin of the first pin connection flat cable RM 0. The DB5 pin of the analog-to-digital conversion chip U7 is coupled with the 3.1 pin of the first pin connection flat cable RM 0. The DB6 pin of the analog-to-digital conversion chip U7 is coupled with the 2.1 pin of the first pin connection flat cable RM 0. The DB7 pin of the analog-to-digital conversion chip U7 is coupled with the 1.1 pin of the first pin connection flat cable RM 0.

The DB8 pin of the analog-to-digital conversion chip U7 is coupled with the 8.1 pin of the second pin connection flat cable RM 1. The DB9 pin of the analog-to-digital conversion chip U7 is coupled with the 7.1 pin of the second pin connection flat cable RM 1. The DB10 pin of the analog-to-digital conversion chip U7 is coupled with the 6.1 pin of the second pin connection flat cable RM 1. The DB11 pin of the analog-to-digital conversion chip U7 is coupled with the 5.1 pin of the second pin connection flat cable RM 1. The DB12 pin of the analog-to-digital conversion chip U7 is coupled with the 4.1 pin of the second pin connection flat cable RM 1. The DB13 pin of the analog-to-digital conversion chip U7 is coupled with the 3.1 pin of the second pin connection flat cable RM 1. The DB14 pin of the analog-to-digital conversion chip U7 is coupled with the 2.1 pin of the second pin connection flat cable RM 1. The DB15 pin of the analog-to-digital conversion chip U7 is coupled with the 1.1 pin of the second pin connection flat cable RM 1.

The DA0 pin of the analog-to-digital conversion chip U7 is coupled with the 8.1 pin of the third pin connection flat cable RM 2. The DA1 pin of the analog-to-digital conversion chip U7 is coupled with the 7.1 pin of the third pin connection flat cable RM 2. The DA2 pin of the analog-to-digital conversion chip U7 is coupled with the 6.1 pin of the third pin connection flat cable RM 2. The DA3 pin of the analog-to-digital conversion chip U7 is coupled with the 5.1 pin of the third pin connection flat cable RM 2. The DA4 pin of the analog-to-digital conversion chip U7 is coupled with the 4.1 pin of the third pin connection flat cable RM 2. The DA5 pin of the analog-to-digital conversion chip U7 is coupled with the 3.1 pin of the third pin connection flat cable RM 2. The DA6 pin of the analog-to-digital conversion chip U7 is coupled with the 2.1 pin of the third pin connection flat cable RM 2. The DA7 pin of the analog-to-digital conversion chip U7 is coupled with the 1.1 pin of the third pin connection flat cable RM 2.

The DA8 pin of the analog-to-digital conversion chip U7 is coupled with the 8.1 pin of the fourth pin connection flat cable RM 3. The DA9 pin of the analog-to-digital conversion chip U7 is coupled with the 7.1 pin of the fourth pin connection flat cable RM 3. The DA10 pin of the analog-to-digital conversion chip U7 is coupled with the 6.1 pin of the fourth pin connection flat cable RM 3. The DA11 pin of the analog-to-digital conversion chip U7 is coupled with the 5.1 pin of the fourth pin connection flat cable RM 3. The DA12 pin of the analog-to-digital conversion chip U7 is coupled with the 4.1 pin of the fourth pin connection flat cable RM 3. The DA13 pin of the analog-to-digital conversion chip U7 is coupled with the 3.1 pin of the fourth pin connection flat cable RM 3. The DA14 pin of the analog-to-digital conversion chip U7 is coupled with the 2.1 pin of the fourth pin connection flat cable RM 3. The DA15 pin of the analog-to-digital conversion chip U7 is coupled with the 1.1 pin of the fourth pin connection flat cable RM 3.

In addition, the 8.2 to 1.2 pins of the first pin header connection bus RM0, the 8.2 to 1.2 pins of the second pin header connection bus RM1, the 8.2 to 1.2 pins of the third pin header connection bus RM2, and the 8.2 to 1.2 pins of the fourth pin header connection bus RM3 are all coupled to a data bus, where the data bus may be an SPI data bus.

Through the coupling relation, the power module 110 is coupled through the connecting terminal G7 and the connecting terminal G15 to obtain a 1.8V voltage signal so as to ensure the working power supply of the analog-digital conversion chip U7. The analog-to-digital conversion chip U7 obtains clock signals through the CLK+ pin and the CLK-pin so as to ensure the normal operation of the chip. The analog-to-digital conversion chip U7 outputs the reference electric signal to the common mode reference voltage module 140 through the connection terminal G6. The analog-to-digital conversion chip U7 is coupled with the I/O port of the programmable control module 160 through the connection terminal G8, the connection terminal G9, the connection terminal G10, the connection terminal G11, the connection terminal G12, the connection terminal G13 and the connection terminal G14 so as to realize communication with the programmable control module 160 and acquire a control instruction sent by the programmable control module 160. The analog-to-digital conversion chip U7 obtains the configuration of the internal register according to the sampling rate, the duty ratio of the input clock, the sampling mode and the bus output mode, and then carries out analog-to-digital conversion on the data signals collected by the connecting terminal G2, the connecting terminal G3, the connecting terminal G/4 and the connecting terminal G5. In addition, the connection terminals G8, G9, G10, G11, and G12 of the analog-to-digital conversion chip U7 are provided with a pull-up or pull-down default level configuration, so that the analog-to-digital conversion chip U7 defaults to a full-speed operation mode and the parallel bus outputs. The first pin connection bus RM0, the second pin connection bus RM1, the third pin connection bus RM2 and the fourth pin connection bus RM3 are respectively coupled with the SPI data bus through the analog-to-digital conversion chip U7. The analog-to-digital conversion chip U7 outputs each path of data signals obtained through the first pin connection and bus bar RM0, the second pin connection and bus bar RM1, the third pin connection and bus bar RM2 and the fourth pin connection and bus bar RM3 to the SPI data bus at a preset speed, so that each path of data signals is output to the programmable control module 160 through the SPI data bus, wherein the preset speed is 100MSPS.

Referring to fig. 2 and 8, the programmable control module 160 includes: a clock signal unit 161, a power supply unit 162, and a programmable gate array 163 (Field Programmable Gate Array, FPGA). The clock signal unit 161 is coupled to the power module 110 and the programmable gate array 163, the power supply unit 162 is coupled to the power module 110 and the programmable gate array 163, and the programmable gate array 163 is coupled to the conversion module 150.

As shown in fig. 2, 8, 9 and 10, in the present embodiment, the clock signal unit 161 is configured to provide an operation clock signal for the programmable logic gate array 163 to ensure the normal operation of the programmable logic gate array 163.

Specifically, in the clock signal unit 161:

one end of a fourth inductor L4 is coupled with the connecting terminal I1, and the other end of the fourth inductor L4 is respectively coupled with one end of a forty-third capacitor C43, a VDD pin of an active crystal oscillator U8 and an E/D pin of the active crystal oscillator U8, and the other end of the forty-third capacitor C43 is grounded, wherein the active crystal oscillator U8 is of an OSC6X4 type. One end of the forty-fourth capacitor C44 is coupled with the E/D pin of the active crystal oscillator U8, and the other end of the forty-fourth capacitor C44 is coupled with the GND pin of the active crystal oscillator U8 and grounded. The OUT pin of the active crystal oscillator U8 is coupled with one end of a fifty second resistor R52, and the other end of the fifty second resistor R52 is coupled with the A pin of a clock driving chip U9, wherein the clock driving chip U9 is of a PI49F CT32803Q E type. The VCC1 pin, the VCC2 pin, the VCC3 pin, and the VCC4 pin of the clock driver chip U9 are all coupled to the other end of the fourth inductor L4. The GND1 pin, the GND2 pin, the GND3 pin and the GND4 pin of the clock driver chip U9 are all grounded. The B0 pin of the clock driving chip U9 is provided with a connecting terminal I2. The B3 pin of the clock driving chip U9 is provided with a connecting terminal I3. Further, one end of the forty-fifth capacitor C45 and one end of the forty-sixth capacitor C46 are coupled to the other end of the fourth inductor L4, and the other end of the forty-fifth capacitor C45 and the other end of the forty-sixth capacitor C46 are grounded.

Through the coupling relation, the active crystal oscillator U8 acquires a 3.3V voltage signal through the connecting terminal I1 so as to generate a 50MHz working clock signal according to the 3.3V voltage signal, and outputs the working clock signal to the clock driving chip U9 through an OUT pin. The clock driving chip U9 also obtains a 3.3V voltage signal according to the connection terminal I1, differentially amplifies the working clock signal, and outputs the amplified working clock signal to the clock pin of the programmable logic gate array 163 through the B0 pin and the B3 pin.

In this embodiment, the power supply unit 162 is used to provide an operating power supply for the normal operation of the programmable logic gate array 163.

Specifically, in the power supply unit 162:

the connection terminal J1 and the connection terminal J2 are both coupled to one end of the fifth inductance L5. The other end of the fifth inductor L5 is coupled to one end of the forty-seventh capacitor C47, one end of the forty-eighth capacitor C48, one end of the forty-ninth capacitor C49, one end of the fifty-first capacitor C50, and one end of the fifty-first capacitor C51, respectively, and the other end of the forty-seventh capacitor C47, the other end of the forty-eighth capacitor C48, the other end of the forty-ninth capacitor C49, the other end of the fifty-first capacitor C50, and the other end of the fifty-first capacitor C51 are all grounded. Further, the connection terminal J3 is also coupled to the other end of the fifth inductance L5.

Through the above coupling relationship, the connection terminal J1 obtains the 1.2V voltage signal output by the power module 110, and supplies the 1.2V voltage signal to the phase-locked loop pins (Phase Locked Logic, PLL) of the programmable logic gate array 163 through the connection terminal J2. And the 1.2V voltage signal through the fifth inductor L5 is used to power the programmable logic gate array 163 core. To reduce noise cross-talk between the pll pin supply of the programmable logic gate array 163 and the core supply of the programmable logic gate array 163 by the fifth inductance L5.

The programmable gate array 163 is a Cyclone IV series EP4CE115F29 chip. In this embodiment, part of the I/O ports of the programmable gate array 163 are coupled to the conversion module 150, and the programmable gate array 163 outputs control instructions generated according to a preset control program to the conversion module 150. Another part of the I/O ports of the programmable logic gate array 163 is coupled to the conversion module 150 through the SPI data bus to acquire the data signals output from the conversion module 150 at a preset rate through the SPI data bus. In this embodiment, the ADDR1 to ADDR16 pins and DATA0 to DATA15 pins of the programmable logic gate array 163 are coupled to the processing module 180. The pins coupled to the processing module 180 by the programmable gate array 163 are normal in the initial state, i.e., in the normal operation state. After the programmable gate array 163 determines that the DATA signal acquired by the conversion module 150 is acquired according to the preset control program, the programmable gate array 163 sends a first interrupt signal to the processing module 180, so that the processing module 180 reads and writes the DATA signal acquired by the programmable gate from pins DATA0 to DATA15 after responding to the first interrupt signal. When the DATA signal of the programmable gate array 163 is read and written, the programmable gate array 163 receives the first high signal sent by the processing module 180, and the pins of the programmable gate array 163 and the processing module 180 coupled with DATA0 to DATA15 are all changed to the high impedance state in normal state. After the programmable gate array 163 receives the first low signal sent by the processing module 180, the programmable gate array 163 and the processing module 180 couple the pins DATA0 to DATA15, and then all the pins are changed from the high-impedance state to the normal state.

Referring to fig. 2 and 11, the temperature detection module 170 is coupled with the processing module 180. In the temperature detection module 170 of the present embodiment:

one end of the first thermistor R53 is coupled with the connecting terminal K1, and the other end of the first thermistor R53 is coupled with the DQ pin and the connecting terminal K2 of the digital temperature sensing chip U10 respectively, wherein the digital temperature sensing chip U10 is of a DS18B20 type. The VDD pin of the digital temperature sensing chip U10 is coupled with the connection terminal K1. The GND pin of the digital temperature sensing chip U10 is grounded.

Through the above coupling relationship, the connection terminal K1 obtains the 3.3V voltage signal of the power module 110 to ensure the normal operation of the digital temperature sensing chip U10. The digital temperature sensing chip U10 outputs a temperature signal corresponding to the temperature value to the connection terminal K2 according to the characteristic of the first thermistor R53 that the resistance value is changed by the temperature change, so as to output the temperature signal to the processing module 180 through the connection terminal K2. In this embodiment, the temperature detection range of the temperature detection module 170 is: -10 ℃ to 85 ℃.

Referring to fig. 2 and 10, the processing module 180 includes: a processing unit 181 and a communication unit 182. Wherein the processing module 180 is coupled to the programmable control module 160, i.e. the processing unit 181 is coupled to the programmable logic gate array 163 and the temperature detection module 170 of the programmable control module 160, respectively. The communication unit 182 is coupled to the processing unit 181 and the terminal device 11, respectively.

The processing unit 181 is configured to obtain a data signal sent by the programmable control module 160, and after the data signal is sent, set the programmable control module 160 to a high impedance state from a normal state. And after generating the collected data according to the data signal, the communication unit 182 is set to be normal from the high impedance state, so as to send the collected data to the communication unit 182.

In this embodiment, the processing unit 181 is a microprocessor (Advanced RISC Machines, ARM) with model number S3C 6410. The ADDR1 to ADDR16 pins of the processing unit 181 are coupled to the ADDR1 to ADDR16 pins of the programmable logic gate array 163, and the DATA0 to DATA15 pins of the processing unit 181 are coupled to the DATA0 to DATA15 pins of the programmable logic gate array 163. In addition, the DATA0 through DATA15 pins of the processing unit 181 are correspondingly coupled to the communication unit 182. When the processing unit 181 receives the first interrupt signal sent by the programmable gate array 163, the processing unit 181 corresponds to the first interrupt signal to read and write DATA signals from the DATA0 to DATA15 pins of the programmable gate array 163 through the DATA0 to DATA15 pins. When the processing unit 181 determines that the reading and writing are completed, the processing unit 181 generates a first high signal to the programmable gate array 163 according to a preset control program to set the DATA0 to DATA15 pins of the programmable gate array 163 to the high-impedance state in a normal state. After the processing unit 181 acquires the data signals, the processing unit 181 generates acquisition data according to the data signals. The processing unit 181 is further coupled to the temperature detection module 170 through a GPE0 port to obtain a temperature signal of the temperature detection module 170, and the processing unit 181 revises the acquired data generated according to the temperature signal to ensure the accuracy of the acquired data. The processing unit 181 performs analysis, processing, display, storage, uploading, and the like in its own memory after revising the collected data. In addition, the processing unit 181 is coupled to the communication unit 182 through its irq_lan pin, OEN pin, WEN pin, CSN1 pin, and XNRSTOUT pin, so the processing unit 181 determines whether an idle signal transmitted by the communication unit 182 is acquired. When the processing unit 181 determines that the idle signal is acquired, the processing unit 181 also generates a second low setting signal to the communication unit 182 according to a preset control program, so as to set pins of the communication unit 182 and the processing unit 181 to be normal in a high-impedance state. The processing unit 181 outputs the revised acquired data to the communication unit 182, and after the acquired data is output, generates a second high signal to the communication unit 182 to set the pins of the communication unit 182 and the processing unit 181 to be in a high-impedance state in a normal state. At this time, the processing unit 181 also generates a first low signal to the programmable gate array 163 to set the DATA0 to DATA15 pins of the programmable gate array 163 from the high-impedance state to the normal state again, and form a cycle.

The communication unit 182 is configured to transmit the acquired acquisition data to the coupled terminal device 11 through a wireless network.

In this embodiment, the communication unit 182 may be a communication chip, and the model thereof may be DM9000A. The DATA0 through DATA15 pins of the communication unit 182 are coupled with the DATA0 through DATA15 pins of the processing unit 181. In the initial state, the DATA0 through DATA15 pins of the communication unit 182 are all in a high impedance state. When the communication unit 182 detects that the communication unit 182 is in the idle state according to the preset control program, the communication unit 182 generates an idle signal to the processing unit 181 to obtain a second low setting signal sent by the processing unit 181, sets all the pins from DATA0 to DATA15 of the communication unit to be in a normal state, and obtains the acquired DATA sent by processing through the pins from DATA0 to DATA15 of the communication unit. After the acquisition of the acquired DATA is completed, the communication unit 182 acquires the second high signal sent by the processing unit 181, and sets the pins DATA0 to DATA15 of the communication unit to the high impedance state in a normal state. At this time, the communication unit 182 encodes and converts the acquired acquisition data, and transmits the acquired acquisition data to the terminal device 11 via the wireless network in a predetermined communication protocol. When the transmission of the acquired data by the communication unit 182 is completed, the communication unit 182 can check again to be in an idle state and generate an idle signal again to the processing unit 181 to form a loop.

Referring to fig. 12, the embodiment of the invention further provides a signal acquisition processing method applied to the signal acquisition processing device. The signal acquisition processing method comprises the following steps: step S110 and step S120.

Step S110: the programmable control module controls the conversion module to acquire the data signals acquired by each signal acquisition module 120, and sends the data signals acquired by the conversion module to the processing module at a preset rate.

Step S120: and the processing module generates acquisition data according to the data signals and sends the acquisition data to the terminal equipment according to a preset rate.

It will be clear to those skilled in the art that, for convenience and brevity of description, reference may be made to corresponding procedures in the foregoing apparatus for specific working procedures of the above-described method, and details are not repeated herein.

In summary, the embodiment of the invention provides a signal acquisition processing device, a signal acquisition processing method and a signal acquisition processing system. The signal acquisition processing device is applied to a signal acquisition processing system, and the signal acquisition processing system comprises: terminal equipment, signal acquisition processing device includes: the system comprises a processing module, a programmable control module, a conversion module and at least two paths of signal acquisition modules, wherein each path of signal acquisition module is coupled with the conversion module, the programmable control module is respectively coupled with the conversion module and the processing module, and the processing module is used for being coupled with terminal equipment.

Various modifications and variations of the present invention will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A signal acquisition and processing device, characterized by being applied to a signal acquisition and processing system, the signal acquisition and processing system comprising: the terminal equipment, the signal acquisition processing device includes: the system comprises a processing module, a programmable control module, a conversion module and at least two paths of signal acquisition modules, wherein each path of signal acquisition module is coupled with the conversion module, the programmable control module is respectively coupled with the conversion module and the processing module, and the processing module is used for being coupled with terminal equipment;

The programmable control module is used for controlling the conversion module to acquire data signals acquired by each path of signal acquisition module and transmitting the data signals acquired by the conversion module to the processing module at a preset rate;

the processing module is used for generating acquisition data according to the data signals and sending the acquisition data to the terminal equipment according to the preset rate;

the signal acquisition processing device further comprises: the power supply module, at least two way the signal acquisition module is: the power supply module is respectively coupled with the processing module, the programmable control module and the conversion module, the power supply end of the first signal acquisition module and the power supply end of the second signal acquisition module are both coupled with the power supply module, and the output end of the first signal acquisition module and the output end of the second signal acquisition module are both coupled with the conversion module;

the first signal acquisition module is used for acquiring the data signals and amplifying the data signals to output the data signals to the conversion module;

the second signal acquisition module is used for acquiring the data signals and amplifying the data signals to output the data signals to the conversion module;

The signal acquisition processing device further comprises: the input end of the clamping protection module is coupled with the power supply module, and the output end of the clamping protection module is respectively coupled with the output end of the first signal acquisition module and the output end of the second signal acquisition module;

the clamping protection module is used for clamping the voltage of the data signal output by the first signal acquisition module and the voltage of the data signal output by the second signal acquisition module into a preset voltage range, wherein the preset voltage range is the working voltage range of the conversion module.

2. The signal acquisition and processing device of claim 1, further comprising: a temperature detection module coupled with the processing module;

the temperature detection module is used for acquiring a temperature signal and sending the acquired temperature signal to the processing module;

the processing module is used for revising the acquired data generated according to the data signals according to the temperature signals.

3. The signal acquisition and processing device of claim 1, wherein the processing module comprises: the processing unit is respectively coupled with the programmable control module and the communication unit, and the communication unit is used for coupling the terminal equipment;

The processing unit is used for setting the communication unit to be normal from a high-resistance state after generating the acquired data according to the data signal so as to send the acquired data to the communication unit;

the communication unit is used for sending the acquired acquisition data to the terminal equipment through a wireless network.

4. The signal acquisition and processing device of claim 1, wherein the conversion module comprises: the system comprises a radio frequency transformation unit and a conversion unit, wherein the radio frequency transformation unit is coupled with the conversion unit, each path of signal acquisition module is coupled with the conversion unit, and the conversion unit and the radio frequency transformation unit are coupled with the programmable control module;

the radio frequency transformation unit is used for acquiring a clock signal of the programmable control module and outputting the clock signal to the conversion unit through electromagnetic coupling;

the conversion unit is used for converting each path of acquired data signals according to the clock signals and the control of the programmable control module and outputting the converted data signals to the programmable control module.

5. The signal acquisition and processing device of claim 1, wherein the clamp protection module comprises: the power supply device comprises a power supply module, a first clamping power supply circuit, a second clamping power supply circuit and a clamping protection circuit, wherein the input end of the first clamping power supply circuit and the input end of the second clamping power supply circuit are coupled with the power supply module, the output end of the first clamping power supply circuit and the output end of the second clamping power supply circuit are coupled with the clamping protection circuit, and the clamping protection circuit is coupled with the output end of the first signal acquisition module and the output end of the second signal acquisition module respectively;

The first clamping power supply circuit is used for reducing the voltage signal acquired by the power supply module into a first preset voltage signal and loading the first preset voltage signal to the clamping protection circuit;

the second clamping power supply circuit is used for reducing the voltage signal acquired by the power supply module to a second preset voltage signal and loading the second preset voltage signal to the clamping protection circuit;

the clamping protection circuit is used for clamping the voltage of the data signal output by the first signal acquisition module and the voltage of the data signal output by the second signal acquisition module into the preset voltage range according to the first preset voltage signal and the second preset voltage signal.

6. The signal acquisition and processing device of claim 5, wherein the clamp protection circuit comprises: a first clamp diode, a second clamp diode, a third clamp diode, a fourth clamp diode, a fifth clamp diode, a sixth clamp diode, a seventh clamp diode, and an eighth clamp diode; the anode end of the first clamping diode, the anode end of the second clamping diode, the anode end of the third clamping diode and the anode end of the fourth clamping diode are all coupled with the output end of the first clamping power supply circuit, the cathode end of the fifth clamping diode, the cathode end of the sixth clamping diode, the cathode end of the seventh clamping diode and the cathode end of the eighth clamping diode are all coupled with the output end of the second clamping power supply circuit, the cathode end of the first clamping diode and the anode end of the fifth clamping diode are all coupled with the positive output end of the first signal acquisition module, the cathode end of the second clamping diode and the anode end of the sixth clamping diode are all coupled with the reverse output end of the first signal acquisition module, the cathode end of the third clamping diode and the anode end of the seventh clamping diode are all coupled with the positive output end of the second signal acquisition module, and the cathode end of the fourth clamping diode and the anode end of the eighth clamping diode are both coupled with the negative output end of the second signal acquisition module.

7. A signal acquisition processing method, characterized in that it is applied to a signal acquisition processing apparatus according to any one of claims 1 to 6, said method comprising:

the programmable control module controls the conversion module to acquire data signals acquired by each path of signal acquisition module, and sends the data signals acquired by the conversion module to the processing module at a preset rate;

and the processing module generates acquisition data according to the data signals and sends the acquisition data to the terminal equipment according to a preset rate.

8. A signal acquisition processing system, the signal acquisition processing system comprising: a terminal device and a signal acquisition and processing means as claimed in any one of claims 1 to 6, said signal acquisition and processing means being coupled to said terminal device.