CN107132552A - A kind of parallel code phase search device and the method for realizing parallel code phase search - Google Patents
A kind of parallel code phase search device and the method for realizing parallel code phase search Download PDFInfo
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- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
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- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
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Abstract
The invention discloses a kind of parallel code phase search device and the method for realizing parallel code phase search, including：The Fourier transformation result from the first Fourier transform unit of reception is subjected to coherent accumulation processing and obtains the first coherent accumulation results；First coherent accumulation results and local code are conjugated to the correlated results carried out after result is multiplied in Fourier inversion processing acquisition time domain；Modulus output is carried out to the correlated results in the time domain of acquisition to carry out phase search；Or, coherent accumulation processing is carried out to the output from parallel code phase search circuit multiplier and obtains the second coherent accumulation results；Second coherent accumulation results are subjected to the correlated results in Fourier inversion processing acquisition time domain；Modulus output is carried out to the correlated results in the time domain of acquisition to carry out phase search.In technical solution of the present invention, handled by increasing coherent accumulation in parallel code phase search circuit, reduce the complexity of parallel code phase search, realize the phase search in the case of weak signal.
Description
Technical Field
The present invention relates to signal processing technology, and more particularly, to a parallel code phase searching apparatus and a method for implementing parallel code phase searching.
Background
Global Navigation Satellite Systems (GNSS) play an increasingly irreplaceable important role in people's daily life, and are increasingly applied to fields such as Navigation, timing, surveying and mapping. Currently, the GLObal Satellite NAvigation System mainly includes a GLObal Positioning System (GPS) in the united states, a Beidou (BD) System in china, a GLObal NAvigation Satellite positioning System (GLONASS) in russia, and a Galileo (Galileo) System in europe. In China and Asia-Pacific region, GPS and Beidou system are widely applied; in Russia, GPS and GLONASS are used more frequently. Since the galileo system is far from mature, formal services are not yet available. When a global satellite navigation system is used for positioning, timing and other services, wireless signals of at least four visible satellites are acquired, and a three-dimensional search algorithm is realized through the acquired wireless signals, wherein the three-dimensional search algorithm comprises the following steps: satellite pseudo code, code phase and doppler shift.
The common linear search method searches step by step according to the sequence of one-dimensional, two-dimensional and three-dimensional, and takes too long time. To be less time consuming, parallel search methods have been developed, such as parallel code phase search algorithms, which significantly reduce the time consumption. Fig. 1 is a schematic diagram of a conventional parallel code phase search circuit, and as shown in fig. 1, after a digital intermediate frequency input signal is mixed with a replica sine carrier signal and a replica cosine carrier signal of a first frequency band in an in-phase (I) branch and a quadrature (Q) branch, respectively, fourier transform is performed by a first fourier transform unit in the form of complex numbers of in-phase and quadrature mixing results to obtain fourier transform results; multiplying the Fourier transform result and a local code conjugation result (copying a local code generated by a coarse capture (C/A) code generator, processing the copied local code by a second Fourier transform unit and a complex conjugation unit to obtain a local code conjugation result) by a multiplier, processing the product obtained by multiplying the product by the multiplier by an inverse Fourier transform unit to obtain a correlation result in a time domain, performing modulus extraction on the obtained correlation result in the time domain by a modulus extraction unit, and detecting and judging whether a parallel code phase signal exists or not. After the search and detection of the current frequency band are completed, the receiver then makes an NCO (Numerical Control Oscillator) perform a second frequency band sine carrier and cosine carrier copy, and then similarly completes the search and detection of other frequency bands, where the values of the first frequency band, the second frequency band, and the other frequency bands are traversal frequency bands used in the parallel code phase search process, which is well known to those skilled in the art. During the search of the same satellite signal in different frequency bands, the phase of the replica C/a code can be kept unchanged, and correspondingly the fourier transform and its conjugate value are also kept unchanged. When searching for another satellite signal, the receiver may cause the C/a code generator to copy the corresponding other C/a code and then repeat the above signal search process in each frequency band.
The parallel code phase search algorithm is only applicable to stronger navigation signals (digital intermediate frequency input signals), and is not applicable to weaker navigation signals; this is because the signal-to-noise ratio is high (i.e., the noise is weak) when the navigation signal is strong; when the navigation signal is weak, the noise is strong, that is, the signal-to-noise ratio is low, and the strong noise greatly interferes with the search and capture of the navigation signal, so that the correct navigation signal cannot be found. For weak navigation signals (referred to as weak signals herein for short), increasing coherent integration length is usually adopted to improve the signal-to-noise ratio of the search acquisition scheme, so as to improve the success rate of the search and acquisition scheme, that is, increase the operation length N of the correlator in the above scheme; however, since the above conventional scheme employs a digital signal processing technique of discrete fourier transform, the discrete fourier transform operation has a large complexity, especially for a transform sequence with a large length. For example, for a strong signal, the correlator length may be 1 millisecond (ms), while for a weak signal, the length may even be up to several seconds, at least up to tens of milliseconds, such as 40 ms. In summary, the complexity of the parallel code phase search algorithm is too high when weak signal search is performed, that is, the parallel code phase search algorithm cannot be applied to a weak signal scene.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a frequency search apparatus and a method for implementing frequency search, which can reduce the complexity of fourier transform.
The embodiment of the invention provides a parallel code phase searching device,
the method comprises the following steps: a coherent accumulator, a multiplier, an inverse Fourier transform unit and a modulus taking unit,
the coherent accumulator is connected with a first Fourier transform unit of the parallel code phase searching circuit, performs coherent accumulation processing on the received Fourier transform result from the first Fourier transform unit to obtain a first coherent accumulation result, and outputs the first coherent accumulation result to a multiplier of the parallel code phase searching circuit; the multiplier multiplies the received first coherent accumulation result by a local code conjugate result; the inverse Fourier transform unit carries out inverse Fourier transform processing on the product output by the multiplier to obtain a correlation result in a time domain; the modulus unit performs modulus output on the obtained correlation result in the time domain so as to perform phase search; or,
the method comprises the following steps: a coherent accumulator, an inverse Fourier transform unit and a modulus taking unit,
the coherent accumulator is connected behind the multiplier of the parallel code phase searching circuit, receives the product output by the multiplier, performs coherent accumulation processing to obtain a second coherent accumulation result, and outputs the second coherent accumulation result to the Fourier inverse transformation unit; the Fourier inversion unit performs Fourier inversion processing on the second coherent accumulation result to obtain a correlation result in a time domain; and the modulus unit performs modulus output on the obtained correlation result in the time domain so as to perform phase search.
Optionally, when the coherent accumulator is connected to the first fourier transform unit, the coherent accumulator is specifically configured to convert the received fourier transform result from the first fourier transform unit into a discrete fourier transform sequence according to a preset value sequence, and perform coherent accumulation processing on the discrete fourier transform sequence obtained by the conversion to obtain the first coherent accumulation result;
outputting the first coherent accumulation result to the multiplier of the parallel code phase search circuit.
Optionally, the coherent accumulator is specifically configured to convert the received fourier transform result from the first fourier transform unit into the discrete fourier transform sequence according to a preset value sequence, and perform coherent accumulation processing on the discrete fourier transform sequence obtained by the conversion to obtain the first coherent accumulation result;
outputting the first coherent accumulation result to the multiplier of the parallel code phase search circuit;
the Fourier transform result is a Fourier transform sequence of the digital intermediate frequency input signal expressed by a sequence length M and a local code length N of the digital intermediate frequency input signal
The preset value sequence is 0, M/N, 2M/N, … and (N-1) M/N, and the discrete Fourier transform sequence obtained by conversion is as follows:
formula (1)
Wherein Y in the formula (1)M/N(k) For the navigation signal to be yM/N(N), k is 0,1, …, N-1.
Optionally, a coherent accumulator is connected after the multiplier of the parallel code phase search circuit, said coherent accumulator being particularly adapted to,
and receiving the output of the multiplier, performing coherent accumulation processing on the product output by the multiplier according to a preset value sequence to obtain a second coherent accumulation result, and outputting the second coherent accumulation result to the Fourier inverse transformation unit.
Optionally, a coherent accumulator is connected after the multiplier of the parallel code phase search circuit, said coherent accumulator being particularly adapted to,
and receiving the output of the multiplier, performing coherent accumulation processing on the product output by the multiplier according to a preset value sequence to obtain a second coherent accumulation result, and outputting the second coherent accumulation result to the Fourier inverse transformation unit.
Wherein the multiplier outputs a product of: the product of the local code conjugate result of the parallel code phase search circuit and the Fourier transform result output by the first Fourier transform unit of the parallel code phase search circuit;
the Fourier transform result is a discrete sequence represented by the digital intermediate frequency input signal with a sequence length M and a local code length N of the digital intermediate frequency input signal
The preset value sequence is 0, M/N, 2M/N, … and (N-1) M/N, and the second coherent accumulation result is:
formula (2)
Wherein, in the formula (1), YM/N(k) For the navigation signal to be yM/N(N) the sequence of N-point discrete fourier transforms, k being 0,1, …, N-1;is the result of the local code conjugation.
On the other hand, an embodiment of the present invention further provides a method for implementing parallel code phase search, including:
carrying out coherent accumulation processing on a received Fourier transform result from the first Fourier transform unit to obtain a first coherent accumulation result; multiplying the first coherent accumulation result by the local code conjugate result, and then performing Fourier inversion processing to obtain a correlation result in a time domain; performing modulus output on the obtained correlation result in the time domain to perform phase search; or,
carrying out coherent accumulation processing on the output from the parallel code phase search circuit multiplier to obtain a second coherent accumulation result; carrying out Fourier inversion processing on the second coherent accumulation result to obtain a correlation result in a time domain; and performing modulus output on the obtained correlation result in the time domain to perform phase search.
Optionally, the coherent accumulation processing on the fourier transform result received from the first fourier transform unit specifically includes:
and converting the received Fourier transform result into a discrete Fourier transform sequence according to a preset value sequence, and performing coherent accumulation processing on the discrete Fourier transform sequence obtained by conversion to obtain the first coherent accumulation result.
Optionally, the fourier transform result is input in a digital intermediate frequencyFourier transform sequence of a digital intermediate frequency input signal represented by a sequence length M of the signal and a local code length N
The preset value sequence is 0, M/N, 2M/N, … and (N-1) M/N, and the sequence of the discrete Fourier transform sequence is as follows:
formula (1)
Wherein, in the formula (1), YM/N(k) For the navigation signal to be yM/N(N), k is 0,1, …, N-1.
Optionally, the performing coherent accumulation processing on the output from the parallel code phase search circuit multiplier specifically includes:
and carrying out coherent accumulation processing on the output from the parallel code phase search circuit multiplier according to a preset value sequence to obtain a second coherent accumulation result.
Optionally, the output of the multiplier is: the product of the local code conjugate result of the parallel code phase searching circuit and the Fourier transform result output by the first Fourier transform unit of the parallel code phase searching circuit;
the Fourier transform result is a Fourier transform sequence of the digital intermediate frequency input signal expressed by a sequence length M and a local code length N of the digital intermediate frequency input signal
The preset value sequence is 0, M/N, 2M/N, … and (N-1) M/N, and the second coherent accumulation result is:
formula (2)
Wherein, in the formula (1), YM/N(k) For the navigation signal to be yM/N(N) the sequence of N-point discrete fourier transforms, k being 0,1, …, N-1;is the result of the local code conjugation.
Compared with the prior art, the technical scheme of the application comprises the following steps: carrying out coherent accumulation processing on a received Fourier transform result from the first Fourier transform unit to obtain a first coherent accumulation result; multiplying the first coherent accumulation result by the local code conjugate result, and then performing Fourier inversion processing to obtain a correlation result in a time domain; performing modulus output on the obtained correlation result in the time domain to perform phase search; or, the output from the parallel code phase search circuit multiplier is processed by coherent accumulation to obtain a second coherent accumulation result; carrying out Fourier inversion processing on the second coherent accumulation result to obtain a correlation result in a time domain; and performing modulus output on the obtained correlation result in the time domain to perform phase search. In the technical scheme of the invention, coherent accumulation processing is added in the parallel code phase searching circuit, so that the complexity of parallel code phase searching is reduced, and phase searching under the condition of weak signals is realized.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
FIG. 1 is a schematic diagram of a prior art parallel code phase search circuit;
FIG. 2 is a block diagram of a parallel code phase search apparatus according to an embodiment of the present invention;
FIG. 3 is a block diagram of another parallel code phase searching apparatus according to an embodiment of the present invention;
FIG. 4 is a flowchart of a method for implementing parallel code phase search according to an embodiment of the present invention;
fig. 5 is a flowchart of another method for implementing parallel code phase search according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
In order to facilitate understanding of the content of the invention, before the scheme of the embodiment of the invention is stated, theoretical demonstration is carried out on the content of a part of parallel code phase searching; the parallel code phase search algorithm actually replaces the correlation operation of the digital correlator with a digital signal processing technique such as fourier transform, and the equivalence of the two is demonstrated below. Let two periodic sequences with length N be l (N) and j (N), and their related value sequence be d (N), where N ═ 0,1, …, N-1, can be expressed as formula (3):
formula (3)
Performing discrete fourier transform on the correlation value sequence d (n), obtaining a discrete fourier transform d (k) of d (n) as shown in formula (4):
formula (4)
Substituting the correlation value sequence d (n) of formula (3) into the discrete fourier transform d (k) of d (n) of formula (4) to obtain formula (5):
formula (5)
Equation (5) can be transformed into equation (6):
formula (6)
Equation (6) can be expressed in simplified form as equation (7):
formula (7)
Wherein L (k) and J (k) are discrete Fourier transforms of l (n) and j (n), respectively,represents the conjugate of the complex number J (k). The above formula shows that: the correlation of the two sequences l (n) and j (n) in the time domain is equivalent to their discrete Fourier transforms L (k) and J (k), or more precisely the conjugate of J (k)) And performing product operation in the frequency domain. Then the product is invertedThe inverse discrete fourier transform of (a) is exactly the correlation value d (n) at each code phase that the receiver needs to detect. Once the receiver obtains the correlation value d (n) through the inverse fourier transform calculation, the following signal detection is the same as the linear search acquisition method, i.e. find the peak of the autocorrelation amplitude | d (n) | in all search units, and compare the peak with the acquisition threshold. If the peak exceeds an acquisition threshold, the receiver acquires the signal and also derives therefrom the frequency and code phase of the signalTwo parameter values. It should be noted that, for the GPS navigation system, the j (N) sequence in the above demonstration process may be a local code sequence generated by the C/a code generator, and the sequence length of the local code sequence is 1023 chips, and the time length is 1 ms.
Fig. 2 is a block diagram of a parallel code phase searching apparatus according to an embodiment of the present invention, as shown in fig. 2, including: a coherent accumulator, a multiplier, an inverse Fourier transform unit and a modulus taking unit,
the coherent accumulator is connected with a first Fourier transform unit of the parallel code phase searching circuit, performs coherent accumulation processing on the received Fourier transform result from the first Fourier transform unit to obtain a first coherent accumulation result, and outputs the first coherent accumulation result to a multiplier of the parallel code phase searching circuit; the multiplier multiplies the received first coherent accumulation result by a local code conjugate result; the inverse Fourier transform unit carries out inverse Fourier transform processing on the product output by the multiplier to obtain a correlation result in a time domain; and the modulus unit performs modulus output on the obtained correlation result in the time domain so as to perform phase search.
In this embodiment, the coherent accumulator is specifically configured to convert a received fourier transform result from the first fourier transform unit into a discrete fourier transform sequence according to a preset value sequence, and perform coherent accumulation processing on the discrete fourier transform sequence obtained by the conversion to obtain a first coherent accumulation result;
and outputting the first coherent accumulation result to a multiplier of the parallel code phase searching circuit.
Optionally, the coherent accumulator is specifically configured to convert a received fourier transform result from the first fourier transform unit into a discrete fourier transform sequence according to a preset value sequence, and perform coherent accumulation processing on the discrete fourier transform sequence obtained by the conversion to obtain a first coherent accumulation result;
outputting the first coherent accumulation result to a multiplier of the parallel code phase searching circuit;
the Fourier transform result is a Fourier transform sequence of the digital intermediate frequency input signal expressed by a sequence length M and a local code length N of the digital intermediate frequency input signal
The preset value sequence is 0, M/N, 2M/N, … and (N-1) M/N, and the discrete Fourier transform sequence obtained by conversion is as follows:
formula (1)
Wherein Y in the formula (1)M/N(k) For the navigation signal to be yM/N(N), k is 0,1, …, N-1.
In the technical scheme of the invention, coherent accumulation processing is added in the parallel code phase searching circuit, so that the complexity of parallel code phase searching is reduced, and phase searching under the condition of weak signals is realized.
Fig. 3 is a block diagram of another parallel code phase searching apparatus according to an embodiment of the present invention, as shown in fig. 3, including: a coherent accumulator, an inverse Fourier transform unit and a modulus taking unit,
the coherent accumulator is connected behind the multiplier of the parallel code phase searching circuit, receives the product output by the multiplier, performs coherent accumulation processing to obtain a second coherent accumulation result, and outputs the second coherent accumulation result to the Fourier inverse transformation unit; the Fourier inversion unit performs Fourier inversion processing on the second coherent accumulation result to obtain a correlation result in a time domain; and the modulus unit performs modulus output on the obtained correlation result in the time domain so as to perform phase search.
In embodiments of the present invention, the coherent accumulator is specifically configured to,
and receiving the output of the multiplier, performing coherent accumulation processing on the product output by the multiplier according to a preset value sequence to obtain a second coherent accumulation result, and outputting the second coherent accumulation result to the Fourier inverse transformation unit.
Optionally, the coherent accumulator is specifically adapted to,
and receiving the output of the multiplier, performing coherent accumulation processing on the product output by the multiplier according to a preset value sequence to obtain a second coherent accumulation result, and outputting the second coherent accumulation result to the Fourier inverse transformation unit.
Wherein, the multiplier outputs the product: the product of the local code conjugate result of the parallel code phase searching circuit and the Fourier transform result output by the first Fourier transform unit of the parallel code phase searching circuit;
the Fourier transform result is a discrete sequence represented by the digital intermediate frequency input signal as represented by a sequence length M and a local code length N of the digital intermediate frequency input signal
The preset value sequence is 0, M/N, 2M/N, … and (N-1) M/N, and the second coherent accumulation result is:
formula (2)
Wherein, in the formula (1), YM/N(k) For the navigation signal to be yM/N(N) the sequence of N-point discrete fourier transforms, k being 0,1, …, N-1;is the result of the local code conjugation.
Fig. 4 is a flowchart of a method for implementing parallel code phase search according to an embodiment of the present invention, as shown in fig. 4, including:
step 400, performing coherent accumulation processing on a received Fourier transform result from a first Fourier transform unit to obtain a first coherent accumulation result;
optionally, the step specifically includes:
and converting the received Fourier transform result into a discrete Fourier transform sequence according to a preset value sequence, and performing coherent accumulation processing on the discrete Fourier transform sequence obtained by conversion to obtain a first coherent accumulation result.
Optionally, the fourier transform result is a fourier transform sequence of the digital intermediate frequency input signal expressed by a sequence length M and a local code length N of the digital intermediate frequency input signal
The preset value sequence is 0, M/N, 2M/N, … and (N-1) M/N, and the sequence of the discrete Fourier transform sequence is as follows:
formula (1)
Wherein, in the formula (1), YM/N(k) For the navigation signal to be yM/N(N), k is 0,1, …, N-1.
Step 401, multiplying the first coherent accumulation result by the local code conjugate result, and then performing inverse fourier transform to obtain a correlation result in the time domain;
and 402, performing modulus output on the obtained correlation result in the time domain to perform phase search.
Fig. 5 is a flowchart of another method for implementing parallel code phase search according to an embodiment of the present invention, as shown in fig. 5, including:
500, performing coherent accumulation processing on the output from the parallel code phase search circuit multiplier to obtain a second coherent accumulation result;
optionally, the step specifically includes:
and carrying out coherent accumulation processing on the output from the parallel code phase search circuit multiplier according to a preset value sequence to obtain a second coherent accumulation result.
Wherein, the output of the multiplier is: the product of the local code conjugate result of the parallel code phase searching circuit and the Fourier transform result output by the first Fourier transform unit of the parallel code phase searching circuit;
the Fourier transform result is a Fourier transform sequence of the digital intermediate frequency input signal expressed by a sequence length M and a local code length N of the digital intermediate frequency input signal
The preset value sequence is 0, M/N, 2M/N, … and (N-1) M/N, and the second coherent accumulation result is:
formula (2)
In the formula (1), YM/N(k) For the navigation signal to be yM/N(N) the sequence of N-point discrete fourier transforms, k being 0,1, …, N-1;is the result of the local code conjugation.
Step 501, performing Fourier inversion processing on the second coherent accumulation result to obtain a correlation result in a time domain;
and 502, performing modulus output on the obtained correlation result in the time domain to perform phase search.
The method of the present invention is described in clear detail by the following application examples, which are only used to illustrate the present invention and are not used to limit the protection scope of the method of the present invention.
Application example
The weak signal parallel code phase search scheme proposed by the present invention is described in detail below.
First, the following formula derivation is performed.
Note that x (N) is a local code sequence, and x (N) is a period sequence, where the period length is N, N is 0,1, …, N-1. Let y (n) be the received navigation signal (digital intermediate frequency input signal), and be the navigation signal sent by multiple satellites mixed together, and the sequence length is infinite, that is, n is 0,1, …. The correlation value sequence of the two can be expressed as formula (8):
formula (8)
Where M ═ cN, c is a positive integer, i.e., M is a number that is an integer multiple of N. For the GPS system, the following values may be taken as an example, and if N is 1ms, M may be determined according to the value of c, for example, if c is 40, M is 40 ms.
The formula (9) can be obtained by performing discrete Fourier transform on z (n)
Formula (9)
Substituting z (n) into the formula (9)
Formula (10)
Carrying out variable replacement on the formula (10) step by step according to the following formula to obtain a formula (14):
formula (11)
Formula (12)
Formula (13)
Formula (14)
Considering that x (n) has periodicity and y (n) has approximate periodicity (the sequence y (n) includes the sequence x (n), obtained by converting x (n)), the equation (14) is modified to obtain:
formula (15)
Simplifying the format to obtain:formula (16)
Wherein X (k) is a discrete Fourier transform of a sequence x (N) of length N, and Y (k) is a discrete Fourier transform of a sequence y (N) of length M, i.e., the discrete Fourier transforms are N and M, respectively.
For weak signals, M may correspond to a long coherent integration length, e.g. 100ms or even longer, while N corresponds to only 1 ms. As a specific example, N may take the value 1023, and M may take an integer multiple of 1023, such as 1023 x 100; due to the complexity problem, the length of discrete fourier transform cannot be increased at will; that is, although the above formula derivation can search for and capture weak navigation signals, the above scheme cannot be realized in practical application because the complexity of discrete fourier transform of M points is too high.
Through analysis of the inventor, the discrete Fourier transform sequence Y (k) of M points actually adopts only partial sample point results, namely sample points 0, M/N, 2M/N, …, and the discrete Fourier transform sequence Y (k) of (N-1) M/N, namely M points only uses a value sequence;
the approximate formula (1) can be obtained by sorting:
formula (1)
The approximate formula (1) is explained as follows:
in the formula (1), M/N is c, and c is a positive integer; recording a digital intermediate frequency input signal as y (n), and taking a y (n) sequence with continuous M points, namely n is 0,1, … and M-1; while noting y of length N points1(N) (N-0, 1, …, N-1) sequence y (m), m-0, 1, …, N-1; noting y as N points in length2(N) (N ═ 0,1, …, N-1) sequence y (m), m ═ N, N +1, …, 2N-1; by analogy, remember y with length Nc(N) (N ═ 0,1, …, N-1) sequence y (m), m ═ N (c-1) N, (c-1) N +1, …, cN-1.
Meanwhile, Y (k) is an M-point discrete Fourier transform sequence of Y (n), Yp(k) Is yp(N) N-point discrete fourier transform sequence, p ═ 1, 2, …, c.
Based on the above description and the contents of the approximate formula (1), formula (18) or formula (2) can be obtained,
formula (18)
Formula (2)
Formula (1) can be obtained by processing a coherent accumulator, the parallel code phase searching device shown in fig. 2 in the embodiment of the invention can be obtained by adding the coherent accumulator to a parallel code phase searching circuit, the coherent accumulator is connected behind a fourier transform unit of the parallel code phase searching circuit, a processing result of the coherent accumulator is output to a multiplier of the parallel code phase searching circuit, multiplication with a conjugate result of a local code is realized through the multiplier, and an inverse fourier transform unit performs inverse fourier transform processing on a product output by the multiplier to obtain a correlation result in a time domain; and the modulus unit performs modulus output on the obtained correlation result in the time domain so as to perform phase search.
The apparatus for parallel code phase search in fig. 3 according to the embodiment of the present invention can be obtained based on formula (2), after the product obtained by multiplying by the multiplier in the parallel code phase search circuit is processed by the coherent accumulator, the inverse fourier transform unit performs inverse fourier transform processing on the second coherent accumulation result to obtain a correlation result in the time domain; and the modulus unit performs modulus output on the obtained correlation result in the time domain so as to perform phase search.
The parallel code phase search apparatus of fig. 2 and the parallel code phase search apparatus of fig. 3 differ only in the position of the coherent accumulator. The device in fig. 2 performs N-point discrete fourier transform on an input signal in a segmented manner to obtain a discrete fourier transform sequence, performs coherent accumulation processing on the discrete fourier transform sequence to still obtain an accumulation result sequence with a length of N points, and finally multiplies a local code conjugate result by the accumulation result sequence, and then performs subsequent operations. It should be noted that, for the conventional scheme, the performance can be improved by non-coherent accumulation after the modulo operation, but the non-coherent accumulation or integration is usually limited in performance, and thus is not in the same category as the coherent integration of the present invention and will not be discussed here. Coherent integration is often performance independent, as long as the complexity can be tolerated. The device in fig. 3 adopts the method of firstly carrying out the product of the local code conjugate result of the code phase search circuit and the fourier transform result output by the first fourier transform unit of the parallel code phase search circuit, and then carrying out coherent accumulation and subsequent processing on the result multiplied by the multiplier. Through simulation verification, the parallel code phase searching performance of the embodiment of the invention on weak signals is improved.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A parallel code phase searching apparatus, characterized in that,
the method comprises the following steps: a coherent accumulator, a multiplier, an inverse Fourier transform unit and a modulus taking unit,
the coherent accumulator is connected with a first Fourier transform unit of the parallel code phase searching circuit, performs coherent accumulation processing on the received Fourier transform result from the first Fourier transform unit to obtain a first coherent accumulation result, and outputs the first coherent accumulation result to a multiplier of the parallel code phase searching circuit; the multiplier multiplies the received first coherent accumulation result by a local code conjugate result; the inverse Fourier transform unit carries out inverse Fourier transform processing on the product output by the multiplier to obtain a correlation result in a time domain; the modulus unit performs modulus output on the obtained correlation result in the time domain so as to perform phase search; or,
the method comprises the following steps: a coherent accumulator, an inverse Fourier transform unit and a modulus taking unit,
the coherent accumulator is connected behind the multiplier of the parallel code phase searching circuit, receives the product output by the multiplier, performs coherent accumulation processing to obtain a second coherent accumulation result, and outputs the second coherent accumulation result to the Fourier inverse transformation unit; the Fourier inversion unit performs Fourier inversion processing on the second coherent accumulation result to obtain a correlation result in a time domain; and the modulus unit performs modulus output on the obtained correlation result in the time domain so as to perform phase search.
2. The apparatus according to claim 1, wherein when the coherent accumulator is connected to the first fourier transform unit, the coherent accumulator is specifically configured to convert the fourier transform result received from the first fourier transform unit into a discrete fourier transform sequence according to a preset value sequence, and perform coherent accumulation processing on the discrete fourier transform sequence obtained by the conversion to obtain the first coherent accumulation result;
outputting the first coherent accumulation result to the multiplier of the parallel code phase search circuit.
3. The apparatus according to claim 2, wherein the coherent accumulator is specifically configured to convert the fourier transform result received from the first fourier transform unit into the discrete fourier transform sequence according to a preset value sequence, and perform coherent accumulation processing on the discrete fourier transform sequence obtained by the conversion to obtain the first coherent accumulation result;
outputting the first coherent accumulation result to the multiplier of the parallel code phase search circuit;
the Fourier transform result is a Fourier transform sequence of the digital intermediate frequency input signal expressed by a sequence length M and a local code length N of the digital intermediate frequency input signal
The preset value sequence is 0, M/N, 2M/N, … and (N-1) M/N, and the discrete Fourier transform sequence obtained by conversion is as follows:
y (mRow) M (mN) k (mo) mo (mo) Y (mFrac) M (mFrac) Y (mn) 1 (mn) 2 mn (mRow) Y (mo) M (M), M (M k) M (M), M To a [ mo ] < mo > + </mo > < msub > < mi > Y </mi > < mRow > < mi > M </mi >/[ mo > < mi > N </mi > </mRow > </msub > < mRow > < mo > ([ mo > < mi > k </mi >) </mo >) </mRow > formula (1)
Wherein Y in the formula (1)M/N(k) For the navigation signal to be yM/N(N), k is 0,1, …, N-1.
4. Parallel code phase searching arrangement according to claim 1, characterized in that the coherent accumulator is connected after the multiplier of the parallel code phase searching circuit, the coherent accumulator being particularly adapted to,
and receiving the output of the multiplier, performing coherent accumulation processing on the product output by the multiplier according to a preset value sequence to obtain a second coherent accumulation result, and outputting the second coherent accumulation result to the Fourier inverse transformation unit.
5. The parallel code phase searching arrangement according to claim 4, characterized in that the coherent accumulator is connected after the multiplier of the parallel code phase searching circuit, the coherent accumulator being particularly adapted to,
receiving the output of the multiplier, performing coherent accumulation processing on the product output by the multiplier according to a preset value sequence to obtain a second coherent accumulation result, and outputting the second coherent accumulation result to the inverse Fourier transform unit;
wherein the multiplier outputs a product of: the product of the local code conjugate result of the parallel code phase search circuit and the Fourier transform result output by the first Fourier transform unit of the parallel code phase search circuit;
the Fourier transform result is a discrete sequence represented by the digital intermediate frequency input signal with a sequence length M and a local code length N of the digital intermediate frequency input signal
The preset value sequence is 0, M/N, 2M/N, … and (N-1) M/N, and the second coherent accumulation result is:
[ mlow ] Z (mo) or [ mo ] m (mo) about (mo) X (mo) k (mo) or [ mo ] m (mo) k) or [ mo ] m (mo) 1 or [ mo ] m (mo) or [ mo ] m (or) about (mo) or [ mo ] or [ Y ] m (m) Y or [ m ] m (m 1 or m ] m (m) 1 or m (m) m (m) m (m) m M < mo > < mrow > </mrow < mn >2</mn > </msub < mrow > < mo > < mo > </mo < M < M > < M > X </mo > < mo > < mo > (</mo > < M > < M > M < M > < M > M < M > M < M > M < M > M < M > M < M > X </M < M > M < M > M [ mi ] < mo ]/[ mo ] < mi > N ] < mrow ] ([ mo ] < mi k ] < mo >) </mo ] </mrow > formula (2)
Wherein, in the formula (1), YM/N(k) For the navigation signal to be yM/N(N) the sequence of N-point discrete fourier transforms, k being 0,1, …, N-1;is the result of the local code conjugation.
6. A method for performing parallel code phase search, comprising:
carrying out coherent accumulation processing on a received Fourier transform result from the first Fourier transform unit to obtain a first coherent accumulation result; multiplying the first coherent accumulation result by the local code conjugate result, and then performing Fourier inversion processing to obtain a correlation result in a time domain; performing modulus output on the obtained correlation result in the time domain to perform phase search; or,
carrying out coherent accumulation processing on the output from the parallel code phase search circuit multiplier to obtain a second coherent accumulation result; carrying out Fourier inversion processing on the second coherent accumulation result to obtain a correlation result in a time domain; and performing modulus output on the obtained correlation result in the time domain to perform phase search.
7. The method of claim 6, wherein the coherently accumulating the fourier transform results received from the first fourier transform unit comprises:
and converting the received Fourier transform result into a discrete Fourier transform sequence according to a preset value sequence, and performing coherent accumulation processing on the discrete Fourier transform sequence obtained by conversion to obtain the first coherent accumulation result.
8. The method of claim 7,
the Fourier transform result is a Fourier transform sequence of the digital intermediate frequency input signal expressed by a sequence length M and a local code length N of the digital intermediate frequency input signal
The preset value sequence is 0, M/N, 2M/N, … and (N-1) M/N, and the sequence of the discrete Fourier transform sequence is as follows:
y (mRow) M (mN) k (mo) mo (mo) Y (mFrac) M (mFrac) Y (mn) 1 (mn) 2 mn (mRow) Y (mo) M (M), M (M k) M (M), M To a [ mo ] < mo > + </mo > < msub > < mi > Y </mi > < mRow > < mi > M </mi >/[ mo > < mi > N </mi > </mRow > </msub > < mRow > < mo > ([ mo > < mi > k </mi >) </mo >) </mRow > formula (1)
Wherein, in the formula (1), YM/N(k) For the navigation signal to be yM/N(N), k is 0,1, …, N-1.
9. The method of claim 6, wherein coherently accumulating the outputs from the parallel code phase search circuit multipliers specifically comprises:
and carrying out coherent accumulation processing on the output from the parallel code phase search circuit multiplier according to a preset value sequence to obtain a second coherent accumulation result.
10. The method of claim 9, wherein the output of the multiplier is: the product of the local code conjugate result of the parallel code phase searching circuit and the Fourier transform result output by the first Fourier transform unit of the parallel code phase searching circuit;
the Fourier transform result is a Fourier transform sequence of the digital intermediate frequency input signal expressed by a sequence length M and a local code length N of the digital intermediate frequency input signal
The preset value sequence is 0, M/N, 2M/N, … and (N-1) M/N, and the second coherent accumulation result is:
[ mlow ] Z (mo) or [ mo ] m (mo) about (mo) X (mo) k (mo) or [ mo ] m (mo) k) or [ mo ] m (mo) 1 or [ mo ] m (mo) or [ mo ] m (or) about (mo) or [ mo ] or [ Y ] m (m) Y or [ m ] m (m 1 or m ] m (m) 1 or m (m) m (m) m (m) m M < mo > < mrow > </mrow < mn >2</mn > </msub < mrow > < mo > < mo > </mo < M < M > < M > X </mo > < mo > < mo > (</mo > < M > < M > M < M > < M > M < M > M < M > M < M > M < M > M < M > X </M < M > M < M > M [ mi ] < mo ]/[ mo ] < mi > N ] < mrow ] ([ mo ] < mi k ] < mo >) </mo ] </mrow > formula (2)
Wherein, in the formula (1), YM/N(k) For the navigation signal to be yM/N(N) N-point discrete Fourier transformPermuting, k ═ 0,1, …, N-1;is the result of the local code conjugation.
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