CN107132424B - Device for collecting C4 signal of transponder - Google Patents
Device for collecting C4 signal of transponder Download PDFInfo
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- CN107132424B CN107132424B CN201710437765.5A CN201710437765A CN107132424B CN 107132424 B CN107132424 B CN 107132424B CN 201710437765 A CN201710437765 A CN 201710437765A CN 107132424 B CN107132424 B CN 107132424B
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- 238000000034 method Methods 0.000 claims abstract description 8
- 239000003990 capacitor Substances 0.000 claims description 12
- 238000002955 isolation Methods 0.000 claims description 9
- 238000000605 extraction Methods 0.000 claims description 6
- 230000000903 blocking effect Effects 0.000 claims description 3
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000011664 signaling Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000004148 unit process Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
- G01R29/023—Measuring pulse width
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Train Traffic Observation, Control, And Security (AREA)
Abstract
The invention relates to a device for collecting a C4 signal of a transponder, which comprises a C6 signal generating end, a pulse width modulation circuit, a comparison circuit and an FPGA, wherein the C6 signal generating end, the pulse width modulation circuit, the comparison circuit and the FPGA are sequentially connected; the change of the current of the C6 signal at the end of the original coil is detected, a pulse width modulation circuit is used for converting the current signal into a voltage signal, a sinusoidal signal is converted into a pulse signal through a comparison circuit, and finally the width of the pulse signal is demodulated by an FPGA, so that the C4 signal is acquired. Compared with the prior art, the method has the advantages of being capable of accurately and rapidly measuring the change of the C4 signal and the like.
Description
Technical Field
The invention relates to a track traffic signal acquisition device, in particular to a device for acquiring a transponder C4 signal.
Background
In both the ETCS-1-level signaling system based on Europe and the CTCS-2-level signaling system based on China, the train control ground electronic unit LEU serves as one of the key subsystems to play an important role in the interaction of the train and ground information. On the one hand the LEU needs to send ground data via the C1 signal and the C6 signal to the ATP system of the train. On the other hand, the LEU can collect the generated C4 signal of the train passing through the transponder as an electrical signal basis for the train passing through the transponder. Therefore, the efficient and accurate acquisition of the C4 signal is very significant for a ground track signal control system.
Disclosure of Invention
The object of the present invention is to overcome the drawbacks of the prior art described above by providing a device for acquiring a transponder C4 signal.
The aim of the invention can be achieved by the following technical scheme:
the device for collecting the C4 signal of the transponder comprises a C6 signal generating end, a pulse width modulation circuit, a comparison circuit and an FPGA, wherein the C6 signal generating end, the pulse width modulation circuit, the comparison circuit and the FPGA are sequentially connected;
the change of the current of the C6 signal at the end of the original coil is detected, a pulse width modulation circuit is used for converting the current signal into a voltage signal, a sinusoidal signal is converted into a pulse signal through a comparison circuit, and finally the width of the pulse signal is demodulated by an FPGA, so that the C4 signal is acquired.
The pulse width modulation circuit comprises an isolation capacitor C25, a first clamping resistor R30 and a second clamping resistor R31, wherein one end of the isolation capacitor C25 is connected with a signal generating end of the C6, and the other end of the isolation capacitor C25 is connected between the first clamping resistor R30 and the second clamping resistor R31;
the C6 signal is converted into a voltage signal through a blocking capacitor C25, a first clamping resistor R30 and a second clamping resistor R31.
The comparison circuit comprises a direct current comparison chip U9A, the positive input end of the direct current comparison chip U9A is connected between a first clamping resistor R30 and a second clamping resistor R31, and the output end of the direct current comparison chip U9A is connected with the FPGA.
The positive input end of the direct current comparison chip U9A is connected between the first clamping resistor R30 and the second clamping resistor R31 through a resistor R36, and the negative input end is connected with a comparison power supply V6 through a resistor R37;
the direct current comparison circuit U9A converts the upper peak and the lower peak of the voltage sinusoidal signal into two paths of pulse signals.
The output end of the direct current comparison chip U9A is connected with the FPGA through a diode D5.
The device also comprises a C6 signal extraction circuit.
The C6 signal extraction circuit comprises a comparison chip U8A, wherein the positive input end of the comparison chip U8A is connected with the C6 signal generation end, the negative input end of the comparison chip U8A is grounded after passing through a resistor R27, and the output end of the comparison chip U8A is output after passing through a diode D4.
The FPGA counts according to pulse voltage change, judges whether the pulse width is widened according to the count value, and comprehensively judges whether a C4 signal arrives or not by calculating the number of the wide pulses.
And the FPGA processes the two converted pulses, one pulse is an up-peak pulse and the other pulse is a down-peak pulse, and when any pulse is acquired to the C4 signal, the C4 signal is considered to be acquired.
Compared with the prior art, the invention has the following advantages:
1) The invention can accurately and rapidly measure the change of the C4 signal, so that the LEU can judge whether the train passes through the connected transponder. And the interlocking signal equipment or the train control center at the upper layer can be used as the basis of the train position according to the signal.
2) The train passing signals of all active transponders are connected by the train control center or the interlocking equipment, the train control center or the interlocking equipment can obtain a series of real-time data such as the running track of the train and the integrity of the train, and a new basis is provided for judging safety signals of the rich control train in the interval running process.
Drawings
FIG. 1 is a graph of impedance versus time as a train passes through a transponder;
FIG. 2 is a specific circuit diagram of the present invention;
fig. 3 is a graph of voltage signal and pulse signal when the C4 signal appears.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
The invention is a testing technique on an autonomous design-based device.
According to the SUBSET-036 european standard for transponder testing, the impedance of a sinusoidal signal (C6 signal) at a voltage VPP of 22V is shifted from a range of 150 Ω < Zia <300 Ω in a normal state to a range of Za <15 Ω for a shift time of 200< t <350us, td <150us when the train passes the transponder, as shown in fig. 1.
This process of impedance change is therefore referred to as the C4 signal. From this signal characteristic, the C4 signal duration is short and the impedance change is significant. Therefore, the invention adopts a pulse width modulation hardware circuit with strong real-time performance to reflect the load change condition, and then uses the software of the FPGA processing unit to judge the change of the generated pulse width so as to detect the C4 signal.
The detection principle is as follows: when the impedance changes, the current at the load terminal also changes. The primary of the transformer at the LEU end will produce a corresponding current amplitude change. The current signal is converted into a voltage signal by detecting the change of the current of the C6 signal at the end of the original coil through a pulse width modulation method, the sinusoidal signal is converted into a pulse signal by a comparison circuit, and the width of the pulse signal is demodulated by a high-speed FPGA, so that the C4 signal is acquired.
As shown in fig. 2, the specific circuit diagram of the present invention: the device comprises a C6 signal generating end, a pulse width modulation circuit, a comparison circuit and an FPGA, wherein the C6 signal generating end, the pulse width modulation circuit, the comparison circuit and the FPGA are sequentially connected; the change of the current of the C6 signal at the end of the original coil is detected, a pulse width modulation circuit is used for converting the current signal into a voltage signal, a sinusoidal signal is converted into a pulse signal through a comparison circuit, and finally the width of the pulse signal is demodulated by an FPGA, so that the C4 signal is acquired.
The pulse width modulation circuit comprises an isolation capacitor C25, a first clamping resistor R30 and a second clamping resistor R31, wherein one end of the isolation capacitor C25 is connected with a signal generating end of the C6, and the other end of the isolation capacitor C25 is connected between the first clamping resistor R30 and the second clamping resistor R31; the C6 signal is converted into a voltage signal through a blocking capacitor C25, a first clamping resistor R30 and a second clamping resistor R31. The comparison circuit comprises a direct current comparison chip U9A, the positive input end of the direct current comparison chip U9A is connected between a first clamping resistor R30 and a second clamping resistor R31, and the output end of the direct current comparison chip U9A is connected with the FPGA.
The positive input end of the direct current comparison chip U9A is connected between the first clamping resistor R30 and the second clamping resistor R31 through a resistor R36, and the negative input end is connected with a comparison power supply V6 through a resistor R37; the direct current comparison circuit U9A converts the upper peak and the lower peak of the voltage sinusoidal signal into two paths of pulse signals.
The output end of the direct current comparison chip U9A is connected with the FPGA through a diode D5. The device also comprises a C6 signal extraction circuit. The C6 signal extraction circuit comprises a comparison chip U8A, wherein the positive input end of the comparison chip U8A is connected with the C6 signal generation end, the negative input end of the comparison chip U8A is grounded after passing through a resistor R27, and the output end of the comparison chip U8A is output after passing through a diode D4.
When the amplitude of the voltage signal (sinusoidal thin line) after current conversion increases as shown in fig. 3, the corresponding pulse (square line) width after conversion is widened, the pulse width is changed from about 34us to 45us, the widened pulse signal is sent to an input pin of the FPGA processing unit in the device, the FPGA counts according to the pulse voltage change, and the FPGA determines whether the pulse width is widened according to the magnitude of the count value. Finally, comprehensively judging whether the C4 signal arrives or not by calculating the number of the wide pulses, and filtering the interference of the common C6 signal.
On the other hand, in order to accurately measure the C4 signal, the FPGA processing unit processes two paths of pulses after conversion, one path is an up-peak pulse, the other path is a down-peak pulse, and when any path is acquired as shown in fig. 3, the channel C4 signal is considered to appear.
When two wide pulses are continuously received at the C4Data_Input pin of the FPGA, and the judgment of the threshold value is reached, the FPGA considers that the C4 signal is generated, so that after the second wide pulse is ended, the C4info_OutPut outputs a pulse as a trigger mark for triggering the C4 signal.
While the invention has been described with reference to certain preferred embodiments, it will be understood by those skilled in the art that various changes and substitutions of equivalents may be made and equivalents will be apparent to those skilled in the art without departing from the scope of the invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
Claims (2)
1. The device for collecting the C4 signal of the transponder is characterized by comprising a C6 signal generating end, a pulse width modulation circuit, a comparison circuit and an FPGA, wherein the C6 signal generating end, the pulse width modulation circuit, the comparison circuit and the FPGA are sequentially connected;
the change of the current of the C6 signal at the end of the original coil is detected, a pulse width modulation circuit is used for converting the current signal into a voltage signal, a comparison circuit is used for converting a sinusoidal signal into a pulse signal, and finally an FPGA is used for demodulating the width of the pulse signal, so that the C4 signal is acquired;
the pulse width modulation circuit comprises an isolation capacitor C25, a first clamping resistor R30 and a second clamping resistor R31, wherein one end of the isolation capacitor C25 is connected with a signal generating end of the C6, and the other end of the isolation capacitor C25 is connected between the first clamping resistor R30 and the second clamping resistor R31;
the C6 signal is converted into a voltage signal through a blocking capacitor C25, a first clamping resistor R30 and a second clamping resistor R31;
the device also comprises a C6 signal extraction circuit; the C6 signal extraction circuit comprises a comparison chip U8A, wherein the positive input end of the comparison chip U8A is connected with the C6 signal generation end, the negative input end of the comparison chip U8A is grounded after passing through a resistor R27, and the output end of the comparison chip U8A is output after passing through a diode D4;
the FPGA counts according to the pulse voltage change, judges whether the pulse width is widened according to the count value, and comprehensively judges whether a C4 signal arrives or not by calculating the number of the wide pulses; the FPGA processes the two converted pulses, wherein one pulse is an up-peak pulse and the other pulse is a down-peak pulse, and when any pulse is acquired by the FPGA, the C4 signal is considered to be acquired;
the comparison circuit comprises a direct current comparison chip U9A, wherein the positive input end of the direct current comparison chip U9A is connected between a first clamping resistor R30 and a second clamping resistor R31, and the output end of the direct current comparison chip U9A is connected with the FPGA; the positive input end of the direct current comparison chip U9A is connected between the first clamping resistor R30 and the second clamping resistor R31 through a resistor R36, and the negative input end is connected with a comparison power supply V6 through a resistor R37; the direct current comparison circuit U9A converts an upper peak and a lower peak of the voltage sinusoidal signal into two paths of pulse signals;
when the impedance changes, the current at the load end also changes, the primary coil of the mutual inductance coil at the LEU end generates corresponding current amplitude change, the current signal is converted into a voltage signal by detecting the change of the primary coil end C6 signal current through a pulse width modulation method, the sinusoidal signal is converted into a pulse signal through a comparison circuit, and the width of the pulse signal is demodulated by a high-speed FPGA, so that the C4 signal acquisition is realized.
2. The device for collecting the C4 signal of the transponder according to claim 1, wherein the output end of the dc comparison chip U9A is connected to the FPGA through a diode D5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710437765.5A CN107132424B (en) | 2017-06-12 | 2017-06-12 | Device for collecting C4 signal of transponder |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710437765.5A CN107132424B (en) | 2017-06-12 | 2017-06-12 | Device for collecting C4 signal of transponder |
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| CN107132424A CN107132424A (en) | 2017-09-05 |
| CN107132424B true CN107132424B (en) | 2024-03-29 |
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| US2727094A (en) * | 1950-05-17 | 1955-12-13 | Post Office | Electrically operating selecting systems |
| GB1527507A (en) * | 1974-12-23 | 1978-10-04 | American Science & Eng Inc | Synchronous power communicating |
| US5166870A (en) * | 1990-11-16 | 1992-11-24 | Honda Giken Kogyo Kabushiki Kaisha | Pulse width-modulation control device for invertor devices |
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| US5166870A (en) * | 1990-11-16 | 1992-11-24 | Honda Giken Kogyo Kabushiki Kaisha | Pulse width-modulation control device for invertor devices |
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| CN107132424A (en) | 2017-09-05 |
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