CN107112330B - Display backplane with multiple types of thin film transistors - Google Patents

Display backplane with multiple types of thin film transistors Download PDF

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CN107112330B
CN107112330B CN201580069527.2A CN201580069527A CN107112330B CN 107112330 B CN107112330 B CN 107112330B CN 201580069527 A CN201580069527 A CN 201580069527A CN 107112330 B CN107112330 B CN 107112330B
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tft
layer
region
oxide
display
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CN107112330A (en
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权会容
金炯洙
李美凜
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LG Display Co Ltd
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LG Display Co Ltd
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    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
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    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Abstract

A TFT backplane is provided that includes at least one TFT with an oxide active layer and at least one TFT with a polysilicon active layer. In the embodiment of the invention, at least one of the TFTs used to implement the pixel circuit in the active region is an oxide TFT (i.e., a TFT having an oxide semiconductor), and at least one of the TFTs used to implement the driving circuit adjacent to the active region is an LTPS TFT (i.e., a TFT having a polysilicon semiconductor).

Description

Display backplane with multiple types of thin film transistors
Technical Field
The present invention relates generally to a display device, and more particularly, to a Thin Film Transistor (TFT) array of a display device.
Description of the Related Art
Flat Panel Displays (FPDs) are used in various electronic devices such as mobile phones, tablets, notebook computers, and televisions and monitors. Examples of the FPD include a Liquid Crystal Display (LCD), a Plasma Display Panel (PDP), an Organic Light Emitting Diode (OLED) display, and an electrophoretic display (EPD). Pixels of the FPD are arranged in a matrix and controlled by a pixel circuit array. Some of the driving circuits for supplying signals for controlling the pixel circuit array are implemented by Thin Film Transistors (TFTs) on the same substrate as the pixel circuit array. The substrate on which the pixel circuits and the driving circuits are formed is referred to as a TFT backplane.
The TFT backplane is an important part of the FPD since it functions as a series of switches for controlling the current flowing to each individual pixel. To date, there are two main TFT backplane technologies, one using TFTs with amorphous silicon (a-Si) active layers and the other using TFTs with poly-silicon (poly-Si) active layers. In general, it is cheaper and easier to fabricate a TFT backplane by using amorphous silicon TFTs than to fabricate a TFT backplane with another TFT. However, a-Si TFTs have low carrier mobility, and thus it is difficult to fabricate a high-speed backplane for a display using a-Si TFTs.
In order to improve the mobility of the a-Si TFT, a-Si may be subjected to a heat treatment using a laser beam annealing the Si layer to form a polysilicon active layer. The material resulting from this process is commonly referred to as low temperature polysilicon or LTPS. LTPS TFT has a carrier mobility almost 100 times higher than that of a-Si TFT(s) ((>100cm2In v.s). LTPS TFTs provide excellent carrier mobility even in a small profile, and thus are ideal choices for fabricating fast circuits in a limited space. However, despite the foregoing advantages, the initial threshold voltage may differ between the LTPS TFTs in the backplane due to grain boundaries of the polysilicon semiconductor layer.
However, due to the polycrystalline nature of the active layer of LTPS TFTs, LTPS TFTs tend to have greater variation in threshold voltage (Vth) between TFTs in the backplane, which can lead to display non-uniformities known as "mura". For this reason, a display driving circuit implemented by LTPS TFT generally requires an additional compensation circuit, which in turn increases the manufacturing time and cost of the display.
A TFT using a semiconductor layer based on an oxide material, such as an Indium Gallium Zinc Oxide (IGZO) semiconductor layer (hereinafter, referred to as an "oxide TFT") is different from an LTPS TFT in many respects. Oxide TFTs provide higher carrier mobility than a-Si TFTs at lower fabrication costs than LTPS TFTs. In addition, the relatively lower initial threshold voltage variation than LTPS TFTs provides scalability for any glass size. Although lower mobility than LTPS TFTs, oxide TFTs are generally more advantageous in terms of efficacy than LTPS TFTs. In addition, the low leakage current of the oxide TFT during the off-state enables a great advantage for designing a power efficient circuit. For example, when high frame rate driving of the pixels is not required, the circuit may be designed to operate the pixels at a reduced frame rate.
However, stable high yield production of oxide TFT-based backplanes requires optimization of TFT design, dielectric and passivation materials, oxide film deposition uniformity, annealing conditions, and the like. Solving one problem often means compromising the performance of the other and the integration in the back plane of the display can become even lower than that of amorphous or polycrystalline silicon.
Therefore, maximum performance of the display cannot be obtained with a TFT backplane implemented with the same type of TFT. Moreover, the display itself may have various requirements such as visual quality (e.g., brightness, uniformity), efficacy, higher pixel density, reduction of bezel, and the like. It can be a difficult task to meet more than one such requirement with a TFT backplane implemented with a single type of TFT.
Brief summary
In view of the above problems, the inventors of the present embodiments have recognized that there is a limit to providing a display having higher resolution with lower power consumption using a conventional TFT backplane employing a single type of TFT. Attempts to expand the application of FPDs in devices for multiple pixel driving methods have further increased the need to provide TFT backplanes that combine the advantages of oxide transistors with those of polysilicon transistors.
According to one aspect of the present invention, there is provided a TFT backplane comprising at least one TFT having an oxide active layer and at least one TFT having a polysilicon active layer.
In the embodiment of the invention, at least one of the TFTs used to implement the pixel circuit in the display region is an oxide TFT (i.e., a TFT having an oxide semiconductor), and at least one of the TFTs used to implement the driving circuit adjacent to the display region is an LTPS TFT (i.e., a TFT having a polysilicon semiconductor). In one embodiment, a light emitting transistor and a driving transistor connected to an organic light emitting diode are implemented by using an LTPS transistor whose active layer is made of a polysilicon semiconductor. In one embodiment, the switching transistor is implemented by an oxide.
It should be noted that the embodiments described in this disclosure are not intended to be bound or limited by any expressed or implied theory presented in the preceding background or brief summary. It should also be understood that the following detailed description is merely exemplary in nature and is not intended to limit the embodiments of the application and uses thereof. Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings.
Brief description of the drawings
FIG. 1 illustrates an exemplary display that may be included in an electronic device.
Figure 2A illustrates one suitable pixel circuit that may be used in embodiments of the present invention.
Fig. 2B illustrates a timing diagram of the exemplary 4T2C pixel circuit shown in fig. 2A.
Fig. 2C illustrates a timing diagram of the exemplary 4T2C pixel circuit shown in fig. 2A provided with a plurality of types of TFTs.
Fig. 3A illustrates an exemplary 5T1C pixel circuit implemented with N-type oxide TFTs and a timing diagram describing the operation of the pixel circuit.
Fig. 3B illustrates the same 5T1C pixel circuit implemented by a combination of N-type oxide TFTs and P-type LTPS TFTs and a timing diagram describing the operation of the pixel circuit.
Fig. 4 illustrates an exemplary pixel circuit having a combination of N-type oxide TFTs and P-type LTPS TFTs configured to share a gate signal line.
Fig. 5 illustrates an exemplary configuration of two pixel circuits, one of which is provided with an N-type oxide TFT and the other of which is provided with a P-type LTPS TFT.
Fig. 6A is a cross-sectional view of an exemplary backplane implemented by multiple types of TFTs according to an embodiment of the present invention.
Fig. 6B-6H are cross-sectional views showing the configurations of the oxide TFT and LTPS TFT in the process of fabricating the oxide TFT and LTPS TFT on the backplane according to the configuration shown in fig. 6A.
Fig. 7A is a cross-sectional view of an exemplary backplane implemented by multiple types of TFTs according to an embodiment of the present invention.
Fig. 7B-7G are cross-sectional views showing the configurations of the oxide TFT and LTPS TFT in the process of fabricating the oxide TFT and LTPS TFT on the backplane according to the configuration described in fig. 7A.
Fig. 8 is a plan view of an exemplary pixel circuit configured with multiple types of TFTs (i.e., at least one LTPS TFT and at least one oxide TFT).
DETAILED DESCRIPTIONS
The various features and advantages described in this disclosure will be more clearly understood from the following description with reference to the accompanying drawings. It is noted that the drawings are merely illustrative and may not be drawn to scale for easier explanation. Further, for the purpose of describing the embodiments, components having the same or similar functions may be denoted by the same reference numerals/numerals throughout the drawings. Descriptions of the same or similar components may be omitted.
It will be understood that when an element as a layer, region or substrate is referred to as being "on" or "over" another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected to" or "directly coupled to" another element, there are no intervening elements present. Further, it will be understood that when an element is described as "overlapping" another element, at least some portion of one element may be located above or below the other element. Further, although numerical terms (e.g., first, second, third, etc.) may be used to designate some elements, it should be understood that such designations are merely used to designate one of a group of similar elements and are not intended to limit the elements in any particular order or hierarchy. As such, elements designated as first elements may be referred to as second elements or third elements without departing from the scope of the exemplary embodiments.
The various features of the various exemplary embodiments of this invention may be combined or combined in part or in whole with one another, as those skilled in the art will readily appreciate, various interactions or drives may be technically realized, and the various exemplary embodiments may be performed independently of one another or together in an associated relationship. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 illustrates an exemplary display that may be included in an electronic device. The display device 100 includes at least one display area in which an array of display pixels is formed. One or more non-display areas may be provided at the periphery of the display area. That is, the non-display area may be adjacent to one or more sides of the display area.
In fig. 1, the non-display area surrounds a display area of a rectangular shape. However, it should be understood that the shape of the display area and the arrangement of the non-display area adjacent to the display area are not particularly limited to the exemplary display 100 shown in fig. 1. The display area and the non-display area may be any shape suitable for the design of the electronic device in which the display 100 is employed. Non-limiting examples of display area shapes for display 100 include pentagonal shapes, hexagonal shapes, circular shapes, elliptical shapes, and the like.
The displays employed in the various devices may generally include display pixels formed from Light Emitting Diodes (LEDs), Organic Light Emitting Diodes (OLEDs), plasma cells, electrowetting pixels, electrophoretic pixels, Liquid Crystal Display (LCD) components, or other suitable image pixel structures. In some cases, it may be desirable to form the display 100 using OLEDs, and thus OLED displays are sometimes used in the present disclosure to describe the construction for the display 100. It should be noted, however, that the invention may be used in other types of display technologies, such as displays having liquid crystal elements and backlight structures.
Each pixel in the display area may be associated with pixel circuitry that includes one or more Thin Film Transistors (TFTs) fabricated on the backplane of the display 100. Each pixel circuit may be electrically connected to the gate line GL and the data line DL to communicate with one or more driving circuits, such as a gate driver and a data driver, located in a non-display area of the display 100.
One or more driving circuits may be implemented by TFTs prepared in the non-display region shown in fig. 1. For example, the gate driver may be implemented by a plurality of TFTs located on a substrate of the display 100. Such a gate driver may be referred to as a gate-in-panel (GIP). Various additional circuits for generating various signals for operating the pixels or for controlling other components of the display 100 may be implemented by the TFTs fabricated on the substrate. Non-limiting examples of such circuits that may be implemented by the TFTs of the backplane include inverter circuits, multiplexers, electrostatic discharge (ESD) circuits, and the like. The substrate on which the TFT array is implemented may be a glass substrate or a polymer substrate. In case the display is a flexible display, the substrate may be a flexible substrate.
Some of the driving circuits may be provided as an Integrated Circuit (IC) chip and may be mounted in a non-display region of the display 100 using a Chip On Glass (COG) or other similar methods. Further, some of the driving circuits may be mounted on another substrate and bonded to connection interfaces (pads/bumps, pins) provided in the non-display region using a printed circuit such as a flexible Printed Circuit Board (PCB), a Chip On Film (COF), a Tape Carrier Package (TCP), or any other suitable technique.
In embodiments of the present invention, at least two different types of TFTs are used in a TFT backplane for a display. The types of TFTs employed in the pixel circuit portion and the driver circuit portion may differ according to the requirements of the display.
For example, the pixel circuit may be implemented by a TFT having an oxide active layer, and the driving circuit is implemented by a TFT having a polysilicon active layer (ltps TFT). Unlike LTPS TFTs, oxide TFTs do not suffer from pixel-to-pixel threshold voltage (V) that occurs due to formation over large areasth) The problem of variation. Therefore, even for a large-sized display, uniform V of the driving TFT and/or the switching TFT can be obtained in the pixel circuit arrayth. The Vth uniformity problem among TFTs used to implement a drive circuit is unlikely to have a direct effect on the luminance uniformity of a pixel. For a driving circuit (e.g., GIP), the required factors may include the ability to provide scan signals at higher speeds and/or the size of the driving circuit for reducing the size of the bezel.
In the case of implementing the driving circuit on the backplane using LTPS TFTs, signals and data can be supplied to the pixels at a higher clock than in the case where all TFTs in the TFT backplane are formed of oxide TFTs. Accordingly, a large-sized display capable of high-speed operation can be provided without moire. In other words, the advantages of oxide TFT and LTPS TFT are combined in the design of the TFT backplane.
The use of oxide TFTs for the pixel circuitry and LTPS TFTs for the drive circuitry may also be advantageous in terms of the efficacy of the display. Conventional displays operate at a fixed refresh rate (e.g., 60Hz, 120Hz, 240Hz, etc.). However, for some image content (e.g., still images), the display need not operate at such a high refresh rate. In some cases, a portion of the display needs to operate at a high refresh rate, while another portion of the display may operate at a low refresh rate. For example, a portion of an active area displaying still image data (e.g., user interface, text) may be refreshed at a lower rate than other portions of the active area displaying rapidly changing image data (e.g., movies). In this manner, the following features may be provided to the display 100: the pixels of the entire active area or selected portions of the active area are driven at a reduced frame rate under specific conditions. In other words, the refresh rate of the display is adjusted according to the image content.
Reducing the duration of driving the pixels at unnecessarily high frequencies will minimize the power wasted by providing the pixels with the same image data. Pixels driven at a reduced refresh rate may have an increased blanking period in which a data signal is not provided to the pixel. Since the oxide TFT has very low leakage current during its off-state compared to the LTPS TFT, the pixel circuit implemented by the oxide TFT is very suitable for low frequency operation as described above. By reducing current leakage from the pixel circuit during the extended blanking period, the pixel can achieve a more stable brightness level even when the display is refreshed at a reduced rate.
Efficient utilization of real estate in the substrate is yet another advantage provided by the TFT backplane using oxide TFT based pixel circuitry and LTPS TFT based driver circuitry. The low current leakage characteristic of the oxide TFT can reduce the size of the capacitor in each pixel. The reduction in capacitor size provides more space for additional pixels within the active area of the substrate to provide a high resolution display without increasing the substrate size. Although the size of a single oxide TFT may be larger than that of an LTPS TFT, a compensation circuit may be removed by implementing a pixel circuit using an oxide TFT, thereby reducing the overall size of the pixel circuit. In addition, the relatively small size of the LTPS TFT makes it easy to implement a dense driving circuit at a region outside the active area, which can reduce the bezel size of the display.
In some embodiments, by implementing the pixel circuit and/or the drive circuit for each pixel using multiple types of TFTs, even more elaborate optimization of the display is achieved. That is, each TFT in the pixel circuit and/or the driver circuit is selected according to the function within the pixel circuit, the operating condition, and the requirements.
At its most basic, each pixel may be configured with a switching transistor, a driving transistor, a capacitor, and an OLED. Additional transistors may be used to achieve a higher performance pixel circuit.
Figure 2A illustrates one suitable pixel circuit that may be used in embodiments of the present invention.
The first switching transistor S1 includes a gate electrode connected to the light emitting signal line EM. The first switching transistor S1 has a source electrode connected to the first node N1, and a drain electrode connected to the source electrode of the driving transistor DT. One end of the first node N1 is connected to the power supply voltage signal line VDD. The driving transistor DT has a gate electrode connected to the second node N2 and a drain electrode connected to the third node N3.
The pixel circuit further includes a second switching transistor S2, the second switching transistor S2 having a source electrode connected to the data line Vdata to receive the data signal, and a drain electrode connected to the second node N2. A gate electrode of the second switching transistor S2 is connected to the SCAN line SCAN1 to turn on/off the second switching transistor S2 according to a SCAN signal from the driving circuit at the periphery of the active area.
The pixel circuit further includes a third switching transistor S3, and the third switching transistor S3 has a gate electrode connected to the second SCAN signal line SCAN 2. The third switching transistor S3 has a source electrode connected to the third node N3 and a drain electrode connected to the initialization signal line Vinit. The anode of the OLED is connected to the third node N3 and the cathode of the OLED is connected to the second power voltage line VSS.
The first capacitor CS1 includes one terminal connected to the second node N2 and the other terminal connected to the third node N3. The second capacitor CS2 includes one terminal connected to the first node N1 and the other terminal connected to the third node N3.
Fig. 2B illustrates a timing diagram of the exemplary 4T2C pixel circuit shown in fig. 2A. The timing of the TFTs in the pixel circuit shown in fig. 2B is based on the operation of the pixel circuit implemented by N-type oxide TFTs.
Although all TFTs on the substrate operate in conjunction to control the emission of light from the OLED element, each TFT in the pixel circuit plays a different role during operation. As such, even between TFTs forming a pixel circuit, the operating conditions and requirements of the TFTs may differ.
As can be seen from the figure, the reference voltage and the data voltage are alternately applied to the data line during the driving of the pixel. Applying the 1H SCAN signal on SCAN1 and EM facilitates maintaining initialization and sampling timing. However, V may occur due to stress caused by the continuous flow of current for an extended period of timethIs referred to as a positive bias stress. This problem is more prevalent in oxide TFTs than in LTPS TFTs. In the operation of the 4T2C pixel circuit as described above, the TFT serving as the light emitting transistor is in the "On" state for a much longer time than the other TFTs. In the case where a current flows over almost the entire frame, a light emitting transistor formed of an oxide TFT may cause various undesirable problems in a display.
As such, in one embodiment, the light emitting transistors of the pixel circuits are formed of P-type LTPS TFTs, while N-type oxide TFTs are used for the remaining pixel circuits. In the case of the light emitting transistor of a pixel circuit formed of P-type LTPS TFTs, the exemplary 4T2C pixel circuit may operate as shown in the timing diagram of fig. 2C. Under such an operating scheme, problems associated with PBTS in the light emitting transistors of the pixel circuits can be suppressed.
Similar configurations may be used for any other TFT of the pixel circuitry and/or driver circuitry on the backplane. That is, some TFTs in the pixel circuit that are subject to more PBTS than other TFTs of the pixel circuit may be formed by P-type LTPS TFTs. Accordingly, certain transistors of the pixel circuit configured to receive current for a longer period of time may be formed from P-type LTPS TFTs that may be more resistant to positive bias stress.
Various other configurations of LTPS TFT and oxide TFT combinations may be used in the pixel circuit. In some embodiments, a TFT connected to a storage capacitor or a node connected to the storage capacitor may be formed of an oxide TFT to minimize leakage. Furthermore, when two types of TFTs are employed in the pixel circuit and/or the driver circuit, the LTPS TFTs can be strategically placed within the circuit to remove bias voltage remaining in the nodes between the oxide TFTs during their off-states and to minimize bias stress (e.g., PBTS, NBTS).
It should be noted that the configuration of the combination of the oxide TFT and LTPS TFT in the pixel circuit described with reference to fig. 2A-2C is merely illustrative. As such, the use of a combination of oxide TFTs and LTPS TFTs within a pixel circuit may be applied in a variety of pixel circuit designs other than the 4T2C pixel circuit design shown above.
Fig. 3A illustrates an exemplary 5T1C pixel circuit implemented with N-type oxide TFTs and a timing diagram describing the operation of the pixel circuit. Fig. 3B illustrates the same 5T1C pixel circuit implemented by a combination of N-type oxide TFTs and P-type LTPS TFTs and a timing diagram describing the operation of the pixel circuit.
As shown in fig. 3A, the switching transistor whose gate electrode is connected to the second SCAN line SCAN2 and the light emitting signal line EM is configured to receive a current for a longer period of time during operation. As mentioned above, these switching transistors are likely to be subject to positive bias stress, which can lead to non-uniformities in the display. Thus, these transistors in the pixel circuit that operate under higher stress conditions (e.g., turn on for longer periods of time) may be formed from P-type LTPS TFTs that are less affected by positive bias stress than N-type LTPS TFTs. Referring to fig. 3B, the transistor controlled by the second SCAN line SCAN2 and the light emitting signal line EM may be formed of a P-type LTPS TFT. With this arrangement, the operation of the pixel circuit can be changed as shown in the timing chart of fig. 3B.
The use of a combination of P-type LTPS TFTs and N-type oxide TFTs in the pixel circuit may eliminate the need to provide an inverter circuit in the drive circuit of the backplane. Removing the inverter circuit from the driver circuit means removing the clock signal that is relevant when controlling the inverter circuit. With a reduced number of clock signals, the power consumption of the display may be reduced. In addition, a typical inverter circuit is implemented with several TFTs (e.g., 5 to 8), which can increase a considerable number of TFTs in the entire driving circuit. Thus, removing the inverter circuits and associated clock signal lines from the backplane may save considerable space from the non-display area of the display, which allows for a narrower bezel to be implemented in the display.
In the case where a CMOS circuit or an inverter circuit is provided in the backplane, it may be implemented by a combination of LTPS TFTs and oxide TFTs. For example, P-type LTPS TFTs and N-type oxide TFTs may be used to implement CMOS circuits in the driver circuits and/or pixel circuits. Therefore, in the case where an inverter circuit is required, the inverter circuit can be simplified by using a combination of an N-type oxide TFT and a P-type LTPS TFT. With this arrangement, when the inverter circuit is implemented by a combination of N-type oxide TFTs and P-type LTPS TFTs, the number of TFTs (e.g., 2) required to implement the inverter circuit can be significantly reduced.
In some embodiments, the pixel circuit array may be implemented by oxide TFTs, and the driving circuit implemented on the backplane may be implemented by a combination of N-type LTPS TFTs and P-type LTPS TFTs. For example, N-type LTPS TFTs and P-type LTPS TFTs may be used to implement CMOS circuitry (e.g., CMOS inverter circuitry) in the GIP, while oxide TFTs are employed in at least a portion of the pixel circuitry. Unlike the GIP formed entirely of P-type or N-type LTPS TFTs, a gate output signal from the GIP having the CMOS circuit may be controlled by a DC signal or a logic high/low signal. This makes it possible to control the gate lines more stably during the blanking period to suppress current leakage from the pixel circuits to the GIP or to suppress undesired activation of the pixels connected to the gate lines.
For each TFT added in the pixel circuit, an additional gate line needs to be laid out in the limited space allocated to each pixel in the display. This can complicate the manufacture of the display and limit the maximum resolution of the display that can be achieved within a fixed scale. The problem is exacerbated for OLED displays because OLED pixel circuits generally require more TFTs than pixel circuits for LCD pixels. In the case of the bottom emission type OLED display, the space occupied by the gate lines arranged within the pixels directly affects the aperture ratio of the pixels. Accordingly, in some embodiments of the present invention, a pixel circuit may be implemented by a combination of an oxide TFT and an LTPS TFT to reduce the number of gate lines.
For example, the pixel circuit may be provided with a plurality of signal lines for controlling TFTs in the pixel circuit. The first signal line may be configured to provide a high level signal (VGH) to the pixel circuit when the second signal line provides a low level signal (VGL). In this case, the one or more TFTs controlled by the first signal line may be formed of one of an N-type oxide TFT and a P-type LTPS TFT, and the one or more TFTs controlled by the second signal line may be formed of the other of an N-type oxide TFT and a P-type LTPS TFT. In this arrangement, a single signal line may be provided for the TFTs controlled by the first and second signal lines.
In other words, any pair of TFTs in the pixel circuit configured to receive signals whose levels are opposite to each other may be formed by a combination of an N-type oxide TFT and a P-type LTPS TFT. More specifically, a first TFT in a pixel circuit may be configured to receive a high level signal (VGH) while a low level signal (VGL) is provided to a second TFT in the same pixel circuit. In this case, one TFT may be formed of an N-type oxide TFT and the other TFT may be formed of a P-type LTPS TFT, and gates of the two TFTs may be connected to the same signal line. With this arrangement, a high level signal (VGH) on the signal line activates one TFT, and a low level signal (VGL) activates the other TFT of the pixel circuit.
Fig. 4 illustrates an exemplary pixel circuit having a combination of N-type oxide TFTs and P-type LTPS TFTs configured to share a gate signal line.
The pixel circuit shown in fig. 4 includes six transistors (denoted by M1 through M6) and a storage capacitor (Cst). For this pixel circuit, two different signal lines (i.e., VG1, VG2) are used to control the TFTs of the pixel circuit. The first TFT M1 is a driving TFT in the pixel circuit. The first TFT M1 has an electrode connected to the driving voltage line VDD, and another electrode connected to the node NET 2. The second transistor M2 has an electrode connected to the anode of the OLED element, and another electrode connected to the node NET2 located between the first TFT M1 and the second TFT M2. The third transistor M3 has an electrode connected to a reference voltage line Vref and is configured to supply a reference voltage to the node NET1, the node NET1 being connected to the gate of the driving TFT M1. The fourth TFTM4 has an electrode connected to the reference voltage line Vref and another electrode connected to a node NET3, the node NET3 being connected to the storage capacitor Cst. The fifth TFT M5 has an electrode connected to the node NET2 located between the driving TFT M1 and the light-emitting TFT M2. The sixth transistor M6 has an electrode connected to a data signal line of the display and transmits a data signal from the data signal line in response to a signal from the gate line.
In particular, the gate of the third TFT M3 is connected to the first signal line VG1, and the gates of the second TFT M2, the fourth TFT M4, the fifth TFT M5 and the sixth TFT M6 are connected to the second signal line VG 2. In this circuit configuration, the second TFT M2 and the fourth TFT M4 are configured to be activated at a timing opposite to that of the fifth TFT M5 and the sixth TFT M6.
Accordingly, in one suitable embodiment, the second TFT M2 and the fourth TFT M4 may be formed of N-type oxide TFTs, and the fifth TFT M5 and the sixth TFT M6 may be formed of P-type LTPS TFTs. In alternative embodiments, the second TFT M2 and the fourth TFT M4 may be formed of P-type LTPS TFTs, and the fifth TFT M5 and the sixth TFT M6 may be formed of N-type oxide TFTs. Since the second TFT M2 and the fourth TFT M4 need to be activated at a timing opposite to that of the fifth TFT M5 and the sixth TFT M6, the second TFT M2 and the fourth TFT M4 may be formed of P-type oxide TFTs, while the fifth TFT M5 and the sixth TFT M6 are formed of N-type LTPS TFTs. In yet another embodiment, the second TFT M2 and the fourth TFT M4 may be formed of P-type LTPS TFTs, and the fifth TFT M5 and the sixth TFT M6 are formed of P-type oxide TFTs.
The use of plural types of TFTs on the same substrate is not necessarily limited to the level of the GIP (stage level) or to a single pixel circuit. That is, at least one TFT in one stage of the shift register of the GIP may be formed of an oxide TFT, and one TFT in another stage of the shift register may be formed of an LTPS TFT. Similarly, one TFT in one pixel circuit may be formed of an oxide TFT, and one TFT in another pixel circuit may be formed of an LTPS TFT.
Fig. 5 illustrates an exemplary configuration of two pixel circuits, one of which is provided with an N-type oxide TFT and the other of which is provided with a P-type LTPS TFT. As shown in fig. 5, the first pixel circuit includes a switching TFT formed of an N-type oxide TFT, and the corresponding TFT in the second pixel circuit is formed of a P-type LTPS TFT. The first pixel circuits may be associated with odd rows of pixels of the display and the second pixel circuits may be associated with even rows of pixels of the display. With this arrangement, the gate of the N-type oxide TFT of the first pixel circuit and the gate of the P-type LTPS TFT of the second pixel circuit may be connected to a single gate line. Thus, the number of gate lines can be reduced in the display.
The TFT in each pixel circuit sharing the gate line may be a TFT configured to provide a data signal in response to a gate signal on the shared gate line. In one illustrative example, the signals used to control the pixel circuits may be set as follows: data signal Vdata between 0 and 5V, VGL of-10V, VGO of 3V, VGH of 15V, Vref of 1V. With this arrangement, the threshold voltages of the N-type oxide TFT in the first pixel circuit and the P-type LTPS TFT in the second pixel circuit can be set to 3V and-2.5V, respectively.
The driving TFT connected to the OLED element in the first pixel circuit and the second pixel circuit is not particularly limited, and may be formed of any one of an N-type oxide TFT and a P-type LTPS TFT. The driving TFTs in the first pixel circuit and the second pixel circuit may be formed of TFTs of different types from each other, if necessary.
It is to be understood that the N-type oxide TFT in the first pixel circuit and the P-type LTPS TFT in the second pixel circuit are not limited to the TFT connected to the data signal line. Other switching TFTs in the two pixel circuits, for example, TFTs connected to the reference signal line may be constituted by TFTs of different kinds from each other according to the design and driving scheme of the pixel circuits. The use of N-type oxide TFTs and P-type LTPS TFTs in adjacent pixel circuits allows the number of gate lines at the boundary of two adjacent pixels to be reduced, which is particularly advantageous in transparent displays. In a transparent display provided with pixels divided into light-emitting regions (i.e., regions having pixel circuits) and transparent regions, the light-emitting regions of two adjacent pixels (e.g., odd-row pixels and even-row pixels) are disposed adjacent to a shared gate line. This configuration allows the transparent regions of the pixels to be located adjacent to each other, which may improve the transparency of the display.
Providing multiple types of TFTs on the same substrate as described in the present invention can be a very challenging process. Some processes associated in forming one type of TFT may damage or degrade other types of TFTs on the same backplane. For example, the annealing process used to form the polycrystalline semiconductor layer may damage the metal oxide semiconductor layer. As such, it is desirable that an annealing process in fabricating the LTPS TFT on the backplate may be performed before the metal oxide layer serving as an active layer of the oxide TFT is disposed. In addition, preparing a back plate having a plurality of types of TFTs may increase the number of masks, thereby reducing yield and increasing manufacturing costs of a display.
Fig. 6A is a cross-sectional view of an exemplary backplane implemented by multiple types of TFTs according to an embodiment of the present invention.
When the back plate of the flexible display is implemented by various semiconductor materials including an oxide semiconductor, the metal oxide semiconductor layer may be patterned and selectively become an electrode of the LTPS TFT. More specifically, the metal oxide semiconductor layer may be patterned into an active layer of an oxide TFT and one or more electrodes for an LTPS TFT. Post-processing, such as plasma treatment for increasing carrier concentration or other implantation and/or thermal annealing processes, may be performed on portions of the patterned oxide semiconductor layer such that the processed portions act as S/D regions of the oxide TFT, with channel regions located between the S/D regions. The same process may be performed on a metal oxide layer patterned in the location of one or more electrodes of the LTPS TFT so that it may serve as an electrode of the LTPS TFT.
Using a metal oxide layer for forming an active layer of an oxide TFT as one or more electrodes in an LTPS TFT allows reducing the number of masks required when fabricating a backplane having a plurality of types of TFTs. Further, although the specific functions of the insulating layers may differ among TFTs, some of the insulating layers used in forming LTPS TFTs on the backplane may also serve as insulating layers of oxide TFTs. Using the insulating layer of one type of TFT for the insulating layer of another type of TFT may also help to reduce the number of masks and simplify the manufacturing process of the backplane.
Fig. 6B-6H are cross-sectional views showing the configurations of the oxide TFT and LTPS TFT in the process of fabricating the oxide TFT and LTPS TFT on the backplane according to the configuration shown in fig. 6A. Referring to fig. 6B, a buffer layer 604 is formed on a substrate 602. In a region for forming the LTPS TFT (denoted by "LTPS TFT region"), a polysilicon active layer 606 is formed on the buffer layer 604. The polysilicon active layer 606 of the LTPS TFT would require a first mask (for polysilicon active layer patterning) to be fabricated as shown in fig. 6B. As described, a laser anneal or other suitable process for changing the amorphous silicon layer into the polysilicon active layer 606 may be performed prior to depositing the metal oxide layer on the backplate.
Referring to fig. 6C, a first insulating layer 608 is disposed on the polysilicon active layer 606 to serve as a gate insulating layer (GI _ L). If necessary, a first insulating layer 608 may be provided in a region for forming an oxide TFT (represented by "oxide TFT region") to serve as an additional buffer layer located under an active layer of the oxide TFT. Then, a metal oxide layer 610 is disposed in the oxide TFT region, which will serve as an active layer of the oxide TFT. Instead of providing a separate conductive layer for the gate of the LTPS TFT, a metal oxide layer 610 is patterned on the gate insulating layer 608 in the LTPS TFT region. In other words, the metal oxide layer 610 serves as a gate electrode of the LTPS TFT and also serves as an active layer of the oxide TFT.
As briefly described above, one or more post-treatments (e.g., plasma treatment, doping, implantation, annealing, etc.) may be performed to increase the conductivity at selected portions of the metal oxide layer 610. In particular, post-processing may be performed to increase the conductivity at the S/D regions of the metal oxide layer 610 at the oxide TFT regions. Post-processing to form S/D regions in the metal oxide layer 610 of the oxide TFT also increases the conductivity of the metal oxide layer 610 patterned on the gate insulation layer 608 at the LTPS TFT regions. With increased conductivity, the metal oxide layer 610 at the LTPS TFT area may effectively serve as the gate electrode of the LTPS TFT. It will be appreciated that by using the metal oxide layer 610 to form the gate electrode of an LTPS TFT, the mask required in fabricating backplanes with multiple types of TFTs is reduced.
In this regard, a Photoresist (PR) layer may be disposed over the metal oxide layer in the LTPS TFT region and the oxide TFT region, and then, selected portions of the PR layer are exposed through a second mask. Here, a half-tone mask (HTM) process may be used such that the PR layer located over the channel region of the oxide TFT region is left with a higher thickness than the PR layer located over the other portions of the metal oxide layer 610. That is, the PR layer located above the channel region in the active layer of the oxide TFT may be left with a greater thickness than the PR layer located above the S/D region in the active layer of the oxide TFT. In addition, the PR layer located above the channel region in the active layer of the oxide TFT may be left with a greater thickness than the PR layer located above the metal oxide layer 610 (which is to serve as the gate electrode of the LTPS TFT) in the LTPS TFT region. The additional thickness of the PR layer over the channel region of the oxide TFT allows the semiconductor characteristics to be maintained even after the process for increasing the conductivity of the metal oxide layer 610 at the LTPS TFT region to become a gate electrode.
Referring to fig. 6D, a second insulating layer 612 is disposed over the LTPS TFT region and the oxide TFT region. Here, the second insulating layer 612 may be patterned using a third mask such that it functions as an interlayer dielectric layer (ILD) at the LTPS TFT region and also functions as a gate insulating layer (GI _ O) in the oxide TFT region. In this regard, the thickness of the second insulating layer 612 at selected regions may be controlled using a half-tone mask processAnd (4) degree. More specifically, the second insulating layer 612 may be formed in the LTPS TFT region at a first thickness suitable to act as an ILD. The second insulating layer 612 may be formed in the oxide TFT region at a second thickness suitable to serve as a gate insulating layer (GI _ O). For example, the second insulating layer 612 may have about in the LTPS TFT region
Figure GDA0002565554820000141
And may have a thickness of about in the oxide TFT region
Figure GDA0002565554820000142
Is measured. As shown in fig. 6D, a contact hole exposing the S/D region of the polysilicon active layer 606 may be provided.
Referring to fig. 6E, a first metal layer 614 may be disposed over the second insulating layer 612. The first metal layer 614 is patterned using a fourth mask. In the LTPS TFT area, the first metal layer 614 is patterned to form S/D electrodes of the LTPS TFT. In the oxide TFT region, the first metal layer 614 is patterned to form a gate electrode of the oxide TFT.
Referring to fig. 6F, a third insulating layer 616 is disposed over the LTPS TFT region and the oxide TFT region. The third insulating layer 616 is patterned using a fifth mask to act as a passivation layer over the S/D electrodes of the LTPS TFT and to act as an ILD for the oxide TFT. Because the third insulating layer 616 serves as a passivation layer over the S/D electrodes of the LTPS TFT, one or more contact holes may be provided through the third insulating layer 616 to expose portions of the S/D electrodes of the LTPS TFT. Contact holes through the third insulating layer 616 may be used to connect signal lines and/or other electrodes to the S/ds of the LTPS TFT.
Referring to fig. 6G, a second metal layer 618 is disposed over the third insulating layer 616. The second metal layer 618 may be patterned into an intermediate metal layer (INT) at the LTPS TFT region using a sixth mask, the intermediate metal layer being connected to the S/D electrodes of the LTPS TFT through contact holes in the third insulating layer 616. Although the second metal layer 618 in the LTPS TFT region is described as an intermediate metal layer in the present embodiment, the function of the second metal layer 618 is not limited thereto. Accordingly, the second metal layer 618 may serve as signal lines, electrodes, and for various other purposes in the backplane. In the oxide TFT region, the second metal layer 618 may be patterned to serve as an S/D electrode of the oxide TFT.
Referring to fig. 6H, a fourth insulating layer 620 is disposed over both the LTPS TFT and the oxide TFT. The fourth insulating layer 620 may be a Planarization Layer (PLN) for providing a flat surface over the LTPS TFT region and the oxide TFT region. A seventh mask may be used to provide contact holes through fourth insulating layer 620 to expose selected portions of second metal layer 618. In fig. 6H, the intermediate metal layer (INT) is exposed through the contact hole of the fourth insulating layer 620. Although the fourth insulating layer 620 serves as a Planarization Layer (PLN) over both the LTPS TFT and the oxide TFT, it also serves as a passivation layer over the S/D electrodes of the oxide TFT. Accordingly, in some embodiments, the fourth insulating layer 620 may be provided with one or more contact holes for exposing the S/D electrodes of the oxide TFT.
Referring to fig. 6A, the third metal layer 622 may be patterned in a desired region over the fourth insulating layer 620 by using an eighth mask. The third metal layer 622 may be in contact with the second metal layer 618 via the fourth insulating layer 620. For example, the third metal layer 622 may be in contact with the intermediate metal layer (INT) as shown in fig. 6A. In some other embodiments, the third metal layer 622 patterned over the fourth insulating layer 620 may be in contact with the S/D electrodes of the oxide TFT.
It should be understood that the LTPS TFT and the oxide TFT shown in FIG. 6A may be configured for various uses in a backplane. Any combination of the use of oxide TFTs and LTPS TFTs described in the present invention may be implemented using the configuration of oxide TFTs and LTPS TFTs shown in FIG. 6A. The LTPS TFT shown in fig. 6A may be a TFT included in a driving circuit, and the oxide TFT may be a TFT included in a pixel circuit. The LTPS TFT shown in fig. 6A may be a TFT included in a pixel circuit, and the oxide TFT may be a TFT included in a driving circuit. Both the LTPS TFT and the oxide TFT shown in fig. 6A may be TFTs included in a single pixel circuit or a plurality of pixel circuits. In addition, both the LTPS TFT and the oxide TFT shown in fig. 6A may be TFTs included in a single driver circuit or a plurality of driver circuits.
Thus, the function of the third metal layer 622 in the backplane may differ depending on the location of the third metal layer 622 within the backplane and the location and function of the TFTs connected to the third metal layer 622. As an example, the LTPS TFT shown in fig. 6A may be a driving TFT in a pixel circuit, and the third metal layer 622 may serve as an anode of an OLED element. In some cases, the LTPS TFT shown in fig. 6A may be a switching TFT in a pixel circuit, and the third metal layer 622 may be a signal line transmitting a signal from a driving circuit. In some cases, the LTPS TFT may be one of TFTs for implementing driving circuits disposed in a non-display region of the display, and the third metal layer 622 may serve as a signal line for transmitting signals from the respective driving circuits. As described above, instead of the LTPS TFT, the third metal layer 622 may contact the S/D electrodes of the oxide TFTs and provide functions related to the respective oxide TFTs.
In the configuration of fig. 6A, the gate of the LTPS TFT is formed of a metal oxide layer forming a semiconductor layer of the oxide TFT. Furthermore, several insulating layers provided in the backplane are used for one purpose in the LTPS TFT area and for another purpose in the oxide TFT area. This may provide a more efficient way of manufacturing backplanes with multiple types of TFTs.
FIG. 7A illustrates another exemplary configuration of an oxide TFT and LTPS TFT of a backplane according to an embodiment of the present invention. Fig. 7B-7G are cross-sectional views showing the configurations of the oxide TFT and LTPS TFT in the process of fabricating the oxide TFT and LTPS TFT on the backplane according to the configuration shown in fig. 7A.
Referring to fig. 7B and 7C, the configuration of the buffer layer 704 and the polysilicon active layer 706 on the substrate 702 is the same as that described with reference to fig. 6B. Reference numeral 708 denotes a first insulating layer. Therefore, forming the gate electrode of the LTPS TFT using the metal oxide layer 710 requires two masks.
A further reduction in the number of masks required is achieved by the configuration described in figure 7D. It should be noted that the interlayer dielectric layer (ILD) of the LTPS TFT and the oxide TFT is formed by different insulating layers in the configuration of fig. 6A. That is, an interlayer dielectric layer (ILD) of the LTPS TFT is formed using the second insulating layer 612, and an interlayer dielectric layer (ILD) of the oxide TFT is formed using the third insulating layer 616.
However, in the configuration shown in FIG. 7D, the same insulating layer is employed to serve as the interlayer dielectric layer (ILD) for both the LTPS TFT and the oxide TFT. More specifically, the second insulating layer 712, which functions as an interlayer dielectric layer (ILD) of the LTPS TFT, also functions as an interlayer dielectric layer (ILD) of the oxide TFT.
In addition, the second insulating layer 712 is also used for another purpose of the oxide TFT. In particular, the second insulating layer 712 is patterned using a third mask so that it also functions as a gate insulating layer (GI _ O) of the oxide TFT. By forming the gate insulating layer (GI _ O) and the interlayer dielectric layer (ILD) of the oxide TFT together with the interlayer dielectric layer (ILD) of the LTPS TFT, the need for at least one mask in a manufacturing process of disposing a plurality of types of TFTs in a backplane is eliminated.
It should be noted that the thickness of the interlayer dielectric layer (ILD) suitable for LTPS TFTs may be different from the thickness of the interlayer dielectric layer (ILD) suitable for oxide TFTs. In addition, the thickness of the gate insulating layer (GI _ O) is generally different from the thickness of the interlayer dielectric layer (ILD). Thus, the second insulating layer 712 can be patterned using a half-tone mask (HTM) to control its thickness at different portions of the backplate. As an example, in the LTPS TFT region, the second insulating layer 712 may be disposed at a first thickness suitable to serve as an interlayer dielectric layer (ILD) of the LTPS TFT. In the oxide TFT region, a portion of the second insulating layer 712, which serves as an interlayer dielectric layer (ILD), may be disposed at a second thickness, and the other portion, which serves as a gate insulating layer (GI _ O), may be disposed at a third thickness.
In some cases, the first thickness and the second thickness of the second insulating layer 712 in the LTPS TFT region and the oxide TFT region may be the same. In one suitable implementation, the second insulating layer 712 may be approximately as long as the second insulating layer 712 acts as an interlayer dielectric layer (ILD)
Figure GDA0002565554820000171
Is set to about a thickness of (d), but in the case where the second insulating layer 712 serves as a gate insulating layer (GI _ O) of the oxide TFT
Figure GDA0002565554820000172
Is set.
Referring to fig. 7E, a first metal layer 714 is disposed over the second insulating layer 712. The first metal layer 714 is patterned using a fourth mask to set the S/D electrodes of the LTPS TFT and the gate electrode of the oxide TFT. Unlike the configuration shown in fig. 6A, the first metal layer 714 also forms the S/D electrodes of the oxide TFT as shown in fig. 7E. In other words, all electrodes of the LTPS TFT and the oxide TFT except for the gate electrode of the LTPS TFT are formed using the same metal layer (i.e., the first metal layer 714). By forming the S/D electrodes of the oxide TFT and LTPS TFT and the gate electrode of the oxide TFT together using a single metal layer, at least one mask is reduced.
Referring to fig. 7F, a third insulating layer 716 and a fourth insulating layer 720 are disposed over the first metal layer 714. The third insulating layer 716 may serve as a passivation layer of S/D electrodes of both the LTPS TFT and the oxide TFT. The fourth insulating layer 720 is disposed over the third insulating layer 716. The fourth insulating layer 720 may serve as a planarization layer providing a flat surface over the LTPS TFT and the oxide TFT.
It should be noted that in the configuration shown in fig. 6A, the third insulating layer 616, which serves as a passivation layer for the LTPS TFT, needs to serve as an interlayer dielectric layer (ILD) for the oxide TFT. Therefore, a contact hole for the S/D electrode must be created before the fourth insulating layer 620 is disposed over the third insulating layer 616, and then a separate process is required to create other contact holes through the fourth insulating layer 620.
However, in the embodiment configured as shown in fig. 7A, each of the third insulating layer 716 and the fourth insulating layer 720 serves the same function for the LTPS TFT and the oxide TFT. In particular, the third insulating layer 716 serves as a passivation layer for both the LTPS TFT and the oxide TFT, and thus the third insulating layer 716 does not need to be patterned before the fourth insulating layer 720 is disposed. Instead, a contact hole for an S/D electrode contact may be created using a single mask after the third insulating layer 716 and the fourth insulating layer 720 are disposed.
Referring to fig. 7G, a second metal layer 718 is disposed over the fourth insulating layer 720 to contact the S/D electrode of one of the TFTs. In fig. 7G, the second metal layer 718 is shown in contact with the S/D electrodes of the oxide TFT through contact holes provided in the third and fourth insulating layers. However, this is merely illustrative. If necessary, contact holes may be provided in the third and fourth insulating layers so that the second metal layer 718 may contact the S/D electrodes of the LTPS TFT. As described above, for any of the exemplary configurations described in the present invention, LTPS TFTs and oxide TFTs may be used within the backplane. Thus, the function of the second metal layer 718 may vary depending on the application of the particular TFT with which it is in contact.
Fig. 8 is a plan view of an exemplary pixel circuit configured with multiple types of TFTs (i.e., at least one LTPS TFT and at least one oxide TFT).
In embodiments having S/D electrodes and gate electrodes (e.g., electrodes configured as in fig. 7A) formed from a single metal layer, the gate lines and S/D lines may cross each other. Of course, the gate lines and the S/D lines should not contact each other. Therefore, the metal oxide layer used as the active layer of the oxide TFT can also be used as a means for laying lines that cross each other without generating short circuits.
Referring to fig. 8, the first line 810 is arranged in a horizontal direction and the second line 820 is arranged in a vertical direction. The first line 810 is provided as a plurality of blocks (e.g., 810(a), 810(B)) divided at an area indicated by "X". Otherwise, the first line 810 will cross the second line 820, creating a short between the lines at the intersection region "X". Further, the metal oxide layer located under the metal layers of the first and second lines (810, 820) is patterned such that it is disposed at the crossing region "X". The conductivity of the metal oxide layer in the intersection region "X" can be increased in a similar manner to the metal oxide layer configured as the gate electrode of the LTPS TFT. Contact holes may be disposed through an insulating layer disposed over the metal oxide layer such that the first block 810(a) and the second block 810(B) of the first line 810 contact the underlying metal oxide layer. As such, the metal oxide layer disposed at the intersection region "X" may serve as a bridge for connecting the blocks (810(a), 810(B)) of the first line 810. Therefore, even in the embodiment in which the S/D electrodes and the gate electrodes of the TFTs are disposed using a single metal layer, the first and second lines 810 and 820 may be arranged to cross each other.
In the present invention, the metal oxide layer serving as the active layer of the oxide TFT is described as being composed of indium gallium zinc oxide. However, this is merely illustrative. Various other compositions may be used for the metal oxide layer of the present invention. Examples of the constituent material of the metal oxide layer include: quaternary metal oxides such as indium tin gallium zinc oxide (In-Sn-Ga-Zn-O) based materials; ternary metal oxides such as indium gallium zinc oxide (In-Ga-Zn-O) -based materials, indium tin zinc oxide (In-Sn-Zn-O) -based materials, indium aluminum zinc oxide (In-Al-Zn-O) -based materials, indium hafnium zinc oxide (In-Hf-Zn-O) -based materials, tin gallium zinc oxide (Sn-Ga-Zn-O) -based materials, aluminum gallium zinc oxide (Al-Ga-Zn-O) -based materials, and tin aluminum zinc oxide (Sn-Al-Zn-O) -based materials; and binary metal oxides such as indium zinc oxide (In-Zn-O) -based materials, tin zinc oxide (Sn-Zn-O) -based materials, aluminum zinc oxide (Al-Zn-O) -based materials, zinc magnesium oxide (Zn-Mg-O) -based materials, tin magnesium oxide (Sn-Mg-O) -based materials, indium magnesium oxide (In-Mg-O) -based materials, indium gallium oxide (In-Ga-O) -based materials, and the like; indium oxide (In-O) -based materials; tin oxide (Sn-O) based materials and zinc oxide (Zn-O) based materials. The composition ratio of the elements contained in each metal oxide layer is not particularly limited, and may be adjusted in various composition ratios.
While the invention has been particularly shown and described with respect to preferred embodiments, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims. Although the low refresh rate drive mode and the TFT backplane adapted for such drive mode are described in the context of OLED displays, it should be understood that similar TFT backplanes of embodiments described in the present disclosure may be used for Liquid Crystal Displays (LCDs) and other various types of displays.

Claims (19)

1. A display device, comprising:
a substrate defining a first region and a second region;
a low temperature polysilicon layer disposed in the first region;
a first insulating layer disposed on the low-temperature polysilicon layer in the first region;
a metal oxide layer disposed in the first region and the second region, the metal oxide layer in the first region disposed on the first insulating layer;
a second insulating layer disposed in the first region and the second region, the second insulating layer in the first region having a contact hole for exposing at least a portion of the underlying low temperature polysilicon layer, and the second insulating layer in the second region being disposed on the metal oxide layer to expose at least two portions of the metal oxide layer separated by a portion covered by the second insulating layer;
a first metal layer in the first region and the second region, the first metal layer in the first region being in contact with the exposed portion of the low temperature polysilicon layer, and the first metal layer in the second region being insulated from the metal oxide layer by an underlying second insulating layer;
a third insulating layer covering the first metal layer in the first region and the second region;
a second metal layer disposed in the first region and the second region, the second metal layer in the first region being in contact with the first metal layer via a contact hole that passes through the third insulating layer, and the second metal layer in the second region being in contact with the metal oxide layer via a contact hole that passes through the third insulating layer; and
a fourth insulating layer disposed in the first and second regions and over the second metal layer, wherein the metal oxide layer in the first region has a higher conductivity than a portion of the metal oxide layer in the second region covered by the second insulating layer,
wherein the low-temperature polysilicon layer serves as an active layer of a low-temperature polysilicon TFT, and the metal oxide layer in the second region serves as an active layer of an oxide TFT.
2. The display device according to claim 1, further comprising a third metal layer over the fourth insulating layer, the third metal layer being in contact with the second metal layer in the first region or the second metal layer in the second region via a contact hole that passes through the fourth insulating layer.
3. The display apparatus of claim 1, wherein a metal oxide layer in the first region serves as a gate electrode of the low temperature polysilicon TFT.
4. The display device according to claim 1, wherein the second insulating layer serves as an interlayer dielectric layer of the low-temperature polysilicon TFT in the first region and serves as a gate insulating layer of the oxide TFT in the second region.
5. The display device according to claim 1, wherein a second insulating layer interposed between the first metal layer and the metal oxide layer in the second region is thinner than a second insulating layer provided in the first region.
6. The display device according to claim 1, wherein the first metal layer provides a source electrode and a drain electrode of the low temperature polysilicon TFT in the first region, and the first metal layer provides a gate electrode of the oxide TFT in the second region.
7. The display device according to claim 2, wherein the third insulating layer serves as a passivation layer of the low-temperature polysilicon TFT in the first region and serves as an interlayer dielectric layer of the oxide TFT in the second region.
8. The display device according to claim 2, wherein the third metal layer in contact with the second metal layer is an anode of an organic light-emitting element.
9. The display device according to claim 2, wherein the third metal layer in contact with the second metal layer is a signal line.
10. A display, comprising:
a TFT array including at least one oxide TFT and at least one low temperature polysilicon TFT, wherein an active layer of the at least one oxide TFT and a gate electrode of the at least one low temperature polysilicon TFT are made of a metal oxide layer,
wherein the metal oxide layer in the low temperature polysilicon TFT has a higher conductivity than a portion of the metal oxide layer in the oxide TFT covered by an insulating layer.
11. The display defined in claim 10 wherein the interlayer dielectric layer of the at least one low temperature polysilicon TFT and the gate insulating layer of the at least one oxide TFT are made from the same insulating layer.
12. The display defined in claim 11 wherein the source/drain electrodes of the at least one low temperature polysilicon TFT and the gate electrode of the at least one oxide TFT are made from the same metal layer.
13. The display defined in claim 12 wherein the intermediate metal layer that contacts the source/drain electrodes of the at least one low temperature polysilicon TFT and the source/drain electrodes of the at least one oxide TFT are made from the same metal layer.
14. The display defined in claim 13 wherein the at least one oxide TFT is disposed in a display area of the display and the at least one low temperature polysilicon TFT is disposed in a non-display area of the display.
15. The display defined in claim 13 further comprising:
a pixel circuit located in the display area and associated with the display pixel;
a driving circuit in a non-display region for supplying a plurality of signals to the pixel circuit, wherein the pixel circuit is implemented by the oxide TFT and the driving circuit is implemented by the low temperature polysilicon TFT.
16. The display defined in claim 13 wherein the array of TFTs comprises an array of pixel circuits in the display area associated with a plurality of display pixels, wherein the array of pixel circuits comprises the oxide TFTs and the low-temperature polysilicon TFTs.
17. The display defined in claim 16 wherein one pixel circuit associated with a single display pixel comprises the oxide TFT and the low-temperature polysilicon TFT.
18. The display defined in claim 13 further comprising drive circuitry in a non-display area that is to provide a plurality of signals to an array of pixel circuitry associated with a plurality of display pixels in a display area, wherein the drive circuitry in the non-display area includes the at least one oxide TFT and the at least one low temperature polysilicon TFT.
19. The display defined in claim 12 wherein the TFT array comprises an array of a plurality of pixel circuits, each pixel circuit associated with an organic light-emitting diode element, wherein an anode of the organic light-emitting diode element is connected to the at least one oxide TFT or the at least one low temperature polysilicon TFT.
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