CN107112330A - Display backplane with polytype thin film transistor (TFT) - Google Patents

Display backplane with polytype thin film transistor (TFT) Download PDF

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Publication number
CN107112330A
CN107112330A CN201580069527.2A CN201580069527A CN107112330A CN 107112330 A CN107112330 A CN 107112330A CN 201580069527 A CN201580069527 A CN 201580069527A CN 107112330 A CN107112330 A CN 107112330A
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Prior art keywords
tft
area
oxide
layer
ltps
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Granted
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CN201580069527.2A
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CN107112330B (en
Inventor
权会容
金炯洙
李美凜
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LG Display Co Ltd
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LG Display Co Ltd
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Priority claimed from US14/588,180 external-priority patent/US9449994B2/en
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    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1229—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with different crystal properties within a device or between different devices
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
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    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
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    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Abstract

There is provided a kind of TFT backplate, the TFT backplate includes at least one TFT with oxide active layer and at least one TFT with polysilicon active layer.In embodiments of the present invention, at least one TFT in TFT for realizing the image element circuit in active region be oxide TFT (i.e., TFT with oxide semiconductor), and it is used to realize that at least one TFT in the TFT of the drive circuit adjacent with active region is LTPS TFT (that is, the TFT with polysilicon semiconductor).

Description

Display backplane with polytype thin film transistor (TFT)
Technical field
This patent disclosure relates generally to a kind of display device, more particularly to a kind of thin film transistor (TFT) of display device (TFT) array.
Description of related art
Flat-panel monitor (FPD) be used in such as mobile phone, flat board, notebook computer etc various electronic installations and In TV and monitor.FPD example includes liquid crystal display (LCD), plasma display (PDP), organic light emission two Pole pipe (OLED) display and electrophoretic display device (EPD) (EPD).FPD pixel is arranged and by pixel circuit array in the matrix form Control.There is provided some drive circuits of signal for controlling pixel circuit array by positioned at pixel circuit array identical base Thin film transistor (TFT) (TFT) on plate is realized.The substrate referred to as TFT backplate of image element circuit and drive circuit is formed with above.
Because TFT backplate acts to be used for controlling stream to a series of switches of each individually electric current of pixel, so TFT Backboard is FPD pith.So far, there are two kinds of main TFT backplate technologies, one kind is used with non-crystalline silicon (a- Si) the TFT of active layer, it is another to use the TFT with polysilicon (poly-Si) active layer.In general, by using amorphous It is more less expensive and easy than making TFT backplate with another TFT that silicon TFT prepares TFT backplate.However, a-Si TFT have it is relatively low Carrier mobility, thus it is relatively difficult to be made of a-Si TFT for the High speed rear panel of display.
In order to improve a-Si TFT mobility, can be used makes a-Si experience heat treatments by the laser beam of Si layers of annealing, with Form polysilicon active layer.Thus the material that technique is produced is commonly referred to as low temperature polycrystalline silicon or LTPS.LTPS TFT carrier Similar 100 times of mobility ratio a-Si TFT height (>100cm2/V.s).When smaller profile, LTPS TFT are still provided The carrier mobility of color, thus for preparing fast circuit in a limited space, LTPS TFT are preferable selections.So And, although with aforementioned advantages, due to the crystal boundary of polysilicon semiconductor layer, initial threshold between the LTPS TFT in backboard Voltage can be different.
However, LTPS TFT are often in threshold between the polycrystalline property of the active layer due to LTPS TFT, the TFT in backboard There is bigger change, this can cause the display inhomogeneities for being referred to as " moire (mura) " in terms of threshold voltage (Vth).Due to this Individual reason, usually requires extra compensation circuit, this in turn increases display by the LTPS TFT display driver circuits realized Preparation time and cost.
Using the semiconductor layer based on oxide material, such as the TFT of indium gallium zinc (IGZO) semiconductor layer is (referred to hereinafter as For " oxide TFT ") it is different from LTPS TFT at many aspects.Oxide TFT is provided with the manufacturing cost lower than LTPS TFT The carrier mobility higher than a-Si TFT.In addition, the initial threshold voltage change more relatively low than LTPS TFT is provided and used In the scalability of any glass size.Although the mobility lower than LTPS TFT, oxide TFT generally compares in terms of effect LTPS TFT are more favourable.In addition, oxide TFT low-leakage current causes for design high effect circuit during cut-off state There can be very big advantage.For example, when not needing the high frame rate driving of pixel, circuit is designed to the frame with reduction Speed operates pixel.
However, the stable, high-yielding rate production of the backboard based on oxide TFT needs TFT designs, dielectric and passivating material, oxygen The optimization of compound film deposition uniformity, annealing conditions etc..A problem is solved to generally mean that another trade-off of performance, and And the integrated level in the backboard of display can become the integrated level of even below non-crystalline silicon or polysilicon.
Therefore, the maximum performance of display can not be obtained using the TFT backplate of the TFT realizations by same type.Moreover, aobvious Show that device itself can have various requirement, such as visual quality (for example, brightness, uniformity), effect, higher picture element density, side Reduction of frame etc..It can be difficult to meet more than one this requirement using the TFT backplate of the TFT realizations by single type Task.
It is briefly summarized
In view of the above problems, embodiment of the present invention it was recognized by the inventor that using using single type TFT routine TFT backplate provides the display with high-resolution with lower power consumption and there is limitation.For a variety of image element driving methods The application that spread F PD is attempted in device is further increased to providing the advantage of oxide transistor and polysilicon transistors The demand of the TFT backplate of advantage combination.
According to an aspect of the invention, there is provided a kind of TFT backplate, it includes at least one with oxide active layer Individual TFT and at least one TFT with polysilicon active layer.
In embodiments of the present invention, at least one TFT in the TFT for realizing the image element circuit in viewing area It is oxide TFT (that is, the TFT with oxide semiconductor), and is used for the TFT of the realization drive circuit adjacent with viewing area In at least one TFT be LTPS TFT (that is, the TFT with polysilicon semiconductor).In one embodiment, by using The LTPS transistors that active layer is made up of polysilicon semiconductor realize lighting transistor and are connected to the drive of Organic Light Emitting Diode Dynamic transistor.In one embodiment, switching transistor is realized by oxide.
It should be noted that the embodiment described in the present invention is not intended to what is proposed in aforementioned background art and brief overview Any statement or the theoretical constraint implied are limited.It is also understood that following detailed description is only example in nature Property, it is not intended to limit presently filed embodiment and application thereof.Hereinafter, it will be described in detail with reference to the accompanying drawings exemplary embodiment party Formula.
Brief Description Of Drawings
Fig. 1 illustrates the exemplary display that can be included in electronic installation.
Fig. 2A illustrates an available appropriate image element circuit in embodiments of the present invention.
Fig. 2 B illustrate the timing diagram of the exemplary 4T2C image element circuits shown in Fig. 2A.
Fig. 2 C illustrate the sequential of the exemplary 4T2C image element circuits for being provided with polytype TFT shown in Fig. 2A Figure.
Fig. 3 A illustrate by the N-type oxide TFT exemplary 5T1C image element circuits realized and described the behaviour of image element circuit The timing diagram of work.
Fig. 3 B illustrate by N-type oxide TFT and p-type LTPS TFT combination realize identical 5T1C image element circuits with And the timing diagram of the operation of description image element circuit.
Fig. 4 illustrates the combination with N-type oxide TFT and p-type the LTPS TFT for being configured to shared gate line Exemplary pixels circuit.
Fig. 5 illustrates the representative configuration of two image element circuits, and one of image element circuit is provided with N-type oxide TFT, One other pixel circuit is provided with p-type LTPS TFT.
Fig. 6 A are the profiles by polytype TFT exemplary backboards realized according to embodiment of the present invention.
Fig. 6 B-6H are shown in prepares oxide TFT and LTPS TFT's according to the construction described in Fig. 6 A on backboard During oxide TFT and LTPS TFT construction profile.
Fig. 7 A are the profiles by polytype TFT exemplary backboards realized according to embodiment of the present invention.
Fig. 7 B-7G are the mistakes that the construction being shown as described in Fig. 6 A prepares oxide TFT and LTPS TFT on backboard The profile of oxide TFT and LTPS TFT construction in journey.
Fig. 8 is equipped with showing for polytype TFT (that is, at least one LTPS TFT and at least one oxide TFT) The plan of example property image element circuit.
Specifically describe
The various features and advantage that will be more clearly understood that from being described below referring to the drawings described in the present invention.Note, What accompanying drawing was merely illustrative, it may be drawn not in scale to be easier to explanation.In addition, in order to describe each embodiment party Formula, the part with same or similar function can be represented in whole accompanying drawing by identical reference marker/numeral.It can omit pair The description of same or similar part.
It will be appreciated that, when the element as layer, region or substrate be described as being located at another element " on " or " top " When, it can be directly on another element or also may be present intermediary element.By contrast, when an element is described as " direct " Positioned at another element " on " or when " top ", in the absence of intermediary element.It will also be understood that when an element is described as " being connected to " Or during " being bonded to " another element, it can be directly connected to or be bonded to another element or intermediary element may be present.By contrast, When an element is described as " being connected directly to " or " being spliced directly to " another element, in the absence of intermediary element.In addition, will reason Solve, when an element is described as with another element " overlapping ", at least some parts of an element can be located at another element Above or below.Although in addition, numerical terms (for example, first, second, third, etc.) have been named to some elements, but it should reason Solution, this name is only used for specifying an element in one group of similar components, but is not with any particular order or grade limitation Element.In this way, in the case of the scope without departing substantially from illustrative embodiments, the element for being named as the first element can be described as Two element or third element.
Each feature of each illustrative embodiments of the present invention partially or entirely can be combined or combined each other, art Technical staff will be fully understood that, can technically realize various interactions or driving, and each illustrative embodiments can Perform or performed together by associated relation independently of one another.Hereinafter, it will be described in detail with reference to the accompanying drawings the present invention's Each embodiment.
Fig. 1 illustrates the exemplary display that can be included in electronic installation.Display device 100 includes being formed with showing Show at least one viewing area of pel array.One or more non-display areas can be set in the periphery of viewing area.It is exactly Say, non-display area can be adjacent with one or more sides of viewing area.
In Fig. 1, non-display area surrounds the viewing area of rectangular shape.It will be appreciated, however, that the shape of viewing area And the arrangement of the non-display area adjacent with viewing area is not specifically limited to the exemplary display 100 shown in Fig. 1.Display Region and non-display area can be suitable for any shape of the design of the electronic installation using display 100.Display 100 The non-limiting example of viewing area shape include pentagon shaped, hexagonal shape, round-shaped, elliptical shape etc..
The display used in various devices typically may include by light emitting diode (LED), Organic Light Emitting Diode (OLED), plasma unit, electrowetting pixel, electrophoretic display, liquid crystal display (LCD) part or other appropriate figures As the display pixel of dot structure formation.In some cases, it may be desirable to can be used OLED formation display 100, thus The construction for display 100 is described using OLED display sometimes in the present invention.It should be noted, however, that the present invention can be used in In other kinds of Display Technique, such as the display with liquid crystal cell and backing structure.
Each pixel in viewing area can be related to image element circuit, and image element circuit is included on the backboard of display 100 The one or more thin film transistor (TFT)s (TFT) prepared.Each image element circuit may be electrically connected to gate line and data wire, with positioned at One or more drive circuits of such as gate drivers and data driver etc in the non-display area of display 100 lead to Letter.
One or more drive circuits can be realized by preparing the TFT in non-display area shown in Fig. 1.For example, grid Driver can be on the substrate positioned at display 100 multiple TFT realize.This gate drivers can be described as panel inner grid (GIP).Operate the various adjunct circuits of the various signals of pixel or the miscellaneous part for controlling display 100 can for producing Realized by preparing the TFT on substrate.Phase inverter electricity can be included by the non-limiting example of the TFT of backboard these circuits realized Road, multiplexer, static discharge (ESD) circuit etc..The substrate achieved above for having tft array can be glass substrate or polymerization Thing substrate.In the situation that display is flexible display, substrate can be flexible base board.
Some drive circuits can be arranged to integrated circuit (IC) chip and chip (COG) or other classes on glass can be used In the non-display area that display 100 is arranged on like method.In addition, some drive circuits can be arranged on another substrate and make With chip (COF) on the printed circuit of such as flexible printed circuit board (PCB) etc, film, carrier tape package (TCP) or any other Appropriate technology is bonded to the connecting interface (pad/projection, pin) being arranged in non-display area.
In embodiments of the present invention, it is different types of using at least two in the TFT backplate for display TFT.The TFT used in pixel circuit section and driving circuit section type can be different according to the requirement of display.
For example, image element circuit can be realized by the TFT with oxide active layer, and drive circuit is by with polycrystalline silicon active The TFT (LTPS TFT) of layer is realized.Different from LTPS TFT, oxide TFT is not exposed to due to being formed over a large area Existing pixel-pixel threshold voltage (Vth) variation issue.Therefore, for even for large-sized monitor, in image element circuit battle array Driving TFT can be also obtained in row and/or switchs TFT uniform Vth.The Vth uniformities between TFT for realizing drive circuit The unlikely brightness uniformity to pixel of problem, which has, to be directly affected.For drive circuit (such as GIP), it is required because Element may include the size for more providing the ability of scanning signal and/or the drive circuit for the size that reduces frame at a high speed.
, can be with than whole TFT in TFT backplate in the case where realizing drive circuit on backboard using LTPS TFT The high clock of the situation that is formed by oxide TFT provides signal and data to pixel.Therefore, can be in the case of without moire The large-sized monitor for being capable of high speed operation is provided.In other words, the combination oxide TFT and LTPS in the design of TFT backplate TFT advantage.
LTPS TFT are used in effect side of display using oxide TFT and for drive circuit for image element circuit Face also can be favourable.Conventional display is operated with fixed refresh rate (for example, 60Hz, 120Hz, 240Hz etc.).However, For some picture materials (for example, rest image), display need not be operated with this high refresh rate.In some situations In, a part for display is needed to operate with high refresh rate, and another part of display can be operated with low refresh rate.Example Such as, a part of of the active region of display Still image data (for example, user interface, text) can be with than showing quick change The low speed of other parts of active region of view data (for example, film) refresh.In this way, can be provided to display 100 Following features：The pixel of the selected part of whole active region or active region is carried out with the frame rate of reduction in specific circumstances Driving.In other words, the refresh rate of display is adjusted according to picture material.
Reduce and drive the duration of pixel to make due to providing identical image number to pixel with unnecessary high-frequency According to and waste minimum power.There can be increased blanking cycle with the powered pixel of the refresh rate of reduction, in blanking week Midcycle data signal is not provided to pixel.Because compared with LTPS TFT, oxide TFT has very during its cut-off state Low leakage current, is operated so being very suitable for low frequency as described above by the oxide TFT image element circuits realized.By subtracting The small current leakage from image element circuit during the blanking cycle of extension, even if refreshed when display with the speed reduced, Pixel can also obtain more stable luminance level.
Effective utilize of actual area in substrate is by using the image element circuit based on oxide TFT and based on LTPS Another advantage that the TFT backplate of TFT drive circuit is provided.Oxide TFT low current leakage characteristics can reduce each picture The size of capacitor in element.The reduction of capacitor sizes provides more empty in the active region of substrate to additional pixels Between, to provide high resolution display in the case where not increasing substrate size.Although single oxide TFT size can be more than LTPS TFT size, but realize that image element circuit can remove compensation circuit by using oxide TFT, thus reduce image element circuit Overall dimensions.In addition, LTPS TFT relatively small size to be easily achieved at the region of active region periphery Dense drive circuit, can reduce the frame size of display.
In some embodiments, by using polytype TFT realize for each pixel image element circuit and/or Drive circuit, or even realize the optimization of more exquisite display.That is, according to the function in image element circuit, operating condition Each TFT in image element circuit and/or drive circuit is selected with requiring.
Most basicly, each pixel may be configured with switching transistor, driving transistor, capacitor and OLED.It can use attached Plus transistor realize the image element circuit of higher performance.
Fig. 2A illustrates an available appropriate image element circuit in embodiments of the present invention.
First switch transistor S1 includes the gate electrode for being connected to luminous signal line EM.First switch transistor S1 has It is connected to first node N1 source electrode and is connected to the drain electrode of driving transistor DT source electrode.First segment Point N1 one end is connected to power supply voltage signal line VDD.Driving transistor DT has the gate electrode for being connected to Section Point N2 With the drain electrode for being connected to the 3rd node N3.
Image element circuit also includes second switch transistor S2, and second switch transistor S2, which has, is connected to data wire Vdata With the drain electrode for receiving the source electrode of data-signal and being connected to Section Point N2.Second switch transistor S2 grid Pole electrode is connected to scan line SCAN1, with the scanning signal conduction and cut-off according to the drive circuit at active region periphery Second switch transistor S2.
Also include the 3rd switching transistor S3 in image element circuit, the 3rd switching transistor S3, which has, is connected to the second scanning letter Number line SCAN2 gate electrode.3rd switching transistor S3 has the source electrode for being connected to the 3rd node N3 and is connected to Initializing signal line VINI drain electrode.OLED anode is connected to the 3rd node N3 and OLED negative electrode is connected to second Power voltage line VSS.
First capacitor CS1 includes being connected to Section Point N2 one end and is connected to the 3rd node N3 other end. Second capacitor CS2 includes being connected to first node N1 one end and is connected to the 3rd node N3 other end.
Fig. 2 B illustrate the timing diagram of the exemplary 4T2C image element circuits shown in Fig. 2A.Image element circuit shown in Fig. 2 B In TFT sequential be based on the operation by the N-type oxide TFT image element circuits realized.
Although all TFT on substrate operate in conjunction with to control the transmitting of the light from OLED element, image element circuit In each TFT serve during operation it is different.In this way, even between the TFT of image element circuit is formed, TFT operation Condition and requirement also can be different.
From figure, it can be seen that alternately applying on the data line in the driving period reference voltage and data voltage of pixel. The scanning signal for applying 1H on SCAN1 and EM to be easy to keep initializing and sampling time sequence.However, because electric current is in extension Stress caused by the constant flow of period, can occur VthIn permanent deflection, the stress is referred to as positive bias stress.It is this Problem in oxide TFT than LTPS TFT in more commonly.In the operation of 4T2C image element circuits as described above, serve as luminous The TFT of transistor is more much longer than the time that other TFT are in " conducting (On) " state.Almost flowed in electric current on whole frame In the case of, the lighting transistor formed by oxide TFT can cause various undesirable problems in the display.
In this way, in one embodiment, the lighting transistor of image element circuit is formed by p-type LTPS TFT, and N-type is aoxidized Thing TFT is used for remaining image element circuit.In the case of the lighting transistor by the p-type LTPS TFT image element circuits formed, show Example property 4T2C image element circuits can be as shown in FIG. 2 C timing diagram operated.Under this operation scheme, it can suppress and pixel The problem of PBTS in the lighting transistor of circuit is related.
Image element circuit and/or any other TFT of drive circuit that similar construction can be used on backboard.That is, with Other TFT of image element circuit are compared and can formed by other TFT in more PBTS image element circuit by p-type LTPS TFT.Cause This, receive the image element circuit of electric current some transistors with being configured to longer period can be by that can resist positive bias stress strongly P-type LTPS TFT formed.
Various other constructions of LTPS TFT and oxide TFT combinations can be used in image element circuit.In some embodiments In, the TFT for being connected to storage or being connected with being connected to the node of storage can be formed by oxide TFT, with It will leak out minimum.In addition, when using two kinds of TFT in image element circuit and/or drive circuit, LTPS TFT can be by tactic Ground is placed in circuit, to remove the bias remained in during its cut-off state in the node between oxide TFT and incite somebody to action inclined Put stress (for example, PBTS, NBTS) minimum.
It should be noted that the construction that oxide TFT and the LTPS TFT in the image element circuit of reference picture 2A-2C descriptions are combined is only Being merely illustrative of property.In this way, the use of oxide TFT and LTPS the TFT combinations in image element circuit can be applicable to except above In other various pixel circuit designs beyond the 4T2C pixel circuit designs of display.
Fig. 3 A illustrate by the N-type oxide TFT exemplary 5T1C image element circuits realized and described the behaviour of image element circuit The timing diagram of work.Fig. 3 B illustrate the identical 5T1C pixels electricity realized by N-type oxide TFT and p-type LTPS TFT combination The timing diagram of the operation of road and description image element circuit.
As shown in fig. 3, its gate electrode is connected to the second scan line SCAN2 and luminous signal line EM switch crystal Pipe is configured to receive electric current during operation longer period.As described above, these switching transistors are likely to by positive bias Stress influence, this can cause the inhomogeneities in display.Therefore, in operation under the conditions of higher stress (for example, when conducting is longer Between section) image element circuit in these transistors can be formed by the p-type LTPS TFT seldom by positive bias stress influence, rather than Formed by N-type LTPS TFT.Reference picture 3B, can be by p-type by the second scan line SCAN2 and luminous signal line EM transistors controlled LTPS TFT are formed.Under this configuration, the operation of image element circuit can be changed as shown in Fig. 3 B timing diagram.
The drive circuit in backboard can be eliminated using p-type LTPS TFT and N-type oxide TFT combination in image element circuit The demand of middle setting inverter circuit.Removing inverter circuit from drive circuit means to eliminate when controlling inverter circuit Related clock signal.In the case where the quantity of clock signal is reduced, it is possible to decrease the power consumption of display.In addition, typical anti- Phase device circuit realizes that this can increase a considerable amount of TFT in whole drive circuit by several TFT (for example, 5~8).Cause This, the clock cable for removing inverter circuit and correlation from backboard can save sizable from the non-display area of display Space, this allows to realize narrower frame in the display.
Set in backboard in the situation of cmos circuit or inverter circuit, can by LTPS TFT and oxide TFT group Close and realize.For example, p-type LTPS TFT and N-type oxide TFT can be used for realizing the CMOS in drive circuit and/or image element circuit Circuit.Therefore, can by using N-type oxide TFT and p-type LTPS TFT combination in the case where needing inverter circuit Simplify inverter circuit.Under this configuration, when inverter circuit is realized by N-type oxide TFT and p-type LTPS TFT combination When can substantially reduce the quantity (for example, 2) for realizing the TFT needed for inverter circuit.
In some embodiments, pixel circuit array can be realized by oxide TFT, and can be by N-type LTPS TFT and p-type The drive circuit realized on backboard is realized in LTPS TFT combination.For example, N-type LTPS TFT and p-type LTPS TFT can be used in fact Cmos circuit (for example, CMOS inverter circuit) in existing GIP, and oxide is used at least a portion of image element circuit TFT.It is different from the GIP entirely formed by p-type or N-type LTPS TFT, the gate output signal from the GIP with cmos circuit It can be controlled by DC signals or logically high/low signal.This causes during blanking cycle more stably control gate polar curve, with suppress from The undesirable activation for the pixel that image element circuit is connected to GIP current leakage or suppression with gate line.
, it is necessary to distribute to the limited of each pixel in the display for adding each TFT in image element circuit Additional gate line is laid in space.This can complicate the manufacture of display and limit can be realized in fixed size aobvious Show the ultimate resolution of device.Problem is more serious for OLED display because OLED pixel circuit generally require than with In the more TFT of the image element circuit of LCD pixel.In the situation of bottom emission type OLED display, by being laid in pixel The space that gate line takes directly affects the aperture opening ratio of pixel.Therefore, in certain embodiments of the present invention, can be by oxide Image element circuit is realized in TFT and LTPS TFT combination, to reduce the quantity of gate line.
For example, image element circuit is provided to control many signal lines of the TFT in image element circuit.First signal wire can It is configured to provide high level signal (VGH) to image element circuit when secondary signal line provides low level signal (VGL).In this feelings , can be by a shape in N-type oxide TFT and p-type LTPS TFT by one or more TFT of the first signal line traffic control in shape Into can be by another shape in N-type oxide TFT and p-type LTPS TFT by one or more TFT of secondary signal line traffic control Into.Under this configuration, it can give and single signal line is set by these TFT of the first and second signal line traffic controls.
In other words, any paired TFT for being configured to receive in the image element circuit of the reciprocal signal of level can be by N Type oxide TFT and p-type LTPS TFT combination are formed.More specifically, the first TFT in image element circuit can be configured to reception High level signal (VGH), and low level signal (VGL) provides the 2nd TFT into same image element circuit.In this case, One TFT can be formed by N-type oxide TFT, and another TFT can be formed by p-type LTPS TFT, and the two TFT grid Pole may be connected to same signal wire.Under this configuration, on signal wire high level signal (VGH) one TFT of activation, and low electricity Ordinary mail number (VGL) activates another TFT of image element circuit.
Fig. 4 illustrates the combination with N-type oxide TFT and p-type the LTPS TFT for being configured to shared gate line Exemplary pixels circuit.
Image element circuit shown in Fig. 4 includes six transistors (being represented by M1 to M6) and storage (Cst).For For this image element circuit, the TFT of image element circuit is controlled using two different signal wires (that is, VG1, VG2).First TFT M1 is the driving TFT in image element circuit.First TFT M1 have the electrode for being connected to drive voltage line VDD and are connected to section Point NET2 another electrode.Second transistor M2 has the electrode for the anode for being connected to OLED element and is connected to positioned at the Another electrode of node NET2 between one TFT M1.Third transistor M3, which has, is connected to reference voltage line Vref electrode simultaneously And node NET1 offer reference voltages are provided, node NET1 is connected to driving TFT M1 grid.4th TFTM4, which has, to be connected It is connected to reference voltage line Vref electrode and is connected to node NET3 another electrode, node NET3 is connected to storage capacitance Device C1.5th TFT M5 have the electrode for the node NET2 being connected between driving TFT M1 and luminous TFT M2.6th Transistor M6 has the electrode for the data signal line for being connected to display and come from response to the signal transmission from gate line The data-signal of data signal line.
Particularly, the 3rd TFT M3 grid is connected to the first signal wire VG1, and the 2nd TFT M2, the 4th TFT M4, 5th TFT M5 and the 6th TFT M6 grid is connected to secondary signal line VG2.In this circuit structure, the 2nd TFT M2 and Four TFT M4 are configured to be activated with the sequential opposite with the 6th TFT M6 with the 5th TFT M5.
Therefore, in an appropriate embodiment, the 2nd TFT M2 and the 4th TFT M4 can be by N-type oxide TFT shapes Into the 5th TFT M5 and the 6th TFT M6 can be formed by p-type LTPS TFT.In alternate embodiments, the 2nd TFT M2 It can be formed with the 4th TFT M4 by p-type LTPS TFT, the 5th TFT M5 and the 6th TFT M6 can be formed by N-type oxide TFT.Cause Need to be activated with the sequential opposite with the 6th TFT M6 with the 5th TFT M5 for the 2nd TFT M2 and the 4th TFT M4, so the Two TFT M2 and the 4th TFT M4 can be formed by p-type oxide TFT, and the 5th TFT M5 and the 6th TFT M6 are by N-type LTPS TFT is formed.In further embodiment, the 2nd TFT M2 and the 4th TFT M4 can be formed by p-type LTPS TFT, and the 5th TFT M5 and the 6th TFT M6 are formed by p-type oxide TFT.
On the same substrate polytype TFT use be not necessarily limited to GIP level level (stage level) or It is not necessarily limited to single pixel circuit.That is, at least one TFT in a level of GIP shift register can be by oxide TFT is formed, and in another grade of shift register a TFT is formed by LTPS TFT.Similarly, in an image element circuit One TFT can be formed by oxide TFT, and in one other pixel circuit a TFT can be formed by LTPS TFT.
Fig. 5 illustrates the representative configuration of two image element circuits, and one of image element circuit is provided with N-type oxide TFT, One other pixel circuit is provided with p-type LTPS TFT.As shown in Figure 5, the first image element circuit is included by N-type oxide TFT shapes Into switch TFT, and corresponding TFT in the second image element circuit formed by p-type LTPS TFT.First image element circuit can be with display The pixel of the odd-numbered line of device is related, and the second image element circuit can be related to the pixel of the even number line of display.Under this configuration, The N-type oxide TFT of first image element circuit grid and the p-type LTPS TFT of the second image element circuit grid may be connected to wall scroll Gate line.In this way, the quantity of gate line can be reduced in the display.
TFT in each image element circuit of shared gate line can be arranged in response to the grid on the gate line that is shared Pole signal provides the TFT of data-signal.In an illustrative example, for controlling the signal of image element circuit such as to divide into Put：Data-signal Vdata, -10V VGL, 3V VGO, 15V VGH, 1V Vref between 0 and 5V.Under this configuration, The threshold voltage of p-type LTPS TFT in N-type oxide TFT and the second image element circuit in first image element circuit can be set to 3V and -2.5V.
The driving TFT for being connected to OLED element in first image element circuit and the second image element circuit is not particularly limited, can Formed by any one in N-type oxide TFT and p-type LTPS TFT.If desired, the first image element circuit and the second picture Driving TFT in plain circuit can be formed by the TFT of type different from each other.
It should be appreciated that the p-type LTPS TFT in N-type oxide TFT and the second image element circuit in the first image element circuit are not It is limited to the TFT for being connected to data signal line.According to the design and drive scheme of image element circuit, other in two image element circuits are opened TFT is closed, being for example connected to the TFT of reference signal line can be made up of the TFT of species different from each other.The N-type in neighboring pixel circuits Oxide TFT and p-type LTPS TFT use allow reduce two adjacent pixels boundary gate line quantity, this It is especially advantageous in transparent display.Light-emitting zone (that is, the region with image element circuit) and clear area are divided into being provided with In the transparent display of the pixel in domain, the light-emitting zone of two adjacent pixels (for example, odd-line pixels and even rows) is set It is set to adjacent with the gate line being shared.This, which is constructed, causes the transparent region of pixel to be disposed adjacent to each other, and this can improve display Transparency.
It can be extremely challenging technique to set polytype TFT on the same substrate as described in the present invention.In shape The other kinds of TFT also or on the same backboard of deterioration may be damaged into some techniques related during a type of TFT.Example Such as, metal oxide semiconductor layer can be damaged for forming the annealing process of polycrystal semiconductor layer.As such, it is desired to be to set Before the metal oxide layer for putting the active layer for serving as oxide TFT, lehr attendant when LTPS TFT are prepared on backboard is performed Skill.In addition, the quantity of mask can be increased by preparing the backboard with polytype TFT, and then reduce yield and increase display Manufacturing cost.
Fig. 6 A are the profiles by polytype TFT exemplary backboards realized according to embodiment of the present invention.
When realizing the backboard of flexible display by a variety of semi-conducting materials including oxide semiconductor, metal oxide Semiconductor layer can be patterned and optionally become LTPS TFT electrode.More specifically, metal-oxide semiconductor (MOS) Layer can be patterned as oxide TFT active layer and one or more electrodes for LTPS TFT.Can be to patterning The some parts of oxide semiconductor layer perform post processing, such as the corona treatment for increasing carrier concentration or its He is implanted into and/or thermal anneal process, so that oxide TFT S/D regions are served as in processed part, channel region is located at S/D Between region.Identical can be performed to the metal oxide layer patterned in the position of LTPS TFT one or more electrodes Technique so that it may act as LTPS TFT electrode.
Metal oxide layer using the active layer for forming oxide TFT is used as one or more of LTPS TFT Electrode allows to reduce the number of masks required when preparing the backboard with polytype TFT.Although in addition, the tool of insulating barrier Body function may be different in TFT, but some insulating barriers used when forming LTPS TFT on backboard also act as oxide TFT insulating barrier.The insulating barrier that a type of TFT insulating barrier is used for another type of TFT can also contribute into reduction to cover Modulus amount and the manufacturing process for simplifying backboard.
Fig. 6 B-6H are shown in prepares oxide TFT and LTPS TFT's according to the construction described in Fig. 6 A on backboard During oxide TFT and LTPS TFT construction profile.Reference picture 6B, forms cushion 604 on substrate 602. For being formed in LTPS TFT region (being represented by " LTPS TFT zones "), polysilicon active layer is formed on cushion 604 606.Preparing LTPS TFT polysilicon active layer 606 as depicted in figure 6b will need the first mask (to be used for polysilicon active layer Patterning).As mentioned, can be performed on backboard before deposit metal oxide layers has for amorphous silicon layer to be become into polysilicon The laser annealing of active layer 606 or other appropriate techniques.
Reference picture 6C, sets the first insulating barrier 608 in polysilicon active layer 606, to serve as gate insulator (GI_L). If desired, in the region (being represented by " oxide TFT zone ") for forming oxide TFT first can be set to insulate Layer 608, to serve as the extra cushion being located at below oxide TFT active layer.Then, set in oxide TFT zone Metal oxide layer 610, it will serve as oxide TFT active layer.Instead of the separation of the grid that is provided for LTPS TFT Conductive layer, metal oxide layer 610 is patterned on the gate insulator 608 in LTPS TFT zones.In other words, metal Oxide skin(coating) 610 is used as LTPS TFT gate electrode and also serves as oxide TFT active layer.
As briefly described above, one or more post processings are can perform (for example, corona treatment, doping, implantation, annealing Deng), the conductance at selected part to increase metal oxide layer 610.Particularly, post processing is can perform, to increase oxidation Conductance at the S/D regions of metal oxide layer 610 at thing TFT zone.In oxide TFT metal oxide layer 610 The post processing in middle formation S/D regions also increases the metal on the gate insulator 608 being patterned at LTPS TFT zones The conductance of oxide skin(coating) 610.In the case of conductance is increased, the metal oxide layer 610 at LTPS TFT zones can have Serve as to effect LTPS TFT gate electrode.It should be appreciated that by using the formation LTPS of metal oxide layer 610 TFT grid Electrode, reduces and is preparing the mask needed for the backboard with polytype TFT.
At this point, photoetching can be set above the metal oxide layer in LTPS TFT zones and oxide TFT zone Glue (PR) layer, then, PR layers of selected part is exposed by the second mask.Here, half-tone mask (HTM) technique can be used, So that the PR layers above the channel region of oxide TFT zone are with than in the other parts of metal oxide layer 610 The thickness that the PR layers of side are higher is left.That is, the PR layers above the channel region in oxide TFT active layer can To be left with the bigger thickness of the PR layers than the S/D overlying regions in oxide TFT active layer.In addition, positioned at oxygen PR layers above channel region in compound TFT active layer can be with than the metal oxide layer in LTPS TFT zones The bigger thickness of PR layers above 610 (it will serve as LTPS TFT gate electrode) is left.Positioned at oxide TFT raceway groove The additional thickness of the PR layers of overlying regions causes even in for increasing leading for the metal oxide layer 610 at LTPS TFT zones Electric rate still keeps characteristic of semiconductor after the technique to be become gate electrode.
Reference picture 6D, sets the second insulating barrier 612 above LTPS TFT zones and oxide TFT zone.Here, can make The second insulating barrier 612 is patterned with the 3rd mask so that its serve as the interlayer dielectric layer (ILD) at LTPS TFT zones and Act also as the gate insulator (GI_O) in oxide TFT zone.At this point, half-tone mask technology controlling and process can be used to select The thickness of the second insulating barrier 612 at region.More specifically, serve as ILD first can be suitable in LTPS TFT zones Thickness the second insulating barrier 612 of formation.The second thickness for serving as gate insulator (GI_O) can be suitable in oxide TFT zone Form the second insulating barrier 612.For example, the second insulating barrier 612 may have about in LTPS TFT zonesThickness simultaneously And may have about in oxide TFT zoneThickness.As shown in figure 6d, exposed polysilicon can be set active The contact hole in the S/D regions of layer 606.
Reference picture 6E, can set the first metal layer 614 in the top of the second insulating barrier 612.Using the 4th mask by the first gold medal Category layer 614 is patterned.In LTPS TFT zones, the first metal layer 614 is patterned to form LTPS TFT S/D electrodes. In oxide TFT zone, the first metal layer 614 is patterned to form oxide TFT gate electrode.
Reference picture 6F, sets the 3rd insulating barrier 616 above LTPS TFT zones and oxide TFT zone.Use the 5th Mask patterns the 3rd insulating barrier 616, to serve as the passivation layer being located above LTPS TFT S/D electrodes and serve as oxidation Thing TFT ILD.Because the 3rd insulating barrier 616 serves as the passivation layer above LTPS TFT S/D electrodes, it can be set Through one or more contact holes of the 3rd insulating barrier 616, with some parts for the S/D electrodes for exposing LTPS TFT.Through The contact hole of three insulating barriers 616 can be used for the S/D that signal wire and/or other electrodes are connected to LTPS TFT.
Reference picture 6G, second metal layer 618 is set in the top of the 3rd insulating barrier 616.The 6th mask can be used by the second gold medal Belong to the intermediate metal layer (INT) at the patterned LTPS TFT zones of layer 618, intermediate metal layer passes through in the 3rd insulating barrier 616 Contact hole be connected to LTPS TFT S/D electrodes.Although in this embodiment by second in LTPS TFT zones Metal level 618 is described as intermediate metal layer, but the function not limited to this of second metal layer 618.Correspondingly, second metal layer 618 It may act as signal wire in backboard, electrode and for various other purposes.In oxide TFT zone, second metal layer 618 can It is patterned to serve as oxide TFT S/D electrodes.
Reference picture 6H, sets the 4th insulating barrier 620 above both LTPS TFT and oxide TFT.4th insulating barrier 620 It can be the planarization layer (PLN) for providing flat surfaces above LTPS TFT zones and oxide TFT zone.It can be used 7th mask is arranged through the contact hole of the 4th insulating barrier 620, to expose the selected part of second metal layer 618.In Fig. 6 H, Pass through the contact holes exposing intermediate metal layer (INT) of the 4th insulating barrier 620.Although the 4th insulating barrier 620 serve as LTPS TFT and Planarization layer (PLN) above both oxide TFT, but it acts also as the passivation layer above oxide TFT S/D electrodes.Cause This, in some embodiments, the one or more of the S/D electrodes for exposed oxide TFT can be set in the 4th insulating barrier 620 Contact hole.
Reference picture 6A, can pattern the 3rd by using the 8th mask in the desired region of the top of the 4th insulating barrier 620 Metal level 622.3rd metal level 622 can be contacted via the 4th insulating barrier 620 with second metal layer 618.For example, the 3rd metal level 622 can contact with intermediate metal layer (INT) as shown in FIG.In some other embodiments, the 4th is patterned in exhausted 3rd metal level 622 of the top of edge layer 620 can be with oxide TFT S/D electrode contacts.
It should be appreciated that the LTPS TFT and oxide TFT shown in Fig. 6 A can be configured for the various uses in backboard. Using the constitution realization of oxide TFT and the LTPS TFT shown in Fig. 6 A heretofore described oxide TFT and LTPS TFT any combinations are used.LTPS TFT shown in Fig. 6 A can be included in the TFT in drive circuit, and oxide TFT The TFT in image element circuit can be included in.LTPS TFT shown in Fig. 6 A can be included in the TFT in image element circuit, And oxide TFT can be included in the TFT in drive circuit.Both LTPS TFT and oxide TFT shown in Fig. 6 A can With the TFT being included in single pixel circuit or multiple image element circuits.In addition, LTPS TFT and oxide shown in Fig. 6 A Both TFT can be included in the TFT in single pixel circuit or multiple image element circuits.
Therefore, the function of the 3rd metal level 622 in backboard can according to position of the 3rd metal level 622 in backboard and Be connected to the TFT of the 3rd metal level 622 position and function and it is different.As an example, LTPS TFT shown in Fig. 6 A can be with It is the driving TFT in image element circuit, the 3rd metal level 622 may act as the anode of OLED element.In some cases, institute in Fig. 6 A The LTPS TFT shown can be the switch TFT in image element circuit, and the 3rd metal level 622 can be the letter that transmission carrys out driving circuit Number signal wire.In some cases, LTPS TFT can be for realizing the drive being arranged in the non-display area of display One of TFT of dynamic circuit, the 3rd metal level 622 may act as the signal wire for transmitting the signal from each drive circuit.Such as Upper described, instead of LTPS TFT, the 3rd metal level 622 can be with oxide TFT S/D electrode contacts and offer and each oxidation Function related thing TFT.
In Fig. 6 A construction, LTPS TFT grid is by forming the metal oxide layer of oxide TFT semiconductor layer Formed.In addition, the several insulating barriers being arranged in backboard are used for a kind of purposes and in oxide TFT in LTPS TFT zones It is used for another purposes in region.This can provide the more efficient way of backboard of the manufacture with polytype TFT.
Fig. 7 A illustrate the another exemplary structure of oxide TFT and the LTPS TFT according to the backboard of embodiment of the present invention Make.Fig. 7 B-7G are shown in oxide TFT and LTPS TFT are prepared on backboard according to the construction described in Fig. 7 A during The profile of oxide TFT and LTPS TFT construction.
The construction of cushion 704 and polysilicon active layer 706 on reference picture 7B and 7C, substrate 702 is retouched with reference picture 6B The construction stated is identical.Therefore, two masks are needed using the formation LTPS of metal oxide layer 710 TFT gate electrode.
Pass through the further reduction of number of masks needed for the constitution realization described in Fig. 7 D.It should be noted that in Fig. 6 A structure Pass through different insulating barrier formation LTPS TFT and oxide TFT interlayer dielectric layer (ILD) in making.That is, utilize second The formation LTPS of insulating barrier 612 TFT interlayer dielectric layer (ILD), and utilize the 3rd insulating barrier 616 formation oxide TFT interlayer Dielectric layer (ILD).
However, in the construction shown in Fig. 7 D, both LTPS TFT and oxide TFT layer are served as using same insulating barrier Between dielectric layer (ILD).More specifically, the second insulating barrier 712 for serving as LTPS TFT interlayer dielectric layer (ILD) acts also as oxygen Compound TFT interlayer dielectric layer (ILD).
In addition, the second insulating barrier 712 is additionally operable to oxide TFT another purposes.Particularly, using the 3rd mask by Two insulating barriers 712 are patterned so that it acts also as oxide TFT gate insulator (GI_O).Pass through the layer with LTPS TFT Between dielectric layer (ILD) form oxide TFT gate insulator (GI_O) and interlayer dielectric layer (ILD) together, eliminate in the back of the body Demand at least one mask in polytype TFT preparation technology is set in plate.
It should be noted that the thickness suitable for LTPS TFT interlayer dielectric layer (ILD) can be with interlayer Jie suitable for oxide TFT The thickness of electric layer (ILD) is different.In addition, the thickness of gate insulator (GI_O) typically with the thickness of interlayer dielectric layer (ILD) not Together.Therefore, half-tone mask (HTM) can be used to pattern the second insulating barrier 712, to control it at backboard different piece Thickness.As an example, in LTPS TFT zones, the second insulating barrier 712 can be suitable for the interlayer dielectric for serving as LTPS TFT The first thickness of layer (ILD) is set.In oxide TFT zone, the second insulating barrier 712 of interlayer dielectric layer (ILD) is served as Part can be set with second thickness, and the other parts for serving as gate insulator (GI_O) are set with the 3rd thickness.
In some cases, the first thickness of the second insulating barrier 712 in LTPS TFT zones and oxide TFT zone and Second thickness can be identical.In an appropriate embodiment, interlayer dielectric layer (ILD) feelings are served as in the second insulating barrier 712 The second insulating barrier 712 can be with about in shapeThickness set, but serve as oxide TFT's in the second insulating barrier 712 With about in the situation of gate insulator (GI_O)Thickness set.
Reference picture 7E, the first metal layer 714 is set in the top of the second insulating barrier 712.Using the 4th mask by the first metal Layer 714 is patterned, to set LTPS TFT S/D electrodes and oxide TFT gate electrode.With the construction shown in Fig. 6 A Difference, the first metal layer 714 also forms oxide TFT S/D electrodes as shown in figure 7e.In other words, except LTPS TFT's Beyond gate electrode, LTPS TFT and oxide TFT all electrodes utilize same metal level (that is, the first metal layer 714) Formed.Form oxide TFT and LTPS TFT S/D electrodes and oxide TFT grid together by using single metal layer Pole electrode, at least reduces a mask.
Reference picture 7F, the 3rd insulating barrier 716 and the 4th insulating barrier 720 are set in the top of the first metal layer 714.3rd insulation Layer 716 may act as the passivation layer of both LTPS TFT and oxide TFT S/D electrodes.It is exhausted that 4th insulating barrier 720 is arranged on the 3rd The top of edge layer 716.4th insulating barrier 720 may act as providing the planarization of flat surfaces above LTPS TFT and oxide TFT Layer.
It should be noted that in the construction shown in Fig. 6 A, serving as the 3rd insulating barrier 616 of LTPS TFT passivation layer needs to fill When oxide TFT interlayer dielectric layer (ILD).Therefore, must before the top of the 3rd insulating barrier 616 sets the 4th insulating barrier 620 The contact hole for S/D electrodes must be produced, then needs single technique to produce other contacts through the 4th insulating barrier 620 Hole.
However, in the embodiment configured as shown in Figure 7A, the 3rd insulating barrier 716 and the 4th insulating barrier 720 it is every One is used for identical function for LTPS TFT and oxide TFT.Especially, the 3rd insulating barrier 716 serves as LTPS Both TFT and oxide TFT passivation layer, therefore need not be by the figure of the 3rd insulating barrier 716 before the 4th insulating barrier 720 is set Case.But, produced after the 3rd insulating barrier 716 and the 4th insulating barrier 720 are set using single mask for S/D electrodes The contact hole of contact.
Reference picture 7G, is set second metal layer 718 in the top of the 4th insulating barrier 716, is connect with the S/D electrodes with one of TFT Touch.In Fig. 7 G, second metal layer 718 is shown as contact hole and oxide by being arranged in the third and fourth insulating barrier TFT S/D electrode contacts.However, this is merely illustrative.If desired, it can be set in the third and fourth insulating barrier Put contact hole so that the S/D electrode contacts that second metal layer 718 can be with LTPS TFT.As described previously for heretofore described Any representative configuration for, LTPS TFT and oxide TFT can be used in backboard.Therefore, the work(of second metal layer 718 It is able to can be changed according to the specific TFT contacted purposes.
Fig. 8 is equipped with showing for polytype TFT (that is, at least one LTPS TFT and at least one oxide TFT) The plan of example property image element circuit.
In the reality with the S/D electrodes formed by single metal layer and gate electrode (such as the electrode configured in such as Fig. 7 A) Apply in mode, gate line and S/D lines can be intersected with each other.Certainly, gate line and S/D lines should not be in contact with each other.Therefore, as oxidation The metal oxide layer of thing TFT active layer also acts as the means for laying line that is intersected with each other and not producing short circuit.
Reference picture 8, First Line 810 is arranged in the horizontal direction and the second line 820 is arranged in vertical direction.First Line 810 are arranged in multiple pieces (for example, 810 (A), 810 (B)) separated by " X " region represented.Otherwise, First Line 810 will The second line 820 is passed through, short circuit is produced between intersection region " X " is in line.In addition, positioned at the first and second lines (810,820) Metal level below metal oxide layer be patterned such that it is arranged on intersection region " X " place.Can be with being configured to The similar mode of the metal oxide layer of LTPS TFT gate electrode increases leading for the metal oxide layer in intersection region " X " Electric rate.It may pass through the insulating barrier being arranged on above metal oxide layer and contact hole be set so that first piece 810 of First Line 810 (A) and second piece 810 (B) contact below metal oxide layer.In this way, being arranged on the metal oxide at intersection region " X " place Layer may act as the bridge part of the block (810 (A), 810 (B)) for connecting First Line 810.Therefore, or even single metal is being utilized Layer is set in TFT S/D electrodes and the embodiment of gate electrode, and the line 820 of First Line 810 and second also can cloth intersected with each other If.
In the present invention, the metal oxide layer for serving as oxide TFT active layer is described as by indium gallium zinc structure Into.However, this is merely illustrative.Various other compositions can be used for the metal oxide layer of the present invention.Metal oxide layer The example of composition material include：The quaternary metal oxidation of such as tin indium oxide gallium zinc (In-Sn-Ga-Zn-O) sill etc Thing；Such as indium gallium zinc (In-Ga-Zn-O) sill, indium tin zinc oxide (In-Sn-Zn-O) sill, indium oxide aluminium zinc (In-Al-Zn-O) sill, indium oxide hafnium zinc (In-Hf-Zn-O) sill, tin oxide gallium zinc (Sn-Ga-Zn-O) sill, Aoxidize the ternary metal oxidation of gallium aluminium zinc (Al-Ga-Zn-O) sill and tin oxide aluminium zinc (Sn-Al-Zn-O) sill etc Thing；And such as indium zinc oxide (In-Zn-O) sill, tin oxide aluminium zinc (Sn-Zn-O) sill, aluminum zinc oxide (Al-Zn- O) sill, magnesium zinc (Zn-Mg-O) sill, tin oxide magnesium (Sn-Mg-O) sill, indium oxide magnesium (In-Mg-O) base The binary metal oxide of material, indium gallium (In-Ga-O) sill etc；Indium oxide (In-O) sill；Tin oxide (Sn-O) sill and zinc oxide (Zn-O) sill.The ratio of components of the element included in each metal oxide layer is not special Limitation, can be adjusted with various ratio of components.
Although the present invention is particularly shown and described for preferred embodiment, it will be appreciated by those skilled in the art that The foregoing and other change in form and details can be carried out without departing from the spirit and scope of the present invention.Therefore, originally Invention is intended to be not limited to strict form and details that be described and illustrating, but the present invention falls in appended claims In the range of.Although describing low refresh rate drive pattern by linguistic context of OLED display and suitable for this drive pattern TFT backplate, it is to be understood that, the present invention described in embodiment similar TFT backplate can be used for liquid crystal display (LCD) and Other various types of displays.

Claims (20)

1. a kind of equipment, including：
Define the substrate of first area and second area；
It is arranged on low temperature polycrystalline silicon (LTPS) layer in the first area；
It is arranged on the first insulating barrier on the LTPS layers in the first area；
It is arranged on the metal oxidation in the metal oxide layer in the first area and the second area, the first area Nitride layer is arranged on first insulating barrier；
It is arranged on the second insulating barrier in the second insulating barrier in the first area and the second area, the first area With at least one of contact hole for the LTPS layers below exposure, and the second insulating barrier cloth in the second area Put on the metal oxide layer, the metal oxide layer separated with exposure by the part covered by second insulating barrier At least two parts；
The first metal layer in the first metal layer in the first area and the second area, the first area with Described LTPS layers expose portion contact, and the first metal layer in the second area by the second insulating barrier of lower section with The metal oxide layer insulation；
Cover the 3rd insulating barrier of the first area and the first metal layer in the second area；
It is arranged on the second metal layer in the second metal layer in the first area and the second area, the first area Contacted via the contact hole through the 3rd insulating barrier with the first metal layer, and the second gold medal in the second area Category layer is contacted via the contact hole through the 3rd insulating barrier with the metal oxide layer；With
The 4th insulating barrier in the first area and the second area and above the second metal layer is arranged on, its Described in metal oxide layer in first area have than the gold covered by second insulating barrier in the second area Belong to the high conductance in the part of oxide skin(coating).
2. equipment according to claim 1, in addition to the 3rd metal level on the 4th insulating barrier, the described 3rd Metal level is via the second metal layer in the contact hole through the 4th insulating barrier and the first area or secondth area Second metal layer contact in domain.
3. equipment according to claim 1, wherein the low temperature polycrystalline silicon (LTPS) layer serves as LTPS TFT active layer, And the metal oxide layer in the second area serves as oxide TFT active layer.
4. equipment according to claim 3, wherein the metal oxide layer in the first area serves as the LTPS TFT gate electrode.
5. equipment according to claim 3, wherein second insulating barrier serves as the LTPS TFT in the first area Interlayer dielectric layer and serve as the gate insulator of the oxide TFT in the second area.
6. equipment according to claim 3, wherein the first metal layer being inserted in the second area is aoxidized with metal The second insulating barrier between nitride layer is thinner than the second insulating barrier being arranged in the first area.
7. equipment according to claim 3, wherein the first metal layer provides the LTPS TFT in the first area Source electrode and drain electrode, and the first metal layer provides the grid electricity of the oxide TFT in the second area Pole.
8. equipment according to claim 3, wherein the 3rd insulating barrier serves as the LTPS TFT in the first area Passivation layer and serve as the interlayer dielectric layer of the oxide TFT in the second area.
9. equipment according to claim 3, wherein the 3rd metal level contacted with the second metal layer is organic The anode of light-emitting component.
10. equipment according to claim 3, wherein the 3rd metal level contacted with the second metal layer is signal Line.
11. a kind of display, including：
Thin film transistor (TFT) (TFT) array, including at least one oxide thin film transistor (TFT) and at least one low temperature polycrystalline silicon (LTPS) TFT, wherein the active layer of at least one oxide TFT and the gate electrode of at least one LTPS TFT by One metal oxide layer is made.
12. display according to claim 11, wherein the interlayer dielectric layer of at least one LTPS TFT and described At least one oxide TFT gate insulator is made up of same insulating barrier.
13. display according to claim 12, wherein source/drain electrodes and the institute of at least one LTPS TFT The gate electrode for stating at least one oxide TFT is made up of same metal level.
14. display according to claim 13, wherein being connect with the source/drain electrodes of at least one LTPS TFT Tactile intermediate metal layer and the source/drain electrodes of at least one oxide TFT are made up of same metal level.
15. display according to claim 14, wherein at least one oxide TFT is arranged on the display In viewing area, and at least one described LTPS TFT is arranged in the non-display area of the display.
16. display according to claim 14, in addition to：
Image element circuit in viewing area, related to display pixel；
Drive circuit in non-display area, for providing multiple signals to the image element circuit, wherein the pixel Circuit is realized by the oxide TFT and the drive circuit is realized by the LTPS TFT.
17. display according to claim 14, wherein the tft array include being located at it is in viewing area, with it is multiple The related pixel circuit array of display pixel, wherein the pixel circuit array includes the oxide TFT and LTPS TFT。
18. display according to claim 17 a, wherein image element circuit related to single display pixel includes institute State oxide TFT and the LTPS TFT.
19. display according to claim 14, in addition to the drive circuit in non-display area, the driving electricity Road is used to provide multiple signals, its middle position to pixel circuit array in viewing area, related to multiple display pixels Drive circuit in the non-display area includes at least one oxide TFT and at least one described LTPS TFT.
20. display according to claim 13, wherein the tft array includes the array of multiple image element circuits, each Image element circuit is related to Organic Light Emitting Diode (OLED) element, wherein the anode of the OLED element is connected to described at least one Individual oxide TFT or at least one described LTPS TFT.
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