CN107103932B - Bit line driving circuit and nonvolatile memory circuit - Google Patents

Bit line driving circuit and nonvolatile memory circuit Download PDF

Info

Publication number
CN107103932B
CN107103932B CN201610094461.9A CN201610094461A CN107103932B CN 107103932 B CN107103932 B CN 107103932B CN 201610094461 A CN201610094461 A CN 201610094461A CN 107103932 B CN107103932 B CN 107103932B
Authority
CN
China
Prior art keywords
nmos transistor
voltage
power supply
bit line
input signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201610094461.9A
Other languages
Chinese (zh)
Other versions
CN107103932A (en
Inventor
權彞振
倪昊
许家铭
刘晓艳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201610094461.9A priority Critical patent/CN107103932B/en
Publication of CN107103932A publication Critical patent/CN107103932A/en
Application granted granted Critical
Publication of CN107103932B publication Critical patent/CN107103932B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits

Abstract

The application provides a bit line driving circuit and a nonvolatile memory circuit including the same, which can increase the reading speed of a sensing amplifying circuit reading signal by improving the reading sensing speed by utilizing the voltage difference between a higher grid electrode of an NMOS transistor and a substrate, and further improve the performance of the nonvolatile memory circuit.

Description

Bit line driving circuit and nonvolatile memory circuit
Technical Field
The present disclosure relates to the field of semiconductor manufacturing, and more particularly, to a bit line driving circuit and a nonvolatile memory circuit.
Background
NVM (Non-Volatile Memory) requires many driving circuits to Control the operation of the Non-Volatile Memory, and the driving circuits are used to Control Word Lines (WL), Control Gates (CG), Bit Lines (BL), Source Lines (SL) and Select gates (SL) to Control the bias voltages of the Non-Volatile Memory during various operations, including programming, deleting and reading operations.
Fig. 1 shows a BL driver circuit 1 '(bit line driver circuit) and an SL driver circuit 2' (source line driver circuit) in the related art. As shown in fig. 1, in the read mode, the source of the first PMOS transistor P1 is connected to a voltage source VCC, when the gate input voltage of the first PMOS transistor P1 is a low level value (e.g., 0V), the first PMOS transistor P1 is turned on, and the voltage of the voltage source VCC is transmitted to the bit line BL through the drain thereof to complete pre-charging (pre-charging), and then when the gate input voltage of the first PMOS transistor P1 is a high level value (e.g., 3.3V), the first PMOS transistor P1 is turned off, and when the select gate SG selects the memory cell, the second PMOS transistor P2, the third PMOS transistor P3, and the first NMOS transistor N1 are turned on, and the sense amplifier circuit 3' obtains a read signal through the bit line BL via the second PMOS transistor P2, the third PMOS transistor P3, and the first NMOS transistor N1. Normally, Vg (gate voltage) of the PMOS transistor is 0.7V, and when the voltage source VCC exceeds 1.5V, the sense amplifier circuit 3' can increase the reading speed through the second PMOS transistor P2 and the third PMOS transistor P3. However, when the voltage source VCC is lowered (e.g., 1.2V or 1V), the lower voltage source VCC input lowers the transfer speed from the bit line BL to the Sense Amplifier circuit 3' (Sense Amplifier, SA), thereby affecting the read speed.
Disclosure of Invention
The present application provides a bit line driving circuit and a nonvolatile memory circuit including the same, which can improve a read sensing speed by using a higher gate-to-substrate voltage difference of an NMOS transistor in a low power supply product.
In order to solve the above technical problem, the present application provides a bit line driving circuit, wherein the bit line driving circuit includes:
a bit line charging unit connected to a first regulated power supply and a first input signal to charge a storage unit to a first regulated power supply value based on the first input signal;
a bit line driving unit connected to a second input signal, a third input signal, an output terminal of a high voltage switching circuit, and an output terminal of the bit line charging unit to control the turn-on of the memory cell based on the second input signal;
the sensing amplification circuit protection unit is connected to a fourth input signal, the output end of the high-voltage switch circuit and the input end of the sensing amplification circuit so as to control the input voltage of the sensing amplification circuit;
the second voltage-stabilized source is connected with the bit line charging unit, the bit line driving unit and the sensing amplification circuit protection unit;
and the third voltage-stabilized power supply is connected with the bit line driving unit and the sensing amplification circuit protection unit.
Further, the bit line charging unit includes:
and the grid electrode of the first NMOS transistor is connected to the first input signal, the drain electrode of the first NMOS transistor is connected to the first stabilized voltage power supply, the source electrode of the first NMOS transistor is connected to the input end of the storage unit, and the substrate of the first NMOS transistor is connected to the second stabilized voltage power supply.
Further, the bit line driving unit includes:
the grid electrode of the second NMOS transistor is connected to a second input signal, the drain electrode of the second NMOS transistor is connected to the source electrode of the first NMOS transistor, and the substrate is connected to the second voltage-stabilizing power supply through a first diode;
the anode of the first diode is connected to the second NMOS transistor and the third stabilized voltage supply, and the cathode of the first diode is connected to the second stabilized voltage supply;
the grid electrode of the third NMOS transistor is connected to a third input signal, the drain electrode of the third NMOS transistor is connected to the source electrode of the second NMOS transistor, and the substrate of the third NMOS transistor is connected to the second voltage-stabilizing power supply through a second diode;
and the anode of the second diode is connected to the third NMOS transistor and the third stabilized voltage power supply, and the cathode of the second diode is connected to the second stabilized voltage power supply.
Further, the sense amplifying circuit protection unit includes:
a fourth NMOS transistor having a gate connected to the fourth input signal, a drain connected to the source of the third NMOS transistor, a substrate connected to the second regulated power supply through a third diode, and a source connected to the input terminal of the sense amplifier circuit;
and the anode of the third diode is connected to the fourth NMOS transistor and the third stabilized voltage power supply, and the cathode of the third diode is connected to the second stabilized voltage power supply.
Further, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are all high voltage NMOS transistors.
Further, in a reading mode, the voltage values of the first voltage-stabilized power supply and the second voltage-stabilized power supply are both 1.0V-1.5V, and in other modes, the voltage value of the first voltage-stabilized power supply is smaller than that of the second voltage-stabilized power supply. The first input signal outputs a high level of 2.8V to 3.5V and a low level of a ground voltage value.
According to another aspect of the present application, a nonvolatile memory circuit is provided, in which a bit line driving circuit, a memory cell, a sense amplifying circuit, a high voltage switching circuit, and a source driving circuit are included.
Wherein the bit line driving circuit includes:
a bit line charging unit connected to a first regulated power supply and a first input signal to charge the memory cell to a first regulated power supply value based on the first input signal;
a bit line driving unit connected to a second input signal, an output terminal of a high voltage switching circuit, and an output terminal of the bit line charging unit to control the turn-on of the memory cell based on the second input signal;
the sensing amplification circuit protection unit is connected to a fourth input signal, the output end of the high-voltage switch circuit and the input end of the sensing amplification circuit so as to control the input voltage of the sensing amplification circuit;
the second voltage-stabilized source is connected with the bit line charging unit, the bit line driving unit and the sensing amplification circuit protection unit;
the third voltage-stabilized source is connected with the bit line driving unit and the sensing amplification circuit protection unit;
the sensing amplifying circuit is used for sensing and amplifying the input voltage of the storage unit;
the source electrode driving circuit is connected to the output end of the high-voltage switch circuit, a fourth input signal and a third stabilized voltage power supply.
Further, the bit line charging unit includes:
and the grid electrode of the first NMOS transistor is connected to the first input signal, the drain electrode of the first NMOS transistor is connected to the first stabilized voltage power supply, the source electrode of the first NMOS transistor is connected to the input end of the storage unit, and the substrate of the first NMOS transistor is connected to the second stabilized voltage power supply.
Further, the bit line driving unit includes:
the grid electrode of the second NMOS transistor is connected to a second input signal, the drain electrode of the second NMOS transistor is connected to the source electrode of the first NMOS transistor, and the substrate is connected to the second voltage-stabilizing power supply through a first diode;
the anode of the first diode is connected to the second NMOS transistor and the third stabilized voltage supply, and the cathode of the first diode is connected to the second stabilized voltage supply;
the grid electrode of the third NMOS transistor is connected to a third input signal, the drain electrode of the third NMOS transistor is connected to the source electrode of the second NMOS transistor, and the substrate of the third NMOS transistor is connected to the second voltage-stabilizing power supply through a second diode;
and the anode of the second diode is connected to the third NMOS transistor and the third stabilized voltage power supply, and the cathode of the second diode is connected to the second stabilized voltage power supply.
Further, the sense amplifier circuit protection unit includes:
a fourth NMOS transistor having a gate connected to the fourth input signal, a drain connected to the source of the third NMOS transistor, a substrate connected to the second regulated power supply through a third diode, and a source connected to the input terminal of the sense amplifier circuit;
and the anode of the third diode is connected to the fourth NMOS transistor and the third stabilized voltage power supply, and the cathode of the third diode is connected to the second stabilized voltage power supply.
Further, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are all high voltage NMOS transistors.
Further, in a reading mode, the voltage values of the first voltage-stabilized power supply and the second voltage-stabilized power supply are both 1.0V-1.5V, and in other modes, the voltage value of the first voltage-stabilized power supply is smaller than that of the second voltage-stabilized power supply. The first input signal outputs a high level of 2.8V to 3.5V and a low level of a ground voltage value.
Compared with the prior art, the bit line driving circuit and the nonvolatile memory circuit comprising the bit line driving circuit improve the reading sensing speed by utilizing the higher voltage difference between the grid electrode and the substrate of the NMOS transistor, and particularly can still increase the reading speed of a reading signal of the sensing amplifying circuit under a lower voltage source in a reading mode, so that the performance of the nonvolatile memory circuit is improved.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
FIG. 1 is a schematic diagram showing a schematic structure of a nonvolatile memory circuit in the prior art;
FIG. 2 illustrates a non-volatile memory circuit having a preferred bit line driver circuit provided in accordance with an aspect of the present application;
FIG. 3 is a diagram illustrating simulation results of input signals at the input terminal of the sense amplifier circuit when the first voltage source is 1.2V according to a preferred embodiment of the present application;
fig. 4 is a diagram illustrating simulation results of input signals of the input terminal of the sense amplifier circuit when the first voltage source is 1.0V according to another preferred embodiment of the present application.
The same or similar reference numbers in the drawings identify the same or similar elements.
Detailed Description
The present application is described in further detail below with reference to the attached figures.
In order to solve the above technical problem, the present application provides a bit line driving circuit 1, wherein the bit line driving circuit 1 includes: the device comprises a bit line charging unit, a bit line driving unit, a sensing amplification circuit protection unit, a second regulated power supply V2 and a third regulated power supply V3.
The bit line charging unit is connected to the first regulated power supply V1 and the first input signal Vin1 to charge the memory cell 4 to the voltage value of the first regulated power supply V1 based on the first input signal Vin 1.
The bit line driving unit is connected to a second input signal Vin2, a third input signal Vin3, an output terminal of a high voltage switch circuit 5, and an output terminal of the bit line charging unit to control the turn-on of the memory cell 4 based on the second input signal Vin 2.
The sense amplifier circuit protection unit is connected to a fourth input signal Vin4, an output terminal of the high voltage switch circuit 5 and an input terminal VSA of the sense amplifier circuit 3 to control an input voltage of the sense amplifier circuit 3.
The second voltage-stabilized power supply V2 is connected with the bit line charging unit, the bit line driving unit and the sensing amplification circuit protection unit; wherein the Well Bias voltage (Well Bias) of the second regulated power supply V2 is always higher than the Bias voltages (Bias) of the first regulated power supply V1 and fourth regulated power supply V4 (shown in fig. 2) in different programming modes of operation. In the read mode, the voltage value of the second regulated power supply V2 may be the same as the voltage values of the first regulated power supply V1 and the fourth regulated power supply V4, for example, 1.2V.
And the third voltage-stabilized power supply V3 is connected with the bit line driving unit and the sensing amplification circuit protection unit. The third regulated voltage supply V3 is a P-well Bias voltage (Pwell Bias) that is 0V or a negative Bias voltage, and in the read mode, the third regulated voltage supply V3 is 0V, which may be set to a negative Bias voltage in other modes.
Further, the bit line charging unit includes a first NMOS transistor N1.
The gate of the first NMOS transistor N1 is connected to the first input signal Vin1, the drain is connected to the first regulated voltage V1, the source is connected to the input terminal of the memory unit 4, and the substrate is connected to the second regulated voltage V2. The first NMOS transistor N1 is used to transfer a bias voltage (e.g., 1.2V) of the first regulated power supply V1 to the bit line BL when the first input signal Vin1 is high in the case of a Read unselected mode (Read Unselect). In the unselected Read Mode (Unselect Read Mode), the first input signal Vin1 outputs 3.3V in the on state and 0V in the off state.
Further, the bit line driving unit includes a second NMOS transistor N2 and a third NMOS transistor N3.
The gate of the second NMOS transistor N2 is connected to the second input signal Vin2, the drain is connected to the source of the first NMOS transistor N1, and the substrate is connected to the second regulated power supply V2 through a first diode D1; the first diode D1, the anode of which is connected to the second NMOS transistor N2 and the third regulated power supply V3, and the cathode of which is connected to the second regulated power supply V2; .
The gate of the third NMOS transistor N3 is connected to the third input signal Vin3, the drain of the third NMOS transistor N3 is connected to the source of the second NMOS transistor N2, and the substrate of the third NMOS transistor N3 is connected to the second regulated power supply V2 through a second diode D2; the anode of the second diode D2 is connected to the third NMOS transistor N3 and the third regulated voltage V3, and the cathode is connected to the second regulated voltage V2.
Further, the sense amplifying circuit protecting unit includes a fourth NMOS transistor N4.
The gate of the fourth NMOS transistor N4 is connected to the fourth input signal Vin4, the drain is connected to the source of the third NMOS transistor N3, the substrate is connected to the second regulated voltage source V2 through a third diode D3, and the source is connected to the input terminal VSA of the sense amplifier circuit 3; the anode of the third diode D3 is connected to the fourth NMOS transistor N4 and the third regulated voltage V3, and the cathode is connected to the second regulated voltage V2.
Further, the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, and the fourth NMOS transistor N4 are all High Voltage NMOS transistors (High Voltage NMOS), and the High Voltage NMOS transistors have a High gate-drain bias Voltage difference (Vgd differential bias) of about 3.6V to 4V at most. The high voltage NMOS transistor may use different power supply conditions (e.g., 1.2V and 3.3V) to enable the circuit to use all modes (read mode, program mode, erase mode, etc.), for example, the maximum bias voltage may reach 3.6V in read mode.
After the first NMOS transistor N1 precharges the bit line BL to the voltage value of the first regulated voltage V1, the second NMOS transistor N2, the third NMOS transistor N3, and the fourth NMOS transistor N4 turn on and transfer the bit line BL voltage to the sensing path (transferred to the input terminal VSA of the sense amplifier circuit 3 via the fifth NMOS transistor N5) the bias voltage of the source line SL is 1.2V, and the sense amplifier circuit 3 starts the sense sensing in the selected state from the source line SL to the bit line BL.
The first diode D1, the second diode D2 and the third diode D3 are parasitic diodes displayed in simulation and layout simulation. Further, in the read mode, the voltage values of the first regulated power supply V1 and the second regulated power supply V2 are both 1.0V-1.5V, preferably 1.2V, and in other modes, the voltage value of the first regulated power supply V1 is smaller than that of the second regulated power supply V2. The first input signal Vin1 outputs a high level of 2.8V to 3.5V and a low level of a ground voltage value.
According to another aspect of the present application, a nonvolatile memory circuit is provided, in which a bit line driving circuit 1, a memory cell 4, a sense amplifier circuit 3, a high voltage switch circuit 5, and a source driver circuit 2 are included.
The sensing amplifying circuit 3 is used for sensing and amplifying an input voltage of the storage unit 4; the source driving circuit 2 is connected to the output end of the high voltage switch circuit 5, a fourth input signal Vin4 and a third regulated power supply V3.
Further, the bit line charging unit includes a first NMOS transistor N1.
The first NMOS transistor N1 has a gate connected to the first input signal Vin1, a drain connected to the first regulated voltage V1, a source connected to the input terminal of the memory unit 4, and a substrate connected to the second regulated voltage V2.
Further, the bit line driving unit includes: a second NMOS transistor N2 and a third NMOS transistor N3.
The gate of the second NMOS transistor N2 is connected to the second input signal Vin2, the drain is connected to the source of the first NMOS transistor N1, and the substrate gate is connected to the second regulated power supply V2 through a first diode D1; .
The first diode D1 has an anode connected to the second NMOS transistor N2 and the third regulated voltage V3, and a cathode connected to the second regulated voltage V2.
The gate of the third NMOS transistor N3 is connected to the third input signal Vin3, the drain is connected to the source of the second NMOS transistor N2, and the substrate gate is connected to the second regulated voltage V2 through a second diode D2.
And the anode of the second diode D2 is connected to the third NMOS transistor N3 and the third regulated voltage V3, and the cathode is connected to the second regulated voltage V2.
Further, the sense amplifying circuit protecting unit includes a fourth NMOS transistor N4.
The gate of the fourth NMOS transistor N4 is connected to the fourth input signal Vin4, the drain is connected to the source of the third NMOS transistor N3, the substrate is connected to the second regulated voltage V2 through a third diode D3, and the source is connected to the input terminal VSA of the sense amplifier circuit 3.
And the anode of the third diode D3 is connected to the fourth NMOS transistor N4 and the third regulated voltage V3, and the cathode is connected to the second regulated voltage V2.
Further, the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, and the fourth NMOS transistor N4 are all High Voltage NMOS transistors (High Voltage NMOS). The use of the high voltage NMOS transistor can accommodate both the first voltage supply V1 being 1V to 1.2V in the read mode, while other modes such as program and erase modes can be used.
Further, the first regulated power supply V1 is 2.8V to 3.5V, the second regulated power supply V2 is 1.0V to 1.5V, and the first input signal Vin1 outputs a high level of 2.8V to 3.5V and a low level of the ground voltage.
In the embodiment of the present application, in the nonvolatile memory circuit, NMOS transistors are disposed in the paths from the source driver circuit 2 to the bit line driver circuit 1 and from the bit line driver circuit 1 to the sense amplifier circuit 3, and have a higher gate-drain bias voltage, and in an on state, the bias voltage of the gate is 3.3V, and the bias voltage of the source line SL is 1.2V. The high-voltage switch circuit 5 is configured to be in another operation mode, and in a read mode, the high-voltage switch circuit 5 is in an off state (Disabled), a bias voltage of the source line SL is 1.2V, in the source line circuit 2, a drain of the fifth NMOS transistor N5 is connected to the fourth regulated power supply V4, and a gate is connected to a signal SX, where when an input voltage of the gate input signal SX is 2.8-3.3V, the fifth NMOS pipe N5 transmits a voltage value (preferably 1.2V) of the fourth regulated power supply V4 to the source line SL, where an anode of the fourth diode D4 is connected to the substrate of the fifth NMOS pipe N5, a cathode of the fourth diode D3884 is connected to the second regulated power supply V2, and the fourth diode D4 is a parasitic diode shown in simulation and layout simulation.
FIG. 3 is a diagram illustrating simulation results of an input signal at an input terminal of a sense amplifier circuit when a first regulated power supply is 1.2V according to a preferred embodiment of the present application; FIG. 4 is a schematic diagram showing simulation results of an input signal at an input terminal of the sense amplifier circuit when the first regulated power supply is 1.0V according to another preferred embodiment of the present application. In FIG. 3, when the first regulated power supply is 1.2V, the P-type (210mv @30ns) is within 30ns when the PMOS transistor is adopted in the prior art shown in FIG. 1, the input signal VSA at the input end of the sensing and amplifying circuit rises by 210mv, and the N-type (332mv @30ns) is within 30ns when the NMOS transistor is adopted in the embodiment of the present application, the input signal VSA at the input end of the sensing and amplifying circuit rises by 332 mv; in fig. 4, when the first voltage source is 1.0V, the P-type (87mv @30ns) is within 30ns when the PMOS transistor is used in the prior art shown in fig. 1, the input signal VSA at the input terminal of the sense amplifier circuit rises by 87mv, 87mv cannot meet the requirement of the sense bias voltage of the sense amplifier circuit, so that the prior art needs to wait for the sensing time exceeding 30ns when the first voltage source is 1.0V, and cannot meet the requirement of the device, and the N-type (157mv @30ns) is within 30ns when the NMOS transistor is used in the embodiment of the present application, the input signal VSA at the input terminal of the sense amplifier circuit rises by 157mv, and 157mv can meet the requirement of the sense bias voltage of the sense amplifier circuit, and then can meet the requirement of the device when the first voltage source is 1.0V.
Compared with the prior art, the bit line driving circuit and the nonvolatile memory circuit comprising the bit line driving circuit improve the reading sensing speed by utilizing the higher voltage difference between the grid electrode and the substrate of the NMOS transistor, so that the voltage source is 1.0V-1.5V, the reading speed of the reading signal of the sensing amplifying circuit can be still increased, and the performance of the nonvolatile memory circuit is further improved.
It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Claims (12)

1. A bit line driver circuit, comprising:
a bit line charging unit connected to a first regulated power supply and a first input signal to charge a storage unit to a first regulated power supply value based on the first input signal;
a bit line driving unit connected to a second input signal, a third input signal, an output terminal of a high voltage switching circuit, and an output terminal of the bit line charging unit to control the turn-on of the memory cell based on the second input signal;
the sensing amplification circuit protection unit is connected to a fourth input signal, the output end of the high-voltage switch circuit and the input end of the sensing amplification circuit so as to control the input voltage of the sensing amplification circuit;
the second voltage-stabilized source is connected with the bit line charging unit, the bit line driving unit and the sensing amplification circuit protection unit;
the third voltage-stabilized source is connected with the bit line driving unit and the sensing amplification circuit protection unit;
the bit line charging unit, the bit line driving unit and the sensing amplification circuit protection unit all comprise at least one NMOS transistor.
2. The bit line driving circuit of claim 1, wherein the bit line charging unit comprises:
and the grid electrode of the first NMOS transistor is connected to the first input signal, the drain electrode of the first NMOS transistor is connected to the first stabilized voltage power supply, the source electrode of the first NMOS transistor is connected to the input end of the storage unit, and the substrate of the first NMOS transistor is connected to the second stabilized voltage power supply.
3. The bit line driver circuit according to claim 2, wherein the bit line driver unit comprises:
a second NMOS transistor, wherein the grid electrode of the second NMOS transistor is connected to the second input signal, the drain electrode of the second NMOS transistor is connected to the source electrode of the first NMOS transistor, and the substrate is connected to the second voltage-stabilizing power supply through a first diode;
the anode of the first diode is connected to the second NMOS transistor and the third stabilized voltage supply, and the cathode of the first diode is connected to the second stabilized voltage supply;
a third NMOS transistor, wherein the grid electrode of the third NMOS transistor is connected to a third input signal, the drain electrode of the third NMOS transistor is connected to the source electrode of the second NMOS transistor, and the substrate is connected to the second voltage-stabilized power supply through a second diode;
and the anode of the second diode is connected to the third NMOS transistor and the third stabilized voltage power supply, and the cathode of the second diode is connected to the second stabilized voltage power supply.
4. The bit line driver circuit according to claim 3, wherein the sense amplifier circuit protection unit comprises:
a fourth NMOS transistor having a gate connected to the fourth input signal, a drain connected to the source of the third NMOS transistor, a substrate connected to the second regulated power supply through a third diode, and a source connected to the input terminal of the sense amplifier circuit;
and the anode of the third diode is connected to the fourth NMOS transistor and the third stabilized voltage power supply, and the cathode of the third diode is connected to the second stabilized voltage power supply.
5. The bit line driver circuit of claim 4, wherein the first, second, third, and fourth NMOS transistors are high voltage NMOS transistors.
6. The bit line driving circuit according to any one of claims 1 to 5, wherein in the read mode, the voltage values of the first and second regulated power supplies are both 1.0V to 1.5V, and in the other mode, the voltage value of the first regulated power supply is smaller than that of the second regulated power supply, and the first input signal outputs a high level of 2.8V to 3.5V and a low level of a ground voltage value.
7. A nonvolatile memory circuit is characterized by comprising a bit line driving circuit, a memory cell, a sensing amplifying circuit, a high-voltage switch circuit and a source electrode driving circuit;
the bit line driving circuit includes:
a bit line charging unit connected to a first regulated power supply and a first input signal to charge the memory cell to a first regulated power supply value based on the first input signal;
a bit line driving unit connected to a second input signal, an output terminal of a high voltage switching circuit, and an output terminal of the bit line charging unit to control the turn-on of the memory cell based on the second input signal;
the sensing amplification circuit protection unit is connected to a fourth input signal, the output end of the high-voltage switch circuit and the input end of the sensing amplification circuit so as to control the input voltage of the sensing amplification circuit;
the second voltage-stabilized source is connected with the bit line charging unit, the bit line driving unit and the sensing amplification circuit protection unit;
the third voltage-stabilized source is connected with the bit line driving unit and the sensing amplification circuit protection unit;
the sensing amplifying circuit is used for sensing and amplifying the input voltage of the storage unit;
the source electrode driving circuit is connected to the output end of the high-voltage switch circuit, a fourth input signal and a third stabilized voltage power supply;
and the bit line charging unit, the bit line driving unit and the sensing amplification circuit protection unit all comprise at least one NMOS transistor.
8. The nonvolatile memory circuit according to claim 7, wherein the bit line charging unit comprises:
and the grid electrode of the first NMOS transistor is connected to the first input signal, the drain electrode of the first NMOS transistor is connected to the first stabilized voltage power supply, the source electrode of the first NMOS transistor is connected to the input end of the storage unit, and the substrate of the first NMOS transistor is connected to the second stabilized voltage power supply.
9. The nonvolatile memory circuit according to claim 8, wherein the bit line driving unit comprises:
a second NMOS transistor, wherein the grid electrode of the second NMOS transistor is connected to a second input signal, the drain electrode of the second NMOS transistor is connected to the source electrode of the first NMOS transistor, and the substrate is connected to the second voltage-stabilizing power supply through a first diode;
the anode of the first diode is connected to the second NMOS transistor and the third stabilized voltage power supply, and the cathode of the first diode is connected to the second stabilized voltage power supply;
a third NMOS transistor, wherein the grid electrode of the third NMOS transistor is connected to a third input signal, the drain electrode of the third NMOS transistor is connected to the source electrode of the second NMOS transistor, and the substrate is connected to the second voltage-stabilized power supply through a second diode;
and the anode of the second diode is connected to the third NMOS transistor and the third stabilized voltage power supply, and the cathode of the second diode is connected to the second stabilized voltage power supply.
10. The nonvolatile memory circuit according to claim 9, wherein the sense amplifier circuit protection unit includes:
a fourth NMOS transistor having a gate connected to the fourth input signal, a drain connected to the source of the third NMOS transistor, a substrate connected to the second regulated power supply through a third diode, and a source connected to the input terminal of the sense amplifier circuit;
and the anode of the third diode is connected to the fourth NMOS transistor and the third stabilized voltage power supply, and the cathode of the third diode is connected to the second stabilized voltage power supply.
11. The non-volatile memory circuit of claim 10, wherein the first, second, third, and fourth NMOS transistors are high voltage NMOS transistors.
12. The nonvolatile memory circuit according to any one of claims 7 to 11, wherein in the read mode, the voltage values of the first and second regulated power supplies are each 1.0V to 1.5V, and in the other mode, the voltage value of the first regulated power supply is smaller than the voltage value of the second regulated power supply, and the first input signal outputs a high level of 2.8V to 3.5V and a low level of a ground voltage value.
CN201610094461.9A 2016-02-19 2016-02-19 Bit line driving circuit and nonvolatile memory circuit Active CN107103932B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610094461.9A CN107103932B (en) 2016-02-19 2016-02-19 Bit line driving circuit and nonvolatile memory circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610094461.9A CN107103932B (en) 2016-02-19 2016-02-19 Bit line driving circuit and nonvolatile memory circuit

Publications (2)

Publication Number Publication Date
CN107103932A CN107103932A (en) 2017-08-29
CN107103932B true CN107103932B (en) 2020-05-01

Family

ID=59658642

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610094461.9A Active CN107103932B (en) 2016-02-19 2016-02-19 Bit line driving circuit and nonvolatile memory circuit

Country Status (1)

Country Link
CN (1) CN107103932B (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6272059B1 (en) * 1998-12-24 2001-08-07 Hyundai Electronics Industries Co., Ltd. Bit line sense-amplifier for a semiconductor memory device and a method for driving the same
CN1702770A (en) * 2004-05-25 2005-11-30 株式会社日立制作所 Semiconductor integrated circuit device
CN101178927A (en) * 2006-11-06 2008-05-14 财团法人工业技术研究院 Multi-stable sensing amplifier applied to memory
CN102855931A (en) * 2012-09-19 2013-01-02 上海宏力半导体制造有限公司 Memory and reading circuit thereof
CN105304122A (en) * 2014-06-16 2016-02-03 爱思开海力士有限公司 Semiconductor device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100855964B1 (en) * 2006-11-03 2008-09-02 삼성전자주식회사 Flash memory device, and method for reading therefrom

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6272059B1 (en) * 1998-12-24 2001-08-07 Hyundai Electronics Industries Co., Ltd. Bit line sense-amplifier for a semiconductor memory device and a method for driving the same
CN1702770A (en) * 2004-05-25 2005-11-30 株式会社日立制作所 Semiconductor integrated circuit device
CN101178927A (en) * 2006-11-06 2008-05-14 财团法人工业技术研究院 Multi-stable sensing amplifier applied to memory
CN102855931A (en) * 2012-09-19 2013-01-02 上海宏力半导体制造有限公司 Memory and reading circuit thereof
CN105304122A (en) * 2014-06-16 2016-02-03 爱思开海力士有限公司 Semiconductor device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Hua Zhang;Ling Lu.A Low-Voltage Sense Amplifier for Embedded Flash Memories.《IEEE Transactions on Circuits and Systems II: Express Briefs》.2015,第62卷 *
ＯＴＰ存储器位线负载对读出速度的影响;吴欣昱，张金旻，罗玉香;《微电子学》;20151031(第05期);第649页-第651页 *

Also Published As

Publication number Publication date
CN107103932A (en) 2017-08-29

Similar Documents

Publication Publication Date Title
JP4746326B2 (en) Nonvolatile semiconductor memory device
US20190115088A1 (en) Flash Memory System Using Negative High Voltage Level Shifter
US8125829B2 (en) Biasing system and method
US9460797B2 (en) Non-volatile memory cell structure and non-volatile memory apparatus using the same
KR100644224B1 (en) Level shifter for reducing leakage current and block driver in nonvolatile semiconductor memory device having the same
US7499327B2 (en) NAND flash memory device having page buffer adapted to discharge bit line voltage during erase operation
US7911864B2 (en) Semiconductor memory device
TWI462279B (en) Non-volatile memory cell
US7738298B2 (en) Flash memory device
JP4703162B2 (en) Nonvolatile semiconductor memory device and writing method thereof
US8483004B2 (en) Semiconductor device with transistor storing data by change in level of threshold voltage
US7586333B1 (en) High speed, low supply voltage tolerant bootstrapped word line driver with high voltage isolation
CN107103932B (en) Bit line driving circuit and nonvolatile memory circuit
JP5477483B2 (en) Nonvolatile semiconductor memory device and nonvolatile semiconductor memory device
US20150256171A1 (en) High voltage switch with two or more outputs
JP2008097758A (en) Semiconductor memory device
US6014331A (en) Circuit for programming a programmable memory cell
KR20150048427A (en) Discharge circuit
JP6201646B2 (en) Semiconductor memory device
US8159877B2 (en) Method of directly reading output voltage to determine data stored in a non-volatile memory cell
JP2015019158A (en) Semiconductor circuit
US11532359B2 (en) Semiconductor device having a level conversion circuit
US11862227B2 (en) Memory cell driver circuit
US8130558B2 (en) System and method for level shifter
US8254176B2 (en) Eeprom device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant