CN107103932A - Bit line drive circuit and non-volatile memory - Google Patents
Bit line drive circuit and non-volatile memory Download PDFInfo
- Publication number
- CN107103932A CN107103932A CN201610094461.9A CN201610094461A CN107103932A CN 107103932 A CN107103932 A CN 107103932A CN 201610094461 A CN201610094461 A CN 201610094461A CN 107103932 A CN107103932 A CN 107103932A
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- China
- Prior art keywords
- voltage
- stabilized power
- power supply
- pass transistor
- nmos pass
- Prior art date
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
Abstract
This application provides a kind of bit line drive circuit and a kind of non-volatile memory including bit line drive circuit, reading sensing speed is improved by using the higher grid of nmos pass transistor and the voltage difference of substrate, the reading speed of sense amp circuit read signal can be increased, and then improve the performance of non-volatile memory.
Description
Technical field
The application is related to field of semiconductor manufacture, more particularly to a kind of bit line drive circuit and it is non-easily
The property lost storage circuit.
Background technology
NVM (Non Volatile Memory, non-volatile memory) needs many driving electricity
Road controls the work of non-volatile memory, and drive circuit is used to control wordline (word
Line, WL), control gate (Control Gate, CG), bit-line drive (Bit Line, BL),
Source electrode line (Source Line, SL) and selection grid (Select line, SL), it is non-to control
Volatile memory circuit is in the bias voltage of each operating process, including programming operation, deletion action
And read operation.
Fig. 1 shows that BL drive circuits 1 ' (bit line drive circuit) in the prior art and SL drive
Dynamic circuit 2 ' (source line driving circuit).As shown in figure 1, under reading mode, the first PMOS is brilliant
Body pipe P1 source electrode is connected with voltage source VCC, when the grid of the first PMOS transistor P1
When pole input voltage is low level value (such as 0V), the first PMOS transistor P1 conductings,
And transmit the voltage of the voltage source VCC into bit line BL through drain electrode, to complete precharge
(pre-charging), then the gate input voltage of the first PMOS transistor P1 is height
During level value (such as 3.3V), the first PMOS transistor P1 cut-offs, when selection grid
When SG chooses the memory cell, the second PMOS transistor P2, the 3rd PMOS transistor
P3 and the first nmos pass transistor N1 conductings, then sense amp circuit 3 ' passes through described second
PMOS transistor P2, the 3rd PMOS transistor P3 and the first nmos pass transistor N1
Read signal is obtained through bit line BL.The Vg (grid voltage) of usual PMOS transistor is 0.7V,
In the case of voltage source VCC is more than 1.5V, without doubt, sense amp circuit 3 ' is through second
PMOS P2 and the 3rd PMOS P3 can accelerate reading rate.However, as voltage source VCC
When reducing (such as 1.2V or 1V), relatively low voltage source VCC inputs can be reduced from bit line BL
To sense amp circuit 3 ' (Sense Amplifier, SA) transmission speed, and then influence to read
Speed.
The content of the invention
The application technical problem to be solved is to provide a kind of bit line drive circuit and driven including bit line
The non-volatile memory of dynamic circuit, so that NMOS can be utilized in low power supply supply product
The higher grid of transistor and the voltage difference of substrate read sensing speed to improve.
In order to solve the above technical problems, this application provides a kind of bit line drive circuit, wherein,
Institute's bit-line driver circuit includes：
Bit line charhing unit, it is connected to the first voltage-stabilized power supply and the first input signal, with based on
Memory cell is charged to the first voltage-stabilized power supply value by first input signal；
Bit-line drive unit, it is connected to the second input signal, the 3rd input signal, high-voltage switch gear
The output end of circuit and the output end of the bit line charhing unit, to be believed based on the described second input
The unlatching of number control memory cell；
Sense amp circuit protection location, it is connected to the 4th input signal, the high-voltage switch gear
The output end of circuit and the input of sense amp circuit, to control the sense amp circuit
Input voltage；
Second voltage-stabilized power supply, itself and the bit line charhing unit, the bit-line drive unit and institute
Sense amp circuit protection location is stated to be connected；
3rd voltage-stabilized power supply, it is protected with the bit-line drive unit and the sense amp circuit
Unit is connected.
Further, the bit line charhing unit includes：
First nmos pass transistor, its grid is connected to first input signal, drain electrode connection
The input of the memory cell, substrate connection are connected to first voltage-stabilized power supply, source electrode
To second voltage-stabilized power supply.
Further, the bit-line drive unit includes：
Second nmos pass transistor, its grid is connected to the second input signal, drain electrode connection
To the source electrode of first nmos pass transistor, substrate described the is connected to by the first diode
Two voltage-stabilized power supplies；
First diode, its positive pole is connected to second nmos pass transistor and described
Three voltage-stabilized power supplies, negative pole are connected to second voltage-stabilized power supply；
3rd nmos pass transistor, its grid is connected to the 3rd input signal, drain electrode connection
To the source electrode of second nmos pass transistor, substrate described the is connected to by the second diode
Two voltage-stabilized power supplies；
Second diode, its positive pole is connected to the 3rd nmos pass transistor and described
Three voltage-stabilized power supplies, negative pole are connected to second voltage-stabilized power supply.
Further, the sense amp circuit protection location includes：
4th nmos pass transistor, its grid is connected to the 4th input signal, drain electrode connection
To the source electrode of the 3rd nmos pass transistor, substrate described the is connected to by the 3rd diode
Two voltage-stabilized power supplies, source electrode are connected to the input of sense amp circuit；
3rd diode, its positive pole is connected to the 4th nmos pass transistor and described
Three voltage-stabilized power supplies, negative pole are connected to second voltage-stabilized power supply.
Further, first nmos pass transistor, the second nmos pass transistor, the 3rd
Nmos pass transistor and the 4th nmos pass transistor are High voltage NMOS transistor.
Further, in read mode, first voltage-stabilized power supply and second voltage-stabilized power supply
Magnitude of voltage be 1.0V~1.5V, under other patterns, the magnitude of voltage of first voltage-stabilized power supply
Less than the magnitude of voltage of the second voltage-stabilized power supply.The height electricity of the first input signal output 2.8V~3.5V
The low level of gentle ground voltage value.
On the other hand a kind of non-volatile memory is provided according to the application, wherein, including
Bit line drive circuit, memory cell, sense amp circuit, high voltage switch circuit and source drive
Circuit.
Wherein, institute's bit-line driver circuit includes：
Bit line charhing unit, it is connected to the first voltage-stabilized power supply and the first input signal, with based on
The memory cell is charged to the first voltage-stabilized power supply value by first input signal；
Bit-line drive unit, it is connected to the second input signal, the output end of high voltage switch circuit
Output end with the bit line charhing unit, with based on being deposited described in second input signal control
The unlatching of storage unit；
Sense amp circuit protection location, it is connected to the 4th input signal, the high-voltage switch gear
The output end of circuit and the input of sense amp circuit, to control the sense amp circuit
Input voltage；
Second voltage-stabilized power supply, itself and the bit line charhing unit, the bit-line drive unit and institute
Sense amp circuit protection location is stated to be connected；
3rd voltage-stabilized power supply, it is protected with the bit-line drive unit and the sense amp circuit
Unit is connected；
The sense amp circuit is used to sense the input voltage with amplifying and storage unit；
The source electrode drive circuit, it is connected to the output end of the high voltage switch circuit, the 4th defeated
Enter signal and the 3rd voltage-stabilized power supply.
Further, the bit line charhing unit includes：
First nmos pass transistor, its grid is connected to first input signal, drain electrode connection
The input of the memory cell, substrate connection are connected to first voltage-stabilized power supply, source electrode
To second voltage-stabilized power supply.
Further, the bit-line drive unit includes：
Second nmos pass transistor, its grid is connected to the second input signal, drain electrode connection
To the source electrode of first nmos pass transistor, substrate described the is connected to by the first diode
Two voltage-stabilized power supplies；
First diode, its positive pole is connected to second nmos pass transistor and described
Three voltage-stabilized power supplies, negative pole are connected to second voltage-stabilized power supply；
3rd nmos pass transistor, its grid is connected to the 3rd input signal, drain electrode connection
To the source electrode of second nmos pass transistor, substrate described the is connected to by the second diode
Two voltage-stabilized power supplies；
Second diode, its positive pole is connected to the 3rd nmos pass transistor and described
Three voltage-stabilized power supplies, negative pole are connected to second voltage-stabilized power supply.
Further, the sense amp circuit protection location includes：
4th nmos pass transistor, its grid is connected to the 4th input signal, drain electrode connection
To the source electrode of the 3rd nmos pass transistor, substrate described the is connected to by the 3rd diode
Two voltage-stabilized power supplies, source electrode are connected to the input of sense amp circuit；
3rd diode, its positive pole is connected to the 4th nmos pass transistor and described
Three voltage-stabilized power supplies, negative pole are connected to second voltage-stabilized power supply.
Further, first nmos pass transistor, the second nmos pass transistor, the 3rd
Nmos pass transistor and the 4th nmos pass transistor are High voltage NMOS transistor.
Further, in read mode, first voltage-stabilized power supply and second voltage-stabilized power supply
Magnitude of voltage be 1.0V~1.5V, under other patterns, the magnitude of voltage of first voltage-stabilized power supply
Less than the magnitude of voltage of the second voltage-stabilized power supply.The height electricity of the first input signal output 2.8V~3.5V
The low level of gentle ground voltage value.
Compared to prior art, herein described bit line drive circuit and including bit line drive circuit
Non-volatile memory, by using the higher grid and substrate of nmos pass transistor
Voltage difference reads sensing speed to improve, especially in read mode, under relatively low voltage source, still
The reading speed of sense amp circuit read signal can be increased, and then improve non-volatile memories electricity
The performance on road.
Brief description of the drawings
Retouched by reading with reference to the detailed of being made to non-limiting example of being made of the following drawings
State, other features, objects and advantages will become more apparent upon：
Fig. 1 shows the brief configuration schematic diagram of non-volatile memory in the prior art；
Fig. 2 show according to the application on the one hand provide it is a kind of with preferred bit line drive circuit
Non-volatile memory；
Fig. 3 shows, according in the preferred embodiment of the application one, when first voltage source is 1.2V, to pass
The simulation result schematic diagram of the input signal of sense amplifying circuit input；
Fig. 4 is shown according in another preferred embodiment of the application, when first voltage source is 1.0V,
The simulation result schematic diagram of the input signal of sense amp circuit input.
Same or analogous reference represents same or analogous part in accompanying drawing.
Embodiment
The application is described in further detail below in conjunction with the accompanying drawings.
In order to solve the above technical problems, this application provides a kind of bit line drive circuit 1, wherein,
Institute's bit-line driver circuit 1 includes：Bit line charhing unit, bit-line drive unit, Sense Amplification electricity
Road protection location, the second voltage-stabilized power supply V2, the 3rd voltage-stabilized power supply V3.
The bit line charhing unit, it is connected to the first voltage-stabilized power supply V1 and the first input signal
Vin1, so that memory cell 4 is charged into the first voltage stabilizing electricity based on the first input signal Vin1
Source V1 magnitude of voltage.
The bit-line drive unit, it is connected to the second input signal Vin2, the 3rd input signal
Vin3, the output end of high voltage switch circuit 5 and the bit line charhing unit output end, with based on
The second input signal Vin2 controls the unlatching of the memory cell 4.
The sense amp circuit protection location, it is connected to the 4th input signal Vin4, the height
The output end of circuit 5 that compresses switch and the input VSA of sense amp circuit 3, to control the biography
The input voltage of sense amplifying circuit 3.
The second voltage-stabilized power supply V2, itself and the bit line charhing unit, the bit-line drive list
It is first to be connected with the sense amp circuit protection location；Wherein, in different program operation modes
In, the trap bias voltage (Well Bias) of the second voltage-stabilized power supply V2 is consistently higher than described
One voltage-stabilized power supply V1 and the 4th voltage-stabilized power supply V4 (shown in Fig. 2) bias voltage (Bias).
In read mode, the magnitude of voltage of the second voltage-stabilized power supply V2 can be with the first voltage-stabilized power supply V1
It is identical with the 4th voltage-stabilized power supply V4 magnitude of voltage, for example it is 1.2V.
The 3rd voltage-stabilized power supply V3, itself and the bit-line drive unit and Sense Amplification electricity
Road protection location is connected.The 3rd voltage-stabilized power supply V3 is p-well bias voltage (Pwell Bias),
It is 0V or negative bias voltage, and in read mode, the 3rd voltage-stabilized power supply V3 is 0V,
Negative bias voltage is could be arranged under other patterns.
Further, the bit line charhing unit includes one first nmos pass transistor N1.
The grid of the first nmos pass transistor N1 be connected to the first input signal Vin1,
Drain electrode is connected to the input that the first voltage-stabilized power supply V1, source electrode are connected to the memory cell 4
End, substrate are connected to the second voltage-stabilized power supply V2.The first nmos pass transistor N1 is used
It is height in the first input signal Vin1 in the case of reading mode unselected (Read Unselect)
When, the first voltage-stabilized power supply V1 of transmission bias voltage (such as 1.2V) arrives bit line BL.Not
Under the reading mode (Unselect Read Mode) chosen, the first input signal Vin1 is being opened
3.3V is exported when opening state, 0V is exported in off position.
Further, the bit-line drive unit includes one second nmos pass transistor N2 and 1 the
Three nmos pass transistor N3.
The second nmos pass transistor N2, its grid is connected to the second input signal Vin2, leakage
Pole is connected to the source electrode of the first nmos pass transistor N1, substrate and passes through the first diode D1
It is connected to the second voltage-stabilized power supply V2；The first diode D1, its positive pole is connected to described
Second nmos pass transistor N2 and the 3rd voltage-stabilized power supply V3, negative pole is connected to described second
Voltage-stabilized power supply V2；.
The 3rd nmos pass transistor N3, its grid is connected to the 3rd input signal Vin3, leakage
Pole is connected to the source electrode of the second nmos pass transistor N2, substrate and passes through the second diode D2
It is connected to the second voltage-stabilized power supply V2；The second diode D2, its positive pole is connected to described
3rd nmos pass transistor N3 and the 3rd voltage-stabilized power supply V3, negative pole be connected to described
Two voltage-stabilized power supply V2.
Further, the sense amp circuit protection location includes one the 4th nmos pass transistor
N4。
The 4th nmos pass transistor N4, its grid is connected to the 4th input signal
Vin4, drain electrode are connected to the source electrode of the 3rd nmos pass transistor N3, substrate by the three or two
Pole pipe D3 is connected to the second voltage-stabilized power supply V2, source electrode and is connected to the defeated of sense amp circuit 3
Enter to hold VSA；The 3rd diode D3, its positive pole is connected to the 4th nmos pass transistor
N4 and the 3rd voltage-stabilized power supply V3, negative pole is connected to the second voltage-stabilized power supply V2.
Further, the first nmos pass transistor N1, the second nmos pass transistor N2,
3rd nmos pass transistor N3 and the 4th nmos pass transistor N4 is high pressure NMOS crystal
Manage (High Voltage NMOS), here, the High voltage NMOS transistor is with higher
Gate-to-drain bias voltage difference (Vgd different bias), the largest of about 3.6V~4V.High pressure
Nmos pass transistor can use different conditions of power supply (such as 1.2V and 3.3V), so as to
Enough make circuit using all patterns (reading mode, programming mode, clash pattern etc.), for example, reading
Under pattern, highest bias voltage can reach 3.6V.
The first voltage stabilizing electricity is pre-charged to the bit line BL in the first nmos pass transistor N1
After source V1 magnitude of voltage, the second nmos pass transistor N2, the 3rd nmos pass transistor N3
Opened with the 4th nmos pass transistor N4 and the bit line BL voltages are transferred to sensory path (warp
5th nmos pass transistor N5 is transferred to the input VSA of the sense amp circuit 3) source electrode
Line SL bias voltage is 1.2V, from source electrode line SL to bit line BL to sense amp circuit 3
Input VSA so that start under selected state read sensing.
The first diode D1, the second diode D2 and the 3rd diode D3 are simulation and version
The parasitic diode shown during figure emulation.Further, in read mode, first voltage stabilizing
Power supply V1 and the second voltage-stabilized power supply V2 magnitude of voltage are 1.0V~1.5V, preferably
1.2V, under other patterns, the magnitude of voltage of the first voltage-stabilized power supply V1 is less than the second voltage stabilizing electricity
Source V2 magnitude of voltage.The first input signal Vin1 exports 2.8V~3.5V high level and connect
The low level of ground voltage value.
On the other hand a kind of non-volatile memory is provided according to the application, wherein, including
Bit line drive circuit 1, memory cell 4, sense amp circuit 3, high voltage switch circuit 5 and source electrode
Drive circuit 2.
Wherein, the sense amp circuit 3 is used to sense the input voltage with amplifying and storage unit 4；
The source electrode drive circuit 2, it is connected to the output end of the high voltage switch circuit 5, the 4th defeated
Enter signal Vin4 and the 3rd voltage-stabilized power supply V3.
Further, the bit line charhing unit includes one first nmos pass transistor N1.
The first nmos pass transistor N1, its grid is connected to first input signal
Vin1, drain electrode are connected to the first voltage-stabilized power supply V1, source electrode and are connected to the memory cell 4
Input, substrate be connected to the second voltage-stabilized power supply V2.
Further, the bit-line drive unit includes：Second nmos pass transistor N2 and the 3rd
Nmos pass transistor N3.
The second nmos pass transistor N2, its grid is connected to the second input signal Vin2, leakage
Source electrode, the substrate gate that pole is connected to the first nmos pass transistor N1 pass through the first diode
D1 is connected to the second voltage-stabilized power supply V2；.
The first diode D1, its positive pole be connected to the second nmos pass transistor N2 and
The 3rd voltage-stabilized power supply V3, negative pole is connected to the second voltage-stabilized power supply V2.
The 3rd nmos pass transistor N3, its grid is connected to the 3rd input signal Vin3, leakage
Source electrode, the substrate gate that pole is connected to the second nmos pass transistor N2 pass through the second diode
D2 is connected to the second voltage-stabilized power supply V2.
The second diode D2, its positive pole be connected to the 3rd nmos pass transistor N3 and
The 3rd voltage-stabilized power supply V3, negative pole are connected to the second voltage-stabilized power supply V2.
Further, the sense amp circuit protection location includes one the 4th nmos pass transistor
N4。
The 4th nmos pass transistor N4, its grid is connected to the 4th input signal
Vin4, drain electrode are connected to the source electrode of the 3rd nmos pass transistor N3, substrate by the three or two
Pole pipe D3 is connected to the second voltage-stabilized power supply V2, source electrode and is connected to the defeated of sense amp circuit 3
Enter to hold VSA.
The 3rd diode D3, its positive pole be connected to the 4th nmos pass transistor N4 and
The 3rd voltage-stabilized power supply V3, negative pole are connected to the second voltage-stabilized power supply V2.
Further, the first nmos pass transistor N1, the second nmos pass transistor N2,
3rd nmos pass transistor N3 and the 4th nmos pass transistor N4 is high pressure NMOS crystal
Manage (High Voltage NMOS).Reading mode can either be adapted to using High voltage NMOS transistor
Lower first source of stable pressure V1 is 1V~1.2V, at the same can use other patterns such as programming mode and
Erasing mode.
Further, the first voltage-stabilized power supply V1 is 2.8V~3.5V, the second voltage stabilizing electricity
Source V2 values are 1.0V~1.5V, the height electricity of the first input signal Vin1 outputs 2.8V~3.5V
The low level of gentle ground voltage value.
In the embodiment of the present application, the non-volatile memory arrives bit line in source electrode drive circuit 2
Drive circuit 1 and bit line drive circuit 1 are provided with to the path between sense amp circuit 3
Nmos pass transistor, with higher gate-to-drain bias voltage, in the on state, grid
Bias voltage use 3.3V, source electrode line SL bias voltage is 1.2V.The high-voltage switch gear electricity
Road 5 is used in other operator schemes, and it is in reading mode, and the high voltage switch circuit 5 is closing
State (Disabled), the bias voltage of the source electrode line SL is 1.2V, in source line circuits 2
In, the drain electrode of the 5th nmos pass transistor N5 meets the 4th voltage-stabilized power supply V4, grid
Signal SX is accessed, when wherein grid input signal SX input voltages are 2.8~3.3V, described the
Five NMSO pipes N5 pass the magnitude of voltage (being preferably 1.2V) of the 4th voltage-stabilized power supply V4
It is defeated to arrive source electrode line SL, wherein, its positive pole of the 4th diode D4 accesses the 5th NMOS
Pipe N5 substrates, negative pole access the second voltage-stabilized power supply V2, the 4th diode D4 for simulation and
The parasitic diode that domain is shown when emulating.
Fig. 3 is shown according in the preferred embodiment of the application one, when the first voltage-stabilized power supply is 1.2V,
The simulation result schematic diagram of the input signal of sense amp circuit input；Fig. 4 is shown according to this Shen
Please be in another preferred embodiment, when the first voltage-stabilized power supply is 1.0V, sense amp circuit input
Input signal simulation result schematic diagram.In Fig. 3, when the first voltage-stabilized power supply is 1.2V,
P-type (210mv@30ns) be Fig. 1 shown in the prior art use PMOS transistor when
In 30ns, the input signal VSA of sense amp circuit input rises 210mv, N-type
(332mv@30ns) be the embodiment of the present application in use nmos pass transistor when in 30ns, pass
The input signal VSA of sense amplifying circuit input rises 332mv；In Fig. 4, first voltage
When source is 1.0V, P-type (87mv@30ns) is to use PMOS shown in Fig. 1 in the prior art
During transistor in 30ns, the input signal VSA of sense amp circuit input rises
87mv, 87mv are can not to meet the sensing bias voltage requirement on sensing electric discharge road, then prior art
It is to need to wait more than 30ns sensitive time when first voltage source is 1.0V, it is impossible to meet device
Part requirement, N-type (157mv@30ns) be the embodiment of the present application in use nmos pass transistor
When in 30ns, the input signal VSA of sense amp circuit input rises 157mv,
157mv can meet the sensing bias voltage requirement of sensing discharge circuit, then be in first voltage source
Requirement on devices can be met during 1.0V.
Compared to prior art, herein described bit line drive circuit and including bit line drive circuit
Non-volatile memory, by using the higher grid and substrate of nmos pass transistor
Voltage difference reads sensing speed to improve, and it is 1.0V~1.5V to make voltage source, can still increase sensing and put
The reading speed of big circuit read signal, and then improve the performance of non-volatile memory.
It is obvious to a person skilled in the art that the application is not limited to above-mentioned one exemplary embodiment
Details, can be with it and in the case of without departing substantially from spirit herein or essential characteristic
His concrete form realizes the application.Therefore, all should be by embodiment no matter from the point of view of which point
Regard exemplary as, and be nonrestrictive, scope of the present application is by appended claims
Rather than described above limit, it is intended that by fall the equivalency of claim implication and
In the range of all changes be included in the application.Should not be by any accompanying drawing mark in claim
Note is considered as the claim involved by limitation.
Obviously, those skilled in the art can to the present invention carry out it is various change and deform without
Depart from the spirit and scope of the present invention.So, if these modifications and variations to the present invention belong to
Within the scope of the claims in the present invention and its equivalent technologies, then the present invention is also intended to include this
It is a little to change and modification.
Claims (12)
1. a kind of bit line drive circuit, it is characterised in that institute's bit-line driver circuit includes：
Bit line charhing unit, it is connected to the first voltage-stabilized power supply and the first input signal, with based on
Memory cell is charged to the first voltage-stabilized power supply value by first input signal；
Bit-line drive unit, it is connected to the second input signal, the 3rd input signal, high-voltage switch gear
The output end of circuit and the output end of the bit line charhing unit, to be believed based on the described second input
The unlatching of number control memory cell；
Sense amp circuit protection location, it is connected to the 4th input signal, the high-voltage switch gear
The output end of circuit and the input of sense amp circuit, to control the sense amp circuit
Input voltage；
Second voltage-stabilized power supply, itself and the bit line charhing unit, the bit-line drive unit and institute
Sense amp circuit protection location is stated to be connected.
3rd voltage-stabilized power supply, it is protected with the bit-line drive unit and the sense amp circuit
Unit is connected.
2. bit line drive circuit according to claim 1, it is characterised in that the bit line
Charhing unit includes：
First nmos pass transistor, its grid is connected to first input signal, drain electrode connection
The input of the memory cell, substrate connection are connected to first voltage-stabilized power supply, source electrode
To second voltage-stabilized power supply.
3. bit line drive circuit according to claim 2, it is characterised in that the bit line
Driver element includes：
Second nmos pass transistor, its grid is connected to second input signal, drain electrode connection
To the source electrode of first nmos pass transistor, substrate described the is connected to by the first diode
Two voltage-stabilized power supplies；
First diode, its positive pole is connected to second nmos pass transistor and described
Three voltage-stabilized power supplies, negative pole are connected to second voltage-stabilized power supply；
3rd nmos pass transistor, its grid is connected to the 3rd input signal, drain electrode and is connected to institute
Stating the source electrode of the second nmos pass transistor, substrate, to be connected to described second by the second diode steady
Voltage source；
Second diode, its positive pole is connected to the 3rd nmos pass transistor and described
Three voltage-stabilized power supplies, negative pole is connected to second voltage-stabilized power supply.
4. bit line drive circuit according to claim 3, it is characterised in that the sensing
Amplifying circuit protection location includes：
4th nmos pass transistor, its grid is connected to the 4th input signal, drain electrode connection
To the source electrode of the 3rd nmos pass transistor, substrate described the is connected to by the 3rd diode
Two voltage-stabilized power supplies, source electrode are connected to the input of sense amp circuit；
3rd diode, its positive pole is connected to the 4th nmos pass transistor and described
Three voltage-stabilized power supplies, negative pole is connected to second voltage-stabilized power supply.
5. bit line drive circuit according to claim 4, it is characterised in that described first
Nmos pass transistor, the second nmos pass transistor, the 3rd nmos pass transistor and the 4th NMOS
Transistor is High voltage NMOS transistor.
6. bit line drive circuit according to any one of claim 1 to 5, its feature exists
In in read mode, the magnitude of voltage of first voltage-stabilized power supply and second voltage-stabilized power supply is equal
For 1.0V~1.5V, under other patterns, the magnitude of voltage of first voltage-stabilized power supply is steady less than second
The magnitude of voltage of voltage source, the high level and ground connection electricity of the first input signal output 2.8V~3.5V
The low level of pressure value.
7. a kind of non-volatile memory, it is characterised in that including bit line drive circuit, deposit
Storage unit, sense amp circuit, high voltage switch circuit and source electrode drive circuit；
Institute's bit-line driver circuit includes：
Bit line charhing unit, it is connected to the first voltage-stabilized power supply and the first input signal, with based on
The memory cell is charged to the first voltage-stabilized power supply value by first input signal；
Bit-line drive unit, it is connected to the second input signal, the output end of high voltage switch circuit
Output end with the bit line charhing unit, with based on being deposited described in second input signal control
The unlatching of storage unit；
Sense amp circuit protection location, it is connected to the 4th input signal, the high-voltage switch gear
The output end of circuit and the input of sense amp circuit, to control the sense amp circuit
Input voltage；
Second voltage-stabilized power supply, itself and the bit line charhing unit, the bit-line drive unit and institute
Sense amp circuit protection location is stated to be connected；
3rd voltage-stabilized power supply, it is protected with the bit-line drive unit and the sense amp circuit
Unit is connected；
The sense amp circuit is used to sense the input voltage with amplifying and storage unit；
The source electrode drive circuit, it is connected to the output end of the high voltage switch circuit, the 4th
Input signal and the 3rd voltage-stabilized power supply.
8. non-volatile memory according to claim 7, it is characterised in that described
Bit line charhing unit includes：
First nmos pass transistor, its grid is connected to first input signal, drain electrode connection
The input of the memory cell, substrate connection are connected to first voltage-stabilized power supply, source electrode
To second voltage-stabilized power supply.
9. non-volatile memories electricity according to claim 8, it is characterised in that institute's rheme
Line driver element includes：
Second nmos pass transistor, its grid is connected to the second input signal, drain electrode and is connected to institute
Stating the source electrode of the first nmos pass transistor, substrate, to be connected to described second by the first diode steady
Voltage source；
First diode, its positive pole is connected to second nmos pass transistor and described
Three voltage-stabilized power supplies, negative pole is connected to second voltage-stabilized power supply；
3rd nmos pass transistor, its grid is connected to the 3rd input signal, drain electrode and is connected to institute
Stating the source electrode of the second nmos pass transistor, substrate, to be connected to described second by the second diode steady
Voltage source；
Second diode, its positive pole is connected to the 3rd nmos pass transistor and described
Three voltage-stabilized power supplies, negative pole are connected to second voltage-stabilized power supply.
10. non-volatile memories electricity according to claim 9, it is characterised in that described to pass
Sense amplifying circuit protection location includes：
4th nmos pass transistor, its grid is connected to the 4th input signal, drain electrode connection
To the source electrode of the 3rd nmos pass transistor, substrate described the is connected to by the 3rd diode
Two voltage-stabilized power supplies, source electrode are connected to the input of sense amp circuit；
3rd diode, its positive pole is connected to the 4th nmos pass transistor and described
Three voltage-stabilized power supplies, negative pole are connected to second voltage-stabilized power supply.
11. non-volatile memory according to claim 10, it is characterised in that institute
State the first nmos pass transistor, the second nmos pass transistor, the 3rd nmos pass transistor and the 4th
Nmos pass transistor is High voltage NMOS transistor.
12. the non-volatile memory according to any one of claim 7 to 11, its
It is characterised by, in read mode, the electricity of first voltage-stabilized power supply and second voltage-stabilized power supply
Pressure value is 1.0V~1.5V, under other patterns, and the magnitude of voltage of first voltage-stabilized power supply is less than
The magnitude of voltage of second voltage-stabilized power supply, first input signal output 2.8V~3.5V high level and
The low level of ground voltage value.
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