CN107102588A - Solar array simulator controls the realization method and system of outer shroud - Google Patents
Solar array simulator controls the realization method and system of outer shroud Download PDFInfo
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Abstract
The present invention discloses the realization method and system that a kind of solar array simulator controls outer shroud, based on UI tables of data and RI tables of data generation UI RI blended data tables；The sampled voltage of solar array simulator output end is obtained, UI RI blended data tables are searched according to sampled voltage, the expectation electric current of correspondence operating point on the I V curves of solar array simulator setting is obtained.The method that the present invention is tabled look-up using UI RI mixing, be conducive to operating points of the SAS on the I V curves that whole piece is set, the linearity controlled power current is more excellent, and stable output can be kept in any operating point and the fill factor, curve factor sizes of set I V curves is not only restricted to.Under the working condition that SAS load operation points fast step switches, the target operation points of switching can be quickly converged on, SAS dynamic response performance is greatly improved, high dynamic response can be tested more reliably spacecraft power supply system.
Description
Technical field
The realization of outer shroud is controlled the present invention relates to power supply test technical field, more particularly to a kind of solar array simulator
Method and system.
Background technology
I-V voltage and current signals generation technique can be simulation or numeral.Solar energy battle array based on analog circuit
Row simulator (Solar Array Simulator, SAS) circuit is simple, and cost is relatively low.The simulator of the type has two controls
Loop：
1) inner ring electric current loop；
2) outer shroud reference rings.
Wherein, inner ring electric current loop is mainly the output current value of control PV sources simulator, is given based on analog hardware I-V benchmark
Fixed solar array simulator typically can be using three kinds of simulation reference circuits：
1) Current Voltage datum curve is produced using the small PV units battle array with light source；
2) Current Voltage datum curve is produced using the photoelectric tube with light emitting diode；
3) Current Voltage datum curve is generated using the diode model of the PV units battle array in belt current source.
First way belongs to real-time on-line simulation, therefore compared to other several precision for simulating benchmark producing methods more
It is high.Second analog current voltage reference be given, and occurring mode is controllable makes, and more flexibly, can effectively simulate under obstruction conditions
Current and voltage signals curve.A kind of last reference signal producing method implementation is simple, the electric current to constant current source here
Size can illumination simulation intensity size.
Except producing Current Voltage datum curve using analog hardware, it would however also be possible to employ digital mode produces corresponding base
Directrix curve.The power curve that PV sources simulator based on digital given unit voltage x current working standard is produced can more flexibly, more
Plus it is reliable and stronger to the antijamming capability of the noise of high frequency.But digital delay may influence the characteristic of control loop
And design.
In order to meet actual PV sources output characteristics, it is necessary to using two control rings in the simulator of digital PV sources.Based on number
The PV sources simulator of word produces voltage x current benchmark Setting signal using two ways：
1) first way is in advance to deposit the current and voltage data surveyed under varying environment condition and loading condition
Storage is got up.The points of storage are more, and the resolution ratio and precision of power adjustment are higher.
2) second way is calculated using the mathematical simulation of PV arrays, and the data signal that needs are told
Processor (DSP) calculates come the diode index and logarithmic model loaded.The general of most common of which has two kinds of models：Too
The parameter model of positive energy battery；Solar cell interpolation model.It is generally rear known to the parameter of PV units (to come from PV mono-
The databook of member) it just can use parameter model；And interpolation model then only needs to know open-circuit voltage, short circuit current flow, maximum work
The voltage and current value at rate point (MPP) place.
Two kinds of implementations that implementation above solar array simulator I-V controls outer shroud are summarized, based on analog circuit
Solar array simulator circuit is simple, and cost is relatively low, real-time on-line simulation can be achieved, and effectively can simulate under obstruction conditions
Current and voltage signals curve, but flexibility is poor, can not realize the simulation output of some specific I-V curves.Based on numeral
The power curve that the SAS simulators of given voltage current work benchmark are produced can be more flexibly relatively reliable, and to high frequency
Noise antijamming capability it is stronger.
Sampled voltage control correspondence work is typically realized using the single look-up tables of UI or RI using the SAS of numeric type I-V outer shrouds
Make point electric current current-output type SAS, also can sampled output current control correspondence operating point voltage output type SAS.But
The either output of what type, simple use UI tables or RI look-up tables are constantly present a certain section of song on the I-V curve of setting
Operating point in line scope shows nonlinear characteristic, and uses traditional linear control method to be difficult to realize whole piece I-V curve
The steady operation of operating point.And the speed of response for improving power stage would generally be used by solving the nonlinear problem, or directly
The size of the fill factor, curve factor of I-V setting curves is limited, so as to reduce influence of this nonlinear element to the stability of a system.But
For space flight and military affairs etc. to testing the dynamic response and the higher occasion of power output required precision of power supply, it is necessary to apply too
Positive energy array simulator can simulate the higher I-V curve of fill factor, curve factor, while but also with faster dynamic response characteristic.
The content of the invention
It is a primary object of the present invention to provide a kind of UI-RI mixing with high linearity and high-speed convergence characteristic to table look-up
The solar array simulator of outer shroud digital control method controls the realization method and system of outer shroud, it is ensured that simulator is complete
Scope operating point all possesses good and stable electric current output, and solution causes output current to shake due to the non-linear of I-V curve
Problem is swung, the size of the fill factor, curve factor of set I-V curve is not limited by.
In order to achieve the above object, the present invention proposes that a kind of solar array simulator controls the implementation method of outer shroud, bag
Include following steps：
Parameter preset is obtained, based on the parameter preset, is calculated by preset formula using dichotomy and respectively and obtains UI
Tables of data and RI tables of data, based on the UI tables of data and RI tables of data generation UI-RI blended data tables；
The sampled voltage of the solar array simulator output end is obtained, the UI- is searched according to the sampled voltage
RI blended data tables, obtain the expectation electric current of correspondence operating point on the I-V curve of the solar array simulator setting.
Wherein, the acquisition parameter preset, based on the parameter preset, is counted respectively using dichotomy and by preset formula
Calculation obtains UI tables of data and RI tables of data, the step of generating UI-RI blended data tables based on the UI tables of data and RI tables of data
Including：
Obtain the open-circuit voltage U of the I-V curve of the solar array simulator settingoc, short circuit current flow Isc, maximum work
The voltage U of rate pointmpWith electric current ImpFour parameters；
The open-circuit voltage U of the I-V curve set based on the solar array simulatoroc, short circuit current flow Isc, maximum work
The voltage U of rate pointmpWith electric current ImpFour parameters, using exponential model equation of the dichotomy by solar array panel, with etc.
The mode of voltage spaces, which is calculated, to be obtained obtaining UI tables of data；
The open-circuit voltage U of the I-V curve set based on the solar array simulatoroc, short circuit current flow Isc, maximum work
The voltage U of rate pointmpWith electric current ImpFour parameters, using exponential model equation of the dichotomy by solar array panel, with etc.
The mode of resistance interval, which is calculated, to be obtained obtaining RI tables of data；
The obtained UI tables of data will be calculated and RI tables of data merges as UI-RI blended data tables.
Wherein, the obtained UI tables of data and the merging of RI tables of data of calculating turns into UI-RI blended data tables
Step includes：
Generation is combined by distributing corresponding table data address position by the UI tables of data and RI tables of data mixed
Look-up table is closed, wherein, from 0 to [(Ntable/ 2) -1] address location is UI data form contents, from (Ntable/ 2) arrive Ntable's
Address location is RI data form contents, NtableIt is the total data points of UI-RI blended data tables.
Wherein, the sampled voltage for obtaining the solar array simulator output end, is looked into according to the sampled voltage
The UI-RI blended datas table is looked for, the expectation of correspondence operating point on the I-V curve of the solar array simulator setting is obtained
The step of electric current, includes：
Obtain the sampled voltage of the solar array simulator output end；
Judge whether the sampled voltage is more than or equal to preset voltage value；
If the sampled voltage is less than preset voltage value, the corresponding address of UI tables of data is calculated, according to UI tables of data pair
The corresponding total table address of synthesis of address computation answered；
The total table address of synthesis obtained according to calculating, searches the UI-RI blended datas table, obtains the solar array
The expectation electric current of correspondence operating point on the I-V curve of simulator setting.
Wherein, it is described judge the sampled voltage whether be more than or equal to preset voltage value the step of after, in addition to：
If the sampled voltage is more than or equal to preset voltage value, the sampling period for calculating the sampled voltage is corresponding
Equivalent resistance；
Judge whether the equivalent resistance is more than or equal to preset limit value；
If equivalent resistance is less than preset limit value, the corresponding address of RI tables of data is calculated, according to RI tables of data correspondence
The total table address of the corresponding synthesis of address computation.
Wherein, it is described to judge also to include after the step of whether equivalent resistance is more than or equal to preset limit value：
If the equivalent resistance is more than or equal to preset limit value, the equivalent resistance is limited as the default pole
Limit value, the corresponding total table address of synthesis is calculated with this.
Wherein, it is described that the UI-RI blended datas table is searched according to the sampled voltage, obtain the solar array mould
The expectation electric current for intending correspondence operating point on the I-V curve of device setting is handled in FPGA digitial controllers.
The present invention also proposes that a kind of solar array simulator control outer shroud realizes system, including：Many level bus tracking
Power converter cells, linear power level unit and FPGA digitial controllers, wherein：Many level bus tracking converter lists
Member, linear power level unit and FPGA digitial controllers are all connected to the tested power supply of solar array simulator output end and set
It is standby；
Many level bus tracking converters, the sampled voltage for receiving the solar array simulator output end
Signal, produces corresponding switching control instruction according to the sampled voltage signal, obtains corresponding bus level voltage；
The FPGA digitial controllers, the sampled voltage signal for receiving the solar array simulator output end,
The UI-RI blended data tables that previously generate are searched according to the sampled voltage signal, output is with reference to control voltage to described linear
Power stage unit；
The linear power level unit, sets for exporting the solar array simulator according to the reference control voltage
The expectation electric current of correspondence operating point on fixed I-V curve.
Wherein, many level bus tracking converters include：Comparator, isolation drive unit, bus level voltage are carried
For unit, wherein：
The input connection solar array simulator output end of the comparator is tested power-supply device, output end connection institute
State the input of isolation drive unit；The output end of the isolation drive unit connects the bus level voltage and provides unit
Input, the output end that the bus level voltage provides unit externally exports bus level voltage.
Wherein, the FPGA digitial controllers include：High-speed AD digital sampling circuitry, digital logic processing circuit, UI-RI
Blended data list processing circuit, high-speed digital-analog conversion DAC；Wherein：
The input connection solar array simulator output end of the high-speed AD digital sampling circuitry is tested power-supply device,
Output end connects the input of the digital logic processing circuit；The output end connection UI-RI of the digital logic processing circuit
The input of blended data list processing circuit, the output end of the UI-RI blended datas list processing circuit connects the high speed number
Mould changes DAC input, and the output end of the high-speed digital-analog conversion DAC connects the input of the linear power level unit.
The present invention is the optimization based on numerically controlled solar array simulator implementation, proposes to mix using UI-RI
Close the method tabled look-up, be conducive to operating points of the SAS on the I-V curve that whole piece set, to the linearity of power current control compared with
It is excellent, stable output can be kept in any operating point and the fill factor, curve factor size of set I-V curve is not only restricted to.Only simultaneously
Need sampled output voltage, the constant control method of the single inner ring electric current loop of control output end electric current is mixed using UI-RI
The method tabled look-up can quickly converge on the target work of switching under the working condition that SAS load operation points fast step switches
Make a little, SAS dynamic response performance can be greatly improved, high dynamic response can be surveyed more reliably to spacecraft power supply system
Examination.Therefore, SAS current control can ensure simulator in gamut operating point in the raising of the linearity of whole piece I-V curve
All possess good and stable electric current output, solve the problems, such as to cause output current oscillations due to the non-linear of I-V curve, from
Without the size for the fill factor, curve factor for being limited to set I-V curve.
Brief description of the drawings
Fig. 1 is the schematic flow sheet of the implementation method of solar array simulator control outer shroud of the present invention；
Fig. 2 is the nonlinear problem schematic diagram for the current control brought using single UI tables or single RI tables；
Fig. 3 a, Fig. 3 b and Fig. 3 c be using single UI look-up tables for the convergence of object run point there are conditional convergence with
And convergence rate it is slow the problem of schematic diagram；
Fig. 4 a, Fig. 4 b are the convergence process schematic diagrames for being switched to point B from point A using RI LUT Methods；
Fig. 5 is the functional flow diagram for generating UI-RI blended data tables；
Fig. 6 is the program function flow chart using UI-RI mixture tables；
Fig. 7 is SAS system block diagram of the present invention.
In order that technical scheme is clearer, clear, it is described in further detail below in conjunction with accompanying drawing.
Embodiment
It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, it is not intended to limit the present invention.
Present invention can apply to the power supply test occasion of space power system test system or high dynamic characteristic it is digital too
Positive energy array simulator occasion, is also applied for the simulator application scenario of industry and civil area.The invention is based on numeral
The optimization of the sun battle array simulator implementation of control, is proposed to be mixed the method tabled look-up using UI-RI, is conducive to SAS in whole piece
Operating point on the I-V curve of setting, the linearity controlled power current is more excellent, and stabilization can be kept in any operating point
Export and be not only restricted to the fill factor, curve factor size of set I-V curve.Only need to sampled output voltage, control output end simultaneously
The constant control method of the single inner ring electric current loop of electric current, the method tabled look-up is mixed using UI-RI quick in SAS load operation points
Under the working condition of step switching, the target operation points of switching can be quickly converged on, SAS dynamic response can be greatly improved
Can, high dynamic response can be tested more reliably spacecraft power supply system.
The invention mainly relates to the generation and application of UI-RI blended data tables.
Specifically, reference picture 1, Fig. 1 is the implementation method embodiment that solar array simulator of the present invention controls outer shroud
Schematic flow sheet.
As shown in figure 1, present pre-ferred embodiments propose that a kind of solar array simulator controls the implementation method of outer shroud,
This method includes：
Step S101, is obtained parameter preset, based on the parameter preset, is counted respectively using dichotomy and by preset formula
Calculation obtains UI tables of data and RI tables of data, based on the UI tables of data and RI tables of data generation UI-RI blended data tables；
First, the open-circuit voltage U of the I-V curve of the solar array simulator setting is obtainedoc, short circuit current flow Isc, most
The voltage U of high-power pointmpWith electric current ImpFour parameters；
The open-circuit voltage U of the I-V curve set based on the solar array simulatoroc, short circuit current flow Isc, maximum work
The voltage U of rate pointmpWith electric current ImpFour parameters, using exponential model equation of the dichotomy by solar array panel, with etc.
The mode of voltage spaces, which is calculated, to be obtained obtaining UI tables of data；
The open-circuit voltage U of the I-V curve set based on the solar array simulatoroc, short circuit current flow Isc, maximum work
The voltage U of rate pointmpWith electric current ImpFour parameters, using exponential model equation of the dichotomy by solar array panel, with etc.
The mode of resistance interval, which is calculated, to be obtained obtaining RI tables of data；
The obtained UI tables of data will be calculated and RI tables of data merges as UI-RI blended data tables.
Wherein, the obtained UI tables of data will be calculated and RI tables of data merges the step of turning into UI-RI blended data tables
Including：
Generation is combined by distributing corresponding table data address position by the UI tables of data and RI tables of data mixed
Look-up table is closed, wherein, from 0 to [(Ntable/ 2) -1] address location is UI data form contents, from (Ntable/ 2) arrive Ntable's
Address location is RI data form contents, NtableIt is the address location sum of UI-RI blended data tables.
Step S102, obtains the sampled voltage of the solar array simulator output end, is looked into according to the sampled voltage
The UI-RI blended datas table is looked for, the expectation of correspondence operating point on the I-V curve of the solar array simulator setting is obtained
Electric current.
Specifically, first, the sampled voltage of the solar array simulator output end is obtained；
Then, judge whether the sampled voltage is more than or equal to preset voltage value；If the sampled voltage is less than default
Magnitude of voltage, then calculate the corresponding address of UI tables of data, according to the corresponding total table address of synthesis of the corresponding address computation of UI tables of data.
If the sampled voltage is more than or equal to preset voltage value, the sampling period for calculating the sampled voltage is corresponding
Equivalent resistance；
Judge whether the equivalent resistance is more than or equal to preset limit value；
If equivalent resistance is less than preset limit value, the corresponding address of RI tables of data is calculated, according to RI tables of data correspondence
The total table address of the corresponding synthesis of address computation.
If the equivalent resistance is more than or equal to preset limit value, the equivalent resistance is limited as the default pole
Limit value, the corresponding total table address of synthesis is calculated with this.
Finally, the total table address of synthesis obtained according to calculating, searches the UI-RI blended datas table, obtains the sun
The expectation electric current of correspondence operating point on the I-V curve of energy array simulator setting.
It is described that the UI-RI blended datas table is searched according to the sampled voltage in the present embodiment, obtain the solar energy
The expectation electric current of correspondence operating point is handled in FPGA digitial controllers on the I-V curve of array simulator setting.
Optimization of the invention based on numerically controlled solar array simulator implementation, is tabled look-up using UI-RI mixing
Method, be conducive to operating points of the SAS on the I-V curve that whole piece is set, the linearity controlled power current is more excellent, can be
Any operating point keeps stable output and is not only restricted to the fill factor, curve factor size of set I-V curve.Only need to adopt simultaneously
Sample output end voltage, the constant control method of the single inner ring electric current loop of control output end electric current, mixes what is tabled look-up using UI-RI
Method can quickly converge on the target operation points of switching under the working condition that SAS load operation points fast step switches, can
SAS dynamic response performance is greatly improved, high dynamic response can be tested more reliably spacecraft power supply system.Therefore,
SAS current control can ensure that simulator all possesses good in gamut operating point in the raising of the linearity of whole piece I-V curve
Good and stable electric current output, solves the problems, such as to cause output current oscillations due to the non-linear of I-V curve, so that will not be by
It is limited to the size of the fill factor, curve factor of set I-V curve.
This embodiment scheme is described in detail below：
Present invention can apply to space power system test system or high dynamic characteristic power supply test occasion it is digital
Solar array simulator occasion, is also applied for local authorities' simulator application scenario of industry and civil area.
The present invention proposes a kind of new of the solar array simulator of the I-V lookup table modes based on digitial controller
UI-RI mixing form look-up tables.Required I-V working curves can be divided into two workspaces, i.e. constant current area and areas of permanent pressure, using list
Individual the problems of (single UI tables or single RI tables) method of tabling look-up is mainly manifested in two aspects：
First problem be under steady-state working condition, it is unstable caused by different nonlinear operation regions to ask
Topic, i.e., setting I-V curve nonlinear operation area operating point steady oscillation problem；
Another problem is the operating point switching in two different zones, and single having ready conditions for UI tables converges on target operation
The problem of point and convergence rate are slow.
Using single UI tables or single RI tables, in set I-V curve, there is voltage x current in corresponding specific region
The nonlinear problem of relation, as shown in Figure 2.
Operating point MPP is the maximum power point (U of set I-V curvemp, Imp)；Two on the left of MPP points are not
With the A of operating pointML(UAL, IAL), BML(UBL, IBL) it is located at constant current zone position；Two other different operating point AMR(UAR, IAR),
BMR(UBR, IBR) on the right side of MPP points, in constant pressure zone position.Solar array simulator (SAS) is operated in point AML, stable state moves
Move on to operating point BML, the voltage difference between two operating points is Δ UML；Difference between current is Δ IML.The work tabled look-up from SAS numeral
Principle analysis, the larger voltage difference in the region can only cause very small curent change, illustrate that outer shroud I-V control loops have
There is the preferably control linearity, outputting current steadily is high.However, because set I-V curve has close to areas of permanent pressure
The poor linearity, so operating point AMRAnd BMRBetween very small voltage change Δ UMRIt is interior to cause electric current in a big way
Quick changes delta IMR.Similarly, it can also draw opposite conclusion, i.e. RI tables at point A from single RI tablesMLAnd BMLBetween
The control poor linearity of electric current and in point AMRAnd BMRBetween the control of electric current there is the more preferable linearity.So SAS I-
V outer shrouds numeral look-up method, is difficult to obtain the steady-working state that whole piece sets I-V curve by single form look-up table.
Second Problem is that the convergence using single UI look-up tables for object run point there are conditional convergence and receipts
Slow-footed problem is held back, as shown in Fig. 3 a, Fig. 3 b, Fig. 3 c, wherein, Fig. 3 a are Fig. 3 b under the conditions of pressing close between switch operating point
It is that the critical condition of convergence is between switch operating point, Fig. 3 c are in dissipating not convergent condition between switch operating point.
Fig. 3 a give two step pressed close to switch operating point A (UA, IA) and B (UB, IB).FPGA digitial controllers are first
First pass through output end voltage U of the high-speed ADC to SASsasSampled, and the moment will not update DAC outputs UIref, until
Whole numeral look-up routine is completed.This means during this, current status keep constant；Operating point A is changed into P1 (UP1, IP1)
And UP1<Uoc, relational expression can be obtained as follows：
The output end voltage U that ADC can samplesasFor UP1, the relevant work point on I-V curve is P2(UP2, IP2)。SAS
Output current is changed into as IP2, but corresponding P3Still it is not target operation points：
ADC sampled output voltages UP3, the relevant work point on I-V curve is P4(UP4, IP4).Source current is changed into IP4,
It is P to reach operating point5(UP5, IP5)：
Logic is restrained according to identical, operating point reaches P6(UP6, IP6), P7(UP7, IP7), eventually converge to target work
Make point B (UB, IB).Such convergence process is periodic cycle convergence process, illustrates repeatedly look into using UI loop up table
Target operation points can just be converged to after the cycle by tabling look-up.
However, can also have not convergent situation there is also operating point switching, as shown in Fig. 3 b and Fig. 3 c.Fig. 3 b represent to work as
Point P3(UP3, IP3) corresponding output current value of tabling look-up it is consistent with A when, target switch operating point is in critical convergence state.Work as a little
P4(UP4, IP4), IP4Output current value be more than IAWhen, Fig. 3 c represent that operating point switching is in diverging not convergence state.Above-mentioned point
Analysis process shows that belonging in the case where using single UI look-up tables, the working condition that target operation points are quickly switched into operating point has
Conditional convergence and convergence process are periodic cycle convergence process, and convergence rate is slow.
Single UI tables or single RI tables are either used, all there is electric current in the different zones of the I-V curve of setting
The nonlinear problem of control.Although there is the nonlinear problem of current control in single RI tables look-up table, in constant current area in I-V
There is the characteristic of Fast Convergent, as shown in figures 4 a and 4b in the handoff procedure of curve operating point.Fig. 4 a correspond to UI look-up tables
Critical convergence working condition, Fig. 4 b correspond to the diverging working condition of UI look-up tables, and Fig. 4 a are to use RI table look-up tables, from work
Point A (UA, IA) switch to operating point B (UB, IB) convergence process schematic diagram, switching state correspond to Fig. 3 b shown in UI tables look into
The critical convergence working condition of table method；Fig. 4 b are to use RI tables look-up table from operating point A (UA, IA) it is switched to point B (UB, IB)
Convergence process schematic diagram, switching state corresponds to the critical convergence working condition of UI table look-up tables as shown in Figure 3 c.
As shown in Fig. 4 a, present operating point is A (RA), load is quickly switched into operating point B (RB), FPGA is maintained at DAC
UIref(k-1), k is currently tables look-up the cycle, and corresponding power current is Isas(k-1).FPGA uses Isas(k-1) equivalent negative is calculated
Carry resistance RP1_equ_load(k), Isas(k-1) be upper one table look-up the cycle acquisition I-V curve on storage operating point.
The equivalent load resistance R of current periodP1_equ_load(k)：
By searching corresponding RI tables, obtaining the cycle tables look-up the expectation electric current value I of outputsas(k)：
Isas(k)=TableRI(RP1_equ_load(k))=f (RB) (6)
The convergence process only only needs to one and tabled look-up the cycle, so that it may so that working condition rapidly converges to target operation points
B, fast convergence rate.
Fig. 4 b correspond to the diverging working condition of UI look-up tables, and the operating point of migration path is P1(UP1, IP1), UP1It is more than
Uoc.Generally, ADP sampling and outputting voltages digital quantity can carry out amplitude limit by FPGA programs, and the operating point of migration path is limited
It is made as P2(UP2, IP2) have：
The equivalent load resistance R in the cycle that tables look-upP2_equ_load(k)：
Isas(k)=TableRI(RP2_equ_load(k))=f (RC) (9)
Obviously, RCIt is not target operation points, work stable state will not be entered；Convergence process will enter next cycle shape of tabling look-up
State, has：
The equivalent load resistance that next cycle is calculated is RP4_equ_load(k+1), target current value Isas(k+1) it is：
Isas(k+1)=TableRI(RP4_equ_load(k+1))=f (RB) (12)
Under the switching working condition, only needing to two cycles of tabling look-up using RI table look-up tables just can quickly converge on target
Operating point B.
Derived and analyzed by above-mentioned theory, using UI-RI mixing look-up tables, can not only improve set I-V bent
The full operating point range of line all has the good current control linearity, has more preferable electric current stable under steady state operating conditions
Property；And it can quickly converge to target operation points under the working condition of the high speed switching between operating point.
Shown in the exponential model of solar array panel such as formula (13) to (16), the equation can be used for calculating UI tables of data.
The parameter R of equation descriptions, NconstWith α solar array simulator exponential model parameter, known open-circuit voltage U is neededocAnd short circuit
Electric current IscAnd maximum power point voltage UmpWith maximum power point electric current ImpFour parameters.
For SAS, the relation between output voltage and electric current is located on given I-V curve, therefore every on I-V curve
One operating point is to correspond to an equivalent load resistance Requ_load：
It is as follows that equivalent output load resistance formula can be obtained from aforementioned four exponential model equation：
Pass through known open-circuit voltage Uoc, short circuit current flow Isc, the voltage and current U of maximum power pointmp, ImpFour parameters；
Use dichotomy equation (13) to (16) with etc. obtain UI data forms by way of voltage spaces.Similarly use dichotomy
Equation (13) to (15) and formula (18) with etc. obtain RI data forms by way of resistance interval.
The generation and application of UI-RI mixture tables are broadly divided into two steps, i.e., in computer and FPGA digitial controllers
The function of completion.The first step is how to generate UI-RI blended data tables, and the functional flow diagram of UI-RI blended datas table generation is such as
Shown in Fig. 5.
UI-RI mixture tables are main synthesis tables, and the total data points of form are Ntable.In the main table of the synthesis, list data
First half be UI tables of data, its function course is input voltage information to obtain expectation electric current value；List data it is another
It is partly RI tables of data, its function course is input equivalent resistance information to obtain expectation electric current value.Calculate the four of UI table data points
Individual formula is formula (13) to (16), UsasAnd IsasBetween relation it is as follows：
It is calculated as follows etc. voltage spaces Δ U：
Δ U=Ump/[(Ntable/2)-1] (20)
It is calculated as follows Deng resistance separation delta R：
Δ R=Rlimit_load/[(Ntable/2)-1] (21)
When SAS output current very littles, Rlimit_loadIt is that maximum equivalent output under equivalent open-circuit voltage condition of work is negative
Carry resistance.UI and RI sublists are obtained by calculating respectively, and synthesis table is will by the corresponding table data address position of reasonable distribution
The hybrid lookup table of two sub- table packs together.From 0 to [(Ntable/ 2) -1] address location is UI data form contents, from
(Ntable/ 2) arrive NtableAddress location be RI data form contents.
Second step is that the address corresponding to UI-RI mixing forms, PFGA how are accurately calculated under given sampled voltage
Digitial controller finds and provides corresponding expectation electric current command value, shown in its program function flow chart 6.
Can accurately it be calculated by two above-mentioned functional flow diagrams and using required UI-RI blended data tables, FPGA
With minimum digital delay, the corresponding expectation electric current instruction of present operating point can be calculated and provided.Look-up table output is being set
All with stable operation characteristic in the full operating point range of fixed I-V curve, and be switched fast in different operating points
Target point operating point can be quickly converged under working condition.
In addition, the present invention also proposes that a kind of solar array simulator control outer shroud realizes system, as shown in fig. 7, conduct
The SAS plateform system block diagrams that UI-RI blended data tables are applied, including：Many level bus tracking power converter cells, linear work(
Rate level unit and FPGA digitial controllers, wherein：The many level buses tracking power converter cells, linear power level unit with
And FPGA digitial controllers are all connected to solar array simulator output end and are tested power-supply device；
Many level bus tracking converters, the sampled voltage for receiving the solar array simulator output end
Signal, produces corresponding switching control instruction according to the sampled voltage signal, obtains corresponding bus level voltage；
The FPGA digitial controllers, the sampled voltage signal for receiving the solar array simulator output end,
The UI-RI blended data tables that previously generate are searched according to the sampled voltage signal, output is with reference to control voltage to described linear
Power stage unit；
The linear power level unit, sets for exporting the solar array simulator according to the reference control voltage
The expectation electric current of correspondence operating point on fixed I-V curve.
Many level bus tracking converters include：Comparator, isolation drive unit, bus level voltage provide single
Member, wherein：
The input connection solar array simulator output end of the comparator is tested power-supply device, output end connection institute
State the input of isolation drive unit；The output end of the isolation drive unit connects the bus level voltage and provides unit
Input, the output end that the bus level voltage provides unit externally exports bus level voltage.
The FPGA digitial controllers include：High-speed AD digital sampling circuitry, digital logic processing circuit, UI-RI mixing
Tables of data process circuit, high-speed digital-analog conversion DAC；Wherein：
The input connection solar array simulator output end of the high-speed AD digital sampling circuitry is tested power-supply device,
Output end connects the input of the digital logic processing circuit；The output end connection UI-RI of the digital logic processing circuit
The input of blended data list processing circuit, the output end of the UI-RI blended datas list processing circuit connects the high speed number
Mould changes DAC input, and the output end of the high-speed digital-analog conversion DAC connects the input of the linear power level unit.
The system of the sun battle array simulator platform of the high-power high dynamic response demand of present invention application detailed below is former
Reason.
Specifically, the sun battle array simulator platform of the high-power high dynamic response demand of present invention application, be particularly suitable for use in sky
Between power detecting system space sun battle array simulator application scenario.Specific SAS system block diagram is as shown in Figure 7.It is wrapped
Include three parts：Many level buses track power converter cells, linear power level unit and scene FPGA digitial controllers, are connected to
SAS output ends are tested power-supply device, i.e. equivalent load ZLIt is unknown.
SAS output voltages are converted to low-voltage sampled signal U by output voltage sampling circuitsas_sa, give many level female
Line tracks power converter cells and FPGA digitial controllers.Many level buses track converter based on given Usas_saSignal is produced
Raw corresponding switching control instruction, so as to set up appropriate bus level voltage.
Reference control voltage U needed for FPGA digitial controller output linearity voltage-controlled current sources (VCCS)Iref, to control
SAS exports desired power current, completes some operating point in the I-V power curve of setting.Generally, current mode
The SAS of output only by sampled output voltage, passes through the expectation of the corresponding operating point on the I-V curve for obtaining setting of tabling look-up
Electric current, the look-up method used is single UI table look-up table.However, UI look-up tables have the Non-Linear Ocsillation of controlled electric current
Problem, the present invention is proposed using UI-RI method for mixed loop-up table, in the left side of the maximum power point of the I-V curve of setting, is used
UI subdatasheets, have more preferable linear characteristic, SAS output steady operation electric currents using the interval UI tables.Similarly, in setting
The right side of the maximum power point of I-V curve, using the RI subdatasheets with the more preferable linearity and Fast Convergent characteristic, wherein
Table content UIrefBy being stored in advance in the RAM of digitial controller.
Compared with prior art, the present invention based on digital I-V table look-up control and current-output type solar array simulation
The application scenario of device, proposes new UI-RI mixing look-up tables, it is only necessary to single sampling simulator output end voltage, control
The output current of simulator correspondence operating point, and keep this single current inner loop control mode constant, just it can realize
All working point on the I-V curve of setting, current control all has the good linearity；And it is switched fast work in operating point
Under the conditions of condition, target can be rapidly converged to and expected on operating point.The linearity of the SAS current control in whole piece I-V curve
Improving can ensure that simulator all possesses good and stable electric current output in gamut operating point, solve due to I-V curve
It is non-linear and cause output current oscillations problem, so as to be not limited by the size of the fill factor, curve factor of set I-V curve.
Operating point on I-V curve is under the working condition being switched fast, using UI-RI look-up tables, and simulator can be caused with most fast
Speed convergence greatly improves the complete machine dynamic response performance of sun battle array simulator to the desired operating point of target.
The preferred embodiments of the present invention are the foregoing is only, are not intended to limit the scope of the invention, it is every to utilize
Equivalent structure or the flow conversion that description of the invention and accompanying drawing content are made, or directly or indirectly it is used in other related skills
Art field, is included within the scope of the present invention.
Claims (10)
1. a kind of solar array simulator controls the implementation method of outer shroud, it is characterised in that comprise the following steps：
Parameter preset is obtained, based on the parameter preset, is respectively calculated using dichotomy and by preset formula and obtains UI data
Table and RI tables of data, based on the UI tables of data and RI tables of data generation UI-RI blended data tables；
The sampled voltage of the solar array simulator output end is obtained, the UI-RI is searched according to the sampled voltage and mixed
Tables of data is closed, the expectation electric current of correspondence operating point on the I-V curve of the solar array simulator setting is obtained.
2. solar array simulator according to claim 1 controls the implementation method of outer shroud, it is characterised in that described to obtain
Parameter preset is taken, based on the parameter preset, is respectively calculated using dichotomy and by preset formula and obtains UI tables of data and RI
Tables of data, the step of generating UI-RI blended data tables based on the UI tables of data and RI tables of data includes：
Obtain the open-circuit voltage U of the I-V curve of the solar array simulator settingoc, short circuit current flow Isc, maximum power point
Voltage UmpWith electric current ImpFour parameters；
The open-circuit voltage U of the I-V curve set based on the solar array simulatoroc, short circuit current flow Isc, maximum power point
Voltage UmpWith electric current ImpFour parameters, using exponential model equation of the dichotomy by solar array panel, between grade voltage
Every mode calculate obtain obtain UI tables of data；
The open-circuit voltage U of the I-V curve set based on the solar array simulatoroc, short circuit current flow Isc, maximum power point
Voltage UmpWith electric current ImpFour parameters, using exponential model equation of the dichotomy by solar array panel, between grade resistance
Every mode calculate obtain obtain RI tables of data；
The obtained UI tables of data will be calculated and RI tables of data merges as UI-RI blended data tables.
3. solar array simulator according to claim 2 controls the implementation method of outer shroud, it is characterised in that described to incite somebody to action
Calculate the obtained UI tables of data and RI tables of data merges the step of turning into UI-RI blended data tables and included：
By distribute corresponding table data address position by the UI tables of data and RI tables of data combine generation mixing look into
Table is looked for, wherein, from 0 to [(Ntable/ 2) -1] address location is UI data form contents, from (Ntable/ 2) arrive NtableAddress
Position is RI data form contents, NtableIt is the total data points of UI-RI blended data tables.
4. the solar array simulator according to claim 1,2 or 3 controls the implementation method of outer shroud, it is characterised in that
The sampled voltage for obtaining the solar array simulator output end, searches the UI-RI according to the sampled voltage and mixes
Tables of data is closed, the step of obtaining the expectation electric current of correspondence operating point on the I-V curve of the solar array simulator setting is wrapped
Include：
Obtain the sampled voltage of the solar array simulator output end；
Judge whether the sampled voltage is more than or equal to preset voltage value；
If the sampled voltage is less than preset voltage value, the corresponding address of UI tables of data is calculated, it is corresponding according to UI tables of data
The corresponding total table address of synthesis of address computation；
The total table address of synthesis obtained according to calculating, searches the UI-RI blended datas table, obtains the solar array simulation
The expectation electric current of correspondence operating point on the I-V curve of device setting.
5. solar array simulator according to claim 4 controls the implementation method of outer shroud, it is characterised in that described to sentence
After the step of whether sampled voltage that breaks is more than or equal to preset voltage value, in addition to：
If the sampled voltage is more than or equal to preset voltage value, the sampling period for calculating the sampled voltage is corresponding equivalent
Resistance value；
Judge whether the equivalent resistance is more than or equal to preset limit value；
If equivalent resistance is less than preset limit value, the corresponding address of RI tables of data is calculated, according to RI tables of data correspondingly
Location calculates the corresponding total table address of synthesis.
6. solar array simulator according to claim 5 controls the implementation method of outer shroud, it is characterised in that described to sentence
Also include after the step of whether equivalent resistance that breaks is more than or equal to preset limit value：
If the equivalent resistance is more than or equal to preset limit value, the equivalent resistance is limited as the predetermined limit
Value, the corresponding total table address of synthesis is calculated with this.
7. the solar array simulator according to claim 1,2 or 3 controls the implementation method of outer shroud, it is characterised in that
It is described that the UI-RI blended datas table is searched according to the sampled voltage, obtain the I-V of the solar array simulator setting
The expectation electric current of correspondence operating point is handled in FPGA digitial controllers on curve.
8. a kind of solar array simulator control outer shroud realizes system, it is characterised in that including：Many level bus tracking conversion
Device unit, linear power level unit and FPGA digitial controllers, wherein：Many level bus tracking power converter cells, line
Property power stage unit and FPGA digitial controllers be all connected to solar array simulator output end be tested power-supply device；
Many level bus tracking converters, the sampled voltage for receiving the solar array simulator output end is believed
Number, corresponding switching control instruction is produced according to the sampled voltage signal, corresponding bus level voltage is obtained；
The FPGA digitial controllers, the sampled voltage signal for receiving the solar array simulator output end, according to
The sampled voltage signal searches the UI-RI blended data tables previously generated, and output is with reference to control voltage to the linear power
Level unit；
The linear power level unit, for exporting what the solar array simulator was set according to the reference control voltage
The expectation electric current of correspondence operating point on I-V curve.
9. solar array simulator control outer shroud according to claim 8 realizes system, it is characterised in that described more electric
Flat bus tracking converter includes：Comparator, isolation drive unit, bus level voltage provide unit, wherein：
The input connection solar array simulator output end of the comparator is tested power-supply device, output end connection it is described every
From the input of driver element；The output end of the isolation drive unit connects the input that the bus level voltage provides unit
End, the output end that the bus level voltage provides unit externally exports bus level voltage.
10. solar array simulator control outer shroud according to claim 8 realizes system, it is characterised in that
The FPGA digitial controllers include：High-speed AD digital sampling circuitry, digital logic processing circuit, UI-RI blended datas
List processing circuit, high-speed digital-analog conversion DAC；Wherein：
The input connection solar array simulator output end of the high-speed AD digital sampling circuitry is tested power-supply device, output
The input of the end connection digital logic processing circuit；The output end connection UI-RI mixing of the digital logic processing circuit
The input of tables of data process circuit, the output end of the UI-RI blended datas list processing circuit connects the high-speed digital-analog and turned
DAC input is changed, the output end of the high-speed digital-analog conversion DAC connects the input of the linear power level unit.
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