CN107092440A - A kind of IRIG106 high-speed data processing systems based on FPGA - Google Patents
A kind of IRIG106 high-speed data processing systems based on FPGA Download PDFInfo
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- CN107092440A CN107092440A CN201710176256.1A CN201710176256A CN107092440A CN 107092440 A CN107092440 A CN 107092440A CN 201710176256 A CN201710176256 A CN 201710176256A CN 107092440 A CN107092440 A CN 107092440A
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0658—Controller construction arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0674—Disk device
- G06F3/0676—Magnetic disk device
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
Abstract
The invention discloses a kind of IRIG106 high-speed data processing systems based on FPGA, it is realized using FPGA, including multi pass acquisition module, IRIG106 package modules and storage control module;Input of the output end of the multi pass acquisition module with IRIG106 package modules is connected, and the output end of the IRIG106 package modules and the input of storage control module are connected, and the storage control module is used to be connected with external storage disk;The multi pass acquisition module, IRIG106 package modules and storage control module are run parallel.The present invention proposes a kind of high speed storing scheme based on FPGA, by directly being operated to storage dish in FPGA indoor designs storage control, the process to data storage is optimized simultaneously, data processing stage and memory phase are separated, make full use of the advantage of FPGA parallel processings, overcome it is existing be based on the embedded slower problem of storage scheme speed, greatly improve the memory rate of data.It the composite can be widely applied to various high-speed memory systems.
Description
Technical field
The present invention relates to field of data storage, more particularly to a kind of high-speed data processing system.
Background technology
FPGA:Field-Programmable Gate Array, field programmable gate array.
IRIG:Measuring instrument group between Inter-Range Instrumentration Group, target range.IRIG106 is that have
The data recording standard that the U.S. target range commandant committee (RCC) formulates, the numeral to a variety of data is realized with more economical method
Change and efficient combination, measuring instrument group IRIG106 (IRIG between current target range:Inter-Range Instrumentration
Group) digital record standard has been increasingly becoming one of internationally recognized standard, is future using based on IRIG106 form storages
The developing direction of airborne testing.
FIFO:First Input First Output abbreviation, First Input First Output.
With advances in technology, airborne testing number demand constantly increases, and information is more more convenient to analyzing and processing afterwards,
The requirement of the increase on-board data record of information content is consequently increased.
In the prior art, write at a slow speed afterwards typically using first write-in high-speed internal memory caching based on instantaneous high-speed record
The mode of memory.But this mode can not meet the demand long lasting for high speed writein.
The content of the invention
In order to solve the above-mentioned technical problem, met it is an object of the invention to provide a kind of long lasting for high speed writein
High-speed memory system.
The technical solution adopted in the present invention is:
A kind of IRIG106 high-speed data processing systems based on FPGA, it is realized using FPGA, including multi pass acquisition mould
Block, IRIG106 package modules and storage control module;The output end of the multi pass acquisition module with IRIG106 package modules
Input connection, the input of the output ends of the IRIG106 package modules and storage control module connects, the storage control
Molding block is used to be connected with external storage disk;The multi pass acquisition module, IRIG106 package modules and storage control module are parallel
Operation.
It is preferred that, the acquisition module includes big FIFO and small FIFO;It is larger that the big FIFO is used for buffer data size
Gathered data, small FIFO is used for the length for storing current gathered data;Acquisition module has stored a data in big FIFO every time
Bag, stores the length of the packet in small FIFO, that is, the packet write is corresponded with data packet length.
It is preferred that, the IRIG106 package modules include multichannel data mixing submodule and data encapsulation submodule, described
The data that multichannel data mixing submodule is used to export multi pass acquisition module carry out data mixing, and the data encapsulate submodule
For being output to storage control module after mixed data are carried out into data encapsulation.
It is preferred that, the data mixing submodule includes mixing FIFO;During work, the data mixing submodule is according to pre-
The length of the acquisition buffer data first set, once reads corresponding data length and corresponding data from multi pass acquisition module
Bag, data pack buffer is read in mixing FIFO so that data encapsulate submodule.
It is preferred that, the total amount of data cached during work in the data mixing submodule record FIFO and last bag
The data volume of data, when total amount of data exceedes setting wrapper size, total amount of data is subtracted the data volume of last bag, shape
Data encapsulation submodule is output into current data group bag.
It is preferred that, the data group encapsulating that the data encapsulation submodule is used to export data mixing submodule is dressed up
IRIG106 wrappers;The IRIG106 wrappers include IRIG106 packets and the IRIG106 times wrap;The IRIG106 numbers
The data group bag collected according to including, the IRIG106 times include the data that time mark is carried out to data group bag.
It is preferred that, the storage control module connects including file management submodule, master controller logic sub-modules and physics
Openning module;The input that the output end of the file management submodule encapsulates submodule with data is connected, the data encapsulation
The output end of submodule is connected with the input of master controller logic sub-modules, the output end of the master controller logic sub-modules
It is connected with the input of physical interface submodule, the physical interface submodule is used to be connected with external storage disk.
It is preferred that, the file management submodule is used to carry out user-defined file management to the IRIG106 wrappers of reception,
The user-defined file management is divided into three levels;First layer is used to be managed data segment, and number is stored in record storage disk
According to the number of section, the second layer is managed to the original position and end position of file index, indicates one piece of data segment index
Starting position and end position, third layer is to the title of file, start recording time, the original position of data storage and stop bits
Put and be managed, storage file title, the time of record and the original position of data when recording beginning are remembered for each second later
Record once current time and current recording position.
It is preferred that, when system exception power down, the stop bits for finding the previous second record of power down is managed by user-defined file
Put, be the data segment for recovering completion by end position information.
It is preferred that, the storage control module is SATA control modules, and the storage dish is SATA hard disc, the SATA controls
Molding block is used to realize SATA II protocol transport layer, link layer and physical layer function, the compatible standards of SATA 3.0.
The beneficial effects of the invention are as follows:
The present invention proposes a kind of high speed storing scheme based on FPGA, by FPGA indoor design storage controls to depositing
Storage disk is directly operated, while the process to data storage is optimized, data processing stage and memory phase is separated, filled
Point using FPGA parallel processings advantage, overcome it is existing be based on the embedded slower problem of storage scheme speed, greatly improve
The memory rate of data.
In addition, the present invention is encapsulated by IRIG106, connect eventually through SATA II also by receiving multichannel Ethernet data
Mouth carries out high speed storing.Digitlization and the efficient combination to a variety of data are realized with more economical method.Acquisition module is based on double
FIFO data Caching Mechanism, the IRIG106 based on FPGA simplifies data framing format, realizes to the quick, reliable of data
Ground processing and storage.Based on customized file management mode, the management is divided into three layers, the number of first layer record data section,
The original position and end position of second layer log file index, the title of third layer record data, the number of the end of each second
According to record position.Farthest prevent loss of data caused by power down or other failures.
It the composite can be widely applied to various high-speed memory systems.
Brief description of the drawings
The embodiment to the present invention is described further below in conjunction with the accompanying drawings:
Fig. 1 is the circuit structure block diagram of an embodiment of the present invention;
Fig. 2 is a kind of logical construction schematic diagram of embodiment of SATA control modules of the present invention.
Embodiment
It should be noted that in the case where not conflicting, the feature in embodiment and embodiment in the application can phase
Mutually combination.
The IRIG106 storage systems based on FPGA of the invention, using the characteristic of FPGA parallel processing, from collection, encapsulation,
Parallel processing is realized in storage, substantially increases memory rate, as shown in Figure 1.
The present embodiment is by taking 4 road acquisition modules as an example, a kind of IRIG106 high-speed data processing systems based on FPGA, its profit
Realized with FPGA, including 4 road acquisition modules, IRIG106 package modules and storage control module;The output end of 4 road acquisition modules
Input with IRIG106 package modules is connected, the output end of IRIG106 package modules and the input of storage control module
Connection, storage control module is used to be connected with external storage disk;4 road acquisition modules, IRIG106 package modules and storage control mould
Block is run parallel.
4 road acquisition modules receive Ethernet Ethernet data, and acquisition module includes big FIFO and small FIFO;Data are adopted
Caching process is carried out to data by double-FIFO structure after collection.Double-FIFO structure is that the combination of small one and large one two kinds of Capacity FIFOs exists
Together, big FIFO is used for the larger gathered data of buffer data size, and small FIFO is then used for the length for storing current gathered data, often
It is secondary that a bag data has been stored in big FIFO, the length of data storage bag in small FIFO, that is, the data write and length are one by one
Correspondence.
In the present embodiment, IRIG106 package modules include 4 circuit-switched datas and mix submodule and data encapsulation submodule, 4 ways
It is used to the data of 4 road acquisition module outputs carrying out data mixing according to mixing submodule, data encapsulation submodule is used for will mixing
Data afterwards are output to storage control module after carrying out data encapsulation.
Data mixing submodule includes mixing FIFO;During work, data mixing submodule is slow according to collection set in advance
The length of data is rushed, corresponding data length and corresponding packet are once read from 4 road acquisition modules, by data pack buffer
So that data encapsulation submodule is read in mixing FIFO.
Data mixing submodule mixes 4 tunnel gathered datas:4 circuit-switched data bags are packaged as a big packet,
Storage is carried out with big data bag and improves writing speed.
Specifically, packet is it is crucial that the length of effective data packets is counted, because the data packet length of receiving is not solid
Fixed, it is impossible to predict the total length of multiple packets, IRIG106 package modules use two stages for the treatment of mode, and the first order is responsible for data
Mix (data mixing submodule), the encapsulation (data encapsulation submodule) of data is responsible in the second level.Data mixing submodule according to
The length of acquisition buffer data, the buffering area (big FIFO and small FIFO) once gathered from 4 tunnels read corresponding data length and
Corresponding data, by data from new reading is buffered in mixing FIFO, while record the data volume cached in mixing FIFO and
The data volume of last bag data bag, when total amount of data exceedes setting wrapper size, last bag is subtracted by total amount of data
Data volume, formed current data group bag be output to data encapsulation submodule.
In the present embodiment, the data group encapsulating that data encapsulation submodule is used to export data mixing submodule is dressed up
IRIG106 wrappers;IRIG106 wrappers include IRIG106 packets and the IRIG106 times wrap;IRIG106 packets contain
The data group bag collected, the IRIG106 times include the data that time mark is carried out to data group bag.
Specifically, IRIG106 storage formats are close, it is necessary to be grasped repeatedly to storage dish with storage dish Relationship Comparison in itself
Make, IRIG106 storage formats are simplified in this programme, two processes of the encapsulation of IRIG106 data and data storage are entered
Row separation, reduces association and improves writing speed.IRIG106 wrappers are divided into two kinds of bag forms:One kind is IRIG106 data
Bag, that is, the packet collected;One kind is wrapped for the IRIG106 times, i.e., outside gathered data data are carried out with time mark and is wrapped.Number
According to encapsulation as shown in table 1-1, time encapsulation is as shown in table 1-2, and time collection bag can be directly according to bag form group bag, packet
Need that 4 tunnel gathered datas are carried out to be blended in a group bag.
Table 1-1 packet encapsulation forms
Table 1-2 time encapsulation forms
As shown in Fig. 2 in the present embodiment, storage control module is SATA control modules, and storage dish is SATA hard disc, SATA
Control module is used to realize SATA II protocol transport layer, link layer and physical layer function, the compatible standards of SATA 3.0.SATA is controlled
Molding block includes file management submodule, master controller logic sub-modules and physical interface submodule;File management submodule
The input that output end encapsulates submodule with data is connected, the output end and master controller logic sub-modules of data encapsulation submodule
Input connection, the output end of master controller logic sub-modules is connected with the input of physical interface submodule, physical interface
Submodule is used to be connected with external storage disk.
SATA control modules are responsible for being managed SATA solid-state disks and reading and writing data, are the Core Feature lists of memory plane
Member, is designed using FPGA, and SATAI works protocol transport layer, link layer and physical layer function are realized comprehensively, compatible
SATA3.0 standards, highest is supported in 6Gbps speed, the design using the realization of A1tera 40nm Series FPGAs, SATAII master controls
Device basic logic block diagram processed 3 functional modules as shown in Fig. 2 be mainly made up of, respectively physical layer interface submodule SATA_
PHY, master controller logic sub-modules LOGIC_CTRL and file management submodule.Wherein, file management submodule is also included
Subscriber Interface Module SIM USER_INF and DMA interface DMA_INF.Subscriber Interface Module SIM USER_INF and DMA interface DMA_INF with
The LOGIC_CTRL connections of main control logic submodule.Subscriber Interface Module SIM USER_INF is used to receive small data packets;DMA interface
DMA_INF is used to receive big data bag.
In the present embodiment, file management submodule is used to carry out user-defined file management to the IRIG106 wrappers of reception,
User-defined file management is divided into three levels;First layer is used to be managed data segment, data storage section in record storage disk
Number, the second layer is managed to the original position and end position of file index, indicates the beginning of one piece of data segment index
Position and end position, third layer are entered to the title of file, start recording time, the original position of data storage and end position
Row management, storage file title, the time of record and the original position of data when recording beginning, later each second record one
Secondary current time and current recording position.
In the present embodiment, when system exception power down, the knot for finding the previous second record of power down is managed by user-defined file
Beam position, is the data segment for recovering completion by end position information.The data of last second are so at most only lost, are passed through
The positional information can recover the data segment of completion, it is ensured that data loss problem caused by powered-off fault.
The present invention proposes a kind of high speed storing scheme based on FPGA, by FPGA indoor design storage controls to depositing
Storage disk is directly operated, while the process to data storage is optimized, data processing stage and memory phase is separated, filled
Point using FPGA parallel processings advantage, overcome it is existing be based on the embedded slower problem of storage scheme speed, greatly improve
The memory rate of data.
In addition, the present invention is encapsulated by IRIG106, connect eventually through SATA II also by receiving multichannel Ethernet data
Mouth carries out high speed storing.Digitlization and the efficient combination to a variety of data are realized with more economical method.Acquisition module is based on double
FIFO data Caching Mechanism, the IRIG106 based on FPGA simplifies data framing format, realizes to the quick, reliable of data
Ground processing and storage.Based on customized file management mode, the management is divided into three layers, of first layer note record data section
Number, the original position and end position of second layer log file index, the title of third layer record data, the end of each second
Data recording position.Farthest prevent loss of data caused by power down or other failures.
It the composite can be widely applied to various high-speed memory systems.
Above is the preferable implementation to the present invention is illustrated, but the invention is not limited to the implementation
Example, those skilled in the art can also make a variety of equivalent variations or replace on the premise of without prejudice to spirit of the invention
Change, these equivalent deformations or replacement are all contained in the application claim limited range.
Claims (10)
1. a kind of IRIG106 high-speed data processing systems based on FPGA, it is characterised in that it is realized using FPGA, including it is many
Road acquisition module, IRIG106 package modules and storage control module;The output end of the multi pass acquisition module is and IRIG106
The input connection of package module, the output end of the IRIG106 package modules and the input of storage control module are connected, institute
Stating storage control module is used to be connected with external storage disk;The multi pass acquisition module, IRIG106 package modules and storage control
Modular concurrent is run.
2. a kind of IRIG106 high-speed data processing systems based on FPGA according to claim 1, it is characterised in that institute
Stating acquisition module includes big FIFO and small FIFO;The big FIFO is used for the larger gathered data of buffer data size, and small FIFO is used
In the length for storing current gathered data;Acquisition module has stored a packet in big FIFO every time, is stored in small FIFO
The length of the packet, that is, the packet write is corresponded with data packet length.
3. a kind of IRIG106 high-speed data processing systems based on FPGA according to claim 1 or 2, it is characterised in that
The IRIG106 package modules include multichannel data mixing submodule and data encapsulation submodule, multichannel data mixing
The data that module is used to export multi pass acquisition module carry out data mixing, and the data encapsulation submodule is used for will be mixed
Data are output to storage control module after carrying out data encapsulation.
4. a kind of IRIG106 high-speed data processing systems based on FPGA according to claim 3, it is characterised in that institute
Stating data mixing submodule includes mixing FIFO;During work, the data mixing submodule is according to acquisition buffer set in advance
The length of data, once reads corresponding data length and corresponding packet, by data pack buffer from multi pass acquisition module
So that data encapsulation submodule is read in mixing FIFO.
5. a kind of IRIG106 high-speed data processing systems based on FPGA according to claim 4, it is characterised in that work
When making, the total amount of data and the data volume of last bag data cached in the data mixing submodule record FIFO, when total
When data volume exceedes setting wrapper size, total amount of data is subtracted to the data volume of last bag, current data group bag is formed defeated
Go out to data and encapsulate submodule.
6. a kind of IRIG106 high-speed data processing systems based on FPGA according to claim 3, it is characterised in that institute
IRIG106 wrappers are dressed up in the data group encapsulating that stating data encapsulation submodule is used to export data mixing submodule;It is described
IRIG106 wrappers include IRIG106 packets and the IRIG106 times wrap;The IRIG106 packets contain the number collected
According to a group bag, the IRIG106 times include the data that time mark is carried out to data group bag.
7. a kind of IRIG106 high-speed data processing systems based on FPGA according to claim 6, it is characterised in that institute
Stating storage control module includes file management submodule, master controller logic sub-modules and physical interface submodule;The file
The output end for managing submodule is connected with the input that data encapsulate submodule, the output end of the data encapsulation submodule and master
The input connection of controller logic submodule, output end and the physical interface submodule of the master controller logic sub-modules
Input is connected, and the physical interface submodule is used to be connected with external storage disk.
8. a kind of IRIG106 high-speed data processing systems based on FPGA according to claim 7, it is characterised in that institute
Stating file management submodule is used to carry out user-defined file management, the user-defined file pipe to the IRIG106 wrappers of reception
Reason is divided into three levels;First layer is used to be managed data segment, the number of data storage section, the second layer in record storage disk
Original position and end position to file index are managed, and indicate starting position and the stop bits of one piece of data segment index
Put, third layer is managed to the title of file, start recording time, the original position of data storage and end position, in note
Storage file title, the time of record and the original position of data when record starts, when record is once current within each second later
Between and current recording position.
9. a kind of IRIG106 high-speed data processing systems based on FPGA according to claim 8, it is characterised in that when
During system exception power down, the end position for finding the previous second record of power down is managed by user-defined file, passes through stop bits confidence
Breath recovers the data segment of completion.
10. a kind of IRIG106 high-speed data processings system based on FPGA according to claim 1,2,4,5,6,7,8 or 9
System, it is characterised in that the storage control module is SATA control modules, the storage dish is SATA hard disc, the SATA controls
Molding block is used to realize SATA II protocol transport layer, link layer and physical layer function, compatible SATA3.0 standards.
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113722271A (en) * | 2021-07-20 | 2021-11-30 | 湖南艾科诺维科技有限公司 | File management method, system and medium for data acquisition and playback |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1752981A (en) * | 2005-10-26 | 2006-03-29 | 东北大学 | Pnp high speed multichannel intelligent comprehensive data acquiring system |
CN101478462A (en) * | 2008-12-17 | 2009-07-08 | 成都市华为赛门铁克科技有限公司 | Apparatus and method for storage data reading and writing, solid hard disk |
CN102523198A (en) * | 2011-11-28 | 2012-06-27 | 曙光信息产业股份有限公司 | Multi-path data collection card |
CN102999644A (en) * | 2011-11-22 | 2013-03-27 | 北京泛华恒兴科技有限公司 | Multifunctional isolated data acquisition card |
CN103577574A (en) * | 2013-11-05 | 2014-02-12 | 中船重工(武汉)凌久电子有限责任公司 | High-reliability linear file system based on nand flash |
CN105426329A (en) * | 2015-10-30 | 2016-03-23 | 北京遥测技术研究所 | High-speed signal acquisition and forwarding method based on embedded 10Gbps network hardware protocol stack |
CN106325162A (en) * | 2016-09-20 | 2017-01-11 | 浙江工业大学 | Embedded intelligent electromechanical equipment condition monitoring system |
-
2017
- 2017-03-22 CN CN201710176256.1A patent/CN107092440B/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1752981A (en) * | 2005-10-26 | 2006-03-29 | 东北大学 | Pnp high speed multichannel intelligent comprehensive data acquiring system |
CN101478462A (en) * | 2008-12-17 | 2009-07-08 | 成都市华为赛门铁克科技有限公司 | Apparatus and method for storage data reading and writing, solid hard disk |
CN102999644A (en) * | 2011-11-22 | 2013-03-27 | 北京泛华恒兴科技有限公司 | Multifunctional isolated data acquisition card |
CN102523198A (en) * | 2011-11-28 | 2012-06-27 | 曙光信息产业股份有限公司 | Multi-path data collection card |
CN103577574A (en) * | 2013-11-05 | 2014-02-12 | 中船重工(武汉)凌久电子有限责任公司 | High-reliability linear file system based on nand flash |
CN105426329A (en) * | 2015-10-30 | 2016-03-23 | 北京遥测技术研究所 | High-speed signal acquisition and forwarding method based on embedded 10Gbps network hardware protocol stack |
CN106325162A (en) * | 2016-09-20 | 2017-01-11 | 浙江工业大学 | Embedded intelligent electromechanical equipment condition monitoring system |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113722271A (en) * | 2021-07-20 | 2021-11-30 | 湖南艾科诺维科技有限公司 | File management method, system and medium for data acquisition and playback |
CN113722271B (en) * | 2021-07-20 | 2023-11-21 | 湖南艾科诺维科技有限公司 | File management method, system and medium for data acquisition and playback |
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