CN107085452B

CN107085452B - Three-dimensional printed memory (3D-P) based processor

Info

Publication number: CN107085452B
Application number: CN201610083747.7A
Authority: CN
Inventors: 张国飙
Original assignee: Hangzhou Haicun Information Technology Co Ltd
Current assignee: Hangzhou Haicun Information Technology Co Ltd
Priority date: 2016-02-13
Filing date: 2016-02-13
Publication date: 2021-01-15
Anticipated expiration: 2036-02-13
Also published as: CN112328535A; CN112328535B; CN112631367A; CN107085452A

Abstract

The invention provides a processor based on a three-dimensional printed memory (3D-P). The 3D-P has large capacity and high speed, does not occupy the area of a substrate basically, and can be integrated on various logic circuits. Therefore, using 3D-P to store a look-up table (LUT) for a processor can increase processor speed and reduce chip area. In addition, after the LUTs based on the 3D-P are adopted in different types of calculation, the time spent by the LUTs is more structured, and sequential circuits can be realized between different types of calculation.

Description

Three-dimensional printed memory (3D-P) based processor

Technical Field

The present invention relates to the field of integrated circuits, and more particularly to processors.

Background

The processor needs to perform various complex calculations. Conventional processors are only efficient for conventional addition and conventional multiplication, but other computations take a large number of clock cycles to complete. To this end, the prior art proposes to use look-up tables (LUTs) to perform part of the calculations. For example, us patent 5,046,038 proposes implementing a divider with a LUT, us patent 5,954,787 proposes implementing a trigonometric function calculator with a LUT, us patent 6,263,470 proposes implementing a Reed-Solomon decoder with a LUT, and so on.

The implementation of an exponent unit using a LUT is described in detail in us patent 9,207,910 below. As shown in fig. 1A, the exponent unit employs two

LUTs

210, 230. Wherein, the log (x) value 240 of the input x can be found by LUT a 210, then the value of log (x) is multiplied by K at the multiplier 220, and the resulting product 250 can be found by LUT B230 to find the exponent value 260 of x. The patent also discloses a digital processor DSP 200X that contains a plurality of parallel exponent units 200. sup. 1,2001-2 … 200-N, so that a plurality of inputs X are calculated simultaneously₁,x₂…x_NIs used as an index of (1).

The above processors using LUTs all face a common problem, namely, the

LUTs

210 and 230 use SRAM cells, which must be formed on a substrate, and the memory cells have a large area, and occupy a large amount of substrate resources. Therefore, the array size of the LUT employed in the prior art cannot be excessive. As described in patent 9,207,910, the size of a single LUT is typically limited to 32 kb. Therefore, in the prior art, the input variable of the LUT can only be a small word width, which results in a limited increase of the calculation speed of the LUT. When a processor employs a large number of parallel computations, these LUTs need to be repeated multiple times, which requires a large amount of substrate area to be consumed, increasing processor cost.

The prior art processors also suffer from the problem that, because the different types of computations employ very different logic circuits, the time they take to complete the computations can vary greatly. This makes it difficult for processors containing multiple computing types to pipeline these computations. This is detrimental to the overall improvement in system performance. Based on the above difficulties, it is necessary to find a large capacity, inexpensive memory to store the LUT for the processor.

Disclosure of Invention

It is a primary object of the present invention to provide a better performing processor.

It is a further object of this invention to provide such a processor which is less costly.

To achieve these and other objects, the present invention proposes a processor based on a three-dimensional printed memory (3D-P). The 3D-P is a kind of three-dimensional memory (3D-M), and the stored information is recorded in a non-electric mode in the factory production process, and the information is permanently fixed and generally can not be changed after being delivered from a factory.

Since the 3D-P memory cell does not need to be electrically programmed, all of the conductivity of its diode can be used to read the data stored in the cell. Therefore, the read circuit of 3D-P can be increased more than ten times compared to 3D-M which can be programmed. The read delay of 3D-P is on the order of 10 ns. If a small array is used (i.e., the number of word lines is less than 1024), the 3D-P read delay can be reduced to ns. Therefore, the 3D-P can meet the requirement of the processor on speed as an LUT memory.

The 3D-P adopts a cross point array, and the area of a memory cell of the cross point array is 4F²(F is the process feature size). And by adopting three-dimensional integration (8 layers or more than 8 layers can be stacked), the 3D-P capacity is far larger than that of an SRAM (the SRAM memory cell area is 50F)²100 times larger than the 3D-P memory element). After the 3D-P storage LUT is adopted, LUTs with the total data quantity of up to 1Tb can be stored on one processor chip. This means that the processor can carry a LUT with a large word width, which can greatly improve the performance of the processor.

More importantly, the 3D-P is located above the substrate circuitry, and the 3D-P occupies substantially no substrate area other than its peripheral circuitry. Thus, the 3D-P may be integrated on a variety of logic circuits. Therefore, 3D-P not only does not increase the processor chip area, but also reduces the chip area. This is not imaginable to the prior art. After the 3D-P is adopted as a carrier of the LUT, the method has the following significant advantages: no matter how complex the computation is, with LUTs, the different types of computation time are structured, i.e. their delays are substantially integer multiples of each other. This facilitates pipelining of complex computations.

Accordingly, the present invention provides a 3D-P based processor, comprising: a substrate, wherein the substrate comprises a substrate circuit, and the substrate circuit comprises at least one logic circuit and at least one peripheral circuit of the 3D-P; at least one printed memory reservoir stacked on the substrate, information of the printed memory reservoir being entered during production in a factory, the printed memory reservoir storing an LUT; the printed memory storage layer is coupled with the logic circuit through the peripheral circuit, and the logic circuit and the lookup table form a computing unit.

Drawings

FIG. 1A is a block circuit diagram of an exponent section of the prior art; fig. 1B is a digital processor based on the above-described exponent unit.

Fig. 2 is a cross-sectional view of a three-dimensional printed memory (3D-P).

Fig. 3 is a circuit diagram of a 3D-P array in the storage layer 16A.

FIG. 4 compares the I-V characteristics of two 3D-P memory cells.

FIG. 5 is a graph of read delay versus number of array word lines, n, for a 3D-P.

FIG. 6 is a top view of the substrate circuitry (i.e., the 3D-P array has been removed) of a 3D-P based index cell.

Fig. 7A is a circuit block diagram of a GF adder; fig. 7B is a 3D-P based GF adder, which is a top view of the substrate circuitry (i.e., the 3D-P array has been removed).

FIG. 8A is an exponential cell based DSP; fig. 8B is a DSP based on multiple computing units.

It is noted that the figures are diagrammatic and not drawn to scale. Dimensions and structures of parts in the figures may be exaggerated or reduced for clarity and convenience. The same reference numbers in different embodiments generally indicate corresponding or similar structures.

Detailed Description

FIG. 2 shows a three-dimensional printed memory (3D-P). It comprises a substrate circuit layer 0K and a plurality of

memory layers

16A, 16B stacked on top of each other. The substrate circuit layer 0K contains the transistor 0t and its interconnect line 0 i. Wherein the transistor 0t is formed in a semiconductor substrate 0; the interconnect line 0i is located above the substrate 0. In this embodiment, to guarantee the speed of the substrate circuit 0K, the interconnect line 0i contains 3 (or more than 3) interconnect layers 0M1-0M 3. Each memory layer (e.g., 16A) contains a plurality of bit lines (e.g., 2a, in the y-direction), word lines (e.g., 1a, in the x-direction), and memory cells (e.g., 16 Aaa). The memory layer (e.g., 16A) is coupled to the substrate 0 through a contact via hole (e.g., 1 av). Here, the substrate circuit layer 0K contains peripheral circuits of a 3D-P array.

Fig. 2 also shows two types of 3D-P memory cells 16Aaa and 16 Baa. Each memory cell contains a diode 14. The diode 12 has the following broad characteristics: under the reading voltage, the resistance is small; when the applied voltage is less than the read voltage or in the opposite direction to the read voltage, the resistance is larger. The diode film may be a P-i-N diode or may be a metal oxide (e.g., TiO)₂) Diodes, etc. Memory cell 16Baa is a low resistance memory cell (commonly referred to as a '1' memory cell); the memory cell 16Aaa is a high resistance memory cell (generally referred to as a '0' memory cell). The high resistance memory cell 16Aaa includes a layer of insulating film (or high resistance film) 12 more than the low resistance memory cell 16 Baa. As a simple example, the insulating film 12 may be a silicon dioxide film. Due to the presence of the high-resistance insulating film 12, the resistance of the high-resistance memory cell 16Aaa is much higher than that of the low-resistance memory cell 16 Baa. The information stored in the 3D-P can be input during factory production and cannot be rewritten after leaving the factory.

Fig. 3 is a circuit diagram of a 3D-P array in the storage layer 16A. In this figure, the presence of a diode represents a low resistance memory cell and the absence of a diode represents a high resistance memory cell. All address lines in the array are contiguous and do not share address lines with other memory arrays of the same memory layer. Accordingly, the 3D-P array has m bit lines and n word lines. In this embodiment, the number of word lines (n) is less than the number of bit lines (m); the bit lines are coupled to an X-decoder 15 and the word lines are coupled to a Y-decoder/sense circuit 17.

As can be seen from FIGS. 2 and 3, the 3D-P uses a cross-point array with 4F cell area²(F is the process feature size). And by adopting three-dimensional integration (8 layers or more than 8 layers can be stacked), the 3D-P capacity is far larger than that of an SRAM (the SRAM memory cell area is 50F)²100 times larger than the 3D-P memory element). After the 3D-P storage LUT is adopted, LUTs with the total data quantity of up to 1Tb can be stored on one processor chip. This means that the processor can carry a LUT with a large word width, which can greatly improve the performance of the processor.

More importantly, the 3D-P is located above the substrate circuitry, and the 3D-P occupies substantially no substrate area other than its peripheral circuitry. Thus, the 3D-P may be integrated on a variety of logic circuits. Therefore, 3D-P not only does not increase the processor chip area, but also reduces the chip area. This is not imaginable to the prior art.

FIG. 4 compares the I-V characteristics of two 3D-P bins ('0' and '1'). Since the 3D-P memory cells are programmed in a non-electrical manner, their '0' and '1' memory cells have different physical/chemical forms (cells 16Aaa and 16Baa of FIG. 2). In this example, the I-V curves for the '0' and '1' bins are very different. 3D-P reads are very different from programmable 3D-M (i.e., 3D-W). Since the 3D-W memory cell needs to be electrically programmed, its read voltage and read current are very limited. The 3D-P does not need electrical programming, and can adopt larger reading voltage V ″_readThe read current I' thereof_readIs an order of magnitude greater than the read current of 3D-W. That is, the read latency of 3D-P is an order of magnitude less than 3D-W. Considering that the read latency of 3D-W is on the order of 100ns and the read latency of 3D-P is on the order of 10ns (assuming the same memory array, 1k x1k) (see patent application "three-dimensional memory based computing system").

FIG. 5 is a graph of read delay versus number of array word lines, n, for a 3D-P. The read delay of 3D-P is proportional to n. If the number of n is reduced from 1k to 100 levels lower (e.g., around 200), the read delay of 3D-P can be further reduced to ns level. This speed enables the 3D-P to act as a LUT memory to meet the speed requirements of the processor

Fig. 6 is a 3D-P based index cell 200, which is a top view of the substrate circuitry (i.e., the 3D-P array has been removed). In this figure, the printed reservoir of LUT a 210 (right slashed area) the printed reservoir of LUT B230 (left slashed area) covers multiplier 220. Input 270 selects the desired log value via

X decoders

15A, 15A' of LUT a 210, and readout circuitry 17A outputs the existing log (X) value 240. After multiplying by K through the multiplier, the result 250 is sent to the X decoders 15B, 15B' of the LUT B230 to select the corresponding index value, and the final result 260 is obtained. Note that LUT a 210 and LUT B230 each have one side, and the substrate thereunder does not contain 3D-P peripheral circuits, which facilitates the routing of multiplier 220.

Fig. 7A is a circuit block diagram of a GF adder. The GF adder 300 is described in detail in U.S. patent application 2006/0123325a 1. Where the polynomial multiplier 310 multiplies X, Y, the first 7 bits 340 of the resulting product are sent to the LUT320 for mod computation, and the last 8 bits 360 are added to the mod computed value 350 at the adder 330 to obtain the final result Z.

Fig. 7B is a 3D-P based GF adder, which is a top view of the substrate circuitry (i.e., the 3D-P array has been removed). Similar to FIG. 6, the multi-hour multiplier 310 and the adder are both covered by a 3D-P array 320. The 3D-P array has one side, and the substrate below the 3D-P array does not contain peripheral circuits of 3D-P, so that the substrate logic circuit is convenient to interface with the outside.

FIG. 8A is a DSP 200X' based on exponent unit. It contains a plurality of parallel index units 200-1 ', 2001-2 ' … 200-N ', which all use 3D-P as the storage carrier of LUT and calculate a plurality of inputs x simultaneously₁,x₂…x_NIs used as an index of (1). FIG. 8B is a DSP 200Z' based on multiple computing units. It contains various calculation units including an exponent unit 200 ', a GF multiplication unit 300, a division unit 400', etc. These calculation units all use 3D-P as a storage carrier for the LUT and perform parallel calculations. After 3D-P is adopted as a carrier of the LUT, the method has a remarkable advantage that: no matter how complex the calculation is, after using LUTThe different types of computation time are structured, i.e. their delays are substantially all integer multiples of each other. This facilitates pipelining of complex computations.

The 3D-P based processor provided by the invention has wide application, and the computing unit using the processor comprises: a multiplication unit, a division unit, a trigonometric function unit, an exponent unit, a logarithm unit, a GF multiplication unit, an error detection and correction ECC unit, an encryption unit, a decryption unit, or a function unit (the function unit may implement any function using LUT). It can be applied to various processors including: the system comprises a Central Processing Unit (CPU), a Field Programming Gate Array (FPGA), a digital processor (DSP), an image processor (GPU), a video processor (video processor) or a communication processor modem and the like.

It will be understood that changes in form and detail may be made therein without departing from the spirit and scope of the invention, and are not intended to impede the practice of the invention. The invention, therefore, is not to be restricted except in the spirit of the appended claims.

Claims

1. A three-dimensional printed memory (3D-P) based processor, comprising:

a substrate having a substrate circuit thereon, said substrate circuit comprising at least one logic circuit and at least one peripheral circuit of said three-dimensional printed memory;

at least one printed memory reservoir stacked on the substrate and not contacting any substrate, information of the printed memory reservoir being entered during factory production and storing a look-up table (LUT), at least a portion of the printed memory reservoir covering at least a portion of the logic circuit;

the printed memory storage layer is coupled with the logic circuit through the peripheral circuit, and the logic circuit and the lookup table form a computing unit.

2. The processor of claim 1, further characterized by: the calculation unit at least comprises one of a multiplication unit, a division unit, a trigonometric function unit, an exponent unit, an logarithm unit, a GF multiplication unit, an error detection and correction (ECC) unit, an encryption unit, a decryption unit or a function unit.

3. The processor of claim 1, further characterized by: the processor is a central processing unit CPU, a field programming gate array FPGA, a digital processor DSP, an image processor GPU, a video processor or a communication processor modem.

4. The processor of claim 1, further characterized by: the printed memory reservoir contains a plurality of memory arrays, all address lines in each memory array being contiguous and not sharing address lines with other memory arrays of the same memory layer.

5. The processor of claim 4, further characterized by: the printed memory storage layer contains a memory array, and the substrate under at least one side of the memory array does not contain peripheral circuits of the memory array.

6. The processor of claim 5, further characterized by: includes adjacent first and second memory arrays overlying the logic circuit.

7. The processor of claim 1, further characterized by: at least a portion of the substrate circuitry contains at least three interconnect layers.

8. The processor of claim 1, further characterized by: the number of word lines of the printed memory reservoir is less than the number of bit lines thereof.

9. The processor of claim 1, further characterized by: the number of word lines of the printed memory reservoir is less than 1024.