CN107070410B

CN107070410B - Dynamic power amplifier

Info

Publication number: CN107070410B
Application number: CN201710238977.0A
Authority: CN
Inventors: 王海时; 文展; 杜江; 李英祥; 孙捷; 杨燕; 杨俊杰; 郑欣
Original assignee: Shanghai Chipstar Microelectronics Ltd; Chengdu University of Information Technology
Current assignee: Shanghai Chipstar Microelectronics Ltd
Priority date: 2017-04-13
Filing date: 2017-04-13
Publication date: 2023-04-28
Anticipated expiration: 2037-04-13
Also published as: CN107070410A

Abstract

A dynamic power amplifier is disclosed, which includes an amplifying circuit, a power supply device for supplying positive power and negative power to the amplifying circuit, and a mode control circuit for controlling the power supply device. The positive power supply negative power supply of the dynamic amplifier can dynamically change along with the output signal, and the power loss of the output transistor of the amplifier is reduced, so that the efficiency of the amplifier is improved.

Description

Dynamic power amplifier

Technical Field

The present invention relates to amplifiers and more particularly, but not exclusively, to a dynamic power amplifier.

Background

Amplifiers play an important role in analog-to-digital conversion circuits and power integrated circuits, and one of the important functions is to amplify an audio signal as an audio amplifier. Whereas the ratio of peak power to average power (Peak Average Ratio, PAR) of a speech or music signal is large, the peak voltage is much larger than the average voltage, and its amplitude usually follows a gaussian distribution, i.e. the amplitude of the transient voltage of the audio signal is much lower than its peak voltage amplitude for most of the time. To avoid clipping distortion, the supply voltage of the amplifier must be large enough to be able to process most audio signals. At this supply voltage, when the amplifier processes audio signals with a low amplitude, energy is lost to the output transistor, which not only reduces the efficiency of the amplifier, but also causes a problem of heat dissipation. For example, for the amplifier 100 shown in fig. 1, when the supply voltage VCC is 5V and the output signal VO is 1V, the voltage drop across the output transistor Q1 will reach 4V, i.e. 80% of the supply voltage will be lost by the transistor P1, instead of being used to generate useful power on the speaker SPK. The amplifier transient efficiency is now less than 20% taking into account the losses of the other components of the amplifier. Experiments have shown that the average efficiency is less than 20% when the PAR of the input signal is 15 dB. How to increase the efficiency of an amplifier is a difficult problem faced by the person skilled in the art.

Disclosure of Invention

In view of one or more problems in the prior art, there is provided a dynamic power amplifier comprising: the power amplifier is provided with a first input end, a second input end, an output end, a first power end and a second power end, wherein the first power end receives positive power, the second power end receives negative power and the output end provides a driving signal; the power supply device is provided with a control end, a first output end for providing positive power and a second output end for providing negative power, wherein the first output end is coupled to the first power end of the power amplifier, and the second output end is coupled to the second power end of the power amplifier; a mode control circuit having a first sampling terminal, a second sampling terminal, a third sampling terminal, and an output terminal, wherein the first sampling terminal is coupled to the first output terminal of the power supply device, the second sampling terminal is coupled to the second output terminal of the power supply device, the third sampling terminal is coupled to one input terminal of the power amplifier, and the output terminal is coupled to the control terminal of the power supply device, the mode control circuit controlling an operation mode of the power supply device based on the power amplifier driving signal and the power supply device output voltage; if the power supply device works in a first mode, the positive power supply and the negative power supply respectively have a first positive voltage and a first negative voltage; if the power supply device works in a second positive mode, the positive power supply and the negative power supply respectively have a second positive voltage and a first negative voltage; if the power supply device works in a second negative mode, the positive power supply and the negative power supply respectively have a first positive voltage and a second negative voltage; wherein the second positive voltage is greater than the first positive voltage, and the second negative voltage is greater than the first negative voltage, and wherein the power supply device operates in a first mode if the input signal of the power amplifier is zero; if the power supply device is in a first working mode, when the positive power supply rises to a first positive number or the difference between the positive power supply and the driving signal is smaller than a first positive threshold value, the power supply device enters a second positive working mode; if the power supply device is in the second working mode, when the driving signal is reduced to a second positive threshold value, the power supply device jumps out of the second positive working mode and enters a first positive dormancy mode; and if the power supply device is in the first positive sleep mode, when the positive power supply of the power supply device is reduced to a third positive threshold value, the power supply device enters a first working mode.

The positive power supply and the negative power supply of the amplifier provided by the invention can be dynamically changed along with the output signal, so that the power loss of the output transistor is reduced, and the efficiency of the amplifier is improved.

Drawings

Specific embodiments of the present invention will be described in detail below with reference to the drawings, wherein like reference numerals refer to like parts or features.

Fig. 1 shows a schematic circuit diagram of a conventional amplifier 100;

fig. 2 shows a schematic circuit diagram of a high efficiency amplifier 200 according to one embodiment of the invention;

FIG. 3 shows a schematic circuit diagram of a power supply 202 according to one embodiment of the invention;

FIG. 4 shows a schematic circuit diagram of a mode control circuit 400 according to one embodiment of the invention;

FIG. 5 illustrates a schematic diagram 500 of an operational waveform of a high efficiency amplifier 200 in accordance with one embodiment of the invention;

FIG. 6 shows a schematic circuit diagram of a mode control circuit 600 according to one embodiment of the invention;

FIG. 7 illustrates a schematic diagram 700 of an operational waveform of the high efficiency amplifier 200 in accordance with one embodiment of the present invention; and

fig. 8 shows a flow chart of a control method of the high efficiency amplifier 200 according to an embodiment of the invention.

Detailed Description

The particular embodiments described below represent exemplary embodiments of the present invention and are merely exemplary in nature and not limiting. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that: these specific details are not necessary for the invention. In other instances, well-known circuits, materials, or methods have not been described in detail in order not to obscure the invention.

Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not all referring to the same embodiment, nor are other embodiments or alternative embodiments mutually exclusive. All of the features disclosed in this specification, or all of the steps in a method or process disclosed, may be combined in any combination, except for mutually exclusive features and/or steps. Moreover, those of ordinary skill in the art will appreciate that the illustrations provided herein are for illustrative purposes and that the illustrations are not necessarily drawn to scale. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected to" or "directly coupled to" another element, there are no intervening elements present. Like reference numerals designate like elements. When an element is said to "receive" a signal, it may be directly received, or may be received through a switch, a resistor, a level shifter, a signal processing unit, or the like. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

Fig. 2 shows a circuit schematic of a high efficiency amplifier 200 according to one embodiment of the invention, comprising a power amplifier 201, a power supply 202 and a mode control circuit 203.

The power amplifier 201 may convert an input signal VIN comprising a non-zero dc component into a drive signal VDRV with a dc component of zero (at a static operating point at ground potential) to drive the generating device SPK. According to one embodiment of the present invention, the power amplifier 201 has a first power terminal receiving the positive power source VSP, a second power terminal receiving the negative power source VSN, a first input terminal and a second input terminal receiving the input signal VIN, and an output terminal providing the driving signal VDRV, and includes a first amplifier 2011 and first to fourth resistors R1 to R4. The first amplifier 2011 has a first input, a second input, and an output. The first resistor R1 has a first end coupled to the first input terminal IN1 of the power amplifier 201 and a second end coupled to the first input terminal of the first amplifier 2011. The second resistor R2 has a first end coupled to the second input terminal IN2 of the power amplifier 201 and a second end coupled to the second input terminal of the first amplifier 2011. The third resistor R3 has a first end and a second end, wherein the first end is coupled to the first input end of the first amplifier 2011, and the second end is coupled to the ground GND. The fourth resistor R4 has a first end and a second end, the first end of the fourth resistor R4 is coupled to the second input end of the first amplifier 2011, and the second end of the fourth resistor R4 is coupled to the output end OUT of the first amplifier 2011, wherein the ratio of the resistance of the first resistor R1 to the resistance of the third resistor R3 is equal to the ratio of the resistance of the second resistor R2 to the resistance of the fourth resistor R4. In one embodiment, the first resistance R1 is equal to the second resistance R2, and the third resistance R3 is equal to the fourth resistance R4. In a particular embodiment, the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 have equal values.

The power supply device 202 has a control terminal, a first output terminal SP for supplying the positive power VSP and a second output terminal SN for supplying the negative power VSN, wherein the first output terminal is coupled to the first power terminal of the power amplifier 201 and the second output terminal is coupled to the second power terminal of the power amplifier 202. Fig. 3 shows a schematic circuit diagram of a power supply 202 according to an embodiment of the present invention, including a first switch S1, a second switch S2, a first diode D1, a second diode D2, a first inductor L1, a second inductor L2, a first capacitor C1, a second capacitor C2, and control logic 2021. The first switch S1 has a first terminal coupled to the input power VCC, a second terminal coupled to the first switch terminal SWP, and a control terminal. The second switch S2 has a first terminal coupled to the input power VCC, a second terminal coupled to the second switch terminal SWN, and a control terminal. The first diode D1 has a cathode coupled to the ground terminal and an anode coupled to the first switch terminal SWP. The first diode D1 has a cathode and an anode, the anode is coupled to the ground GND, and the anode is coupled to the second switch SWN. The first inductor L1 has a first end and a second end, the first end is coupled to the first switch end SWP, and the second end is coupled to the first output end SP. The second inductor L2 has a first end and a second end, the first end is coupled to the second switch end SWN, and the second end is coupled to the second output end SN. The first capacitor C1 has a first end and a second end, the first end is coupled to the first output end SP, and the second end is grounded. The second capacitor C2 has a first end and a second end, the first end is coupled to the second output end SN, and the second end is grounded. The first switch S1, the first diode D1, the first inductor L1 and the first capacitor C1 form a positive power supply circuit to provide a positive power supply VSP; the second switch S2, the second diode D2, the second inductor L2, and the second capacitor C2 form a negative power supply circuit to supply the negative power VSN. The control logic 2021 receives the control signals and provides a first control signal CP and a second control signal CN for controlling the positive power supply circuit and the negative power supply circuit, respectively. In one embodiment, changing the duty cycle of the first control signal CP and the second control signal CN may change the value of the positive power source VSP or the negative power source VSN. In one embodiment, the first switch S1 and the second switch S2 are PMOS transistors, and the first diode D1 and the second diode D2 are schottky diodes. In one embodiment, NMOS transistors are employed in place of the first diode D1 and the second diode D2.

A mode control circuit 203 having a first sampling terminal coupled to the first output terminal SP of the power supply 202, a second sampling terminal coupled to the second output terminal SN of the power supply 202, a third sampling terminal coupled to the output terminal of the power amplifier 201 or (one or both) inputs (IN 1 or/and IN 2) to monitor the amplitude of the output signal, and an output terminal coupled to the control terminal of the power supply 202, the mode control circuit 203 controlling the operation mode of the power supply 202 based on the input signals (VIN 1, VIN2, or/and VIN (VIN 1-VIN 2)) of the power amplifier 201 and the output voltage (VSP or/and VSN) of the power supply.

According to one embodiment of the present invention, when the input signal VIN is 0, the positive power source VSP and the negative power source VSN have a standby positive voltage VSP0 (e.g., 0.5V) and a standby negative voltage VSN0 (e.g., -0.5V), respectively, when the power supply 202 is operated in the standby mode. At this time, the power supply amplitude is smaller, and the voltage wasted on the output power tube of the first amplifier 2011 is minimum, so that the static power consumption is minimum.

When the input signal VIN is smaller, the power supply 202 operates in the first operation mode, and the positive power source VSP and the negative power source VSN have a first positive voltage VSP1 (e.g., 0.9V) and a first negative voltage VSN1 (e.g., -0.9V), respectively. At this time, the power supply amplitude is small, and the voltage wasted on the output power tube of the first amplifier 2011 is small, so that the high efficiency amplifier 200 maintains low power consumption. In one embodiment, the standby mode and the first operation mode are the same mode, i.e., the standby positive voltage VSP0 is equal to the first positive voltage VSP1, and the standby negative voltage VSN0 is equal to the first negative voltage VSN1.

When the power supply device operates in the second positive operation mode, the positive power supply VSP has a second positive voltage VSP2 (e.g., 1.8V), and the negative power supply VSN has a first negative voltage VSN1 (e.g., -1.8V). As the drive signal VDRV increases, the positive supply also increases to prevent clipping distortion of the drive signal VDRV, while the negative supply VSN still maintains the first negative voltage VSN1 to reduce energy loss on the output transistor.

When the power supply 202 operates in the second negative mode, the positive power supply VSP has a first positive voltage VSP1 (0.9V) and the negative power supply VSN has a second negative voltage VSN2 (e.g., -1.8V). As the drive signal VDRV increases negatively, the negative supply also increases to prevent clipping distortion of the drive signal VDRV, while the positive supply VSP remains at the first positive voltage to reduce energy loss on the output transistor. In the present specification, unless otherwise specified, the magnitude or the level refers to a comparison of signal amplitudes (absolute values). In addition, as the power supply device inputs power or load current changes, the first positive voltage VSP1, the first negative voltage VSN1, the second positive voltage VSP2 and the second negative voltage VSN2 are difficult to keep constant, and may fluctuate or change accordingly, without departing from the protection scope of the present invention.

Fig. 4 shows a circuit schematic of a mode control circuit 400 according to an embodiment of the present invention, comprising a first monitoring circuit 401, a second monitoring circuit 402, a third monitoring circuit 403, a fourth monitoring circuit 404, a fifth monitoring circuit 405 and a sixth monitoring circuit 406. Fig. 5 shows a schematic diagram 500 of one operational waveform when the mode control circuit 400 is used in the high efficiency amplifier 200.

When the driving signal VDRV is substantially smaller, the power supply device 202 is in the first operation mode (mode 1), and the first power terminal voltage thereof is VSP1. As the driving signal VDRV becomes larger, the distance (voltage difference) between the driving signal VDRV and the first positive voltage VSP1 becomes smaller. When the difference between the voltage value of the positive power supply VSP (the first positive voltage VSP1 is usually the first positive voltage VSP1 when the power supply and the load current are ignored) and the driving signal VDRV is less than or equal to the first positive threshold VTP1 (at time T1), the first monitoring circuit 401 controls the power supply 202 to enter the second positive operation mode (mode 2+), and the voltage of the first power supply terminal of the power supply 202 is rapidly increased to the second positive voltage VSP2 to prevent the driving signal from being clipped and distorted. The negative power supply VSN still maintains the first negative voltage VSN1 to reduce power consumption. In some embodiments, the first positive voltage VSP1 of the power supply device is substantially fixed and does not change with the input power of the power supply device (e.g. using a BUCK or BOOST of closed loop control), and the first monitoring circuit 601 may only monitor the magnitude of the driving signal VDRV without monitoring the distance between the driving signal VDRV and the first positive voltage VSP1. The power supply device 501 may enter the second operation mode directly based on the magnitude of the driving signal VDRV, i.e. when the driving signal VDRV increases to the first positive number VP1, the first monitoring circuit 601 will control the power supply device 501 to enter the second operation mode.

If the power supply 202 is in the second positive operation mode (mode 2+), the first power terminal voltage is the second positive voltage VSP2. As the drive signal VDRV decreases, the power amplifier 202 continues to use such a high positive voltage VSP2, which creates energy waste. Therefore, when the driving signal VDRV decreases to the second positive threshold VTP2 (at time T2), the second monitoring circuit 402 causes the power supply device 202 to jump out of the second operation mode. In one embodiment, the second positive threshold VTP2 may be just equal to the first positive voltage VSP1. In another embodiment, the second positive threshold value VTP2 may be a value between VSP1-VTP1 and VSP1. In other embodiments, a value less than or equal to VSP1-VTP1 is also possible.

When the power supply 202 jumps out of the second operation mode, the first operation mode may not be entered first, but the first positive sleep mode may be entered, during which the power supply 202 stops or reduces the power supply to the capacitor (e.g. capacitor C1) coupled to its first output. Due to the effect of the storage (of the electric charges) of the output capacitor, the voltage of the first output terminal of the power supply device 202 will be gradually reduced by VSP2, and when the positive power supply of the power supply device is reduced to the third positive threshold VTP3 (at time T3), the third monitoring circuit 403 makes the power supply device jump out of the first positive sleep mode and enter the first operation mode. The third positive threshold VTP3 may or may not be equal to the second positive threshold VTP 2. In one embodiment, the third positive threshold VTP3 may be just equal to the first positive voltage VSP1. In another embodiment, the third positive threshold value VTP3 may be a value between VSP1-VTP1 and VSP1. In other embodiments, a value less than or equal to VSP1-VTP1 is also possible.

If the power supply device 202 is in the first operation mode and the voltage at the second power supply terminal is VSN1, as the driving signal VDRV gradually (negatively) increases, the distance (voltage difference) between the driving signal VDRV and the first negative voltage VSN1 is smaller and smaller, and when the difference between the voltage value of the negative power supply VSN (the first negative voltage VSN1 is usually the first negative voltage VSN1 when the power supply and the load current are ignored) and the output signal VDRV is smaller than the first negative threshold VTN1 (time T4), the fourth monitoring circuit 404 controls the power supply device 202 to enter the second negative operation mode, and the voltage at the second power supply terminal of the power supply device 202 is rapidly increased to VSN2 to prevent the driving signal from being clipped and distortion. The positive power supply VSN still maintains the negative power supply VSN1 to reduce power consumption. In some embodiments, the first negative voltage VSN1 of the power supply device is fixed and does not change with the input power of the power supply device (e.g. using a BUCK with closed loop control), and the first monitoring circuit 601 may only monitor the magnitude of the driving signal VDRV without monitoring the distance between the driving signal VDRV and the first negative voltage VSN 1. The power supply device 501 may enter the second operation mode directly based on the magnitude of the driving signal VDRV, i.e. when the driving signal VDRV increases to the first negative number VN1, the first monitoring circuit 601 will control the power supply device 501 to enter the second operation mode.

If the power supply 202 is in the second negative operation mode, the voltage of the first power terminal is VSN2. As the drive signal decreases, continued use of such a high positive voltage VSN2 by the power amplifier 202 will produce a waste of energy. Therefore, when the driving signal VDRV decreases to the second negative threshold VTN2 (at time T5), the fifth monitoring circuit 405 causes the power supply device 202 to jump out of the second operation mode. In one embodiment, the second threshold value VTN2 may be just equal to the first negative voltage VSN1. In another embodiment, the second threshold value VTN2 may be a value between VSN1-VTN1 and VSN1. And in other embodiments may be a value less than or equal to VSN1-VTN 1.

When the power supply 202 jumps out of the second negative mode of operation, the first mode of operation may not be entered first, but rather the first negative sleep mode, during which the power supply 203 stops or reduces the supply of power to the capacitor (e.g. C2) coupled to its second output. Due to the effect of the output capacitance storage (of the charge) etc., the voltage at the second output terminal of the power supply device 202 will gradually decrease from VSN2 (near ground potential), when the negative power supply of the power supply device decreases to the third negative threshold VTN3 (time T6), the power supply device will jump out of the sleep mode and enter the first operation mode. The third negative threshold VTN3 may or may not be equal to the second negative threshold VTN 2. In one embodiment, the third negative threshold VTN3 may be just the first negative voltage VSN1. In another embodiment, the second threshold value VTN2 may be a value between VSN1-VTN1 and VSN1. And in other embodiments may be a value less than or equal to VSN1-VTN 1.

Fig. 6 shows a circuit schematic of a mode control circuit 600 according to an embodiment of the present invention, including sixth to eleventh resistors R6 to R11, comparators CM1 to CM6, and a current source I1. The mode control circuit 600 may be used for the high efficiency amplifier 200 to control the power supply 202. In contrast to the mode control circuit 400 shown in fig. 4, the mode control circuit 600 monitors the variation of the driving signal VDRV by monitoring the first input signal VIN1 and the second input signal VIN 2. Meanwhile, since the mode control circuit 600 can monitor the variation of the signals VIN1, VIN2, VSP, VSN, etc., including but not limited to monitoring the approximation of the driving signal VDRV with the positive power supply VSP or the negative power supply VSN, the amplitude of the driving signal VDRV, the amplitude of the positive power supply VSP and the negative power supply VSN, the mode control circuit 600 may also be referred to as the multi-signal dynamic monitoring circuit 600.

The sixth resistor R6 has a first end and a second end, and the first end is coupled to the first input terminal IN1 of the power amplifier 201 to receive the first input signal VIN1 (or the third sampling end of the mode control circuit 800 receives the first input signal VIN 1). The seventh resistor R7 has a first end and a second end, and the first end is coupled to the second end of the sixth resistor R6. The first current source I1 has a first terminal and a second terminal, the first terminal is coupled to the second terminal of the seventh resistor R7, and the second terminal is coupled to the ground. The first comparator CM1 has a first input terminal coupled to the second terminal of the sixth resistor R6, a second input terminal coupled to the first power terminal SP of the power supply device 202 through the eighth resistor R8 to receive the positive power VSP (or the eighth resistor R8 is configured as the first sampling terminal of the mode control circuit 800 and coupled to the first power terminal SP of the power supply device 202 to receive the positive power VSP). The second comparator CM2 has a first input terminal coupled to the second terminal of the seventh resistor R7, a second input terminal coupled to the second power terminal SN of the power supply device 202 through the ninth resistor R9 to receive the negative power source VSN (or the ninth resistor R9 is configured as the second sampling terminal of the mode control circuit 600 and coupled to the second power terminal SN of the power supply device 202 to receive the negative power source VSN). The tenth resistor R10 has a first end coupled to the second end of the first comparator CM1, and a second end coupled to the first reference voltage terminal RF1 to receive the first reference voltage VRF1. The eleventh resistor R11 has a first end coupled to the second input end of the second comparator CM2 and a second end coupled to the first reference voltage VRF1.

For ease of analysis, it is assumed that the two inputs of the power amplifier 201 respectively receive differential signals VIN1 and VIN2 (vin=vin1-VIN 2) having the same common mode level but opposite ac amplitudes. In other embodiments, the two inputs of the power amplifier 201 may receive a reference signal, one receiving a single-ended signal, the other receiving a single-ended signal. Meanwhile, it is assumed that the voltage amplification factor from the output differential signal VIN of the power amplifier 201 to the output end of the power amplifier is a (or the ratio of the driving signal VDRV to the input signal VIN of the power amplifier 201 is a)

VDRV＝VIN×A (1)

Then there is

Wherein VIN1 represents the first input voltage of the power amplifier 201, VIN2 represents the first input voltage of the power amplifier 201, VRF1 represents the common mode level voltage, VDRV represents the output voltage of the power amplifier 202, the first divided voltage VD1 represents the first input voltage of the first comparator CM1, and the second divided voltage VD2 represents the first input voltage of the second comparator CM 2.

Assuming that the ratio of the resistance of the tenth resistor R10 to the resistance of the eighth resistor R8 is P (r10:r8=p:1), the ratio of the resistance of the eleventh resistor R11 to the resistance of the ninth resistor R9 is Q (r11:r9=q:1), the voltage at the second end of the first comparator CM1 (i.e., the third divided voltage VD 3) may be expressed as

The voltage at the second end of the second comparator CM2 (i.e. the fourth divided voltage VD 4)

When the first partial pressure VD1 is equal to the third partial pressure VD3, i.e

At this time, the first comparator CM1 is turned over, and then there is

If the command is issued,

then there is

VSP-VDRV＝(2A-1)×VRF1-2A×R6×I1＝VTP1 (11)

That is, the first monitoring circuit 801 may flip the output signal (hereinafter referred to as the positive binary signal) when the driving signal DRV is raised to be the first positive threshold value VTP1 from the positive power source VSP, so that the power source providing device 202 enters the second operation mode. In particular, a=p=1 can be made, and the resulting first positive threshold VTP1 is the difference between the positive power supply and the driving signal, and the circuit design and calculation are also most convenient.

It should be noted that the condition defined by equation (10) is an optimal design that can accurately measure the voltage at each power supply. In fact, even

Equation (9) still reflects the approximation of the drive signal VDRV and the positive power supply VSP, and one of ordinary skill in the art can still flexibly determine the different P, A, R and I1 values to set the desired first positive threshold VTP1. That is, the condition defined by equation (10) is an optimized embodiment of the present invention, and is not a limitation of the present invention.

When the second partial pressure VD2 is equal to the fourth partial pressure VD4, i.e

At this time, the second comparator CM2 is turned over, and then there is

If the command is issued,

then there is

VSN-VDRV＝(2A-1)×VRF1-2A×(R6+R7)×I1＝VTN1 (16)

That is, the first monitoring circuit 801 may flip the output signal (hereinafter referred to as the negative two-way signal) when the driving signal VDRV is raised to be the first negative threshold VTN1 from the negative power supply VSN, so as to make the power supply device 202 enter the second operation mode. In particular, a=q=1 can be made.

The third comparator CM3 has a first input terminal coupled to the first input terminal of the power amplifier 201, a second input terminal coupled to the second reference voltage VREF2, and an output terminal. The fourth comparator CM4 has a first input terminal coupled to the second input terminal O2 of the power amplifier 201 (or the first terminal of the fourth comparator CM4 is configured as the fourth sampling terminal of the mode control circuit 800 and coupled to the second input terminal O2 of the power amplifier 201), and a second input terminal coupled to the third reference voltage VRF3.

When the first voltage VIN1 of the power amplifier 201 is equal to the second reference voltage VREF2, that is

When the third comparator CM3 is inverted, the power supply device is controlled to jump out of the second mode by the subsequent circuit. In an optimized embodiment, the settings are

I.e. when the output signal VDRV just decreases to the first voltage VSP1, the third comparator CM3 makes a transition to end the second mode of operation. In another embodiment, it is also possible to set

That is, when the driving signal VDRV just decreases to the vicinity of the first voltage VSP1, the output signal of the third comparator CM3 (hereinafter referred to as a positive one-rest signal) is flipped to end the second positive operation mode and enter the first positive sleep mode. It should be noted that the above is only one preferred embodiment. One skilled in the art can flexibly set the second reference voltage, e.g., proportional to the first voltage VSP1, to maintain a fixed difference from the first voltage VSP 1.

Based on the same principle, when the second voltage VIN2 at the second input end of the power amplifier 201 is equal to the third reference voltage VREF3, that is

When the output signal (hereinafter referred to as a negative one-rest signal) of the fourth comparator CM4 is inverted, the power supply device is controlled to jump out of the first negative sleep mode and enter the first sleep mode by the rear-stage circuit. In an optimized embodiment, the settings are

That is, when the output signal VDRV just decreases to the first voltage VSP1, the fourth comparator CM4 outputs a signal to turn to end the second operation mode. In another embodiment, it is also possible to set

That is, when the driving signal VDRV just decreases to the vicinity of the first voltage VSN1, the output signal of the fourth comparator CM4 (hereinafter referred to as a negative one-time signal) is turned to end the second negative operation mode. It should be noted that the above is only one preferred embodiment. One skilled in the art can flexibly set the third reference voltage, for example, in proportion to the first voltage VSN1, maintaining a fixed difference from the first voltage VSN 1.

In a particular embodiment, the first positive voltage VSP1 is equal in magnitude to the first negative voltage VSN1, i.e

-VSN1＝VSP1 (23)

The second reference voltage VRF2 is equal to the third reference voltage VRF3, i.e. the third comparator CM3 second input and the fourth comparator second input may be coupled to the same reference signal, according to equations (18) and (21), thereby simplifying the circuit design.

The mode control circuit 600 further includes five comparators CM5 and a sixth comparator CM6. The fifth comparator CM5 has a first input terminal coupled to the first input terminal (the third divided voltage VD 3) of the first comparator CM1, a second input terminal coupled to the fourth reference voltage VRF4, and an output terminal. The sixth comparator CM6 has a first input terminal coupled to the second input terminal (the fourth divided voltage VD 4) of the second comparator CM1, a second input terminal coupled to the fifth reference voltage VRF5, and an output terminal.

When the third divided voltage VD3 voltage is equal to the fourth reference voltage VRF4, i.e

The fifth comparator CM5 inverts and issues a sleep end signal (step-down signal) through the subsequent logic gate. In an optimized embodiment, the settings are

That is, when the positive power VSP just decreases to the first voltage VSP1, the output signal of the fifth comparator CM5 (hereinafter referred to as a positive rest signal) is flipped, and the power supply 202 is controlled to jump out of the first positive sleep mode and enter the first operation mode by the following circuit.

When the fourth divided voltage VD4 voltage is equal to the fifth reference voltage VRF5, i.e

The fifth comparator CM5 inverts and issues a sleep end signal through the subsequent logic gate. In an optimized embodiment, the settings are

That is, when the negative power supply VSN just decreases to the first negative voltage VSN1, the output signal of the sixth comparator CM6 (hereinafter referred to as a negative rest signal) is flipped, and the power supply 202 is controlled to jump out of the first negative sleep mode and enter the first operation mode by the following circuit.

In one embodiment, the mode control circuit 600 further includes a control circuit 601 having a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, a fifth input terminal, a sixth input terminal, and an output terminal, wherein the first input terminal is coupled to the output terminal of the first comparator CM1 to receive the positive two-way signal, the second input terminal is coupled to the output terminal of the second comparator CM2 to receive the negative two-way signal, the third input terminal is coupled to the output terminal of the third comparator CM3 to receive the positive one-way signal, the fourth input terminal is coupled to the output terminal of the fourth comparator CM4 to receive the negative one-way signal, the fifth input terminal is coupled to the output terminal of the fifth comparator CM5 to receive the positive one-way signal, the sixth input terminal is coupled to the output terminal of the sixth comparator CM6 to receive the negative one-way signal, and the output terminal provides the control signal CON to control the operation mode of the power supply device 202.

In one embodiment, when the positive two-way signal is enabled (e.g., the comparator CM1 toggles, as described above), the control signal CON controls the power supply 202 to enter the second positive mode of operation; when the negative two-way signal is enabled (e.g. the comparator CM2 toggles, as described above), the control signal CON controls the power supply 202 to enter the second negative mode. When the positive one-rest signal is enabled, the control signal CON controls the power supply device 202 to jump out of the second positive working mode and enter the first positive sleep mode; when the negative one-rest signal is enabled, the control signal CON controls the power supply device 202 to jump out of the second negative working mode and enter the first negative sleep mode. When the positive one-rest signal is enabled, the control signal CON controls the power supply device 202 to jump out of the first positive sleep mode and enter the first working mode; when the negative one-rest signal is enabled, the control signal CON controls the power supply device 202 to jump out of the first negative sleep mode and enter the first working mode.

Fig. 7 illustrates a waveform diagram 700 of the operation of the high efficiency amplifier 200 in accordance with one embodiment of the present invention. Fig. 8 illustrates a timing diagram 800 of the operation of the high efficiency amplifier 200 according to one embodiment of the invention.

As shown in fig. 7, the high efficiency amplifier 200 may further operate in a third positive mode of operation and a third negative mode of operation. If the power supply device is operated in the third positive operation mode, the positive power supply and the negative power supply respectively have a third positive voltage VSP3 (e.g., 2.7V) and a first negative voltage VSN1; if the power supply device is operated in the third negative operation mode, the positive power supply and the negative power supply respectively have a first positive voltage VSP1 and a third negative voltage VSN3 (e.g., -2.7V).

If the power supply device 202 is in the first operation mode (mode 1), the first power voltage is VSP1, and as the driving signal VDRV becomes larger, the distance (voltage difference) between the driving signal VDRV and the first positive voltage VSP1 becomes smaller, and when the difference between the positive power VSP (the first positive voltage VSP1 when the power and the load current change are ignored) and the output signal VDRV is smaller than the first positive threshold VTP1 (time T1), the mode control circuit 203 controls the power supply device 202 to enter the second positive operation mode (mode 2+), and the first power voltage of the power supply device 202 is rapidly increased to VSP2, so as to prevent the driving signal from being clipped and distorted. The negative power supply VSN still maintains the negative first negative voltage VSN1 to reduce power consumption.

If the power supply 202 is in the second positive mode (modulo 2+), the first power terminal voltage is VSP2. As the driving signal VDRV gradually increases, the distance (voltage difference) between the driving signal VDRV and the second positive voltage VSP2 becomes smaller, and when the difference between the positive power VSP (the second positive voltage VSP2 is usually the second positive voltage when the power and load current changes are ignored) and the output signal VDRV is smaller than the fourth positive threshold VTP4 (time T2), the mode control circuit 203 controls the power supply 202 to enter the third positive operation mode (mode 3+), and the voltage of the first power terminal of the power supply 202 is rapidly increased to the third positive voltage VSP3 to prevent the driving signal from being clipped and distorted. The negative power supply VSN still maintains the negative power supply VSN1 to reduce power consumption. In some embodiments, the first positive voltage VSP1 of the power supply device is substantially fixed and does not change with the input power of the power supply device (e.g., BUCK or BOOST with closed loop control), and the mode control circuit 203 can only monitor the magnitude of the driving signal VDRV without monitoring the distance between the driving signal VDRV and the positive power VSP. The power supply device may enter the second operation mode directly based on the magnitude of the driving signal VDRV, i.e. when the driving signal VDRV increases to the first positive number VP1, the mode control circuit 203 will control the power supply device 202 to enter the second positive operation mode; when the drive signal VDRV increases to the second positive number VP2, the mode control circuit 203 will control the power supply 202 to enter the third positive operation mode.

When the power supply device 202 operates in the third positive operation mode, the voltage value of the positive power supply provided by the first terminal is the third positive voltage VSP3, but as the driving signal VDRV decreases, the power amplifier 202 continues to use such high positive voltage VSP3 to generate energy waste. Therefore, when the driving signal VDRV decreases to the fifth positive threshold VTP5 (time T3), the mode control circuit 203 causes the power supply apparatus 202 to jump out of the third positive operation mode.

When the power supply 202 jumps out of the third positive mode of operation, the second mode of operation may not be entered first, but rather the second positive sleep mode, during which the power supply 202 stops or reduces the supply of power to the capacitor coupled to its first output. Due to the effect of the storage of the output capacitance (of the charge), the voltage of the first output terminal of the power supply device 202 will be gradually reduced by VSP3, and when the positive power supply of the power supply device is reduced to the sixth positive threshold VTP6 (at time T4), the mode control circuit will decide whether to enter the second positive operation mode or to continue to sleep according to the condition of the audio signal at this time. According to one embodiment of the present invention, if the driving signal VDRV is smaller than the second positive threshold (VTP 2), as shown in fig. 8, the first positive sleep mode is entered. If the driving signal VDRV is greater than the second positive threshold (VTP 2), as shown in fig. 7, the mode control circuit will make the power supply device 202 go out of the sleep mode and enter the second positive operation mode.

When the power supply device 202 operates in the second positive operation mode, the voltage value of the positive power supply provided by the first end is the third positive voltage VSP2, and as the driving signal VDRV further decreases, the power amplifier 202 continues to use such high positive voltage VSP2 as the positive power supply, which generates energy waste. Therefore, when the driving signal VDRV decreases to the second positive threshold VTP2 (time T5), the mode control circuit 203 causes the power supply apparatus 202 to jump out of the second positive operation mode.

When the power supply 202 jumps out of the second positive mode of operation, the first mode of operation may not be entered first, but rather the first positive sleep mode, during which the power supply 202 stops or reduces the supply of power to the capacitor coupled to its first output. Due to the effect of the storage of the output capacitance (of the charge), the voltage of the first output terminal of the power supply device 202 will be gradually reduced by VSP2, and when the positive power supply of the power supply device is reduced to the third positive threshold VTP3 (at time T6), the mode control circuit 203 causes the power supply device to go out of the sleep mode and enter the first operation mode.

Based on the same principle, if the power supply device 202 is in the first operation mode, the voltage of the second power terminal is VSN1, and as the driving signal VDRV becomes larger, the distance (voltage difference) between the driving signal VDRV and the first negative voltage VSN1 becomes smaller, and when the voltage value of the negative power supply VSN (the difference between the first negative voltage VSN1 and the output signal VDRV is smaller than the first negative threshold VTN1 when the voltage value is ignored as the power supply and the load current change) (time T7), the mode control circuit 203 will control the power supply device 202 to enter the second negative operation mode, and the voltage of the second power terminal of the power supply device 202 is rapidly increased to VSN2, so as to prevent the driving signal from being clipped and further distorted. The positive power supply VSP still maintains the first positive voltage VSP1 to reduce power consumption.

If the power supply 202 is in the second negative mode (mode 2-), the second power terminal voltage is VSN2. As the driving signal VDRV gradually (negatively) increases, the distance (voltage difference) between the driving signal VDRV and the second negative voltage VSN2 becomes smaller, and when the difference between the voltage value of the negative power source VSN (the second negative voltage VSN2 is usually the second negative voltage VSN2 when the power source and the load current are ignored) and the output signal VDRV is smaller than the fourth negative threshold VTN4 (time T8), the mode control circuit 203 controls the power supply device 202 to enter the third negative working mode (mode 3-), so as to prevent the voltage of the second power source terminal of the power supply device 202 from rapidly increasing to the third negative voltage VSN3, thereby preventing the driving signal from being clipped and further distorted. The positive power supply VSP still maintains the first positive voltage VSP1 to reduce power consumption. In some embodiments, the first negative voltage VSN1 of the power supply device is substantially fixed and does not change with the input power of the power supply device (e.g., using a closed-loop control BUCK), and the mode control circuit 203 can only monitor the magnitude of the driving signal VDRV without monitoring the distance between the driving signal VDRV and the negative power supply VSN. The power supply device may enter the second operation mode directly based on the magnitude of the driving signal VDRV, i.e. when the driving signal VDRV increases to the first negative number VN1, the mode control circuit 203 will control the power supply device 202 to enter the second negative operation mode; when the drive signal VDRV increases to the second negative number VN2, the mode control circuit 203 will control the power supply 202 into the third negative mode of operation.

When the power supply device 202 operates in the third negative operation mode, the voltage value of the negative power supply provided by the second end is the third negative voltage VSN3, and as the driving signal VDRV decreases, the power amplifier 202 continues to use such high negative voltage VSN3 to generate energy waste. Therefore, when the driving signal VDRV decreases to the fifth negative threshold VTN5 (timing T9), the mode control circuit 203 causes the power supply apparatus 202 to go out of the third negative operation mode.

When the power supply 202 jumps out of the third negative mode of operation, the second mode of operation may not be entered first, but rather the second negative sleep mode, during which the power supply 202 stops or reduces the supply of power to the capacitor (e.g. capacitor C2) coupled to its second output. Due to the effect of the storage (charge) of the output capacitor, the voltage of the second output terminal of the power supply device 202 will be gradually reduced by VSN3, and when the negative power supply of the power supply device is reduced to the sixth negative threshold VTN6 (at time T10), the mode control circuit will determine whether to enter the second operation mode or to continue to sleep according to the condition of the driving signal VDRV at this time.

According to one embodiment of the present invention, if the driving signal VDRV (at point a in fig. 7) is smaller than the second negative threshold VTN2 (at point B in fig. 7), the power supply device 202 will continue to sleep (or enter the first negative sleep mode). During this time, the power supply 203 stops or reduces the capacitive power supply to its second output terminal coupling. Due to the effect of the output capacitance storage (of the charge) etc., the voltage at the second output terminal of the power supply device 202 will gradually decrease from VSN2 (near ground potential), when the negative power supply of the power supply device decreases to the third negative threshold VTN3 (time T10), the power supply device will jump out of the sleep mode and enter the first operation mode.

According to an embodiment of the present invention, if the driving signal VDRV is greater than the second negative threshold VTN2, as shown in fig. 8, the mode control circuit 203 will make the power supply device 202 jump out of the second negative sleep mode and enter the second negative working mode. If the power supply 202 is in the second negative operation mode, the voltage of the first power terminal is VSN2. As the drive signal is further reduced, continued use of such a high negative voltage VSN2 by the power amplifier 202 will result in energy waste. Therefore, when the driving signal VDRV decreases to the second negative threshold VTN2 (at time T5 in fig. 5), the mode control circuit 203 causes the power supply apparatus 202 to jump out of the second negative operation mode. When the power supply 202 jumps out of the second negative mode of operation, the first mode of operation may not be entered first, but rather the first negative sleep mode, during which the power supply 202 stops or reduces the supply of power to the capacitor coupled to its second output. Due to the effect of the storage of the output capacitance (of the charge), the voltage of the second output terminal of the power supply device 202 will gradually decrease from VSN2, and when the positive power supply of the power supply device decreases to the third negative threshold VTN3 (at time T6 in fig. 5), the mode control circuit 203 causes the power supply device to go out of the sleep mode and enter the first operation mode.

As shown in fig. 8, the present invention further provides a method 800 of controlling the power supply device 202 of an amplifier, the amplifier receiving an input signal VIN and providing a driving signal VDRV at an output, the power supply device 202 providing a positive power supply and a negative power supply to the amplifier 201, the method 800 comprising:

if the input signal is zero or substantially small, the power supply device operates in the first operation mode (mode 1), the positive power supply has a first positive voltage VSP1, and the negative power supply has a first negative voltage VSN1.

The power supply device works in a first working mode: when the driving signal VDRV rises to a first positive number VP1 or when the driving signal VDRV rises to a first positive threshold VTP1 from the positive power supply VSP, the control power supply 202 enters a second positive operating mode (modulo 2+), the positive power supply VSP has a second positive voltage VSP2 and the negative power supply has a first negative voltage VSN1.

The power supply device works in a second positive working mode: if the driving signal VDRV increases, when the driving signal VDRV increases by a second positive number VP2, and when the driving signal VDRV increases to a fourth positive threshold VTP4 from the positive power supply VSP, the power supply device is controlled to enter a third positive operation mode (modulo 3+), the positive power supply VSP has a third positive voltage VSP3, and the negative power supply has a first negative voltage VSN1; in the second positive operation mode, if the driving signal VDRV is not increased but decreased, the power supply apparatus 202 is controlled to enter the first positive sleep mode (dormant 1+) when the driving signal VDRV is decreased to the second positive threshold VTP 2.

The power supply device operates in the third positive operation mode, and enters the second positive sleep mode (sleep 2+) when the input signal decreases to the fifth positive threshold VTP 5.

If the power supply device works in the second positive sleep mode, when the positive power supply is reduced to a sixth positive threshold value VTP6, a first positive judgment is carried out, and if the driving signal VDRV is smaller than the second positive threshold value VTP2, the power supply device enters the first positive sleep mode (sleep 1+); if the driving signal VERV is greater than the second positive threshold value VTP2, the second positive working mode is entered.

If the power supply device works in the first positive sleep mode, if the positive power supply is reduced to a second positive threshold value VTP2, the first working mode is entered.

Wherein the third positive voltage VSP3 is greater than the second positive voltage VSP2, the second positive voltage VSP2 is greater than the first positive voltage VSP1, the fifth positive threshold VTP5 is greater than the second positive threshold VTP2, and the sixth positive threshold VTP6 is greater than the third positive threshold VTP3.

According to one embodiment of the invention, the control method 800 further comprises:

the power supply device works in a first working mode: when the driving signal VDRV rises to the first negative number VN1 or when the driving signal VDRV rises to the first negative threshold VTN1 from the negative power supply VSN, the control power supply 202 enters the second negative operation mode (mode 2-), the negative power supply VSN has the second negative voltage VSN2, and the positive power supply VSP has the first positive voltage VSP1.

The power supply device works in a second negative working mode: if the driving signal VDRV increases, when the driving signal VDRV increases by a second negative number V2, when the driving signal VDRV increases to a fourth negative threshold VTN4 from the negative power supply VSN, the power supply device is controlled to enter a third negative working mode (mode 3-), the negative power supply VSN has a third negative voltage VSN3, and the positive power supply VSP has a first positive voltage VSP1; in the second negative operation mode, if the driving signal VDRV is not increased but decreased, the power supply apparatus 202 is controlled to enter the first negative sleep mode (sleep 1-) when the driving signal VDRV is decreased to the second negative threshold VTN 2.

The power supply device operates in the third negative operation mode, and enters the second negative sleep mode (sleep 2-) when the input signal decreases to the fifth negative threshold VTN 5.

If the power supply device works in the second negative sleep mode, when the negative power supply is reduced to a sixth negative threshold value VTN6, performing first negative judgment, and if the driving signal VDRV is smaller than the second negative threshold value VTN2, the power supply device enters the first negative sleep mode (sleep 1-); if the driving signal VERV is greater than the second negative threshold VTN2, the second negative working mode is entered.

If the power supply device works in the first negative sleep mode, if the negative power supply is reduced to the second negative threshold value VTN2, the first working mode is entered.

Wherein the third negative voltage VSN3 is greater than the second negative voltage VSN2, the second negative voltage VSN2 is greater than the first negative voltage VSN1, the fifth negative threshold VTN5 is greater than the second negative threshold VTN2, and the sixth negative threshold VTN6 is greater than the third negative threshold VTN3.

According to one embodiment of the present invention, the power supply 202 also has a positive N mode of operation and a negative N mode of operation,

if the power supply 202 is operating in the nth positive mode, the positive power source and the negative power source have an nth positive voltage and a first negative voltage, respectively; if the power supply 202 is operating in the nth negative mode, the positive power source and the negative power source have a first positive voltage and an nth negative voltage, respectively; wherein N is greater than 3, the Nth positive voltage is greater than the (N-1) th positive voltage, and the Nth negative voltage is greater than the (N-1) th negative voltage.

The use of the terms "a," "an," and the like in this disclosure do not exclude a plurality. The terms "first," "second," and the like herein merely denote the order of appearance in the description of the embodiments, in order to distinguish one element from another. The presence of "first" and "second" in the claims is only for the purpose of facilitating a quick understanding of the claims and is not intended to be limiting. Any reference signs in the claims shall not be construed as limiting the scope.

Claims

1. A dynamic power amplifier, comprising:

the power amplifier is provided with a first input end, a second input end, an output end, a first power end and a second power end, wherein the first power end receives positive power, the second power end receives negative power and the output end provides a driving signal;

the power supply device is provided with a control end, a first output end for providing positive power and a second output end for providing negative power, wherein the first output end is coupled to the first power end of the power amplifier, and the second output end is coupled to the second power end of the power amplifier;

a mode control circuit having a first sampling terminal, a second sampling terminal, a third sampling terminal, and an output terminal, wherein the first sampling terminal is coupled to the first output terminal of the power supply device, the second sampling terminal is coupled to the second output terminal of the power supply device, the third sampling terminal is coupled to one input terminal of the power amplifier, and the output terminal is coupled to the control terminal of the power supply device, the mode control circuit controlling an operation mode of the power supply device based on the power amplifier driving signal and the power supply device output voltage;

if the power supply device works in a first mode, the positive power supply and the negative power supply respectively have a first positive voltage and a first negative voltage; if the power supply device works in a second positive mode, the positive power supply and the negative power supply respectively have a second positive voltage and a first negative voltage; if the power supply device works in a second negative mode, the positive power supply and the negative power supply respectively have a first positive voltage and a second negative voltage; wherein the second positive voltage is greater than the first positive voltage, the second negative voltage is greater than the first negative voltage, wherein,

If the input signal of the power amplifier is zero, the power supply device works in a first mode;

if the power supply device is in a first working mode, when the positive power supply rises to a first positive number or the difference between the positive power supply and the driving signal is smaller than a first positive threshold value, the power supply device enters a second positive working mode;

if the power supply device is in the second working mode, when the driving signal is reduced to a second positive threshold value, the power supply device jumps out of the second positive working mode and enters a first positive dormancy mode;

and if the power supply device is in the first positive sleep mode, when the positive power supply of the power supply device is reduced to a third positive threshold value, the power supply device enters a first working mode.

2. The dynamic power amplifier of claim 1, wherein the power amplifier comprises

The first amplifier is provided with a first input end, a second input end, an output end, a first power end and a second power end, wherein the first power end receives a positive power supply, the second power end receives a negative power supply, and the output end provides a driving signal;

a first resistor having a first end and a second end, the first end of the first resistor is coupled to the first input end of the power amplifier, and the second end of the first resistor is coupled to the first input end of the first amplifier;

A second resistor having a first end and a second end, the first end of the second resistor being coupled to the second input end of the power amplifier, the second end of the second resistor being coupled to the second input end of the first amplifier;

a third resistor having a first end and a second end, the first end of the third resistor is coupled to the first input end of the first amplifier, and the second end of the third resistor is coupled to the ground; and

and a fourth resistor having a first end and a second end, wherein the first end is coupled to the second input end of the first amplifier, the second end is coupled to the output end of the power amplifier, and the ratio of the first resistance to the third resistance is equal to the ratio of the second resistance to the fourth resistance.

3. The dynamic power amplifier of claim 1, wherein,

if the power supply device is in a first working mode, when the negative power supply rises to a first negative number or the difference between the negative power supply and the driving signal is smaller than a first negative threshold value, the power supply device enters a second negative working mode;

if the power supply device is in the second negative working mode, when the driving signal is reduced to a second negative threshold value, the power supply device jumps out of the second negative working mode and enters the first negative sleep mode;

And if the power supply device is in the first negative sleep mode, when the negative power supply of the power supply device is reduced to a third negative threshold value, the power supply device enters the first working mode.

4. The dynamic power amplifier of claim 3, wherein the second positive threshold and the third positive threshold are first positive voltages, the second negative threshold and the third negative threshold are first negative voltages, the first positive voltages and the first negative voltages are equal in magnitude and opposite in polarity.

5. The dynamic power amplifier of claim 1, wherein the mode control circuit comprises:

a sixth resistor having a first end and a second end, the first end coupled to the first input of the power amplifier;

a seventh resistor having a first end and a second end, the first end coupled to the sixth resistor second end;

a first current source having a first terminal and a second terminal, the first terminal coupled to the second terminal of the seventh resistor, and the second terminal coupled to the ground terminal;

a first comparator having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the second terminal of the sixth resistor, the second terminal is coupled to the first output terminal of the power supply device through the eighth resistor, and the output terminal provides a positive-going and a negative-going signal;

A second comparator having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the second terminal of the seventh resistor, the second terminal is coupled to the second output terminal of the power supply device through a ninth resistor, and the output terminal provides a negative-working signal;

a tenth resistor having a first end and a second end, wherein the first end is coupled to the second end of the first comparator, and the second end is coupled to a first reference voltage; and

an eleventh resistor having a first end coupled to the second end of the second comparator and a second end coupled to the first reference voltage.

6. The dynamic power amplifier according to claim 5, wherein the power amplifier has a voltage amplification factor A, a ratio of the tenth resistance to the eighth resistance is P, a ratio of the eleventh resistance to the ninth resistance is Q,

7. the dynamic power amplifier of claim 5, wherein the mode control circuit further comprises,

a third comparator having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the first input terminal of the power amplifier, the second terminal is coupled to the second reference voltage, and the output terminal is provided with a positive one-rest signal;

A fourth comparator having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the second input terminal of the power amplifier, the second terminal is coupled to a third reference voltage, and the output terminal provides a negative one-stop signal;

a fifth comparator having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the second terminal of the first comparator, the second terminal receives a fourth reference voltage, and the output terminal provides a positive one-rest signal; and

the sixth comparator is provided with a first input end, a second input end and an output end, wherein the first input end is coupled to the second end of the second comparator, the second end receives a fifth reference voltage, and the output end provides a negative one-rest signal.

8. The dynamic power amplifier of claim 7, wherein the ratio of the tenth resistance to the eighth resistance is P, the voltage amplification of the power amplifier is a, the ratio of the eleventh resistance to the ninth resistance is Q, the first reference voltage (VRF 1), the second reference voltage (VRF 2), the third reference voltage (VRF 3), the fourth reference voltage (VRF 4), the fifth reference voltage (VRF 5), the first positive voltage (VSP 1), and the first negative voltage (VSN 1) satisfy

9. The dynamic power amplifier of claim 8, wherein the mode control circuit comprises a control circuit having a first input coupled to the output of the first comparator for receiving the positive two-way signal, a second input coupled to the output of the second comparator for receiving the negative two-way signal, a third input coupled to the output of the third comparator for receiving the positive one-way signal, a fourth input coupled to the output of the fourth comparator for receiving the negative one-way signal, a fifth input coupled to the output of the fifth comparator for receiving the positive one-way signal, a sixth input coupled to the output of the sixth comparator for receiving the negative one-way signal, and an output for providing a control signal to control the mode of operation of the power supply;

when the positive reworking signal is enabled, the power supply device enters a second positive working mode; when the negative secondary signal is enabled, the power supply device enters a second negative working mode; when the positive one-rest signal is enabled, the power supply device jumps out of the second positive working mode and enters the first positive dormancy mode; when the negative one-rest signal is enabled, the power supply device jumps out of the second negative working mode and enters the first negative sleep mode; when the positive one-rest signal is enabled, the power supply device jumps out of the first positive sleep mode and enters a first working mode; when the negative one-rest signal is enabled, the power supply device is controlled to jump out of the first negative sleep mode and enter the first working mode.