CN107066392A - For accessing the method for heterogeneous memory and memory module containing heterogeneous memory - Google Patents
For accessing the method for heterogeneous memory and memory module containing heterogeneous memory Download PDFInfo
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- CN107066392A CN107066392A CN201710019237.8A CN201710019237A CN107066392A CN 107066392 A CN107066392 A CN 107066392A CN 201710019237 A CN201710019237 A CN 201710019237A CN 107066392 A CN107066392 A CN 107066392A
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
Abstract
The method that the main storage of a kind of method for accessing volatile memory devices, non-volatile memory device and the controller being controlled to the volatile memory devices and the non-volatile memory device, the cache memory of a kind of memory module and a kind of access first kind and Second Type is provided.The method of access volatile memory devices, non-volatile memory device and the controller being controlled to the volatile memory devices and the non-volatile memory device includes：Receive the row address associated with the volatile memory devices and the non-volatile memory device via First Line in the first timing by the controller；Receive the extended address associated with the non-volatile memory device via the second line in the second timing by the controller；And receive the column address associated with the non-volatile memory device and the volatile memory devices via the 3rd line in the 3rd timing by the controller.
Description
Reference to priority application
Advocate the U.S. Provisional Application No. 62/278 filed an application on January 14th, 2016 in United States Patent (USP) and trademark office,
No. 610, the korean patent application 10-2016-0008210 filed an application on January 22nd, 2016 in Korean Intellectual Property Office
Number, the korean patent application filed an application on January 22nd, 2016 in Korean Intellectual Property Office the 10-2016-0008214th with
And the korean patent application the 10-2016-0029743rd filed an application on March 11st, 2016 in Korean Intellectual Property Office
Priority, the full content of the patent application is hereby incorporated by reference.
Technical field
Concept of the present invention is related to semiconductor memory system, and more specifically to for accessing heterogeneous memory
Method and the memory module for including heterogeneous memory.
Background technology
Semiconductor memory refers to using semiconductor (for example, silicon (Si), germanium (Ge), GaAs (GaAs), indium phosphide
(InP) storage arrangement of implementation etc.) is carried out.Semiconductor memory system is typically categorized into volatile memory devices or non-
Volatile memory devices.
Volatile memory devices refer to that the storage arrangement for the data being stored therein can be lost when power is off.It is described easy
Lose property storage arrangement include static RAM (static random access memory, SRAM), dynamic with
Machine access memory (dynamic random access memory, DRAM), Synchronous Dynamic Random Access Memory etc..It is non-easy
The property lost storage arrangement refers to even if can also remain stored at the storage arrangement of data therein when power is off.It is non-volatile to deposit
Reservoir device includes read-only storage (read only memory, ROM), programmable read only memory (programmable
Read only memory, PROM), EPROM (electrically programmable read only
Memory, EPROM), Electrically Erasable Read Only Memory (electrically erasable and programmable
Read only memory, EEPROM), flash memory device, phase change random access memory devices (phase-change
Random access memory, PRAM), magnetic RAM (magnetic random access memory,
MRAM), resistive random access memory (resistive random access memory, RRAM), ferro-electric random access
Memory (ferroelectric random access memory, FRAM) etc..
Because the reaction speed and the speed of service of dynamic random access memory are generally very fast, therefore dynamic randon access
Memory is widely used as the main storage of system.However, because dynamic random access memory is the number when power supply is closed
According to the volatile memory that can be lost, therefore the number remained stored at using isolated system in dynamic random access memory
According to.Further, since dynamic random access memory use capacitor data storage, and the size of unit cell element be typically it is big,
So as to be difficult to the capacity for increasing dynamic random access memory in limited region.
The content of the invention
The embodiment of concept of the present invention provides one kind to be had by using nonvolatile memory and volatile memory
Large Copacity and high performance non-volatile memory module.
The one side of the embodiment of concept of the present invention is related to a kind of access volatile memory devices of offer, non-volatile
Storage arrangement and the controller that is controlled to the volatile memory devices and the non-volatile memory device
Method, methods described includes：Received and the volatile memory devices via First Line in the first timing by the controller
And the associated row address of the non-volatile memory device；By the controller the second timing via the second line receive with
The associated extended address of the non-volatile memory device；And connect by the controller in the 3rd timing via the 3rd line
Receive the column address associated with the non-volatile memory device and the volatile memory devices.The First Line includes
Second line and the 3rd line.
The another aspect of the embodiment of concept of the present invention is related to a kind of memory module of offer, the memory module bag
Include：Non-volatile memory device；Volatile memory devices；And controller, to control the nonvolatile memory
Device and the volatile memory devices, wherein the controller is received and the volatibility in the first timing via First Line
Storage arrangement and the associated row address of the non-volatile memory device, are received and institute in the second timing via the second line
State the associated extended address of non-volatile memory device, and the 3rd timing via the 3rd line receive with it is described non-volatile
Property the storage arrangement and associated column address of the volatile memory devices.
The embodiment of concept of the present invention relates in one aspect to provide a kind of cache memory for accessing the first kind again
And the method for the main storage of Second Type, methods described includes：Using multiple sequences via the high speed with the first kind
The associated address wire of buffer memory sends shared address to the cache memory of the first kind and institute
State the main storage of Second Type；And
Using at least one sequence via associated with the cache memory of the first kind described
Location line sends extended address to the main storage of the Second Type.
According to the further embodiment of the present invention, operation wherein containing volatile memory devices and non-volatile is deposited
While the method for the accumulator system of reservoir device is included in offer proactive command, via the first address wire to memory control
Device provides the row address associated with the volatile memory devices and the non-volatile memory device.Next, from
The row address is provided and plays beginning, after very first time interval is passed through, via at least some of first ground in the first address wire
Location line provides related to the volatile memory devices and the non-volatile memory device to the Memory Controller
The column address of connection.In addition to the column address is provided, while also via at least additional a plurality of first ground in the first address wire
Location line provides non-volatile extension block address.It is described to the Memory Controller provide column address also can be via the first address
At least some of first address wire in line is performed while activation explosion command is provided to the Memory Controller.
According to some further embodiments of the present invention, it can perform from the volatile memory devices and read mark simultaneously
Then the mark and the non-volatile extension block address are compared to judge the operation of the equivalence between it.Can
Further perform the dirty mark with dirty situation with write-in data while writing into the volatile memory devices
Operation.In addition, reading mark from the volatile memory devices and being marked described and the non-volatile expansion area
Block address is compared after judging to have between it non-equivalence, then to read from the volatile memory devices dirty
Mark.
Brief description of the drawings
Following explanation is read by referring to the following drawings, above-mentioned and other purpose and feature will be easy to understand, wherein
Except as otherwise noted, otherwise identical Ref. No. refers to identical part in all accompanying drawings, and wherein：
Fig. 1 is the block diagram for illustrating the custom system according to conceptual embodiment of the present invention.
Fig. 2 is the block diagram for illustrating the non-volatile memory module shown in Fig. 1.
Fig. 3 is to illustrate wherein to send order and address to based on dual-inline memory module or non-volatile biserial
The timing diagram of the process of the non-volatile memory module of straight cutting memory module.
Fig. 4 is the flow chart for the operation method for illustrating the non-volatile memory module according to conceptual embodiment of the present invention.
Fig. 5 is to illustrate that wherein non-volatile memory module writes the flow of the method for data under the control of a processor
Figure.
Fig. 6 is to illustrate that wherein non-volatile memory module reads the flow of the method for data under the control of a processor
Figure.
Fig. 7 is to illustrate wherein to send order and address to straight based on dual-inline memory module or non-volatile biserial
Insert the timing diagram of the application of the process of the non-volatile memory module of memory module.
Fig. 8 is to illustrate that wherein non-volatile memory module obtains row address, extended address and row from extension proactive command
The flow chart of the method for address.
Fig. 9 is the square for illustrating the non-volatile memory module according to Fig. 1 of another embodiment of concept of the present invention
Figure.
Figure 10 is the flow chart for illustrating the non-volatile memory module shown in operation diagram 9.
Figure 11 is the view for the cache structure for illustrating the volatile memory shown in Fig. 9.
Figure 12 is the timing diagram for elaborating the read operation shown in Figure 10.
Figure 13 is the timing diagram for the implementation for illustrating data and validity information shown in Figure 12.
Figure 14 is the timing diagram for elaborating the read operation shown in Figure 10.
Figure 15 is the timing diagram for the implementation for illustrating data and validity information shown in Figure 14.
Figure 16 is the block diagram of other features of the memory module for illustrating another embodiment according to concept of the present invention.
Figure 17 is the flow chart for illustrating the handshaking procedure between the processor shown in Figure 16 and non-volatile memory module.
Figure 18 is the timing diagram for elaborating the handshake operation shown in Figure 17.
Figure 19 is the block diagram for illustrating the memory module according to Fig. 1 of another embodiment of concept of the present invention.
Figure 20 is the square for illustrating the non-volatile memory module according to Fig. 1 of another embodiment of concept of the present invention
Figure.
Figure 21 is the square for illustrating the non-volatile memory module according to Fig. 1 of another embodiment of concept of the present invention
Figure.
Figure 22 is the square for illustrating the non-volatile memory module according to Fig. 1 of another embodiment of concept of the present invention
Figure.
Figure 23 is the square for illustrating the non-volatile memory module according to Fig. 1 of another embodiment of concept of the present invention
Figure.
Figure 24 is the square for illustrating the non-volatile memory module according to Fig. 1 of another embodiment of concept of the present invention
Figure.
Figure 25 is the square for illustrating the non-volatile memory module according to Fig. 1 of another embodiment of concept of the present invention
Figure.
Figure 26 is the square for illustrating the non-volatile memory module according to Fig. 1 of another embodiment of concept of the present invention
Figure.
Figure 27 is the square for illustrating the non-volatile memory module according to Fig. 1 of another embodiment of concept of the present invention
Figure.
Figure 28 is the square for illustrating the non-volatile memory module according to Fig. 1 of another embodiment of concept of the present invention
Figure.
Figure 29 is to illustrate the nonvolatile memory being included in non-volatile memory module according to concept of the present invention
Block diagram.
Figure 30 is the Cellular structure and physical property for illustrating the phase-changing storage device according to conceptual embodiment of the present invention
View, its as non-volatile memory device example.
Figure 31 to Figure 32 is illustrated according to conceptual embodiment of the present invention comprising memory in the nonvolatile memory
The view of cell element.
Figure 33 is the side for the volatile memory for illustrating the non-volatile memory module according to conceptual embodiment of the present invention
Block figure.
Figure 34 is the side for the custom system for illustrating the application non-volatile memory module according to conceptual embodiment of the present invention
Block figure.
Figure 35 is the server system for illustrating the application Nonvolatile memory system according to conceptual embodiment of the present invention
View.
[explanation of symbol]
10、3000：Custom system
100、200、300、400、500、600、700、800、900、1000、1100、1200、1300、2200：It is non-volatile
Memory module
101、3001：Processor
102：Chipset
103：Graphics processing unit
104：Input/output device
105：Storage device
110、210、310、410：Module controller
120、220、320、420、520、620：Heterogeneous storage arrangement
121、221、321、421、521、621、1800、VM、VM11、VM12、VM13、VM14、VM15、VM1n、VM21、
VM22、VM23、VM24、VM25、VM2m：Volatile memory
122、222、522、622、922、1322：Non-volatile memory controller
123、223、323、523、623、1400、NVM、NVM11、NVM12、NVM13、NVM14、NVM1k、NVM21、
NVM22、NVM23、NVM24、NVM2i：Nonvolatile memory
130、230、330、430、530、630：Data buffer
140、240、340、440：Serially there is detection chip
215、315、415：Cache manger
251、261、351、361：Validity part
252、262、352、362：Transaction ID part
350：Information
822a、1022a、1222a：First non-volatile memory controller
822b、1022b、1222b：Second non-volatile memory controller
1410、1810：Memory cell array
1420：Address decoder
1430：Control logic circuit
1440：Page buffer
1450：Input/output circuitry
1500、1600、1700：Memory cell
1510：Top electrode
1520：Phase-change material
1530：Contact plunger
1540：Hearth electrode
1610：Magnetic tunnel junction element
1611：Free layer
1612：Tunnel layer
1613：Fixed bed
1620：Cell transistor
1710：Variable resistor element
1711、1713：Electrode
1712：Data storage film
1720：Selection element
1820：Address buffer
1830：Row decoder (X- decoders)
1840：Column decoder (Y- decoders)
1850：Sense amplifier and write driver
1860：Input/output circuitry
2000：Server system
2100 server racks
2150：Amorphous volume
3002：Memory Controller
3003：Bus
3110、3140：Memory
A0、A1、A2、A3、A4、A5、A6、A7、A8、A9、A10、A1、A12、A13、A14、A15、A16、A17：Address wire
A10/AP：Auto-precharge signal wire
ACT：Proactive command/storehouse proactive command
ACTe：Extend proactive command
ACT_n：Proactive command input line
ADD、ADDR：Address
ADD_col、CA：Column address
ADD_row、RA：Row address
ADD1：First address
ADD2：Second address
ADDR0：0th address
ADDR1：1st address
ADDR2：2nd address
ADDR3：3rd address
ADDR4：4th address
ADDR5：5th address
ADDR6：6th address
ADDR7：7th address
ADDR8：8th address
ADDR9：9th address
ADDR10：10th address
ADDR11：11st address
ADDR12：12nd address
ADDR13：13rd address
ADDR14：14th address
ADDR15：15th address
ADDR16：16th address
ADDR17：17th address
ADDR18：18th address
ADDR19：19th address
ADDR20：20th address
ADDR21：21st address
ADDR22：22nd address
ADDR23：23rd address
AP：Auto-precharge/auto-precharge signal
BA：Storehouse address
BA0、BA1：Storehouse address input line
BANK1：First storehouse
BANK2：Second storehouse
BANK3：3rd storehouse
BANK4：4th storehouse
BC：Truncated signal is blocked/happened suddenly in burst
BC_n/A12：Happen suddenly truncated signal line
BG：Storehouse group signals
BG0、BG1：Storehouse group input line
BL：Burst-length/bit line
BL0：Bit line
BO0、BO1、BO2：Burst order
BT：Outburst type
C0、C1、C2：Chip identifier line
Cache_INFO：Cache information
CA_n, nonvolatile memory command/address
CA_v：Volatile memory commands/address
CAS：Column address gating signal
CAS_n/A15、RAS_n/A16、WE_n/A14：Order input line
CID：Chip identifier
CKE：Clock enables signal wire/clock signal
CL、CL0、CL1、CL2、CL3：Cache line
CMD、RD：Order
CMD/ADD：Command/address
CMD0：0th order
CMD1：1st order
CMD2：2nd order
CS_n：Chip selection enables signal wire/chip select signal line
CT：Cell transistor
CTRL：Control logic/control signal
D1、D2、D3、D4：Data
DATA_1：First data
DATA_2：Second data
DB：Data buffer
DI：Device information
DL、DQ：Data wire
DRT：Dirty information
DT_v：Data
DQ_INFO：Validity information
EA：Extended address
ECC_DT：Data error correcting code
ECC_TAG：Marked erroneous correction code
EXT：Activate explosion command/storehouse activation explosion command/extension order FC：Special removing channel
G1：First chart
G2：Second chart
H：High level
HMD：Heterogeneous storage arrangement
INFO：Cache information
L：Low level
Line0、Line1、Line2、Line3：Line
MC：Module controller
MDQ：Memory data line
MDQ1：First memory data wire
MDQn：N-th memory data line
MSG_EN、MSG_DQ：Information
NT：Access transistor
NVM_0：First area/memory areas
NVM_1：Second area/memory areas
NVM_2：Three areas/memory areas
NVM_3：Four areas/memory areas
NVM_4：Five areas/memory areas
NVM_5：Six areas/memory areas
NVM_BLK1、NVM_BLK2、NVM_BLKn：Non-volatile extension block
Op Code：Command code
OPT：Option
RAS：Rwo address strobe signals
RD/ADD：Order and address
REV：Retain line
RFU：For the reservation of future usage
RL：Read delay
Rv：Variable resistor element
S11、S12、S13、S14、S15、S21、S22、S23、S24、S25、S26、S27、S28、S29、S110、S120、
S130、S210、S220、S230、S240、S250、S260、S270、S280、S310、S320、S330、S340、S350、S360、
S370、S380、S390、S410、S420、S430：Operation
SL0：Source electrode line
STR：Selection element
TAG、“TAG”_v：Mark
TC：Marking of control circuit
TDQ：Flag data line
TID：Transaction ID
TVM：Mark special volatile memory
V：" H " and one of " L " particular level
VM1：First volatile memory
VMn：N-th volatile memory
WL：Write latency/wordline
WL0：Wordline
X：Definition or undefined (for example, floating) or incoherent level
Embodiment
Fig. 1 is the block diagram for illustrating the custom system according to conceptual embodiment of the present invention.Reference picture 1, custom system 10 is wrapped
Include non-volatile memory module 100, processor 101, chipset 102, graphics processing unit (graphic processing
Unit, GPU) 103, input/output device 104 and storage device 105.In embodiment, custom system 10 can be computing system,
Such as computer, notebook, server, work station, mobile terminals, personal digital assistant (personal
Digital assistant, PDA), portable media player (portable multimedia player, PMP), intelligence
Can mobile phone or wearable device.
Processor 101 can control the integrated operation of custom system 10.Processor 101 can perform the various behaviour of custom system 10
Make and can processing data.
Non-volatile memory module 100 may be connected directly to processor 101.For example, nonvolatile memory mould
Each of block 100 can have the shape of dual-inline memory module (dual in-line memory module, DIMM)
Formula and can be arranged on be connected directly in the dual-inline memory module socket of processor 101, to be led to processor 101
Letter.In embodiment, each of non-volatile memory module 100 can be based on non-volatile dual-inline memory module
Agreement is communicated with processor 101.
Each of non-volatile memory module 100 is used as main storage or working storage, and (or operation is deposited
Reservoir).Each of non-volatile memory module 100 may include nonvolatile memory and volatile memory.It is described
Nonvolatile memory is included even if will not also lose the memory for the data being stored therein when power is off, such as read-only storage
Device (ROM), programmable read only memory (PROM), EPROM (EPROM), electrically erasable is read-only deposits
Reservoir (EEPROM), flash memory, phase change random access memory devices (PRAM), magnetic RAM (MRAM), electricity
Resistive random access memory (RRAM) or ferroelectric RAM (FRAM).The volatile memory may include disconnected
The memory for the data being stored therein, such as static RAM (SRAM), dynamic randon access can be lost when electric
Memory (DRAM) or Synchronous Dynamic Random Access Memory (synchronous dynamic random access
Memory, SDRAM).
In embodiment, the nonvolatile memory in each non-volatile memory module 100 is used as user system
The main storage of system 10 or the main storage of processor 101, and the volatile storage in each non-volatile memory module 100
Device is used as the cache memory of custom system 10, the cache memory of processor 101 or corresponding non-volatile
The cache memory of property memory module 100.
Chipset 102 may be electrically connected to processor 101 and can be under the control of processor 101 to custom system 10 hardware
It is controlled.For example, chipset 102 can be respectively connecting to graphics processing unit 103, input/output dress via main bus
Put 104 and storage device 105 and can to the main bus perform bridge operation (bridge operation).
Graphics processing unit 103 can perform a series of arithmetical operations of the view data for exporting custom system 10.
In embodiment, graphics processing unit 103 can be embedded in processor 101 in the form of on-chip system (system-on-chip, SoC)
In.
Input/output device 104 may include so that by data or instruction input to custom system 10 or by data output
The various devices being possibly realized to external device (ED).For example, input/output device 104 may include user input apparatus (for example
Keyboard, keypad, button, touch panel, touch screen, touch pad, touch ball, camera, microphone, gyro sensor,
Vibrating sensor, piezoelectric element, temperature sensor and biometric sensor) and user's output device (such as liquid crystal display
(liquid crystal display, LCD), Organic Light Emitting Diode (organic light emitting diode,
OLED) display device, active matrix organic light-emitting diode (active matrix organic light emitting
Diode, AMOLED) display device, light emitting diode (light emitting diode, LED), loudspeaker and motor).
Storage device 105 is used as the massive store media of custom system 10.Storage device 105 may include Large Copacity
Storage media (such as hard disk drive (hard disk drive, HDD), solid-state drive (solid state drive,
SSD), memory card and memory stick).
Fig. 2 is the block diagram for illustrating the non-volatile memory module shown in Fig. 1.Reference picture 1 and Fig. 2, it is non-volatile to deposit
Memory modules 100 include module controller 110, heterogeneous storage arrangement 120, data buffer (data buffer, DB) 130
And serially there is detection chip (serial presence detect, SPD) 140.
Module controller 110 can receive command/address CA from processor 101 and may be in response to received command/address
CA and control heterogeneous storage arrangement 120.For example, module controller 110 may be in response to the order from processor 101/
Address CA and to heterogeneous storage arrangement 120 provide command/address CA_n and command/address CA_v.
In embodiment, command/address CA_n can be non-volatile included in heterogeneous storage arrangement 120 for controlling
Property memory 123 command/address, and command/address CA_v can be for control be included in heterogeneous storage arrangement 120 in
The command/address of volatile memory 121.
Hereinafter, for the sake of for ease of illustration, the command/address CA from processor 101 can be referred to as " module command/ground
Location ", slave module controller 110, which is provided to the command/address CA_v of volatile memory 121, can be referred to as " volatile memory
(volatile memory, VM) command/address ", and slave module controller 110 provided to nonvolatile memory
The command/address CA_n of (nonvolatile memory, NVM) controller 122 can be referred to as " nonvolatile memory (NVM)
Command/address ".
In embodiment, nonvolatile memory command/address CA_n can be provided via different command/address bus
And volatile memory commands/address CA_v.
In embodiment, module controller 110 can for register clock driver (register clock driver,
RCD)。
Heterogeneous storage arrangement 120 may include volatile memory 121, non-volatile memory controller 122 and it is non-easily
The property lost memory 123.Volatile memory 121 may be in response to volatile memory commands/address from module controller 110
CA_v and run.Volatile memory 121 may be in response to volatile memory commands/address CA_v and respectively via memory number
Come output data and mark " TAG " according to line MDQ and flag data line TDQ.Volatile memory 121 can be based on volatile memory
Command/address CA_v write-ins are respectively via the memory data line MDQ and flag data line TDQ data received and mark.
Non-volatile memory controller 122 may be in response to the nonvolatile memory order from module controller 110/
Address CA_n and run.For example, it is non-based on the nonvolatile memory command/address CA_n from module controller 110
Volatile memory controller 122 can be in nonvolatile memory 123 to entering via the memory data line MDQ data received
Row programming can export the data in nonvolatile memory 123 by programming via memory data line MDQ.
Non-volatile memory controller 122 can perform the various operations for controlling nonvolatile memory 123.Citing
For, non-volatile memory controller 122 can perform such as refuse collection, loss balancing (wear leaveling) and address
Conversion etc. operates that nonvolatile memory 123 is efficiently used.In embodiment, non-volatile memory controller 122 can
Further comprise the element such as error correcting circuit and randomizer (randomizer).
In embodiment, non-volatile memory controller 122 can will be contained in received nonvolatile memory life
Address in order/address CA_n is used as the logical address of nonvolatile memory 123.Non-volatile memory controller 122 can
The logical address is converted into the physical address of nonvolatile memory 123 and the converted physical address can be sent
To nonvolatile memory 123.Deposited in addition, non-volatile memory controller 122 can will be contained in received non-volatile
Order in reservoir command/address CA_n be converted into for nonvolatile memory 123 order and can will be described converted
Order is sent to nonvolatile memory 123.In embodiment, non-volatile memory controller 122 can via with memory
Data wire MDQ, flag data line TDQ, the line for sending nonvolatile memory command/address CA_n and transmission volatile memory
The line of command/address CA_v line separation to nonvolatile memory 123 provides the converted physical address and order.
In embodiment, volatile memory 121 can share same memory number with non-volatile memory controller 122
According to line MDQ.
In embodiment, volatile memory 121 can share flag data line TDQ with module controller 110.As in addition
One kind selection, volatile memory 121, non-volatile memory controller 122 and module controller 110 can share flag data
Line TDQ.Non-volatile memory controller 122 or module controller 110 can be via flag data line TDQ output tokens " TAG "
Or mark " TAG " can be received via flag data line TDQ.
Data buffer 130 can receive data via memory data line MDQ and be able to will be received via data wire DQ
Data are provided to processor 101.Alternatively, data buffer 130 can receive data via data wire DQ and can
Received data is exported via memory data line MDQ.In embodiment, data buffer 130 may be in response to module control
The control (for example, buffer order (not shown)) of device 110 and run.In embodiment, data buffer 130 can distinguish storage
The signal on signal and data wire DQ on device data wire MDQ.Alternatively, data buffer 130 can stop and deposit
Signal between memory data line MDQ and data wire DQ.That is, passing through data buffer 130, memory data line MDQ
Signal can not influence data wire DQ, or by data buffer 130, data wire DQ signal can not influence memory data line
MDQ。
In embodiment, memory data line MDQ can be included in nonvolatile memory (for example, volatile memory,
Nonvolatile memory, data buffer etc.) in element between data transfer path, and data wire DQ can be non-volatile
Data transfer path between memory module 100 and processor 101.Flag data line TDQ can be for sending and receiving mark
Remember the transmission path of " TAG ".
In embodiment, each of memory data line MDQ, data wire DQ and flag data line TDQ may include many
Bar wire.Although in addition, not shown, each of memory data line MDQ, data wire DQ and flag data line TDQ can
Including memory data select lines MDQS, data strobe line DQS and flag data select lines TDQS.Hereinafter, for ease of explanation,
Eliminate memory data select lines MDQS, data strobe line DQS and flag data select lines TDQS Ref. No. and configuration.
However, the embodiment of concept of the present invention can be not limited to that.For example, selected with memory data select lines MDQS, data
Logical line DQS and the element of flag data select lines TDQS connections can with memory data select lines MDQS, data strobe line DQS and
Flag data select lines TDQS signal synchronously sends and received data or mark.
Serially there is detection chip 140 (can deposit for programmable read only memory device for example, electrically erasable is read-only
Reservoir (EEPROM)).Serially there is detection chip 140 may include the initial information or device of non-volatile memory module 100
Information DI.In embodiment, serially there is detection chip 140 may include device information DI (such as with nonvolatile memory mould
Block 100 associated modular form, module configuration, memory capacity, module type and performing environment).Deposited when including non-volatile
When the custom systems 10 of memory modules 100 starts, can be from serially there is the reading device information DI of detection chip 140 in processor 101
And non-volatile memory module 100 can be recognized based on device information DI.Processor 101 can be based on from serially there is detection chip
The 140 device information DI read control non-volatile memory module 100.
Hereinafter, for the sake of for ease of illustration, it is assumed that volatile memory 121 is dynamic random access memory and non-volatile
The right and wrong flash memory of memory 123.However, the embodiment of concept of the present invention is not limited to that.For example, volatibility
Memory 121 may include the random access memory of another species, and nonvolatile memory 123 may include the non-of another species
Volatile memory devices.In embodiment, nonvolatile memory 123 may include phase transition storage.
In embodiment, volatile memory 121 may include multiple volatile memory chips, and the multiple volatibility is deposited
Each of memory chip carries out implementation by independent chip, independent encapsulation etc..Volatile memory chip can be via not
Same memory data line or different flag data lines enters with module controller 110 or non-volatile memory controller 122
Row connection.
In embodiment, the nonvolatile memory 123 of non-volatile memory module 100 can be used as by processor 101
Main storage.That is, the memory space of nonvolatile memory 123 can be recognized as main storage area by processor 101.Easily
The property lost memory 121 can be stored as the cache memory of processor 101 and the cache of nonvolatile memory 123
Device is run.In embodiment, volatile memory 121 is used as write-back cache (write-back cache).
That is, module controller 110 may be in response to the module command from processor 101/address CA to judge that cache is ordered
In or cache-miss and volatile memory 121 or nonvolatile memory 123 can be controlled based on judged result.
In embodiment, the cache hit can represent module command/CA pairs of address with being received from processor 101
Situation of the data storage answered in volatile memory 121.The cache-miss can represent not with from processor
101 module command/situations of the CA corresponding data storages in address in volatile memory 121 received.
In embodiment, module controller 110 can judge whether occur cache hit or height based on mark " TAG "
Fast cache miss.Module controller 110 can based on to the module command from processor 101/address CA with mark " TAG " enter
Row result of the comparison judges whether to occur cache hit or cache-miss.
In embodiment, mark " TAG " may include the corresponding with the data being stored in volatile memory 121 of address
A part.In embodiment, module controller 110 can will mark " TAG " and volatile memory via flag data line TDQ
121 swap.In embodiment, when writing data into volatile memory 121, mark corresponding with the data
" TAG " can write under the control of module controller 110 together with the data.
In embodiment, volatile memory 121 can have n with nonvolatile memory 123：1 direct mapping relations.This
Place, " n " is natural number.That is, volatile memory 121 can be slow at a high speed for the direct mapping of nonvolatile memory 123
Deposit.For example, the first volatile storage area of volatile memory 121 may correspond to the first of nonvolatile memory 123
Nonvolatile storage to the n-th nonvolatile storage.In this case, the big I of the first volatile storage area with it is non-
The size of each of volatile storage area is identical.In embodiment, the first volatile storage area can further comprise
Region for storing additional information (for example, mark, error correcting code, dirty information etc.).
In embodiment, volatile memory 121 can have n with nonvolatile memory 123：K in groups close by relationship maps
System.Herein, " k " is less than the natural number of " n ".That is, volatile memory 121 can be nonvolatile memory 123
Into set-associative cache.
Although not shown in FIG. 2, non-volatile memory module 100 can further comprise that single memory (does not show
Go out).The single memory be storable in used in non-volatile memory controller 122 information (such as data, program and
Software).For example, the single memory can store the information managed by non-volatile memory controller 122 and (for example reflect
Firing table and flash translation layer (flash translation layer, FTL)).Alternatively, the independent storage
Data or will be stored in nonvolatile memory 123 that device can read for interim storage from nonvolatile memory 123
The buffer storage of data.
Volatile memory 121 may include the first storehouse BANK1 to the 4th storehouse BANK4.First storehouse BANK1 to the 4th storehouse
BANK4 can perform write operation independent of each other and read operation.For example, the first storehouse BANK1 to the 4th storehouse BANK4 can be right
Ying Yu is by Double Data Rate dynamic random access memory (double data rate dynamic random access
Memory, DDR DRAM) the storehouse that defines of specification.
Processor 101 can be accessed based on dual-inline memory module (DIMM) or non-volatile lilline Memory mould
The non-volatile memory module 100 of block (nonvolatile dual in-line memory module, NVDIMM).Biserial
Straight cutting memory module or non-volatile dual-inline memory module can have to be deposited with Double Data Rate dynamic randon access
The associated order system of reservoir and address system.Alternatively, to enable processor 101 to access dual-in-line
The nonvolatile memory 123 of memory module or non-volatile dual-inline memory module, nonvolatile memory 123 can
With based on the first storehouse BANK1 to the 4th storehouse defined in the specification as Double Data Rate dynamic random access memory
BANK4 and the address system organized.For example, the memory space of nonvolatile memory 123 may include multiple non-volatile
Extend block NVM_BLK1 to NVM_BLKn.The multiple non-volatile extension block NVM_BLK1 is each into NVM_BLKn
Person may include the first storehouse BANK1 to the 4th storehouse BANK4.
The memory space of nonvolatile memory 123 can be recognized as non-volatile memory module 100 by processor 101
Memory space.Processor 101 can be accessed based on dual-inline memory module or non-volatile dual-inline memory module
Non-volatile memory module 100.However, the boundary of dual-inline memory module or non-volatile dual-inline memory module
Face is defined as consistent with Double Data Rate dynamic random access memory.For example, lilline Memory
Module or non-volatile dual-inline memory module are provided the first storehouse BANK1 to the 4th storehouse of volatile memory 121
Address system that BANK4 (or storehouse group) is distinguished and do not provide can be by the multiple non-volatile extension block NVM_BLK1
The address system distinguished to NVM_BLKn.
That is, non-volatile memory module 100 is based on traditional dual-inline memory module or non-wherein
Volatibility dual-inline memory module will be described come processor 101 during in the situation run, may alternatively appear in accessing operation
The problem of multiple non-volatile extension block NVM_BLK1 to NVM_BLKn are distinguished.
In order to solve this problem, according to the embodiment of concept of the present invention, non-volatile memory module 100 provides one kind
Solution, in the solution, using optional signal or can route selection as it is non-volatile extension block address (or extension
Address) with will be the multiple in the address system of dual-inline memory module or non-volatile dual-inline memory module
Non-volatile extension block NVM_BLK1 to NVM_BLKn is distinguished.
Fig. 3 is to illustrate wherein to send order and address to straight based on dual-inline memory module or non-volatile biserial
Insert the timing diagram of the process of the non-volatile memory module of memory module.Show to be transferred into module control in Fig. 2 and Fig. 3
The proactive command input line ACT_n and address wire A0 to address wire A17 of device 110 processed signal and it is transferred into data buffer
130 data wire DQ signal.For ease of illustration for the sake of, do not show to be used for the first storehouse BANK1 to the 4th storehouse in figure 3
The storehouse address that BANK4 is distinguished.
, can be via the 0th address when receiving proactive command (or active signal) ACT via proactive command input line ACT_n
Line A0 to the 17th address wire A17 provides the 0th address AD DR0 to the 17th address AD DR17 (for example, address to module controller 110
Signal).In embodiment, the 1st address AD DR1 to the 17th address AD DR17 may make up row address, in volatile storage
The row in selected storehouse or the institute for selecting selected non-volatile extension block in nonvolatile memory 123 are selected in device 121
Select the row in storehouse.Proactive command ACT may indicate that via the 0th address wire A0 to the 17th address wire A17 signals received be row address.
, can be via the 0th address wire A0 to the 17th if having passed through the pre-defined time from input proactive command ACT
Address wire A17 receives ensuing signal.The signal received via the 14th address wire A14 to the 16th address wire A16 can be the 0th life
CMD0 to the 2nd is made to order CMD2.The signal received via the 4th address wire A4 to the 9th address wire A9 can be the 18th address AD DR18
To the 23rd address AD DR23.For example, the 18th address AD DR18 to the 23rd address AD DR23 may make up column address, for
The row in selected storehouse are selected in volatile memory 121 or for selecting selected non-volatile expansion in nonvolatile memory 123
The row in the selected storehouse of exhibition section block.
Burst order BO0 to BO2 is may indicate that via the 0th address wire A0 to the 2nd address wire A2 signals received.Citing comes
Say, burst order BO0 to BO2, which may indicate that, to be received according to burst-length that is pre-defined or being individually determined or output data
The order of data segment during section.Outburst type BT is may indicate that via the 3rd address wire A3 signals received.Outburst type BT may include
" succession " or " intersection ".12nd address wire A12 may indicate that (burst chopping) BC is blocked in burst.BC is blocked in burst
It may indicate that the part being not used of burst-length pre-defined or being individually determined.10th address wire A10 may indicate that automatically
It is pre-charged AP.
It is to be used to set non-volatile that BC is blocked in burst order BO0 to BO2, outburst type BT, auto-precharge AP and burst
The optional information of the operation of property memory module 100, rather than set the address for each position of memory space to be distinguished
Optional information.Non-volatile memory module 100 can be by via address wire A0 to address wire A3, address wire A10 and address wire
At least some of signal in the signal that A12 is received is recognized as being used for non-volatile extension together with order CMD0 to order CMD2
The non-volatile extension block address that block NVM_BLK1 to NVM_BLKn is distinguished.
When accessing non-volatile memory module 100, processor 101 can send order CMD0 determining to order CMD2
When at it is non-volatile to send via at least some of address wire in address wire A0 to address wire A3, address wire A10 and address wire A12
Property extension block address.
When sending non-volatile extension block address using the 0th address wire A0 to the 2nd address wire A2, processor 101 is not
Burst order BO0 to BO2 can be sent to non-volatile memory module 100 and non-volatile memory module 100 and fail to connect
Receive burst order BO0 to BO2.In this case, non-volatile memory module 100 can be based on advance with processor 101
Burst order definition or being individually determined communicates with one another.For example, the information about burst order, which is storable in, serially deposits
It can be detected when processor 101 is initialized with non-volatile memory module 100 in detection chip 140 and by processor 101.
Processor 101 can be communicated based on the burst order detected with non-volatile memory module 100.
When sending non-volatile extension block address using the 3rd address wire A3, processor 101 fails outburst type BT
Send to non-volatile memory module 100 and non-volatile memory module 100 and fail to receive outburst type BT.This
In situation, non-volatile memory module 100 and processor 101 can based on outburst type pre-defined or being individually determined that
This communication.For example, the information about outburst type, which is storable in, serial is present in detection chip 140 and can be in processor
101 are detected when being initialized with non-volatile memory module 100 by processor 101.Processor 101 can be based on the burst detected
Type is communicated with non-volatile memory module 100.
When sending non-volatile extension block address using the 12nd address wire A12, processor 101 fails to block burst
BC, which sends to non-volatile memory module 100 and non-volatile memory module 100 to fail to receive burst, blocks BC.At this
Plant in situation, non-volatile memory module 100 can be blocked with processor 101 based on burst pre-defined or being individually determined
Communicate with one another.For example, it is storable in and serial exists in detection chip 140 and can be in processor about the information blocked of happening suddenly
101 are detected when being initialized with non-volatile memory module 100 by processor 101.Processor 101 can be based on the burst detected
Block and communicated with non-volatile memory module 100.
When sending non-volatile extension block address using the 10th address wire A10, processor 101 fails automatic preliminary filling
Electric AP, which is sent to non-volatile memory module 100 and non-volatile memory module 100, to fail to receive auto-precharge AP.
In this case, non-volatile memory module 100 can be judged whether based on information pre-defined or being individually determined
Perform auto-precharge.
With continued reference to Fig. 3, when receiving order CMD0 to order CMD2, address wire A11, address wire A13 and address wire A17
It is reserved line REV.Therefore, line REV is reserved to can be used to send non-volatile extension block address.
When the first timing receipt and volatile memory 121 and nonvolatile memory 123 in transmission proactive command ACT
During associated row address, and order CMD0 is being received to ordering CMD2 the second timing to send and volatile memory 121
And the associated column address of nonvolatile memory 123 and the non-volatile extension associated with nonvolatile memory 123
During block address, data can be passed on via data wire DQ.
Fig. 4 is the flow chart for the operation method for illustrating the non-volatile memory module according to conceptual embodiment of the present invention.
Reference picture 2 is to Fig. 4, and in operation sl 10, when receiving proactive command ACT, module controller 110 will can be received via First Line
First be used as row address.For example, the First Line can be address wire A0 to address wire A17.
In operation s 120, when receiving order CMD0 to when ordering CMD2, module controller 110 will can connect via the second line
The second of receipts is used as column address.For example, second line can be address wire A4 to address wire A9.
In operation S130, when receiving order CMD0 to when ordering CMD2, module controller 110 will can connect via the 3rd line
The 3rd received is used as non-volatile extension block address.For example, the 3rd line may include address wire A0 to address wire
At least some of address wire in A3, address wire A10 and address wire A12.In addition, the 3rd line may include address wire A11, address
At least some of address wire in line A13 and address wire A17.
The embodiment of concept of the present invention is illustrated with reference to address wire.However, term " address wire " is simply will be general with the present invention
Read the title that associated line is distinguished and set with other lines.Therefore, the embodiment of concept of the present invention is not limited to that.Lift
It is not the order CMD0 of address to ordering CMD2 although having used term " address wire " as reference picture 3 is illustrated for example
And optional signal BO0 to BO2, burst is blocked, outburst type and auto-precharge can also be passed on via " address wire ".
Fig. 5 is to illustrate that wherein non-volatile memory module writes the flow of the method for data under the control of a processor
Figure.Reference picture 1, Fig. 2 and Fig. 5, in operation S210, non-volatile memory module 100 can receive row ground from processor 101
Location, column address, non-volatile extension block address and data.The row address, the column address and the non-volatile extension
Block address can be sent to module controller 110 as module command/address CA.The data can be set via data wire DQ
Determine to data buffer 130.Module controller 110 can produce volatile memory commands/address CA_v and can deposit volatibility
Reservoir command/address CA_v is sent to volatile memory 121 and non-volatile memory controller 122.Module controller 110
Nonvolatile memory command/address CA_n can be produced and nonvolatile memory command/address CA_n can be sent to non-easy
The property lost Memory Controller 122.
In operation S220, module controller 110 or non-volatile memory controller 122 can be from volatile memory
121 read mark corresponding with row address and column address.For example, module controller 110 will can be used to ask read operation
Volatile memory commands/address CA_v send to volatile memory 121.For example, volatile memory 121 can be
On flag data line TDQ loading mark " TAG " and can on memory data line MDQ load store device data.Module controller
110 or non-volatile memory controller 122 can receive the mark " TAG " that is loaded on flag data line TDQ and in memory
The memory data loaded on data wire MDQ.
In operation S230, module controller 110 or non-volatile memory controller 122 can determine whether to produce hit
Or it is miss.For example, when the non-volatile extension block address that is received from processor 101 with from volatile memory 121
When the mark of reading is identical, it may be determined that for hit.If determined as hit, then operation S240 and operation S250 is omitted, and perform
Operate S260.
In operation S230, when the non-volatile extension block address that is received from processor 101 and from volatile memory
When 121 marks read are different, it may be determined that be miss.If determined as miss, then operation S240 is performed.
In operation S240, module controller 110 or non-volatile memory controller 122 judge whether to deposit in volatibility
Dirty mark is written with the memory space corresponding with row address and column address of reservoir 121.If not in the memory space
The dirty mark is write, then omits operation S250, and perform operation S260.
If determining to be written with the dirty mark, module controller 110 in the memory space in operation S240
Or the executable operation S250 of non-volatile memory controller 122.In operation S250, module controller 110 or non-volatile
Memory Controller 122 can be based on the row address, the column address and the non-volatile extension block address non-volatile
Property memory 123 in write from volatile memory 121 read data.For example, module controller 110 can be to non-volatile
Property Memory Controller 122 provide nonvolatile memory command/address CA_n to ask write-in to be loaded in memory data
Data on line MDQ.Afterwards, operation S260 is performed.
In operation S260, module controller 110 or non-volatile memory controller 122 can be based on row address and row ground
Location writes data in volatile memory 121.Module controller 110 can control data buffer 130 in memory data line
The data received via data wire DQ are loaded on MDQ.Module controller 110 can be by the volatile storage for asking write operation
Device command/address CA_v is sent to volatile memory 121.
In operation S270, module controller 110 or non-volatile memory controller 122 can be in volatile memory
Dirty mark is write in 121 memory space corresponding with the row address and the column address.It can be incited somebody to action via flag data line TDQ
The dirty mark is write in volatile memory 121 or via memory data line MDQ together with mark " TAG " by the dirty mark
Will is write together with data in volatile memory 121.For example, module controller 110 or nonvolatile memory control
Device 122 can be loaded on flag data line TDQ or memory data line MDQ will be written as the information of dirty mark.Module control
Device 110 processed can provide volatile memory commands/address CA_v to ask write-in to be loaded in mark to volatile memory 121
Data on data wire TDQ or memory data line MDQ.For example, the dirty mark can be write together with the data.
For example, operation S240 and operation S250 can be performed simultaneously.
In operation S280, module controller 110 or non-volatile memory controller 122 can with row address and row ground
Non-volatile extension block address is written as marking " TAG " in the corresponding volatile memory 121 in location.For example, module
Controller 110 or non-volatile memory controller 122 can on flag data line TDQ loading non-volatile extension block
Location.Module controller 110 can provide volatile memory commands/address CA_v to ask to write quilt to volatile memory 121
It is carried in the data on flag data line TDQ.For example, mark " TAG " can be write together with dirty mark or data.Citing
For, operation S280 and operation S240 and operation S250 can be performed simultaneously.
Fig. 6 is to illustrate that wherein non-volatile memory module reads the flow of the method for data under the control of a processor
Figure.Reference picture 1, Fig. 2 and Fig. 6, in operation s 310, non-volatile memory module 100 can receive row ground from processor 101
Location, column address, non-volatile extension block address and data.The row address, the column address and the non-volatile extension
Block address can be sent to module controller 110 as module command/address CA.Module controller 110 can produce volatibility
Memory command/address CA_v and the volatile memory commands/address CA_v can be sent to volatile memory 121 and
Non-volatile memory controller 122.Module controller 110 can produce nonvolatile memory command/address CA_n and can be by
The nonvolatile memory command/address CA_n is sent to non-volatile memory controller 122.
In operation S320, module controller 110 or non-volatile memory controller 122 can be from volatile memory
121 read mark corresponding with the row address and the column address.For example, module controller 110 will can be used to ask
The volatile memory commands of read operation/address CA_v is sent to volatile memory 121.For example, volatile storage
Device 121 can be loaded on flag data line TDQ mark " TAG " and can on memory data line MDQ load store device data.Mould
Block controller 110 or non-volatile memory controller 122 can receive the mark " TAG " being loaded on flag data line TDQ
And it is loaded in the memory data on memory data line MDQ.
In operation s 330, module controller 110 or non-volatile memory controller 122 can determine whether to produce hit
Or it is miss.For example, when the non-volatile extension block address that is received from processor 101 with from volatile memory 121
When the mark of reading is identical, it may be determined that for hit.If determined as hit, then operation S340 and operation S380 is omitted, and perform
Operate S390.
In operation s 330, when the non-volatile extension block address that is received from processor 101 with from volatile memory
When 121 marks read are different, it may be determined that be miss.If determined as miss, then operation S340 is performed.
In operation S340, module controller 110 or non-volatile memory controller 122 judge whether to deposit in volatibility
Dirty mark is written with the memory space corresponding with the row address and the column address of reservoir 121.If do not deposited described
Storage is written with the dirty mark in space, then omits operation S350, and perform operation S360.
If operation S340 in determine to write the dirty mark in the memory space, module controller 110 or
The executable operation S350 of non-volatile memory controller 122.In operation S350, module controller 110 or non-volatile deposit
Memory controller 122 can be based on the row address, the column address and the non-volatile extension block address non-volatile
The data read from volatile memory 121 are write in memory 123.For example, module controller 110 can be to non-volatile
Memory Controller 122 provides nonvolatile memory command/address CA_n to ask write-in to be loaded in memory data line
Data on MDQ.Afterwards, operation S360 is performed.
In operation S360, module controller 110 or non-volatile memory controller 122 can based on the row address,
The column address and the non-volatile extension block address read data from nonvolatile memory 123.For example, module
Controller 110 can provide nonvolatile memory command/address CA_n to read data to non-volatile memory controller 122
And read data are loaded on memory data line MDQ.
In operation S370, module controller 110 or non-volatile memory controller 122 can based on the row address and
The column address writes data in volatile memory 121.For example, module controller 110 can be to volatile memory
121 provide volatile memory commands/address CA_v to write the data being loaded on memory data line MDQ.
In operation S380, module controller 110 or non-volatile memory controller 122 can with the row address and
Non-volatile extension block address is written as marking " TAG " in the corresponding volatile memory 121 of the column address.Citing comes
Say, module controller 110 or non-volatile memory controller 122 loading non-volatile can extend on flag data line TDQ
Block address.Module controller 110 can provide volatile memory commands/address CA_v to ask to volatile memory 121
Write-in is loaded in the data on flag data line TDQ.For example, mark " TAG " can be write together with data.Citing comes
Say, operation S380 and operation S370 can be performed simultaneously.
In step S390, the exportable data of non-volatile memory module A200.For example, module controller
110 controllable data buffers 130 are loaded in the data on memory data line MDQ with output.
Table 1 and table 2 illustrate wherein to send extended address (or non-volatile extension block according to the application of concept of the present invention
Location) example.Show to send to the various orders of non-volatile memory module 100 and according to described in table 1 and table 2
The module command of order/address CA.
Table 1
Table 2
Reference picture 2, table 1 and table 2, signal wire CKE, chip selection can be enabled via clock and enables signal wire CS_n, active
Order input line ACT_n, order input line RAS_n/A16, order input line CAS_n/A15 and order input line WE_n/A14,
Storehouse group input line BG0 and storehouse group input line BG1, storehouse address input line BA0 and storehouse address input line BA1, chip identifier
Line C0 to chip identifier line C2, burst truncated signal line BC_n/A12, address wire A11, address wire A13 and address wire A17, from
Dynamic precharging signal line A10/AP and address wire A0 to A9 sending module command/address CA.
Clock, which enables signal wire CKE and can sent in non-volatile memory module 100 or volatile memory 121, to be used for
The internal clocking and clock of activation and the deactivation of control input buffer and output driver enable signal.Make using clock
Energy signal wire CKE previous circulation and the level of previous cycle are ordered to determine to be included in one kind in module command/address CA.
It is may indicate that via the chip select signal line CS_n chip select signals sent in non-volatile memory module 100
Or module command/address CA is effective or invalid in volatile memory 121.
Proactive command input line ACT_n can transmit proactive command ACT, and proactive command ACT can be recognized as proactive command.
Each of order input line RAS_n/A16, order input line CAS_n/A15 and order input line WE_n/A14
For multipurpose.When proactive command ACT is activated, order input line RAS_n/A16, order input line CAS_n/A15 and
Order input line WE_n/A14 can transmit row address RA corresponding with address wire A14 to address wire A16.When proactive command ACT quilts
It is each in order input line RAS_n/A16, order input line CAS_n/A15 and order input line WE_n/A14 during deactivation
Person can transmit order.
Storehouse group input line BG0 and storehouse group input line BG1 can transmit the storehouse group for the storehouse group for indicating to be activated
Signal BG.
Storehouse group input line BG0 and storehouse group input line BG1 can transmit the storehouse address for the storehouse address for indicating to be activated
BA。
Chip identifier line C0 to chip identifier line C2 can be transmitted for based on through-silicon via (through
Silicon via, TSV) identifier of each section is selected in the three-dimensional structure of multiple sections that is stacked.
The truncated signal line BC_n/A12 that happens suddenly is used for multipurpose.When proactive command ACT is activated, happen suddenly truncated signal
Line BC_n/A12 can transmit row address RA corresponding with address wire A12.When proactive command ACT is deactivated and included in module life
When order in order/address indicates read operation, burst truncated signal line BC_n/A12, which can be transmitted, indicates whether that performing burst cuts
Disconnected burst truncated signal BC.
Address wire A11, address wire A13 and address wire A17 are used for multipurpose.When proactive command ACT is activated, address
Each of line A11, address wire A13 and address wire A17 can transmit row address RA.When proactive command ACT is deactivated, ground
Each of location line A11, address wire A13 and address wire A17 can not transmit useful signal.For example, address wire A11,
Location line A13 and address wire A17 can be reserved line.
Auto-precharge signal wire A10/AP is used for multipurpose.When proactive command ACT is activated, auto-precharge letter
Number line A10/AP can transmit row address RA corresponding with address wire A10.When proactive command ACT is deactivated and is inputted via order
Line RAS_n/A16, order input line CAS_n/A15 and the signal of order input line WE_n/A14 transmission (for example, order) have
During pre-defined pattern (for example, reserved pattern), auto-precharge signal wire A10/AP can transmit indicates whether to perform it is automatic
The auto-precharge signal AP of precharge.In addition, when proactive command ACT be deactivated and via order input line RAS_n/A16,
The signal (for example, order) of order input line CAS_n/A15 and order input line WE_n/A14 transmission has pre-defined figure
During case (for example, reserved pattern), auto-precharge signal wire A10/AP can transmit activation explosion command EXT.
Address wire A0 to address wire A9 is used for multipurpose.When proactive command ACT is activated, address wire A0 to address wire
Each of A9 can transmit row address RA.When proactive command ACT be deactivated and order input line RAS_n/A16, order it is defeated
When entering line CAS_n/A15 and order input line WE_n/A14 without reserved pattern, order input line RAS_n/A16, order are defeated
Column address CA can be transmitted by entering each of line CAS_n/A15 and order input line WE_n/A14.When proactive command ACT is deactivated
Living and order input line RAS_n/A16, order input line CAS_n/A15 and order input line WE_n/A14 have reserved pattern
When, order input line RAS_n/A16, order input line CAS_n/A15 and activation explosion command EXT and address wire A0 are to address
Each of line A9 can transmitting extended address EA.
As shown in table 1 and table 2, signal wire CKE, chip can be enabled according to the clock included in module command/address CA
Selection enables signal wire CS_n, proactive command input line ACT_n, order input line RAS_n/A16, order input line CAS_n/
A15 and order input line WE_n/A14, storehouse group input line BG0 and storehouse group input line BG1, storehouse address input line BA0 and storehouse
Address input line BA1, chip identifier line C0 are to chip identifier line C2, happen suddenly truncated signal line BC_n/A12, address wire
A11, address wire A13 and address wire A17, auto-precharge signal wire A10/AP and address wire A0 to A9 are included in recognize respectively
Order and address in module command/address CA.
For example, the order included in module command/address CA may include：Storehouse proactive command ACT (or actively order
Make)；Storehouse activation explosion command EXT (or extension order)；For the reserved RFU of future usage；It is fixation with burst-length
" BL8 " or burst block reading (read (fixed BL8 or BC4) for " BC4 ")；It is fixed " BL8 " with burst-length
Or burst block as " BC4 " and with auto-precharge reading (have auto-precharge reading (fixed BL8 or
BC4))；It is " BL8 " value and reading (reading (BL8, in operation being adjusted in operation by default with burst-length
In))；It is " BL8 " value, reading for being adjusted in operation and being accompanied by auto-precharge by default with burst-length
(reading (BL8, in operation) with auto-precharge)；Blocked with burst as " BC4 " value and in operation by default
The reading (reading (BL4, in operation)) being adjusted；And blocked with burst as " BC4 " value, in operation by default
It is adjusted and with the reading (reading (BL4, in operation) with auto-precharge) of auto-precharge.
For example, the order included in module command/address CA may include：It is fixed with burst-length
The write-in (write-in (fixed BL8 or BC4)) for " BC4 " is blocked in " BL8 " or burst；With burst-length for fixed " BL8 " or
Burst is blocked for " BC4 " and with the write-in (write-in (fixed BL8 or BC4) with auto-precharge) of auto-precharge；
It is " BL8 " value and write-in (write-in (BL8, in operation)) being adjusted in operation by default with burst-length；Tool
Having burst-length, value, the write-in for being adjusted in operation and being accompanied by auto-precharge (have certainly by default for " BL8 "
The write-in (BL8, in operation) of dynamic precharge)；Block and value and be adjusted in operation by default for " BC4 " with burst
Write-in (write-in (BL4, in operation))；And with burst block for " BC4 " by default value, adjusted in operation
Write-in (write-in (BL4, in operation) with auto-precharge) whole and with auto-precharge.
Order included in module command/address CA can further comprise that mode register setting, refreshing, self-refresh enter
Mouth (self-refresh entry), self-refresh outlet (self-refresh exit), single library precharge, precharge are all
Storehouse, without operation, unselected device, shutdown entrance, shutdown outlet, ZQ calibrations are long and ZQ calibrations are short.
In table 1 and table 2, " H " indicates high level, and " L " indicates low level." V " indicates to be defined as in " H " and " L "
One of particular level." X " demonstrative definition or undefined (for example, float) or incoherent level." RA " is indicated
Send row address RA." CA " indicates to send column address CA." RFU " is indicated for the reserved of future usage.Herein, term " reserved " is
Used, and be defined and for another purposes after the application is proposed based on current state." BG " indicates to send storehouse group
Signal BG." BA " indicates to send storehouse address BA." EA " indicates to send extended address EA." Op Code " indicate to send command code.
In table 1 and table 2, storehouse activation explosion command EXT is defined.When the signal that clock enables signal wire CKE is above being followed
High level " H " is in ring and previous cycle, the signal that chip enables signal wire CS_n is in low level " L ", and proactive command is defeated
The signal for entering line ACT_n is in high level " H ", and order input line RAS_n/A16, order input line CAS_n/A15 and order are defeated
The signal for entering line WE_n/A14 is respectively at low level " L ", high level " H " and high level " H ", and auto-precharge signal wire
When A10/AP signal is in high level " H ", storehouse activation explosion command EXT can be recognized.Can be via address wire A0 to address
Line A9 is sent together with extended address EA is activated into explosion command EXT with storehouse.
In embodiment, storehouse activation explosion command EXT can constitute extension proactive command together with the proactive command ACT of storehouse
ACTe.In embodiment, storehouse proactive command ACT and storehouse activation explosion command EXT can be continuously sent, and can not actively be ordered in storehouse
ACT and storehouse is made to send another order between activating explosion command EXT.That is, transmission includes storehouse proactive command ACT and storehouse is swashed
Explosion command EXT living extension proactive command ACTe, and row address RA and extended address EA are sent to nonvolatile memory
Module 100.
In the embodiment illustrated with reference to table 1 and table 2, as order input line RAS_n/A16, order input line CAS_n/
A15 and order input line WE_n/A14 form reserved pattern (for example, low level " L ", high level " H " and high level " H ")
And auto-precharge signal wire A10/AP signal be in high level " H " when, storehouse activation explosion command EXT recognized.However,
When auto-precharge signal wire A10/AP signal is in low level " L ", storehouse activation explosion command EXT can be recognized.
In this situation, the order that wherein auto-precharge signal wire A10/AP signal is in high level " H " can be for supplying future
The reserved order RFU used.In another embodiment, as order input line RAS_n/A16, order input line CAS_n/A15 and
When order input line WE_n/A14 forms reserved pattern (for example, low level " L ", high level " H " and high level " H "), no
How is pipe auto-precharge signal wire A10/AP signal, and storehouse activation explosion command EXT is recognized.
Fig. 7 is to illustrate wherein to send order and address to straight based on dual-inline memory module or non-volatile biserial
Insert the timing diagram of the application of the process of the non-volatile memory module of memory module.In the figure 7, the first chart G1 show through
The signal transmitted by signal wire.Second chart G2 is shown by using the life briefly represented via the signal that signal wire is transmitted
Make CMD, address AD DR and data DQ.
With reference to table 1, table 2, Fig. 2 and Fig. 7, at T1, inputted proactive command ACT as order CMD via proactive command
Line ACT_n is transmitted.In addition, row address RA as address AD DR via order input line RAS_n/A16, order input line CAS_
N/A15 and order input line WE_n/A14, burst truncated signal line BC_n/A12, address wire A11, address wire A13 and address wire
A17, auto-precharge signal wire A10/AP and address wire A0 are transmitted to address wire A9.Storehouse group signals BG, storehouse address BA and
Chip identifier CID is respectively via storehouse group input line BG0 and storehouse group input line BG1, storehouse address input line BA0 and storehouse address
Input line BA1 and chip identifier line C0 are transmitted to chip identifier line C2.
At T2, storehouse is activated to explosion command EXT and inputted as order CMD via order input line RAS_n/A16, order
Line CAS_n/A15 and order input line WE_n/A14 and auto-precharge signal wire A10/AP is transmitted.Extended address EA makees
Transmitted for address AD DR via address wire A0 to address wire A9.
Proactive command ACT and storehouse activation explosion command EXT can be transmitted continuously.Proactive command ACT is together with line command RA
Transmit, and storehouse activation explosion command EXT is transmitted together with extended address EA.Proactive command ACT and storehouse activation explosion command EXT can
Constitute extension proactive command ACTe.
It is complete in response to extension proactive command ACTe in non-volatile memory module 100 or volatile memory 121
Activate after access target (that is, memory space), at T3, CMD will be ordered via order input line RAS_n/A16, order defeated
Enter line CAS_n/A15 and order input line WE_n/A14 to transmit.Order CMD may indicate that in the order illustrated with reference to table 1 and table 2
One of remaining order in addition to proactive command ACT and storehouse activation explosion command EXT.Column address CA is passed through as address AD DR
By address wire A0 is transmitted to address wire A9.Storehouse group signals BG and storehouse address BA are respectively via storehouse group input line BG0 and storehouse
Group input line BG1 and storehouse address input line BA0 and storehouse address input line BA1 is transmitted.Signal can alternatively OPT via
Truncated signal line BC_n/A12 and auto-precharge signal wire A10/AP is happened suddenly to transmit.
At T4, it may be in response to the order CMD of the transmission at T3 to exchange data.
As described above, can be used to according to the non-volatile memory module 100 of conceptual embodiment of the present invention defeated based on ordering
Enter line RAS_n/A16, order input line CAS_n/A15 and order input line WE_n/A14 signal or order input line RAS_n/
A16, order input line CAS_n/A15, order input line WE_n/A14 and additional wire (for example, auto-precharge signal wire
A10/AP signal) activates explosion command EXT to recognize.Non-volatile memory module 100 can be based on activation explosion command EXT
Recognize extended address EA.
The row address RA received together with proactive command ACT and the column address CA received together with order CMD can be common
Using to volatile memory 121 and nonvolatile memory 123, and the extension received together with activation explosion command EXT
Location can not apply to volatile memory 121 and can apply to nonvolatile memory 123.In embodiment, such as reference picture 5 and
Fig. 6 is illustrated that extended address EA is used as mark.
In embodiment, whether non-volatile memory module 100 can be supported activation explosion command EXT to be stored in serially
Exist in detection chip 140.Processor 101 (reference picture 1) can be based on sentencing from the information that serially there is the reading of detection chip 140
Whether disconnected non-volatile memory module 100 supports activation explosion command EXT.If non-volatile memory module 100 is supported
Activate explosion command EXT, as illustrated with reference to table 1, table 2 and Fig. 7, processor 101 can will extend proactive command ACTe send to
Non-volatile memory module 100.If non-volatile memory module 100 is not supported to activate explosion command EXT, such as reference picture
3 and Fig. 4 is illustrated that processor 101 can send non-volatile extension block address together with proactive command ACT.
In the situation that wherein processor 101 sends extension proactive command ACTe, non-volatile memory module 100 or mould
Block controller 110 can from included in extension proactive command ACTe in proactive command ACT obtain row address RA and can from included in
The activation explosion command EXT extended in proactive command ACTe obtains extended address EA.
Fig. 8 is to illustrate that wherein non-volatile memory module 100 obtains row address RA, extension from extension proactive command ACTe
The flow chart of address EA and column address CA method.It is non-volatile in operation S410 with reference to table 1, table 2, Fig. 2, Fig. 7 and Fig. 8
Memory module 100 is used as row address RA by first received when receiving proactive command ACT via First Line.Citing comes
Say, proactive command ACT can be received via proactive command input line ACT_n.For example, First Line may include order input line
RAS_n/A16, order input line CAS_n/A15 and order input line WE_n/A14, burst truncated signal line BC_nA12, address
Line A11, address wire A13 and address wire A17, auto-precharge signal wire A10/AP and address wire A0 are to address wire A9.
In operation S420, non-volatile memory module 100 will be when receiving activation explosion command EXT via the second line
The second of reception is used as extended address EA.For example, can be via order input line RAS_n/A16, order input line CAS_
N/A15 and order input line WE_n/A14 or defeated via order input line RAS_n/A16, order input line CAS_n/A15, order
Enter line WE_n/A14 and additional wire (for example, auto-precharge signal wire A10/AP) to receive activation explosion command EXT.The
Two wires can be address wire A0 to address wire A9.
In operation S410 and operation S420, row address RA and extended address are received together with extension proactive command ACTe
EA。
In operation S430, non-volatile memory module 100 will be received when receiving order CMD via the 3rd line the
Three are used as column address CA.Can be via order input line RAS_n/A16, order input line CAS_n/A15 and order input line WE_
N/A14 receives order CMD.3rd line can be address wire A0 to address wire A9.
Fig. 9 is the square for illustrating the non-volatile memory module according to Fig. 1 of another embodiment of concept of the present invention
Figure.Reference picture 1 and Fig. 9, non-volatile memory module 200 include module controller 210 (or random access memory control dress
Put), heterogeneous storage arrangement 220, data buffer (DB) 230 and serially there is detection chip 240.
Module controller 210 can be similar to module controller 110 mode run.
Heterogeneous storage arrangement 220 may include volatile memory 221, non-volatile memory controller 222 and it is non-easily
The property lost memory 223.Volatile memory 221 may be in response to volatile memory commands/address from module controller 210
CA_v is run.Volatile memory 221 may be in response to volatile memory commands/address CA_v respectively via memory data
Line MDQ and flag data line TDQ come output data and mark " TAG ".Volatile memory 221 can be based on volatile memory life
Order/address CA_v writes respectively via memory data line MDQ and flag data line the TDQ data received and mark.
Non-volatile memory controller 222 may be in response to the nonvolatile memory order from module controller 210/
Address CA_n is run.For example, it is non-based on the nonvolatile memory command/address CA_n from module controller 210
Volatile memory controller 222 can be in nonvolatile memory 223 to entering via the memory data line MDQ data received
Row programming can export the data in nonvolatile memory 223 by programming via memory data line MDQ.
Non-volatile memory controller 222 can be similar to non-volatile memory controller 122 mode run.
In embodiment, volatile memory 221 can share same memory number with non-volatile memory controller 222
According to line MDQ.
In embodiment, volatile memory 221 can share flag data line TDQ with module controller 210.As in addition
One kind selection, volatile memory 221, non-volatile memory controller 222 and module controller 210 can share flag data
Line TDQ.Non-volatile memory controller 222 can be via flag data line TDQ output tokens " TAG ".
Data buffer 230 can be similar in appearance to the data buffer associated with memory data line MDQ and data wire DQ
130 mode is run or configured.
Serial have the mode that detection chip 240 can be similar to serially there is detection chip 140 and run or configured.
In embodiment, cache manger 215 can assign cache-miss address transaction ID TID and manage
Manage the transaction ID TID.First, cache-miss can be during the read operation associated with the first address AD D_1
Produce.In this case, cache manger 215 can assign first to hand over the first address AD of cache-miss D_1
Easily mark TID1.Second, cache hit can be produced during the read operation associated with the second address AD D_2.At this
Plant in situation, cache manger 215 not can perform individually operated.3rd, cache-miss can with the 3rd address
Produced during read operation associated ADD_3.In this case, cache manger 215 can not be ordered cache
In the 3rd address AD D_3 assign the second transaction ID TID2.Similarly, cache hit can with the 4th address AD D_4 and
Produced during each of read operation associated 5th address AD D_5；When cache-miss with the 6th address
When being produced during read operation associated ADD_6, cache manger 215 can assign the 3rd to hand over the 6th address AD D_6
Easily mark TID3.Each of first transaction ID to the 3rd transaction ID TID1, TID2, TID3 can be implemented as monotone increasing
Greatly.
That is, cache manger 215 can manage cache-miss address, so that slow at a high speed whenever producing
When depositing miss, transaction ID TID is assigned to cache-miss address respectively.In this case, transaction ID can be single
Adjust increase.Transaction ID can be provided to place together with indicating whether to produce the validity information DQ_INFO of cache hit
Manage device 101.
In embodiment, mark " TAG " may include a part for address, and it is with being stored in volatile memory 221
Data correspondence.In embodiment, module controller 210 can come to exchange mark with volatile memory 221 via flag data line TDQ
Remember " TAG ".In embodiment, when writing data in volatile memory 221, mark " TAG " corresponding with the data
It can be write under the control of module controller 210 together with data in volatile memory 221.
In detail, can be after fixed delay RL via data wire DQ in response to the reading order from processor 101
Export read requests data (read-requested data).Module controller 210 can check the knot of operation based on cache
Fruit will be sent to processor 101 via the validity information DQ_INFO of the data wire DQ data exported.Validity information DQ_
INFO may include the validity associated with the data exported via data wire DQ and transaction ID TID.It can refer to validity letter
Cease the cache-miss data that DQ_INFO provides processor 101 time point output that can be after delay RL.Also
It is to say, processor 101 can refer to transaction ID TID and ask cache-miss data again.
In embodiment, volatile memory 221 and nonvolatile memory 223 can have n：1 direct mapping relations (n
For natural number).That is, volatile memory 221 can be the direct mapping cache of nonvolatile memory 223.Lift
For example, the first volatile storage that the first volatile storage area of volatile memory 221 can be with nonvolatile memory 223
Area is corresponding to the n-th volatile storage area.In this case, the big I of the first volatile storage area non-volatile is deposited with first
Size of the storage area to each of the n-th nonvolatile storage is identical.In embodiment, the first volatile storage area can enter one
Step includes the area for being used to store additional information (for example, mark, error correcting code, dirty information etc.).
Although not shown in fig .9, non-volatile memory module 200 can further comprise that single memory (does not show
Go out).The single memory be storable in used in non-volatile memory controller 222 information (such as data, program and
Software).For example, the single memory can store the information managed by non-volatile memory controller 222 and (for example reflect
Firing table and flash translation layer (FTL)).Alternatively, the single memory can be interim storage from non-volatile
Data or the buffer storage for the data that will be stored in nonvolatile memory 223 that memory 223 is read.
Hereinafter, for the sake of for ease of illustration, can by " _ v " be attached to the key element associated with volatile memory 221 (for example,
Data, mark, command/address etc.).For example, slave module controller 210 export to control volatile memory 221
Volatile memory commands/address can be represented by " CA_v ", and from volatile storage under the control of module controller 210
The data that device 221 is exported can be represented by " DT_v ".In more detail, for writing data in volatile memory 221
Volatile memory writing commands can be represented by " WR_v ", and be used for the volatibility from the reading data of volatile memory 221
Reading order can be represented by " RD_v ".
Similarly, " _ n " is attached to the element associated with nonvolatile memory 223 (for example, data, mark, life
Order/address etc.).For example, slave module controller 210 export to control the non-volatile of nonvolatile memory 223
Command/address can represent by " CA_n ", and exported under the control of module controller 210 from nonvolatile memory 223
Data can be represented by " DT_n ".In more detail, deposited for writing the non-volatile of data in nonvolatile memory 223
Reservoir writing commands can be represented by " WR_n ", and be used for the non-volatile memories from the reading data of nonvolatile memory 223
Device reading order can be represented by " RD_n ".
As described above, be can refer to according to the non-volatile memory module 200 of conceptual embodiment of the present invention to read requests
Data perform the result of cache verification operation to provide the validity associated with the data of the output at fixed delay RL
Information DQ_INFO.
Figure 10 is the flow chart for the read operation for illustrating the non-volatile memory module 200 shown in Fig. 9.Reference picture 1, figure
9 and Figure 10, non-volatile memory module 200 in response to the read requests from processor 101 come output data and with it is described
The associated validity information DQ_INFO of data.
In operation S11, module reading order and address (RD and ADD) can be transmitted in processor 101.Nonvolatile memory
Module 200 may be in response to received module reading order and address (RD and ADD) to perform reading to volatile memory 221
Operation.For example, module reading order and address (RD and ADD) may include to be stored in nonvolatile memory mould for reading
The reading order of data in block 200 and reading address corresponding with the reading data.Non-volatile memory module 200 can
Read the data and mark being stored in the part corresponding with the reading address in the area of volatile memory 221.
In operation S12, non-volatile memory module 200 can be performed based on result is read to be used to judge cache
The cache verification operation of hit or cache-miss.As described above, mark " TAG " includes having with a part for address
The information of pass.Non-volatile memory module 200 can be by the way that " TAG " will be marked to be compared to judgement with address for being received
No generation cache hit or cache-miss.
In operation S13, there is branch according to cache checked result in process.If the part and mark of the address
Remember that " TAG " is identical, then non-volatile memory module 200 can determine that generation cache hit.Otherwise nonvolatile memory
Module 200 can determine that generation cache-miss.
If producing cache hit, in operation S14, non-volatile memory module 200 will be deposited from volatibility
The data and validity information DQ_INFO that reservoir 221 is read are sent to processor 101.Validity information DQ_INFO include on
Whether output data corresponds to the information of cache hit or cache-miss.Processor 101 can determine whether via effective
Property the information DQ_INFO data DT_v that receives whether be valid data.That is, non-volatile memory module 200 can be to
Processor 101 provides the information on cache hit as validity information DQ_INFO, so that processor 101 will can be read
Access evidence is recognized as valid data.
If producing cache-miss, in operation S15, non-volatile memory module 200 believes validity
Breath DQ_INFO is sent to processor 101, and it indicates that via the data that data wire DQ is exported be invalid data.That is, non-easy
The property lost memory module 200 can export the validity information DQ_INFO for indicating cache-miss to processor 101.
In this situation, non-volatile memory module 200 can provide the transaction ID TID of data to processor 101, and it is slow with high speed
Miss correspondence is deposited, to be used as additional validity information DQ_INFO.Processor 101 can refer to transaction ID TID to ask later
The data of cache-miss.
In embodiment, operation S14 can be being performed after predetermined delay RL from operation S11.Namely
Say, after predetermined delay, processor 101 can send module reading order and address (RD and ADD) to non-easy
Lose property memory module 200 and can from non-volatile memory module 200 receive read data.In this case, in advance really
Fixed delay can postpone RL to read.It can be true according to the operation characteristic of non-volatile memory module 200 to read delay RL
The fixed time or clock cycle.Serial exist on reading delay RL information and being storable in detection chip 240 and can conduct
Device information DI is provided to processor 101.Processor 101 can control non-volatile memory module based on delay RL is read
200。
Figure 11 is the view for illustrating the cache structure of the volatile memory shown in Fig. 9.For ease of illustration rise
See, eliminate the unwanted element of institute for the cache structure for illustrating volatile memory 221.Furthermore, it is assumed that will
The memory block of nonvolatile memory 223 is divided into multiple area NVM_0 to area NVM_5.The multiple area NVM_0 to area NVM_5
It can be the area logically divided.The memory block of nonvolatile memory 223 can further comprise memory space and the firstth area
NVM_0 to the 6th area NVM_5.
Reference picture 9 and Figure 11, the access speed of volatile memory 221 can be faster than the access of nonvolatile memory 223
Speed.That is, the part being stored in nonvolatile memory 223 of data is storable in volatile memory 221
In, so that the speed of the accessing operation performed according to the request of module controller 210 or processor 101 can be improved.Citing
For, volatile memory 221 is used as the cache memory of nonvolatile memory 223.For example, volatibility
Memory 221 can be stored to a part for the data being stored in nonvolatile memory 223 and may be in response to module control
The request of device 210 or processor 101 processed data storage to export.
In embodiment, volatile memory 221 can have direct mapping relations with nonvolatile memory 223.Citing
For, volatile memory 221 may include a plurality of cache line CL0 to cache line CL3.Cache line CL may indicate that
Store cached data and mark " TAG ", data error correcting code ECC_DT, marked erroneous correction code ECC_TAG and dirty letter
Cease DRT memory space.
Cache line may indicate that the minimum access unit of the request of module controller 210 or processor 101.Volatibility is deposited
Reservoir 221 can have memory capacity corresponding with the multiple entrance CL0 to entrance CL3.Mark " TAG " can be with being stored in together
At least a portion of the corresponding addresses of data DT_v in one entrance.Data error correcting code ECC_DT can be stored in it is same enter
The error correcting code of data DT_v in mouthful.Marked erroneous correction code ECC_TAG can be the mark being stored in same entrance
The error correcting code of " TAG ".Dirty information DRT may indicate that the dirty information of the data DT_v on being stored in same entrance.
Nonvolatile memory 223 may include the multiple area NVM_0 to area NVM_5.The multiple area NVM_0 is to area
Each of NVM_5 may include a plurality of line Line0 to line Line3.In embodiment, line Line0 is each into line Line3
Person may indicate that memory space corresponding with the data access unit of the request of processor 101 or module controller 210.
For example, memory areas NVM_0 may include line Line0 corresponding with cache element to line Line3.Line
Line0 to line Line3 can correspond respectively to cache line CL0 to cache line CL3.That is, line Line0 can be corresponded to
In cache line CL0, and line Line1 may correspond to cache line CL1.Memory areas NVM_1 may include to correspond respectively to
The cache line Line0 to cache line Line3 of a plurality of cache line CL0 to CL3.Similarly, memory areas
Each of NVM_2 to memory areas NVM_5 may include to correspond respectively to a plurality of cache line CL0 to cache
Line CL3 line Line0 to line Line3.
As described above, volatile memory 221 can have direct mapping relations with nonvolatile memory 223.Volatibility
The cache line CL0 of memory 221 may correspond to each of the multiple area NVM_0 to area NVM_5 line Line0 and
Data DT_v in one of line Line0 that can be to being stored in the multiple area NVM_0 to area NVM_5 is stored.Change sentence
Talk about, the data DT_v being stored in cache line CL0 may correspond to the multiple area NVM_0 to area NVM_5 line Line0
One of.
Cache line Line0 may include the mark " TAG " associated with institute data storage DT_v.In embodiment, mark
Whether the data DT_v that note " TAG " can be stored in cache line CL0 for instruction corresponds to the multiple area NVM_0 to area
Any one of NVM_5 line Line0 information.
In embodiment, each of described a plurality of line Line0 to line Line3 can be by the ground that is provided from processor 101
Location ADD is selected or recognized.That is, the multiple memory areas NVM_0 is to each of memory areas NVM_5's
At least one of described a plurality of line Line0 to line Line3 can be selected by the address AD D provided from processor 101, and can
Accessing operation is performed to selected line.
Each of described a plurality of cache line CL0 to cache line CL3 can be by the ground that is provided from processor 101
Location ADD at least a portion is selected or distinguished.That is, a plurality of cache line CL0 to cache line CL3
At least one of can be selected by the address AD D provided from processor 101 at least a portion, and can be to selected height
Fast cache lines perform accessing operation.
Mark " TAG " may include the address AD D provided from processor 101 at least a portion or remainder.Citing comes
Say, at least one of described a plurality of cache line CL0 to cache line CL3 can be carried out by an address AD D part
Select and situations of mark " the TAG " _ v from selected cache line included in address AD D is defined as producing at a high speed
Cache hit.Alternatively, can be by a plurality of cache line CL0 at least one into cache line CL3
Person is selected by an address AD D part and mark " TAG " _ v from selected cache line is not included in address
Situation in ADD is defined as producing cache-miss.
As described above, volatile memory 221 can be used as cache memory by non-volatile memory module 200,
So as to improve the performance of non-volatile memory module 200.In this case, non-volatile memory module 200 can be based on
The mark " TAG " that is stored in volatile memory 221 judges the generation of cache hit or cache-miss.
In embodiment, illustrated hereinafter with reference to accompanying drawing between volatile memory 221 and nonvolatile memory 223
Data trade method.However, the embodiment that will be elaborated below is only the scope and essence for being used to easily illustrate concept of the present invention
The example of god, and therefore, the embodiment is not limited to that.In addition, the embodiment of concept of the present invention is illustrated as using easy
The property lost memory 221 is as the cache memory of nonvolatile memory 223, but the embodiment is not limited to that.
Figure 12 is the timing diagram of the read operation for being set forth in shown in Figure 10.Reference picture 12, non-volatile memories
Device module 200 can be from the receiving module reading order of processor 101.For example, non-volatile memory module 200 can be with reception
Proactive command ACT simultaneously receives the first address AD D1 and can receive reading order RD and the second address AD D2.
It may be in response to received signal and come inside of the performing module controller 210 to non-volatile memory module 200
Cache verification operation.For example, the exportable nonvolatile memory command/address CA_n of module controller 210 and easily
The property lost memory command/address CA_v.Volatile memory 221 may be in response to volatile memory reading order/address CA_v
And export be stored in data DT_v in the part corresponding to address AD D1 or address AD D2 in the area of volatile memory 221 and
Mark " TAG " _ v.For example, as described above, volatile memory 221 can be by driving memory data based on data DT_v
Line MDQ voltage comes via memory data line MDQ output datas DT_v.Volatile memory 221 can be by based on mark
" TAG " _ v driving flag data lines TDQ voltage comes via flag data line TDQ output tokens " TAG " _ v.Module controller
210 can receive mark " TAG " _ v and can be based on mark " TAG " _ v to being received and address AD D1 via flag data line TDQ
Or the results that are compared of address AD D2 judge whether to produce cache hit or cache-miss.
After receiving reading order RD and the second address AD D2 and passing through fixed delay RL, data can be via data wire DQ
Export to volatile memory 221.In this case, the data of output are to perform cache core in module controller 210
It is confirmed as the data of cache hit during to operation.Therefore, module controller 210 can will be by via the output of independent pin
There is provided to the validity information DQ_INFO of processor 101.That is, validity information DQ_INFO may include to indicate from volatile
Property memory 221 read data be valid data validity part 251.Validity information DQ_INFO may include later to
The transaction ID part 252 of elaboration.However, when it is determined that data for it is effective when, due to transaction ID part 252 be it is unnecessary,
Therefore transaction ID part 252 can be neglected in processor 101.Processor 101 can judge data based on validity information DQ_INFO
Whether it is effective.
Figure 13 is the timing diagram for the implementation for illustrating data and validity information DQ_INFO shown in Figure 12.Reference picture
13, it is assumed that the digital independent asked by processor 101 is continuously exported via data wire DQ.For ease of illustrating, in fig. 13
Eliminate reading order, address etc..Each segment data D1, data D2, data D3 and data D4 are in response to reading order and address
Through being exported by multiple pins after specific delays.With data output synchronously, believed according to the validity of conceptual embodiment of the present invention
Breath DQ_INFO can be exported via the pin individually distributed.
Each segment data D1, data D2, data D3 and data D4 can be with the rising edges and trailing edge of clock signal clk synchronously
Output.In addition, validity information DQ_INFO can be synchronously outputted to processor via the pin distributed and clock signal clk
101.Validity information DQ_INFO includes validity part 251 and transaction ID part 252.If from volatile memory 221
The data D1 of output to data D4 corresponds to the validity part of cache hit, then exportable validity information DQ_INFO
251, the validity part 251, which has, indicates that data D1 to data D4 is effectively worth " V ".For example, it is exportable have patrol
Collect the validity part 251 of value " 1 ".In addition, even if processor 101 ignores transaction ID part 252 corresponding with valid data,
Also can there is no problem.Therefore, the exportable transaction ID part 252 for example with logical value " 111 ".Figure 13 illustrates
In embodiment, the number of the position of validity part 251 is that the number of " 1 " and the position of transaction ID part 252 is " 3 ".However, having
The number of the position of effect property each of part 251 and transaction ID part 252 can change according to embodiment.
Figure 14 is the timing diagram for elaborating the read operation shown in Figure 10.Figure 14 illustrates slow at a high speed in generation
From the validity information DQ_ exported according to the non-volatile memory module 200 of conceptual embodiment of the present invention when depositing miss
INFO.Non-volatile memory module 200 can be from the receiving module reading order of processor 101.For example, non-volatile memories
Device module 200 can simultaneously receive the first address AD D1 with receiving proactive command ACT and can receive the lives of reading order RD and second
Make ADD2.
Module controller 210 may be in response to received order and address to perform to non-volatile memory module 200
Internally cached verification operation.The internally cached core of non-volatile memory module 200 is elaborated with reference to Figure 12
To operation, and therefore the description thereof will be omitted.Module controller 210 can be received and read request address pair via flag data line TDQ
Mark " the TAG " _ v answered and the knot that can be compared based on mark " TAG " _ v to being received and address AD D1 or address AD D2
Fruit judges whether to produce cache hit or cache-miss.
After receiving reading order RD and the second address AD D2 and passing through fixed delay RL, data can be via data wire DQ
Export to volatile memory 221.In this case, it is assumed that the result pair of cache verification operation is performed to output data
Should be in cache-miss.In this case, module controller 210 can export validity information DQ_ via independent pin
INFO with processor 101 to be shaken hands (handshaking).Validity information DQ_INFO may include to indicate to deposit from volatibility
The data that reservoir 221 is read are the validity parts 261 of valid data.Validity information DQ_INFO may include transaction ID portion
Divide 262.It can be numbered by the dull increase form of pair transaction corresponding with cache-miss come implementation transaction ID
Part 262.
Processor 101 can be cache-miss data based on validity information DQ_INFO identification data.Processor
101 can be based on transaction ID TID in right times request data read operation again.
Figure 15 is the timing diagram for the implementation for illustrating data and validity information DQ_INFO shown in Figure 14.Reference picture
15, it is assumed that the digital independent asked by processor 101 is continuously exported via data wire DQ.For ease of illustrating, in fig .15
Eliminate reading order, address etc..Each segment data D1, data D2, data D3 and data D4 are in response to reading order and address
Through being exported by multiple pins after specific delays RL.With data output synchronously, according to the validity of conceptual embodiment of the present invention
Information DQ_INFO can be exported via the pin individually distributed.
Each segment data D1, data D2, data D3 and data D4 can be with the rising edges and trailing edge of clock signal clk synchronously
Output.In addition, validity information DQ_INFO can be synchronously outputted to processor via the pin distributed and clock signal clk
101.Validity information DQ_INFO includes validity part 261 and transaction ID part 262.If from volatile memory 221
The data D1 of output to data D4 corresponds to the validity portion of cache-miss, then exportable validity information DQ_INFO
Divide 261, the validity part 261, which has, indicates data D1 to value " I " invalid data D4.For example, it is exportable to have
The validity part 261 of logical value " 0 ".In addition, exportable with being confirmed as invalid data due to cache-miss
The corresponding transaction ID TID of data D1 to data D4.If transaction ID TID has logical value " 010 ", corresponding to trading standard
Knowing TID logical value " 010 " can send to processor 101 via the pin for being provided for validity information DQ_INFO.
It should be completely understood by, the number of validity information DQ_INFO position or constitute the effective of validity information DQ_INFO
The number of the position of property each of part 261 and transaction ID part 262 is not limited to described above.
Figure 16 is the block diagram of other features of the memory module for illustrating another embodiment according to concept of the present invention.Ginseng
According to Fig. 1 and Figure 16, non-volatile memory module 300 may include that module controller 310, heterogeneous storage arrangement 320, data are delayed
Rush device 330 and serially there is detection chip 340.Heterogeneous storage arrangement 320, data buffer 330 and serial presence detection core
The operation and configuration of piece 340 and the heterogeneous storage arrangement 220 shown in Fig. 9, data buffer 230 and serially there is detection chip
240 operation and configuration is substantially the same, and therefore its explanation omitted below.
Module controller 310 from the receiving module command/address CA of processor 101 and can may be in response to received module life
Order/address CA controls heterogeneous storage arrangement 320.For example, module controller 310 may be in response to come from processor 101
Module command/address CA to provide nonvolatile memory command/address CA_n and volatibility to heterogeneous storage arrangement 320
Memory command/address CA_v.
Module controller 310 can judge to be based on the module command from processor 101/address CA and mark " TAG "
No generation cache hit or cache-miss.Module controller 310 can be by ordering the module from processor 101
Order/address CA is compared to judge whether to produce cache hit or cache-miss with mark " TAG ".In order to true
Determine cache hit or cache-miss, module controller 310 may include cache manger 315.
Cache manger 315 can assign cache-miss address transaction ID TID and to the trading standard
Know TID to be managed.For example, cache manger 315 can perform cache verification operation and can be by transaction ID
TID is assigned to determining that result is the corresponding read requests of cache-miss and address.In this case, dull increase
The transaction ID of form can be assigned to multiple read requests corresponding with cache-miss or address.Transaction ID TID
It can be provided together with indicating whether to produce the validity information DQ_INFO of cache hit to processor 101.
Herein, mark " TAG " may include a part for address, itself and the data pair being stored in volatile memory 221
Should.In embodiment, module controller 310 can come and the exchange labeling of volatile memory 321 via flag data line TDQ
“TAG”.In embodiment, when writing data in volatile memory 321, mark " TAG " corresponding with the data can
Write under the control of module controller 310 together with the data in volatile memory 321.
In response to the reading order from processor 101, it can export and read via data wire DQ after fixed delay RL
Request data.Module controller 310 can check the result of operation by via the data wire DQ data exported based on cache
Validity information DQ_INFO is sent to processor 101.Validity information DQ_INFO may include and via data wire DQ outputs
The associated validity of data and transaction ID TID.Can refer to that validity information DQ_INFO provided processor 101 can be
The cache-miss data of time point output after delay RL.That is, processor 101 can refer to transaction ID
TID asks cache-miss data again.
In addition, module controller 310 can be based on cache checked result by having via the data wire DQ data exported
Effect property information DQ_INFO is sent to processor 101.Validity information DQ_INFO may include the number with being exported via data wire DQ
According to associated validity and transaction ID TID.It can refer to validity information DQ_INFO and processor 101 provided and can prolonged
The cache-miss data of time point output after slow RL.That is, processor 101 can refer to transaction ID TID
Cache-miss data are asked again.
Module controller 310 can be by information MSG_EN and information MSG_DQ (with reference to 350) and validity information
DQ_INFO is sent to processor 101 together.Validity information DQ_INFO is the letter exported with command/address and data syn-chronization
Breath, and information MSG_EN and information MSG_DQ are not exported then with command/address and data syn-chronization.Can be by using
The unidirectional pin for the notice that non-volatile memory module 300 gets out output is provided to being confirmed as cache-miss
Read requests provide information 350., can be via two pin output message information 350 in embodiment.However, it should be understood that
Information 350 is serially exported via a pin.Information 350 may include that being confirmed as cache before this does not order
In transaction ID in transaction ID corresponding with the data that can be exported.Processor 101 can refer to information 350 (i.e.,
MSG_EN and MSG_DQ) by with indicating that the corresponding read requests of response of invalid data are sent to nonvolatile memory mould again
Block 300.Furthermore, it is to be understood that information 350 (that is, MSG_EN and MSG_DQ) further comprises various information and friendship
Easily mark TID.For example, information 350 (that is, MSG_EN and MSG_DQ) may include associated with the data prepared
Label information TAG.
According to reference picture 16 illustrate embodiment, non-volatile memory module 300 can be exported with data syn-chronization with it is right
The corresponding validity information DQ_INFO of result for the cache verification operation that the read requests are performed.In addition, non-volatile
Memory module 300 can provide the message not exported in cache-miss situation with data syn-chronization to processor 101
Information MSG_EN and information MSG_DQ.Information MSG_EN and information MSG_DQ may include transaction ID and data
The similar information for being capable of internal output.
Figure 17 is to illustrate the handshaking procedure between the processor 101 shown in Figure 16 and non-volatile memory module 300
Flow chart.Reference picture 16 and Figure 17, non-volatile memory module 300 are defeated in response to the read requests from processor 101
Go out data and validity information DQ_INFO corresponding with the data.
In operation S21, the sending module reading order of processor 101 and address (RD and ADD).Nonvolatile memory mould
Block 300 performs read operation in response to the module reading order received and address (RD and ADD) to volatile memory 321.
For example, module reading order and address (RD and ADD) may include to be stored in non-volatile memory module 300 for reading
In data reading order and with the corresponding reading address of the reading data.Non-volatile memory module 300 can be read
It is stored in the data and mark that the corresponding part in address is read described in the Qu Zhongyu of volatile memory 321.
In operation S22, non-volatile memory module 300 can be performed based on result is read to be used to determine cache
The cache verification operation of hit or cache-miss.As described above, cache manger 315 can be by from
The address that reason device 101 is received is compared to perform the cache verification operation with mark " TAG ".
In operation S23, there is branch according to cache checked result in process.If the part and mark of the address
Remember that " TAG " is identical, then non-volatile memory module 300 can determine that generation cache hit.Otherwise nonvolatile memory
Module 300 can determine that generation cache-miss.
If producing cache hit, in operation S24, non-volatile memory module 300 will be deposited from volatibility
The data and validity information DQ_INFO that reservoir 321 is read are sent to processor 101.Validity information DQ_INFO include on
Whether output data corresponds to the information of cache hit or cache-miss.Processor 101 can determine whether via effective
Property the information DQ_INFO data DT_v that receives whether be valid data.That is, non-volatile memory module 300 can be to
Processor 101 provides the information on cache hit as validity information DQ_INFO, so that processor 101 will can be read
Access evidence is recognized as valid data.If the checked data provided from non-volatile memory module 300 are valid data,
The whole data read operation of processor 101 just can terminate.
If producing cache-miss, in operation S25, non-volatile memory module 300 will can indicate to pass through
Sent by the validity information DQ_INFO that the data wire DQ data exported are invalid datas to processor 101.That is, non-
Volatile 300 can export the validity information DQ_INFO for indicating cache-miss to processor 101.
In this case, non-volatile memory module 300 can provide data corresponding with cache-miss to processor 101
Transaction ID TID be used as additional validity information DQ_INFO.Processor 101 can identify TID by store transaction in a tabular form.
After the validity information DQ_INFO for indicating cache-miss is provided to processor 101, in operation
In S26, non-volatile memory module 300 can be read from nonvolatile memory 323 not in the high speed of volatile memory 321
The data of caching.Non-volatile memory module 300 can be in the cache line of volatile memory 321 or individually volatile
Property stores the reading data in memory areas.
In operation S27, if being ready to export the data for being confirmed as cache-miss, non-volatile memories
Device module 300 can send information MSG_EN and information MSG_DQ to processor 101.For example, it is non-volatile
Memory module 300 can activate message enable signal MSG_EN and can via message pin MSG_DQ to processor 101 provide with
Get out the corresponding transaction ID TID of data of output.Information MSG_EN and information MSG_DQ can not be same with data
Step is provided.
In operation S28, processor 101 can receive information MSG_EN and information MSG_DQ and can send and it
Corresponding reading order.Address corresponding with transaction ID TID can individually be managed by processor 101.
In step S29, the exportable data asked by processor 101 of non-volatile memory module 300.In this feelings
Can in the validity information DQ_INFO that the high speed of volatile memory 321 caches this notice there is provided the data asked in shape
Exported together with data.
By using the validity information DQ_INFO exported with data syn-chronization and the message not exported with data syn-chronization
Information MSG_EN and information MSG_DQ illustrates the handshake method between processor 101 and non-volatile memory module 300.
Figure 18 is the timing diagram for elaborating the handshake operation shown in Figure 17.Reference picture 18, is not ordered in cache
In middle situation, according to the non-volatile memory module 300 of conceptual embodiment of the present invention can by validity information DQ_INFO and
Information MSG_EN and information MSG_DQ are sent to processor 101.In this case, processor 101 can refer to
Effect property information DQ_INFO and information MSG_EN and information MSG_DQ again reads off corresponding with cache-miss
Data.
Processor 101 provides the reading order RD and ground for data read request to non-volatile memory module 300
Location ADD.Non-volatile memory module 300 may be in response to received reading order RD and address AD D to volatile memory
321 perform read operation.In detail, the cache manger 315 in module controller 310 may be in response to received life
Order and address operate to perform internally cached verification.Reference picture 12 illustrates that the high speed of non-volatile memory module 300 is delayed
Verification operation is deposited, and therefore the description thereof will be omitted.Module controller 310 with can receiving with read requests via flag data line TDQ
Corresponding mark " the TAG " _ v in location and the result that can be compared based on mark " TAG " _ v to being received with address AD D are judged
Whether cache hit or cache-miss are produced.
Reading order RD and address AD D can received and after specific delays RL, counted via data wire DQ by first
Exported according to DATA_1 to volatile memory 321.In this case, it is assumed that 310 couple of first data DATA_1 of module controller
The result for performing cache verification operation corresponds to cache-miss.In this case, module controller 310 can be defeated
Go out the validity information DQ_INFO for being shaken hands with processor 101.Validity information DQ_INFO may include instruction first
Data DATA_1 is the validity part (that is, " I ") 361 of invalid data.Validity information DQ_INFO can further comprise transaction
Identification division (that is, TID) 362.It can be numbered via the dull increase form of pair transaction corresponding with cache-miss
Come implementation transaction ID part 362.
Processor 101 can be recognized based on validity information DQ_INFO the first data DATA_1 be cache-miss without
Imitate data.Processor 101 can refer to transaction ID TID to store and manage the whole on cache-miss read requests
Information.
After validity information DQ_INFO is sent, non-volatile memory module 300 can internally access non-volatile
Memory 323 is to read cache-miss data.It is non-volatile if getting out output caching miss data
Memory module 300 can send information MSG_EN and information MSG_DQ to processor 101.Can be via a bars
Line disappears by using the independent pin that signal MSG_EN and message data signal MSG_DQ is enabled for output message to provide
Cease information MSG_EN and information MSG_DQ.If providing message by using independent pin to enable signal MSG_EN and disappear
Data-signal MSG_DQ is ceased, then message data signal MSG_DQ may include transaction ID corresponding with the data for getting out output
TID.Different from validity the information DQ_INFO, information MSG_EN and information MSG_DQ exported with data syn-chronization
It can not be exported with data syn-chronization.That is, when non-volatile memory module 300 extract cache-miss data and
During the DSR output extracted, exportable information MSG_EN and information MSG_DQ.
Processor 101 may be in response to information MSG_EN and information MSG_DQ output and by reading order RD and
Address AD D is sent to non-volatile memory module 300 again.In this case, it can be based on being included in information MSG_
Transaction ID TID in EN and information MSG_DQ produces reading order RD and address AD D.
Non-volatile memory module 300 may be in response to received reading order RD and address AD D to volatile storage
Device 321 performs cache verification operation.If producing cache hit, non-volatile memory module 300 will can have
Effect property information DQ_INFO is synchronously outputted with the second data DATA_2 exported after delay RL is read.In this case,
The validity information DQ_INFO of output may include to mean the effective validity parts 351 of the second data DATA_2.It is slow in high speed
Deposit in hit, because transaction ID part 352 is insignificant, therefore can pseudo- state (dummy state) form offer friendship
Easy identification division 352.
Illustrate that one kind exports validity when asking read operation to non-volatile memory module 300 with data syn-chronization
Information DQ_INFO and not with data syn-chronization output message information MSG_EN and information MSG_DQ method.Processor 101
It can recognize that synchronous output data is invalid data based on validity information DQ_INFO, and transaction ID can be received.Processor
101 can via information MSG_EN and information MSG_DQ verification be ready to output data transaction ID TID and can
The read operation associated with the none obtained data due to cache-miss is performed again.
Figure 19 is the block diagram for illustrating the memory module according to Fig. 1 of another embodiment of concept of the present invention.Reference
Fig. 1 and Figure 19, non-volatile memory module 400 may include module controller 410, heterogeneous storage arrangement 420, data buffering
Device 430 and serially there is detection chip 440.Herein, heterogeneous storage arrangement 420, data buffer 430 and serially presence detection
The operation and configuration of chip 440 are with the heterogeneous storage arrangement 220 shown in Fig. 9, data buffer 230 and serially in the presence of detection core
The operation and configuration of piece 240 are substantially the same, and therefore its explanation omitted below.
Module controller 410 from the receiving module command/address CMD/ADD of processor 101 and can may be in response to what is received
Module command/address CMD/ADD controls heterogeneous storage arrangement 420.For example, module controller 410 may be in response to come
From module command/address CMD/ADD of processor 101 come to heterogeneous storage arrangement 420 provide nonvolatile memory order/
Address CA_n and volatile memory commands/address CA_v.
Module controller 410 can be sentenced based on the module command from processor 101/address CMD/ADD and mark " TAG "
It is disconnected whether to produce cache hit or cache-miss.In order to determine cache hit or cache-miss,
Module controller 410 may include cache manger 415.
Cache manger 415 can assign transaction ID TID to cache-miss address and manage the transaction
Identify TID.For example, cache manger 415 can perform cache verification operation and can assign transaction ID TID
To with determining that result is the corresponding read requests of cache-miss or address.In this case, dull increase form
Transaction ID can be assigned to multiple read requests corresponding with cache-miss or address.Transaction ID TID can be with finger
Show that the validity information DQ_INFO for whether producing cache hit is provided to processor 101 together.
Herein, mark " TAG " may include the one of address AD D corresponding with the data being stored in volatile memory 421
Part.In embodiment, module controller 410 can come and the exchange labeling of volatile memory 421 via flag data line TDQ
“TAG”.In embodiment, when writing data in volatile memory 421, mark " TAG " corresponding with the data can
Write under the control of module controller 410 together with the data in volatile memory 421.
In response to the reading order from processor 101, it can export and read via data wire DQ after specific delays RL
Request data.Module controller 410 can be based on cache checked result by via the validity of the data wire DQ data exported
Information DQ_INFO is sent to processor 101.Validity information DQ_INFO may include the data phase with being exported via data wire DQ
The validity and transaction ID TID of association.In addition, when produce cache-miss when, module controller 410 it is exportable not with
The information MSG_EN and information MSG_DQ of data syn-chronization and the validity information DQ_ exported with data syn-chronization
INFO.In addition, module controller 410 synchronously can provide cache information with validity information DQ_INFO to processor 101
Cache_INFO.Cache information Cache_INFO may include the mark " TAG " or read requests of read requests data at a high speed
The dirty information of cache lines.It should be understood that module controller 410 has individually drawing to output caching information Cache_INFO
Pin.
Elaborate non-volatile memory module 100, the non-volatile memory module according to conceptual embodiment of the present invention
200 and the feature of non-volatile memory module 300.Herein, by using wherein volatile memory 121, volatibility are deposited
Reservoir 221 and volatile memory 321 are used as the example of cache memory to illustrate according to conceptual embodiment of the present invention
Handshake method.However, the embodiment of concept of the present invention is not limited to that.Including access speed memory different from each other
In memory module, the feature of concept of the present invention is applicable to meet all memory modules of same reading delay standard.
Figure 20 is the block diagram of the non-volatile memory module according to Fig. 1 of another embodiment of concept of the present invention.
For ease of explanation, the element in addition to heterogeneous storage arrangement 520 and data buffer 530 is eliminated (for example, module is controlled
Device and serially there is detection chip).In addition, for the sake of for ease of illustration, eliminating the detailed description associated with said elements.Ginseng
According to Figure 20, non-volatile memory module 500 includes heterogeneous storage arrangement 520 and data buffer 530.
Different from the heterogeneous storage arrangement 120 shown in Fig. 2, the heterogeneous storage arrangement 520 shown in Figure 20 includes multiple
Volatile memory 521, non-volatile memory controller 522 and multiple nonvolatile memories 523.Volatile memory
521st, each of non-volatile memory controller 522 and nonvolatile memory 523 can pass through independent crystal grain, independent core
Piece or individually encapsulation carry out implementation.Volatile memory 521, non-volatile memory controller 522 and nonvolatile memory
Each of 523 can carry out implementation by independent chip, and individually chip can be via multi-chip package (multi-chip
Package, MCP) implementation is carried out in a package.
Each of the multiple volatile memory 521, which is used to share with non-volatile memory controller 522, deposits
Memory data line MDQ.For example, the first volatile memory VM1 can be with non-volatile memory controller 522 shared first
Memory data line MDQ1.First memory data wire MDQ1 can be connected with data buffer 530.In embodiment, first deposits
Memory data line MDQ1 may include eight lines.N-th volatile memory VMn can be shared with non-volatile memory controller 522
N-th memory data line MDQn.N-th memory data line MDQn can be connected with data buffer 530.In embodiment, n-th deposits
Memory data line MDQn may include eight lines.Each of the multiple volatile memory 521 can be with non-volatile memories
Corresponding one of the shared memory line MDQ1 of device controller 522 into memory data line MDQn, and the multiple storage
Device data wire MDQ1 to memory data line MDQn can be connected with a data buffer 530.
Data buffer 530 can be attached via data wire DQ with processor 101 (reference picture 1).In this case,
Data wire DQ may include a plurality of line, and the number of the line is according to memory data line MDQ1 to memory data line MDQn number
Determined.
In embodiment, the fortune that the non-volatile memory module 500 shown in Figure 20 can be illustrated according to reference picture 3 to Figure 19
Row method is run.For example, when in the first timing receipt to proactive command ACT_n, non-volatile memory module 500
The address associated with volatile memory 521 and nonvolatile memory 523 can be received via address wire.When in the second timing
Order CMD0 is received to when ordering CMD2, non-volatile memory module 500 can be via some of address wire address
Line receives the address associated with volatile memory 521 and nonvolatile memory 523 and can be via in the address wire
Can route selection or reserved line receive the non-volatile expansion associated with volatile memory 521 and nonvolatile memory 523
Site of an exhibition location.
Figure 21 is the square for illustrating the non-volatile memory module according to Fig. 1 of another embodiment of concept of the present invention
Figure.For ease of illustration for the sake of, the explanation associated with the element that reference picture 20 is illustrated is eliminated.Reference picture 21, it is non-volatile to deposit
Memory modules 600 include heterogeneous storage arrangement 620 and data buffer 630.Heterogeneous storage arrangement 620 includes multiple volatile
Property memory 621, non-volatile memory controller 622 and multiple nonvolatile memories 623.
Different from the heterogeneous storage arrangement 520 shown in Figure 20, heterogeneous storage arrangement 620 includes special removing channel
(flush channel)FC.Special removing channel FC is in each of volatile memory 621 and nonvolatile memory control
Data transfer path is provided between device 622 processed.Non-volatile memory module 600 is executable to will be stored in volatile memory
Data in 621 are write to the clear operation of nonvolatile memory 623.Non-volatile memory module 600 can control heterogeneous
Storage arrangement 620 is so that data can be provided to non-volatile memories via special removing channel FC from volatile memory 621
Device controller 622.
In embodiment, the fortune that the non-volatile memory module 600 shown in Figure 21 can be illustrated according to reference picture 3 to Figure 19
Row method is run.
Figure 22 is the block diagram of the non-volatile memory module according to Fig. 1 of another embodiment of concept of the present invention.
Reference picture 22, non-volatile memory module 700 includes module controller MC, multiple heterogeneous storage arrangement HMD, multiple data
Buffer DB, serial there is detection chip and mark special volatile memory TVM.In embodiment, nonvolatile memory
Module 700 can have load reduction dual-inline memory module (load reduced dual in-line memory
Module, LRDIMM) form.For ease of illustration for the sake of, the repeat specification to said elements is omitted.
As described above, module controller MC from processor 101 (reference picture 1) receiving module command/address CA and in response to
The module command received/address CA exports nonvolatile memory command/address CA_n and volatile memory commands/ground
Location CA_v.Can be via different buses by nonvolatile memory command/address CA_n and volatile memory commands/address
CA_v is provided to heterogeneous storage arrangement HMD.
Each of the multiple heterogeneous storage arrangement HMD can carry out implementation by individually encapsulation and can be reference picture
1 to Figure 20 heterogeneous storage arrangement 120 illustrated is one of to heterogeneous storage arrangement 620.As described above, the multiple different
Each of matter storage arrangement HMD may be in response to the nonvolatile memory command/address CA_ from module controller MC
N and volatile memory commands/address CA_v and run., can be by nonvolatile memory command/address CA_n in embodiment
There is provided to the non-volatile memory controller being included in each heterogeneous storage arrangement HMD, and can be by volatile memory
Command/address CA_v is provided to the volatile memory and non-volatile memories included in each heterogeneous storage arrangement HMD
Device controller.
It is serial exist detection chip may include on non-volatile memory module 700 device information DI and can be by device
Information DI is provided to processor 101 (reference picture 1).
Special volatile memory TVM is marked to may be in response to volatile memory commands/ground from module controller MC
Location CA_v and run.The volatibility that heterogeneous storage arrangement HMD can be stored and be stored in by marking special volatile memory TVM is deposited
The mark TAG that data segment in reservoir is associated.Special volatile memory TVM is marked to be sent via flag data line TDQ
And receive mark " TAG ".In embodiment, flag data line TDQ can be by module controller MC, the multiple heterogeneous memory device
Put HMD and mark special volatile memory TVM to share.
Although figure 22 illustrates do not mark special volatile memory TVM to can be configured to and heterogeneous storage arrangement
HMD is similar.For example, the volatile memory included at least one of the multiple heterogeneous storage arrangement HMD
It is used as marking special volatile memory TVM.
In embodiment, the fortune that the non-volatile memory module 700 shown in Figure 22 can be illustrated according to reference picture 3 to Figure 19
Row method is run.
Figure 23 is the square for illustrating the non-volatile memory module according to Fig. 1 of another embodiment of concept of the present invention
Figure.For ease of illustration for the sake of, the explanation to said elements is eliminated.Reference picture 23, non-volatile memory module 800 may include
Module controller MC, multiple volatile memory VM11 to VM1n and VM21 to VM2m, the first non-volatile memory controller
822a and the second non-volatile memory controller 822b, multiple nonvolatile memory NVM11 to NVM1k and NVM21 are extremely
NVM2i, mark special volatile memory TVM, serially there is detection chip and the multiple data buffer DB.In embodiment
In, the non-volatile memory module 800 shown in Figure 23 can have load reduction dual-inline memory module structure.
Some of the multiple volatile memory VM11 to VM1n and VM21 to VM2m volatile memory (for example,
VM11 to VM1n) it can be configured to and the first non-volatile memory controller 822a shared memory lines MDQ.Remaining
Volatile memory VM21 to VM2m can be configured to and the second non-volatile memory controller 822b shared memories
Line MDQ.Each of the multiple volatile memory VM11 to VM1n and VM21 to VM2m can be configured to it is described many
Corresponding one shared memory line MDQ in individual data buffer DB.
Some of the multiple nonvolatile memory NVM11 to NVM1k and NVM21 to NVM2i non-volatile memories
Device (for example, NVM11 to NVM1k) can be configured to transport in response to the first non-volatile memory controller 822a control
OK.Remaining nonvolatile memory NVM21 to NVM2i can be configured in response to the second non-volatile memory controller
822b control and run.
Special volatile memory TVM is marked to can be configured to and module controller MC, the first nonvolatile memory control
Device 822a processed and the second non-volatile memory controller 822b shares flag data line TDQ.
In embodiment, each of element shown in Figure 23 can carry out implementation by multiple semiconductor chips, and
At least some of semiconductor chip in the semiconductor chip can implementation in a package.For example, it is the multiple volatile
Property memory VM11 to VM1n and VM21 to VM2m, the multiple nonvolatile memory NVM11 to NVM1k and NVM21 are extremely
Each of NVM2i, the first non-volatile memory controller 822a and second non-volatile memory controller 822b can
Implementation is carried out by independent semiconductor chip.It is the multiple volatile memory VM11 to VM1n and VM21 to VM2m, described many
Individual nonvolatile memory NVM11 to NVM1k and NVM21 to NVM2i, the first non-volatile memory controller 822a and second
Some of non-volatile memory controller 822b can implementation in a package.
For example, some of the multiple volatile memory VM11 to VM1n and VM21 to VM2m volatile storages
Device (for example, VM11 to VM1n) can implementation in a package, and the first non-volatile memory controller 822a and described many
Some of individual nonvolatile memory NVM11 to NVM1k and NVM21 to NVM2i nonvolatile memory is (for example, NVM11 is extremely
NVM1k) it can be embodied in another encapsulation.
In embodiment, special volatile memory TVM is marked to may include multiple semiconductor chips.For example, mark
Special volatile memory TVM may include multiple special volatile memory chips of mark, the multiple special volatibility of mark
Each of memory chip storage identical mark, error correcting code and dirty information.In this case, though any one
Mark the operation of special volatile memory chip to occur exception, also can come normal via another special volatile memory of mark
Ground writes or output token information, error correcting code information and dirty information.In embodiment, the special volatile storage of mark is included
Device TVM encapsulation may differ from including the encapsulation of other elements.Alternatively, special volatile memory is marked
TVM can carry out implementation in the encapsulation of at least some of element in comprising other elements.
In embodiment, the fortune that the non-volatile memory module 800 shown in Figure 23 can be illustrated according to reference picture 3 to Figure 19
Row method is run.
Figure 24 is the square for illustrating the non-volatile memory module according to Fig. 1 of another embodiment of concept of the present invention
Figure.Reference picture 24, non-volatile memory module 900 may include module controller MC, multiple volatile memory VM, non-volatile
Property Memory Controller 922, nonvolatile memory NVM, mark special volatile memory TVM, serially there is detection chip
And the multiple data buffer DB.For ease of illustration for the sake of, the detailed description to said elements is eliminated.In embodiment,
Non-volatile memory module 900 shown in Figure 24 can have load reduction dual-inline memory module structure.
Different from the non-volatile memory module 800 shown in Figure 23, the non-volatile memory module 900 shown in Figure 24
Nonvolatile memory NVM can be controlled via a non-volatile memory controller 922.That is, the multiple easy
Each of the property lost memory VM is configured to and the shared memory line MDQ of non-volatile memory controller 922.
Special volatile memory TVM is marked to be configured to and module controller MC and non-volatile memory controller
922 shared flag data line TDQ.As described above, based on volatile memory commands/address CA_v, marking special volatibility to deposit
Reservoir TVM can store mark " TAG " or the exportable mark " TAG " being stored therein.
In embodiment, what the non-volatile memory module 900 shown in Figure 24 can be illustrated according to reference picture 3 to Figure 19
Operation method is run.
Figure 25 is the square for illustrating the non-volatile memory module according to Fig. 1 of another embodiment of concept of the present invention
Figure.Reference picture 1 and Figure 25, non-volatile memory module 1000 may include module controller MC, multiple volatile memory
VM11 to VM1n and VM21 to VM2m, the first non-volatile memory controller 1022a and the control of the second nonvolatile memory
Device 1022b, multiple nonvolatile memory NVM11 to NVM1k and NVM21 to NVM2i, mark special volatile memory TVM,
Serially there is detection chip, the multiple data buffer DB and marking of control circuit TC.For ease of illustration for the sake of, eliminate pair
The explanation of said elements.In embodiment, the non-volatile memory module 1000 shown in Figure 25 can have load reduction biserial
Straight cutting memory module structure.
Different from the non-volatile memory module 700 shown in Figure 22 to Figure 24, non-volatile memory module 800 and non-
Volatile 900, the non-volatile memory module 1000 shown in Figure 25 can further comprise marking of control circuit
TC.The control circuit TC is configured to marking special volatile memory TVM to share flag data line TDQ.That is,
Marking of control circuit TC can via flag data line TDQ from mark special volatile memory TVM receive mark " TAG " or via
Flag data line TDQ will mark " TAG " to send to marking special volatile memory TVM.
Module controller MC can control marking of control circuit TC to judge whether to produce cache hit or cache
It is miss, and the exportable judged results of marking of control circuit TC are used as cache information INFO.For example, marking of control electricity
Road TC can be received from the special volatile memory TVM of mark under module controller MC control and be marked " TAG ".Marking of control electricity
Road TC can mark special volatile memory by by the mark " TAG " (or address AD D) from module controller MC with coming from
TVM mark " TAG " is compared to judge whether to produce cache-miss or cache hit.
In embodiment, marking of control circuit TC can carry out implementation in software or hardware, and marking of control circuit TC can
Included in module controller MC or it can be included in the first non-volatile memory controller 1022a and the second non-volatile memories
In each of device controller 1022b.
In embodiment, what the non-volatile memory module 1000 shown in Figure 25 can be illustrated according to reference picture 3 to Figure 19
Operation method is run.
Figure 26 is the square for illustrating the non-volatile memory module according to Fig. 1 of another embodiment of concept of the present invention
Figure.Reference picture 26, non-volatile memory module 1100 includes module controller MC, the multiple heterogeneous memory HMD, mark
Special volatile memory TVM and serially there is detection chip.For ease of illustration for the sake of, eliminate to said elements specifically
It is bright.
Different from the non-volatile memory module 700 shown in Figure 22, the non-volatile memory module shown in Figure 26
1100 do not include multiple data buffers.That is, non-volatile memory module 1100 can have the biserial with register
Straight cutting memory module (registered DIMM, RDIMM) structure.
Each of the multiple heterogeneous memory HMD is directly connected to data wire DQ.In embodiment, described many
In each of individual heterogeneous memory HMD, the nonvolatile memory of control nonvolatile memory and volatile memory
Controller can be configured to shared data line DQ.
In embodiment, processor 101 (reference picture 1) can have detection from the serial of non-volatile memory module 1100
Chip reception device information DI and non-volatile memory module 1100 can be controlled based on the device information DI that is received.This
In situation, device information DI may include non-volatile memory module 1100 above-mentioned operation information (for example read delay RL and
Write latency WL).Even if that is, volatile memory included in each heterogeneous storage arrangement HMD and non-volatile
Property Memory Controller shared data line DQ and exchange number each other via with the independent data wire DQ of request of processor 101
According to, non-volatile memory module 1100 is controlled because processor 101 is based on described device information, therefore processor 101 also may be used
Read operation or write operation are normally performed to non-volatile memory module 1100.
In embodiment, what the non-volatile memory module 1100 shown in Figure 26 can be illustrated according to reference picture 3 to Figure 19
Operation method is run.
Figure 27 is the square for illustrating the non-volatile memory module according to Fig. 1 of another embodiment of concept of the present invention
Figure.Reference picture 27, non-volatile memory module 1200 includes module controller MC, the multiple volatile memory VM11 extremely
VM1n and VM21 to VM2m, the first non-volatile memory controller 1222a and the second non-volatile memory controller
1222b, the multiple nonvolatile memory NVM11 to NVM1k and NVM21 to NVM2i, the special volatile memory of mark
TVM and serially there is detection chip.For ease of illustration for the sake of, the detailed description to said elements is eliminated.
Different from the non-volatile memory module 800 described in Figure 23, the non-volatile memory module shown in Figure 27
1200 may not include multiple data buffer DB.That is, non-volatile memory module 1200 can have with register
Dual-inline memory module structure.In this case, the multiple volatile memory VM11 to VM1n and VM21 is extremely
Some of VM2m volatile memory (for example, VM11 to VM1n) can be common with the first non-volatile memory controller 1222a
Data wire DQ is enjoyed, and remaining volatile memory (for example, VM21 to VM2m) can be with the second non-volatile memory controller
1222b shared data lines DQ.
As in the explanation that reference picture 26 is provided, though data wire DQ by the multiple volatile memory VM11 extremely
VM1n and VM21 to VM2m and the first non-volatile memory controller 1222a and the second non-volatile memory controller
1222b shares, because processor 101 is based on from the device information DI operations that serially there is detection chip, therefore processor 101
Also non-volatile memory module can be normally controlled, but regardless of volatile memory VM11 to VM1n and VM21 to VM2m and
How is data exchange between one non-volatile memory controller 1222a and the second non-volatile memory controller 1222b.
In embodiment, what the non-volatile memory module 1200 shown in Figure 27 can be illustrated according to reference picture 3 to Figure 19
Operation method is run.
Figure 28 is the square for illustrating the non-volatile memory module according to Fig. 1 of another embodiment of concept of the present invention
Figure.Reference picture 28, non-volatile memory module 1300 includes module controller MC, multiple volatile memory VM, non-volatile
Property Memory Controller 1322, nonvolatile memory NVM, mark special volatile memory TVM and serially there is detection core
Piece.For ease of illustration for the sake of, the detailed description to said elements is eliminated.
Different from the non-volatile memory module 900 shown in Figure 24, the non-volatile memory module shown in Figure 28
1300 may not include multiple data buffer DB.That is, non-volatile memory module 1300 can have with register
Dual-inline memory module structure.The multiple volatile memory VM is configured to and non-volatile memory controller
1322 shared data line DQ.
As noted previously, as processor 101 based on from serially there is detection chip device information DI operation, therefore place
Reason device 101 can normally control non-volatile memory module 1300, but regardless of the multiple volatile memory VM with it is non-easily
How is data exchange between the property lost Memory Controller 1322.
Above-mentioned non-volatile memory module is only example, and embodiment is not limited to that.Can be to according to of the invention general
The non-volatile memory module for reading embodiment carries out various combinations or modification.
Figure 29 is to illustrate the nonvolatile memory being included in non-volatile memory module according to concept of the present invention
Block diagram.Reference picture 29, nonvolatile memory 1400 may include memory cell array 1410, address decoder 1420,
Control logic circuit 1430, page buffer 1440 and input/output circuitry 1450.
Memory cell array 1410 includes multiple memory blocks each with multiple memory cells.It is the multiple
Memory cell can be connected with a plurality of wordline WL.Each memory cell can be single level cell element (single of one position of storage
Level cell, SLC) or storage many level cell elements (multi-level cell, MLC) of at least two.
Address decoder 1420 can receive from non-volatile memory controller 122 (reference picture 2) and decode address AD DR.
In embodiment, the address AD DR received from non-volatile memory controller 122 can be instruction nonvolatile memory 1400
Memory block provider location physical address.Address decoder 1420 can be selected in wordline WL based on decoded address
At least one and the voltage of selected wordline can be driven.
Control logic circuit 1430 may be in response to the order received from non-volatile memory controller 122 (reference picture 2)
CMD and control logic CTRL controls address decoder 1420, page buffer 1440 and input/output circuitry 1450.
Page buffer 1440 is connected via multiple bit lines BL with memory cell array 1410 and via a plurality of data lines DL
It is connected with input/output circuitry 1450.Page buffer 1440 can be by sensing the voltage of the multiple bit lines BL come to being stored in
Data in memory cell array 1410 are stored.Alternatively, page buffer 1440 can be based on via institute
The data of a plurality of data lines DL receptions are stated to adjust the voltage of the multiple bit lines BL.
Under the control of control logic circuit 1430, input/output circuitry 1450 can be from non-volatile memory controller
122 (reference pictures 2) receive data and can sent received data to page buffer 1440.Alternatively, it is defeated
Enter/output circuit 1450 can receive from page buffer 1440 and data and can send received data to nonvolatile memory
Controller 122.
In embodiment, non-volatile memory controller 122 can be based on from module controller 110 (reference picture 2)
Nonvolatile memory command/address CA_n come produce address AD DR, order CMD and control signal CTRL.
Figure 30 is illustrated according to the Cellular structure of conceptual embodiment phase-changing storage device of the present invention and regarding for physical characteristic
Figure, its as non-volatile memory device example.Reference picture 30, memory cell 1500 includes variable resistance and access
Transistor NT.Variable resistance is made up of top electrode 1510, phase-change material 1520, contact plunger 1530 and hearth electrode 1540.Top
Electrode 1510 is connected to bit line BL.Hearth electrode 1540 is connected between contact plunger 1530 and access transistor NT.Contact plunger
1530 are formed by conductive material (for example, titanium nitride) and are also designated as " heater connector ".Phase-change material 1520 is located at top electrode
Between 1510 and contact plunger 1530.The phase of phase-change material 1520 can according to the amplitude of the current impulse provided, continue when
Between, fall time etc. and change.The phase of phase-change material 1520 corresponding with " set " or RESET is by as shown in Figure 30
Amorphous volume 2150 is determined.In general, amorphous phase corresponds respectively to reset phase and set phase with crystalline phase.With phase transformation material
The phase of material 1520 advances to crystalline phase from amorphous phase, and amorphous volume reduces.Phase-change material 1520 has non-according to what is formed
The resistance that crystal accumulates 2150 and changed.That is, the value of write data according to different current impulses based on being formed
The amorphous volume 2150 of phase-change material 1520 is determined.
Figure 31 to Figure 32 is illustrated according to conceptual embodiment of the present invention comprising memory in the nonvolatile memory
The view of cell element.Figure 31 illustrates spin-transfer torque magnetic RAM (spin-transfer torque
Magnetic random access memory, STT-MRAM) three-dimensional Cellular structure.By reference picture 32 illustrate reluctance type with
Machine accesses the Cellular structure of memory.
Figure 31 illustrates the memory cell 1600 of spin-transfer torque magnetic RAM.Memory cell
1600 may include MTJ (magnetic tunnel junction, MTJ) element 1610 and cell transistor (cell
Transistor, CT) 1620.Wordline WL0 is connected with the gate pole of cell transistor 1620.The first end warp of cell transistor 1620
It is connected by magnetic tunnel junction element 1610 with bit line BL0.Second end of cell transistor 1620 is connected to source electrode line SL0.
Magnetic tunnel junction element 1610 may include fixed bed (pinned layer) 1613, free layer 1611 and be interposed in it
Between tunnel layer 1612.The direction of magnetization of fixed bed 1613 can be fixed, and free layer 1611 the direction of magnetization certain
Under the conditions of can be identical or opposite with the direction of magnetization of the fixed bed.Memory cell 1600 can further comprise for example antiferromagnetic
Property layer a (not shown) be fixed with the direction of magnetization to fixed bed 1613.
In order to write data in memory cell 1600, cell transistor is connected by applying voltage to wordline WL0
1620, and apply reset current between bit line BL0 and source electrode line SL0.In order to read data from memory cell 1600, pass through
Apply voltage to wordline WL0 to connect cell transistor 1620, and read from bit line BL0 to application on source electrode line SL0 direction
Obtaining current.In this case, the data being stored in memory cell 1600 are according to the resistance value measured under these conditions
To determine.
Figure 32 is the circuit diagram for the memory cell 1700 for illustrating reluctance type storage arrangement.Reference picture 32, reluctance type is deposited
The memory cell 1700 of reservoir device includes variable resistor element (Rv) 1710 and selection element (STR) 1720.
Variable resistor element 1710 includes the variable-resistance material for data storage.Based on wordline WL voltage, selection
Element 1720 supplies variable resistor element 1710 electric current or stops the electric current supplied variable resistor element 1710.Selection element
1720 carry out implementation by nmos pass transistor as shown in figure 32.However, selection element 1720 can be by such as PMOS transistor and two poles
One of switch elements such as pipe carry out implementation.
Variable resistor element 1710 includes a pair of electrodes 1711 and 1713 and the number formed between the pair of electrode
According to storage film 1712.Data storage film 1712 can be formed by bipolar resistive memory material or Unipolar resistance storage material.Bipolar electric
Resistance storage material is programmed for SM set mode or reset state by pulse polarity.Unipolar resistance storage material can be by same pulse polarity
It is programmed for SM set mode or reset state.Unipolar resistance storage material includes single transition metal oxide (such as nickel oxide
(NiOx) or titanium nitride (TiOx)).Bipolar resistive memory material includes perovskite series material.
Spin-transfer torque magnetic RAM and resistive random access memory are illustrated as included in non-easy
The example of memory cell in the property lost memory.However, it should be understood that according to the non-volatile memories of conceptual embodiment of the present invention
The memory cell of device is not limited to that.That is, the memory cell of nonvolatile memory can with flash memory,
The form of one of phase change random access memory devices, magnetic RAM or ferroelectric RAM (FRAM)
There is provided.
Figure 33 is the side for the volatile memory for illustrating the non-volatile memory module according to conceptual embodiment of the present invention
Block figure.Reference picture 33, volatile memory 1800 may include memory cell array 1810, address buffer 1820, row decoding
Device (X- decoders) 1830, column decoder (Y- decoders) 1840, sense amplifier and write driver 1850 and input/output
Circuit 1860.
Memory cell array 1810 may include the multiple memory cells being connected with a plurality of wordline WL and multiple bit lines BL.
The multiple memory cell can be located at the wordline and the intersection of the bit line respectively.It is the multiple in embodiment
Each of memory cell may include storage and access transistor.
Address buffer 1820 can slave module controller 110 (reference picture 2) reception and interim storage address AD D.Implementing
In example, address buffer 1820 can provide X- decoders 1830 and receive address AD D row address ADD_row and Y- can be solved
Code device 1840 provides the column address ADD_col for receiving address AD D.
X- decoders 1830 are connected via bit line BL with memory cell array 1810.X- decoders 1830 may be in response to come
Activated from the rwo address strobe signals RAS of module controller 110 in a plurality of wordline WL and correspond to row address ADD_row
At least one.
Y- decoders 1840 can receive column address ADD_col from address buffer 1820.Believe when receiving column address strobe
During number CAS, Y- decoders 1840 can control sense amplifier and write driver 1850 based on column address ADD_col.
Sense amplifier and write driver 1850 are connected via the multiple bit lines BL with memory cell array 1810.
Sense amplifier and write driver 1850 can sense the voltage change of each bit line.Alternatively, amplification is read
Device and write driver 1850 can adjust the electricity of the multiple bit lines based on the data received from input/output circuitry 1860
Pressure.
Input/output circuitry 1860 can receive data from sense amplifier and write driver 1850 and can be via memory
Data wire MDQ (or data wire DQ) exports received data.Alternatively, input/output circuitry 1860 can be through
Received data by memory data line MDQ (or data wire DQ) and sense amplifier and write driver 1850 can be provided and connect
The data of receipts.
In embodiment, address AD D can be the volatile storage provided included in slave module controller 110 (reference picture 2)
Address in device command/address CA_v.Rwo address strobe signals RAS and column address gating signal CAS can be included in slave module
Signal in volatile memory commands/address CA_v that controller 110 is provided.
Figure 34 is the side for the custom system for illustrating the application non-volatile memory module according to conceptual embodiment of the present invention
Block figure.Reference picture 34, custom system 3000 may include processor 3001 and multiple memories 3110 to memory 3140.
Processor 3001 may include Memory Controller 3002.Memory Controller 3002 can via a bus 3003 with
Memory 3110 and memory 3140 are communicated.In embodiment, bus 3003 may include respectively with the multiple memory
3110 dedicated bus connected to memory 3140 or by the multiple memory 3110 to memory 3140 share it is shared total
Line.In embodiment, bus 3003 may include data wire DQ, memory data line MDQ and the mark illustrated referring to figs. 1 to Figure 34
At least one of data wire TDQ.
In embodiment, at least some of memory of the multiple memory 3110 into memory 3140 can be reference picture
1 to Figure 34 non-volatile memory module illustrated can be run according to the operation method illustrated referring to figs. 1 to Figure 34.
Alternatively, at least some of into memory module 3140 of the multiple memory module 3110 deposits
It is volatile that each of memory modules may include that each of nonvolatile memory, and its remaining memory module may include
Property memory.Memory module including volatile memory is used as including the memory module of nonvolatile memory
Cache memory.That is, as illustrated referring to figs. 1 to Figure 34, the multiple memory module 3110 to memory
Some of module 3140 memory module is used as the main storage of custom system 3000, and its remaining memory module can
It is used as cache memory.It can be referring to figs. 1 to Figure 33 to be used as each of memory of cache memory
The volatile memory of elaboration can be with running referring to figs. 1 to the volatile memory identical mode that Figure 33 is illustrated.
In embodiment, the control that Memory Controller 3002 can illustrate for Memory Controller or referring to figs. 1 to Figure 33
Device can be with running referring to figs. 1 to the Memory Controller identical mode that Figure 33 is illustrated.
Figure 35 is the server system for illustrating the application Nonvolatile memory system according to conceptual embodiment of the present invention
View.Reference picture 34, server system 2000 may include multiple server racks 2100.Each of server rack 2100
It may include multiple non-volatile memory modules 2200.Non-volatile memory module 2200 can be with being separately contained in server machine
Processor in frame 2100 is directly connected to.For example, non-volatile memory module 2200 can have lilline Memory
The form of module and it can be arranged on electrically connect with processor dual-inline memory module socket enter with the processor
Row communication.In embodiment, non-volatile memory module 2200 is used as the memory of server system 2000.Implementing
In example, each of the multiple non-volatile memory module 2200 can be referring to figs. 1 to the non-volatile of Figure 33 elaborations
Memory module can be run according to the operation method illustrated referring to figs. 1 to Figure 33.
Although elaborating concept of the present invention with reference to exemplary embodiment, one of skill in the art will be shown and
It is clear to, under conditions of the spirit and scope without departing substantially from concept of the present invention, can be variously modified and change.It will be understood, therefore, that
Above-described embodiment is simultaneously nonrestrictive but illustrative.
Claims (20)
1. one kind accesses volatile memory devices, non-volatile memory device and to the volatile memory devices and institute
The method for stating the controller that non-volatile memory device is controlled, it is characterised in that methods described includes：
Received and volatile memory devices and described non-volatile via First Line in the first timing by the controller
The associated row address of storage arrangement；
Receive the extension associated with the non-volatile memory device via the second line in the second timing by the controller
Address；And
Received and the non-volatile memory device and the volatibility via the 3rd line in the 3rd timing by the controller
The associated column address of storage arrangement.
2. according to the method described in claim 1, it is characterised in that further comprise：
Activation explosion command is received via order input line, the activation explosion command is indicated described in second timing transmission
Extended address.
3. method according to claim 2, it is characterised in that further comprise：
Additional activation explosion command is received via auto-precharge input line, and the additional activation explosion command is indicated described the
Extended address described in two timing transmissions.
4. according to the method described in claim 1, it is characterised in that further comprise：
In the first timing receipt proactive command；
Explosion command is activated in second timing receipt；And
In the 3rd timing receipt read or write command.
5. method according to claim 4, it is characterised in that forbid between the described first timing and second timing
Receive another order.
6. method according to claim 4, it is characterised in that described second regularly, the signal of " RAS_n/A16 " line,
The signal, the signal of " WE_n/A14 " line of " CAS_n/A15 " line are respectively low level, high level and high level.
7. method according to claim 6, it is characterised in that the signal of " A10/AP " line is high electricity in second timing
It is flat.
8. according to the method described in claim 1, it is characterised in that second line includes the 0th article of address wire to Article 9
Location line.
9. according to the method described in claim 1, it is characterised in that in the described second timing, storehouse group address line, storehouse address are defeated
Enter line, chip identifier line, burst truncated signal line and Sub_clause 11 address wire, the 13rd article of address wire and the 17th article of address wire each
From with the arbitrary value defined by one of high level and low level.
10. according to the method described in claim 1, it is characterised in that further comprise：
The mark associated with the row address and the column address is read from the volatile memory devices by the controller
Note；And
If the mark is identical with the extended address, the volatile memory devices are accessed by the controller.
11. method according to claim 10, it is characterised in that further comprise：
, will be with the row address by the controller when the controller writes data in the volatile memory devices
And the associated dirty mark of the column address is written as dirty situation in the volatile memory devices.
12. method according to claim 11, it is characterised in that further comprise：
When the controller writes data in the volatile memory devices, by the controller by the extended address
Write as the mark associated with the row address and the column address in the volatile memory devices.
13. method according to claim 10, it is characterised in that further comprise：
If it is described mark be different from the extended address, by the controller from the volatile memory devices read with
The row address and the associated dirty mark of the column address；And
If the dirty mark indicates dirty situation, the row address is based on by the controller and the column address reads data
And the reading data are write by the nonvolatile memory based on the row address, the column address and the extended address
In device.
14. method according to claim 13, it is characterised in that further comprise：
During read operation, after write operation is completed to the non-volatile memory device, it is based on by the controller
The row address, the column address and the extended address read the second data from the non-volatile memory device and are based on
The row address and the column address write second data in the volatile memory devices.
15. method according to claim 13, it is characterised in that further comprise：
During write operation, after write operation is completed to the non-volatile memory device, it is based on by the controller
The row address and the column address write the second data in the volatile memory devices and based on the row address, institute
Column address and the extended address is stated to write second data in the non-volatile memory device.
16. a kind of memory module, it is characterised in that including：
Non-volatile memory device；
Volatile memory devices；And
Controller, to control the non-volatile memory device and the volatile memory devices,
Wherein described controller is received and volatile memory devices and described non-volatile in the first timing via First Line
Property the associated row address of storage arrangement, received in the second timing via the second line and the non-volatile memory device phase
The extended address of association, and received and the non-volatile memory device and described volatile via the 3rd line in the 3rd timing
Property the associated column address of storage arrangement.
17. a kind of method of the main storage of cache memory for accessing the first kind and Second Type, it is characterised in that
Methods described includes：
Shared address is sent out via the address wire associated with the cache memory of the first kind using multiple sequences
Deliver to the cache memory of the first kind and the main storage of the Second Type；And
Using at least one sequence via the address wire associated with the cache memory of the first kind
Extended address is sent to the main storage of the Second Type.
18. method according to claim 17, it is characterised in that the shared address and the extended address are converted into
The home address of the main storage of the Second Type, and the converted home address is via only with the address wire
Vertical independent line is transmitted to the main storage of the Second Type.
19. method according to claim 17, it is characterised in that at least one described sequence is performed in the multiple sequence
Row.
20. method according to claim 17, it is characterised in that further comprise：
Described first is sent commands to via the order wire associated with the cache memory of the first kind
The cache memory of type and the main storage of the Second Type,
Wherein described order is converted into the order of the main storage of the Second Type, and the converted order warp
Transmitted by the independent line with the order wire independence to the main storage of the Second Type.
Applications Claiming Priority (8)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201662278610P | 2016-01-14 | 2016-01-14 | |
| US62/278,610 | 2016-01-14 | ||
| KR10-2016-0008210 | 2016-01-22 | ||
| KR1020160008214A KR20170085918A (en) | 2016-01-14 | 2016-01-22 | Memory module comprising heterogeneous memory devices and operation method thereof |
| KR20160008210 | 2016-01-22 | ||
| KR10-2016-0008214 | 2016-01-22 | ||
| KR1020160029743A KR20170085923A (en) | 2016-01-14 | 2016-03-11 | Method for accessing heterogeneous memories and memory module including heterogeneous memories |
| KR10-2016-0029743 | 2016-03-11 |
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| TWI688859B (en) | 2018-12-19 | 2020-03-21 | 財團法人工業技術研究院 | Memory controller and memory page management method |
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