CN107040208B

CN107040208B - Circuit device, oscillator, electronic apparatus, and moving object

Info

Publication number: CN107040208B
Application number: CN201611167174.2A
Authority: CN
Inventors: 米泽岳美
Original assignee: Seiko Epson Corp
Current assignee: Seiko Epson Corp
Priority date: 2016-01-06
Filing date: 2016-12-16
Publication date: 2022-03-22
Anticipated expiration: 2036-12-16
Also published as: JP6680121B2; JP2017123631A; CN107040208A

Abstract

A circuit device, an oscillator, an electronic apparatus, and a moving object. The circuit device includes: a digital interface section; a processing unit; an oscillation signal generation circuit that generates an oscillation signal; a clock signal generation circuit that generates a clock signal having a frequency obtained by multiplying the frequency of the oscillation signal; and the 1 st and 3 rd terminal groups for connecting the digital interface part and the clock signal generating circuit. The 1 st terminal group is disposed in the 1 st region along the 1 st side of the circuit device, and the 3 rd terminal group is disposed in any one of the 2 nd, 3 rd and 4 th terminal regions.

Description

Circuit device, oscillator, electronic apparatus, and moving object

Technical Field

The present invention relates to a circuit device, an oscillator, an electronic apparatus, a mobile object, and the like.

Background

Oscillators such as an OCXO (oven controlled crystal oscillator) and a TCXO (temperature compensated crystal oscillator) have been known. For example, OCXO is used as a reference signal source in a base station, a network router, a measurement device, and the like. In such oscillators such as OCXO and TCXO, there is a demand for high accuracy of oscillation frequency.

As a conventional technique of such an oscillator, for example, there is a technique disclosed in japanese patent laid-open No. 2015-82815. In this conventional technique, aging correction of the oscillation frequency is performed in order to increase the accuracy of the oscillation frequency. Specifically, a storage unit for storing information on correspondence between a correction value of a control voltage of an oscillation frequency and an elapsed time measurement unit are provided. Also, aging correction is performed based on the correspondence information of the correction value and the elapsed time stored in the storage section, and the elapsed time measured by the elapsed time measurement section.

As described above, oscillators such as OCXOs and TCXOs are required to have a high oscillation frequency of an oscillation signal. In addition, an external system sometimes requires a clock signal having a frequency different from the oscillation frequency.

On the other hand, in order to cope with applications such as forming a loop of a PLL circuit using a frequency control data generation unit outside the circuit device, it is also conceivable to provide a digital interface unit in the circuit device.

However, it is known that when such a digital interface unit is provided, the accuracy of the clock signal and the oscillation signal may be degraded due to phase noise or the like caused by communication noise in the digital interface unit.

Disclosure of Invention

According to some aspects of the present invention, a circuit device, an oscillator, an electronic apparatus, a mobile object, and the like, which can generate a clock signal and the like with less noise, can be provided.

One embodiment of the present invention relates to a circuit device including: a digital interface section; a processing unit which receives data from an external device via the digital interface unit and performs signal processing; an oscillation signal generation circuit that generates an oscillation signal having an oscillation frequency set by the frequency control data using an oscillator and the frequency control data from the processing unit; a clock signal generation circuit having at least a phase comparison unit and generating a clock signal having a frequency obtained by multiplying an oscillation frequency of the oscillation signal; a1 st terminal group for connection of the digital interface part; a2 nd terminal group for connection of an oscillation circuit of the oscillation signal generation circuit; and a3 rd terminal group for connection of the clock signal generation circuit, wherein when a side of the circuit device intersecting with a1 st side is a2 nd side, a side opposite to the 1 st side is a3 rd side, and a side opposite to the 2 nd side is a4 th side, the 1 st terminal group is disposed in a1 st terminal region along the 1 st side, and the 3 rd terminal group is disposed in any one of a2 nd terminal region along the 2 nd side, a3 rd terminal region along the 3 rd side, and a4 th terminal region along the 4 th side.

In one embodiment of the present invention, data is input from an external device to the processing unit via the digital interface unit, and signal processing is executed. An oscillation signal is generated by an oscillation signal generation circuit using the oscillator and frequency control data from the processing unit, and a clock signal having a frequency obtained by multiplying the oscillation frequency of the oscillation signal is generated by a clock signal generation circuit. In one embodiment of the present invention, the 1 st terminal group for connection of the digital interface is disposed in the 1 st terminal region along the 1 st side of the circuit device. On the other hand, the 3 rd terminal group for connection of the clock signal generating circuit is disposed in any one of the 2 nd, 3 rd, and 4 th terminal regions. In this way, the 1 st terminal group for connection of the digital interface unit and the 3 rd terminal group for connection of the clock signal generation circuit can be separated by a distance. This can reduce phase noise and the like generated in the clock signal due to communication noise and the like in the digital interface unit, and can realize a circuit device capable of generating a clock signal and the like with less noise.

In one aspect of the present invention, the 2 nd terminal group may be disposed in one of the 2 nd terminal region and the 3 rd terminal region, and the 3 rd terminal group may be disposed in the other of the 2 nd terminal region and the 3 rd terminal region.

In this way, the distance between the 1 st terminal group for connection of the digital interface unit and the 2 nd terminal group for connection of the oscillator circuit and the distance between the 1 st terminal group for connection of the digital interface unit and the 3 rd terminal group for connection of the clock signal generation circuit can be separated. This reduces phase noise and the like generated in the clock signal and the oscillation signal due to communication noise and the like in the digital interface unit.

In one aspect of the present invention, the 1 st side may be a short side of the circuit device, and the 1 st terminal group may be disposed in the 1 st terminal region along the 1 st side which is the short side.

In this way, the 1 st terminal group and the other terminal groups can be separated by a distance corresponding to the length of the long side of the circuit device, for example, and phase noise and the like due to communication noise and the like in the digital interface section can be reduced.

In one embodiment of the present invention, when a distance between the 1 st terminal group and the 2 nd terminal group is L12, a distance between the 1 st terminal group and the 3 rd terminal group is L13, and a distance between the 2 nd terminal group and the 3 rd terminal group is L23, at least one of L12 and L13 may be longer than L23.

Thus, the distance L12 between the 1 st terminal group and the 2 nd terminal group and the distance L13 between the 1 st terminal group and the 3 rd terminal group can be increased, thereby reducing phase noise.

In one aspect of the present invention, the oscillation signal generation circuit may be configured such that frequency control data from an external frequency control data generation unit that compares an input signal based on the oscillation signal with a reference signal is input to the processing unit via the 1 st terminal group and the digital interface unit, and the oscillation signal generation circuit generates the oscillation signal based on the frequency control data input from the external frequency control data generation unit via the processing unit.

In this way, the external frequency control data generation unit provided outside the circuit device can be effectively and flexibly used to generate the oscillation signal in which the oscillation frequency is set by the frequency control data from the external frequency control data generation unit.

In one aspect of the present invention, the circuit device may include a phase comparison unit that compares phases of an input signal based on the oscillation signal and the reference signal, wherein the oscillation signal generation circuit may generate the oscillation signal based on the frequency control data input from the external frequency control data generation unit via the processing unit in a1 st mode, and generate the oscillation signal based on the frequency control data input from the phase comparison unit via the processing unit in a2 nd mode.

In this way, it is possible to cope with both the case where the external system has the external frequency control data generation unit and the case where the external system does not have the external frequency control data generation unit, and convenience is improved.

In one embodiment of the present invention, the digital interface unit may be a 2-wire, 3-wire, or 4-wire serial interface circuit including a serial data line and a serial clock line.

In this way, when the external device has a 2-wire, 3-wire, or 4-wire serial interface circuit, 2-wire, 3-wire, or 4-wire serial interface processing can be performed with the external device, and data from the external device can be input to the processing unit.

In one aspect of the present invention, when a direction from the 1 st side to the 3 rd side is a1 st direction, the processing unit may be disposed on the 1 st direction side of the 1 st terminal group.

In this way, data from an external device input using the terminal of the 1 st terminal group can be input to the processing unit via the digital interface unit via a short-path signal path. This can reduce adverse effects caused by communication noise generated in the digital interface unit.

In one aspect of the present invention, the 2 nd terminal group may be disposed in the 2 nd terminal region, the 3 rd terminal group may be disposed in the 3 rd terminal region, and the clock signal generation circuit may be disposed on the 2 nd direction side of the 3 rd terminal group when the direction opposite to the 1 st direction is the 2 nd direction.

In this way, the output signal or the input signal of the clock signal generation circuit can be output or input through a short-path signal path between the clock signal generation circuit and the terminal of the 3 rd terminal group. This can reduce adverse effects caused by clock noise generated in the clock signal generation circuit.

In one aspect of the present invention, the processing unit may be disposed between the 1 st terminal region and the clock signal generation circuit.

In this way, the processing unit and the clock signal generation circuit are interposed between the 1 st terminal group in the 1 st terminal region and the 3 rd terminal group in the 3 rd terminal region. Therefore, at least a distance corresponding to the width of the processing unit and the width of the clock signal generation circuit can be secured as the distance between the 1 st terminal group and the 3 rd terminal group, and adverse effects due to communication noise and the like generated in the digital interface unit can be reduced.

In one aspect of the present invention, the oscillation circuit may be disposed between the processing unit and the clock signal generation circuit.

In this way, the processing unit, the oscillation circuit, and the clock signal generation circuit are interposed between the 1 st terminal group in the 1 st terminal region and the 3 rd terminal group in the 3 rd terminal region. Therefore, as the distance between the 1 st terminal group and the 3 rd terminal group, at least the distance corresponding to the width of the processing unit, the width of the oscillation circuit, and the width of the clock signal generation circuit can be secured, and adverse effects due to communication noise and the like generated in the digital interface unit can be reduced.

In one aspect of the present invention, when a direction from the 2 nd side to the 4 th side is a3 rd direction, the oscillation circuit may be disposed on the 3 rd direction side of the 2 nd terminal group.

In this way, the oscillation circuit can be connected to the terminal of the 2 nd terminal group by the signal line having a short path, and adverse effects due to parasitic capacitance of the signal line and the like can be reduced.

In one aspect of the present invention, the vibrator may be a thermostat-groove-shaped vibrator having a thermostat, and the 4 th terminal group including the thermostat control terminal of the thermostat-groove-shaped vibrator may be disposed in the 4 th terminal region along the 4 th side.

In this way, the 4 th terminal group including the thermostatic bath control terminal can be arranged by effectively utilizing the 4 th terminal region of the circuit device.

In one aspect of the present invention, the circuit device may include a constant temperature bath control circuit connected to the constant temperature bath control terminal and configured to control a constant temperature bath of the constant temperature bath-type oscillator, and the constant temperature bath control circuit may be disposed on the 4 th direction side of the 4 th terminal region when a direction from the 4 th side to the 2 nd side is a4 th direction.

In this way, the thermostat control circuit can be connected to the thermostat control terminal of the 4 th terminal group through a short-path signal path, and more appropriate thermostat control can be achieved.

In one aspect of the present invention, the oscillation circuit may be disposed between the thermostatic bath control circuit and the 2 nd terminal area.

Thus, the thermostat control circuit and the oscillator circuit can be arranged by effectively utilizing the region between the 4 th terminal region and the 2 nd terminal region, and layout efficiency can be improved and noise can be reduced.

In one aspect of the present invention, the processing unit may perform processing for estimating a true value of the frequency control data by kalman filtering processing, and perform aging correction of the frequency control data based on the estimated true value.

Thus, aging correction can be realized in consideration of the influence of observation noise and system noise, and the accuracy of aging correction can be improved.

Another aspect of the present invention relates to an oscillator including: the circuit device according to any one of the above aspects; and the vibrator.

Another embodiment of the present invention relates to an electronic device including the circuit device according to any one of the above embodiments.

Another aspect of the present invention relates to a mobile body including the circuit device according to any one of the above aspects.

Drawings

Fig. 1 shows a basic configuration example of a circuit device according to the present embodiment.

Fig. 2 is a detailed configuration example of the circuit device of the present embodiment.

Fig. 3 is an explanatory diagram of a phase noise problem with respect to the oscillation signal.

Fig. 4 is an explanatory diagram of a phase noise problem with respect to the oscillation signal.

Fig. 5 shows an example of a layout arrangement of the circuit device according to the present embodiment.

Fig. 6 shows another example of the layout arrangement of the circuit device according to the present embodiment.

Fig. 7 shows another example of the layout arrangement of the circuit device according to the present embodiment.

Fig. 8 shows another example of the layout arrangement of the circuit device according to the present embodiment.

Fig. 9 shows another example of the layout arrangement of the circuit device according to the present embodiment.

Fig. 10 shows another example of the layout arrangement of the circuit device according to the present embodiment.

Fig. 11 shows a configuration example 1 of the clock signal generation circuit.

Fig. 12 shows an example of the 2 nd configuration of the clock signal generation circuit.

Fig. 13 shows an example of the structure of the temperature sensor.

Fig. 14 shows an example of the configuration of the oscillation circuit.

FIG. 15 shows a configuration example 1 of the digital I/F section.

FIG. 16 shows an example of the structure of the digital I/F section 2.

Fig. 17 shows an example of the configuration of the reference signal generating circuit.

FIG. 18 shows an example of the structure of the thermostatic bath control circuit.

Fig. 19 is an explanatory diagram of element variations with respect to aging characteristics.

Fig. 20 is an explanatory diagram for hold-over mode (hold-over).

Fig. 21 is an explanatory diagram for the hold mode.

Fig. 22 is an explanatory diagram of the aging correction using the kalman filter process.

Fig. 23 is an explanatory diagram of the aging correction using the kalman filter process.

Fig. 24 is a detailed configuration example of the processing unit.

Fig. 25 is an explanatory diagram of the operation of the processing unit.

Fig. 26 is an explanatory diagram of the operation of the processing unit.

Fig. 27 shows an example of the configuration of the aging correcting unit.

Fig. 28 is an explanatory diagram of a modification of the present embodiment.

Fig. 29 shows an example of the structure of the oscillator.

Fig. 30 shows an example of the structure of the electronic device.

Fig. 31 shows a configuration example of a mobile body.

Fig. 32 shows a detailed configuration example of the oscillator.

Fig. 33 is a configuration example of a base station as one of electronic devices.

Detailed Description

Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below is not intended to unduly limit the contents of the present invention described in the claims, and all of the configurations described in the present embodiment are not necessarily means for solving the problems of the present invention.

1. Structure of circuit device

Fig. 1 shows a basic circuit configuration of a circuit device according to the present embodiment. As shown in fig. 1, the circuit device of the present embodiment includes: a digital I/F section 30, a processing section 50, an oscillation signal generating circuit 140, a clock

signal generating circuit

160, and 1 st, 2 nd, and 3 rd terminal groups TG1, TG2, TG 3. Further, the register unit 32 can be included. The circuit device of the present embodiment is not limited to the configuration of fig. 1, and various modifications may be made such as omitting a part of the components (for example, a clock signal generating circuit) or adding another component.

The digital I/F section (interface section) 30 is a circuit that performs interface processing with an external device (microcomputer, controller, etc.) of the circuit device. For example, the digital I/F section 30 is an interface for inputting data (digital data, digital signal) from an external device or outputting data to an external device. Data from an external device is input to the processing unit 50 via the digital I/F unit 30. For example, data from an external device is input via the register unit 32. The processing unit 50 performs various signal processes based on the input data.

The digital I/F section 30 can be realized by a circuit that performs serial interface processing. For example, the digital I/F unit 30 can be implemented by a 2-wire, 3-wire, or 4-wire serial interface circuit including a serial data line and a serial clock line. That is, the interface processing of the digital I/F section 30 can be realized by a synchronous serial communication method using a serial clock line and a serial data line. For example, the present invention can be implemented by an I2C (Inter-Integrated Circuit) system, a 3-wire or 4-wire SPI (Serial Peripheral Interface) system, or the like.

The register unit 32 is a circuit including a plurality of registers such as a status register, a command register, and a data register. An external device of the circuit device accesses each register of the register unit 32 via the digital I/F unit 30. Further, the external device can confirm the state of the circuit device or issue a command to the circuit device using the register of the register section 32. Alternatively, data can be transferred to the circuit device (processing unit 50), data can be read from the circuit device (processing unit 50), or the like.

The processing unit 50 performs various signal processes based on the input data. For example, the frequency control data DFCI (frequency control code) input from an external device (for example, an external frequency control data generation unit) via the digital I/F unit 30 is signal-processed. As will be described later, when the frequency control data generation unit is provided inside the circuit device, the frequency control data DFCI (frequency control data based on the phase comparison result of the internal phase comparison unit) from the internal frequency control data generation unit may be subjected to signal processing.

Specifically, the processing unit 50 (digital signal processing unit) performs aging correction processing and kalman filter processing on the frequency control data DFCI (frequency control data from the outside or the inside), and also performs signal processing (digital signal processing) such as temperature compensation processing as necessary. Then, the frequency control data DFCQ after the signal processing is output to the oscillation signal generation circuit 140. The processing unit 50 may be implemented by an ASIC circuit such as a gate array, or may be implemented by a processor (DSP, CPU) and a program (program module) operating on the processor.

The vibrator XTAL is, for example, a quartz vibrator of thickness shear vibration type such as AT-cut type or SC-cut type, or a piezoelectric vibrator of bending vibration type or the like. As an example, the oscillator XTAL is a type provided in an oven of an oven controlled oscillator (OCXO), but is not limited thereto, and may be an oscillator for TCXO that does not have an oven. The vibrator XTAL may be a resonator (an electromechanical resonator or an electrical resonant circuit). As the transducer XTAL, a SAW (Surface Acoustic Wave) resonator, a MEMS (Micro Electro Mechanical Systems) transducer as a silicon transducer, or the like can be used as a piezoelectric transducer. As a substrate material of the resonator XTAL, a piezoelectric single crystal such as quartz, lithium tantalate, or lithium niobate, a piezoelectric material such as piezoelectric ceramics such as lead zirconate titanate, or a silicon semiconductor material can be used. As the excitation means of the vibrator XTAL, a means based on a piezoelectric effect may be used, or electrostatic driving based on coulomb force may be used.

The oscillation signal generation circuit 140 generates an oscillation signal OSCK. For example, the oscillation signal generation circuit 140 generates the oscillation signal OSCK of the oscillation frequency set by the frequency control data DFCQ (frequency control data after signal processing) from the processing unit 50 using the frequency control data DFCQ and the oscillator XTAL. For example, the oscillation signal generation circuit 140 oscillates the oscillator XTAL at the oscillation frequency set by the frequency control data DFCQ to generate the oscillation signal OSCK.

In addition, the oscillation signal generation circuit 140 may be a circuit that generates the oscillation signal OSCK in a direct digital synthesizer manner. For example, the oscillation signal OSCK of the oscillation frequency set by the frequency control data DFCQ may be generated digitally using the oscillation signal of the oscillator XTAL (oscillation source of fixed oscillation frequency) as a reference signal.

The oscillation signal generation circuit 140 may include a D/a conversion section 80 and an oscillation circuit 150. However, the oscillation signal generating circuit 140 is not limited to such a configuration, and various modifications may be made such as omitting some of the components or adding other components.

The D/a conversion section 80 performs D/a conversion of the frequency control data DFCQ (output data of the processing section) from the processing section 50. The frequency control data DFCQ input to the D/a conversion unit 80 is frequency control data (frequency control code) after signal processing (for example, after aging correction, temperature compensation, or kalman filter processing) by the processing unit 50. As a D/a conversion method of the D/a conversion section 80, for example, a resistor string type (resistor division type) can be used. However, the D/a conversion method is not limited to this, and various methods such as a resistance ladder type (R-2R ladder type, etc.), a capacitance array type, or a pulse width modulation type may be employed. The D/a converter 80 may include a control circuit, a modulation circuit (jitter modulation, PWM modulation, or the like), a filter circuit, and the like, in addition to the D/a converter.

Oscillation circuit 150 generates oscillation signal OSCK using output voltage VQ of D/a conversion unit 80 and oscillator XTAL. The oscillation circuit 150 is connected to the oscillator XTAL via the 1 st and 2 nd oscillator terminals (oscillator pads). For example, the oscillation circuit 150 generates an oscillation signal OSCK by oscillating a vibrator XTAL (a piezoelectric vibrator, a resonator, or the like). Specifically, the oscillation circuit 150 oscillates the oscillator XTAL at an oscillation frequency that uses the output voltage VQ of the D/a conversion unit 80 as a frequency control voltage (oscillation control voltage). For example, when the oscillation circuit 150 is a circuit (VCO) that controls oscillation of the oscillator XTAL by voltage control, the oscillation circuit 150 may include a variable capacitance capacitor (a varactor diode or the like) whose capacitance value changes in accordance with the frequency control voltage.

As described above, the oscillation circuit 150 can be realized by a direct digital synthesizer system, and in this case, the oscillation frequency of the oscillator XTAL becomes a reference frequency and a frequency different from the oscillation frequency of the oscillation signal OSCK.

The clock signal generation circuit 160 generates a clock signal CK from the oscillation signal OSCK. For example, the clock signal generation circuit 160 has at least a phase comparison unit 161 (comparison operation unit) and generates a clock signal CK having a frequency obtained by multiplying the oscillation frequency of the oscillation signal OSCK. The clock signal generation circuit 160 includes, for example, an output buffer circuit 168, and outputs the clock signal CK buffered by the output buffer circuit 168. The clock signal generation circuit 160 is a PLL circuit having, for example, a PLL loop. The PLL circuit may be either analog or digital (ADPLL). In the case of generating the clock signal CK having the oscillation frequency of the oscillation signal OSCK multiplied by a frequency, the frequency multiplication factor (frequency multiplication) may be 1 or more, or may be smaller than 1. The frequency multiplication factor is not limited to an integer, and may be a decimal number.

The circuit device includes a1 st terminal group TG1 for connection of the digital I/F section 30, a2 nd terminal group TG2 for connection of the oscillation circuit 150 of the oscillation signal generation circuit 140, and a3 rd terminal group TG3 for connection of the clock signal generation circuit 160(PLL circuit). Here, the connection terminal group means an external connection terminal group for connecting each circuit block to the outside. Each terminal group (pad group) of the TG1 to TG3 includes a plurality of terminals (pads), for example. The terminal is an external connection terminal for inputting or outputting a signal (digital signal, analog signal) to or from the outside (external device).

For example, the 1 st, 2 nd, and 3 rd terminal groups TG1, TG2, and TG3 are terminal groups connected to the digital I/F unit 30, the oscillation circuit 150, and the clock signal generation circuit 160. The 1 st, 2 nd, and 3 rd terminal groups TG1, TG2, and TG3 may be connected to the respective circuit blocks of the digital I/F section 30, the oscillation circuit 150, and the clock signal generation circuit 160 via I/O cells. As the I/O cell, there are an input I/O cell having an input buffer, an output I/O cell having an output buffer, an input output I/O cell having an input buffer and an output buffer, and the like. For example, when signals are externally input to the respective circuit blocks of the digital I/F section 30, the oscillation circuit 150, and the clock signal generation circuit 160, signals may be input to the respective circuit blocks from the respective terminals of the 1 st, 2 nd, and 3 rd terminal groups TG1, TG2, and TG3 via the input I/O cells (or input/output I/O cells). In the case of outputting signals from each circuit block to the outside, each circuit block may output signals to each terminal of the 1 st, 2 nd, and 3 rd terminal groups TG1, TG2, TG3 via an output I/O unit (or an input-output I/O unit). These I/O cells may be provided between each circuit block and each terminal, or may not be provided.

The 1 st terminal group TG1 for the digital I/F section 30 may include, for example, a terminal (pad) of a serial clock line for a serial interface of the digital I/F section 30 and a terminal (pad) of a serial data line. In the case where there are a serial data line for signal input and a serial data line for signal output, the 1 st terminal group TG1 may include a terminal of the serial data line for signal input and a terminal of the serial data line for signal output. The 1 st terminal group TG1 may include, for example, a terminal for the power supply voltage vss (gnd), a chip select terminal, and the like, in addition to these terminals.

The 2 nd terminal group TG2 for the oscillator circuit 150 can include, for example, the 1 st and 2 nd oscillator terminals (oscillator pads) connected to the oscillator XTAL. For example, the 1 st oscillator terminal is connected to one end of the oscillator XTAL, and the 2 nd oscillator terminal is connected to the other end of the oscillator XTAL. The 2 nd terminal group TG2 may include, for example, an output terminal of the oscillation signal OSCK, a connection terminal of a stabilizing capacitor, a connection terminal of an oscillation frequency adjusting capacitor, a connection terminal of a filter, or the like.

The 3 rd terminal group TG3 for the clock signal generation circuit 160 may include, for example, an output terminal of the clock signal CK. For example, when the clock signal generation circuit 160 outputs a plurality of clock signals CK1 to CKj (for example, CK1 to CK5 in fig. 33) having different frequencies (frequency multiplication numbers), a plurality of output terminals for outputting the plurality of clock signals CK1 to CKj may be included. The 3 rd terminal group TG3 may include an output terminal (PLL clock signal output terminal) for outputting a clock signal before buffering by the buffer circuit 168 and an input terminal (PLL clock signal input terminal) for outputting a clock signal before buffering. As shown in fig. 11, when an external oscillator VCXO of the circuit device is used to generate the clock signal CK by the clock signal generation circuit 160, the 3 rd terminal group TG3 may include an output terminal for a frequency control voltage to the oscillator VCXO.

Fig. 2 shows a detailed configuration example of the circuit device of the present embodiment. In fig. 2, the temperature sensor 10, the a/D converter 20, the storage unit 34, the frequency control data generator 40 (phase comparator in a broad sense), the reference signal generator circuit 180, the thermostat control circuit 190, the 4 th terminal group TG4, and the like are further provided in comparison with the configuration of fig. 1. The configuration of the circuit device is not limited to the configuration shown in fig. 2, and various modifications may be made, such as omitting a part of the components (for example, the frequency control data generating unit, the reference signal generating circuit, the thermostat control circuit, and the like), and adding other components. For example, a temperature sensor provided outside the circuit device may be used as the temperature sensor 10.

The temperature sensor 10 outputs a temperature detection voltage VTD. Specifically, a temperature-dependent voltage that changes in accordance with the temperature of the environment (circuit device) is output as the temperature detection voltage VTD. A specific configuration example of the temperature sensor 10 will be described later.

The a/D conversion unit 20 performs a/D conversion of the temperature detection voltage VTD from the temperature sensor 10 and outputs temperature detection data DTD. For example, digital temperature detection data DTD (a/D result data) corresponding to the a/D conversion result of the temperature detection voltage VTD is output. As the a/D conversion method of the a/D conversion unit 20, for example, a successive approximation method or a method similar to the successive approximation method can be used. The A/D conversion method is not limited to this method, and various methods (counter type, parallel comparison type, series-parallel type, etc.) can be adopted

The storage unit 34 stores various information necessary for various processes and operations of the circuit device. The storage unit 34 can be realized by, for example, a nonvolatile memory. As the nonvolatile memory, for example, EEPROM or the like can be used. As the EEPROM, for example, a MONOS (Metal-Oxide-Nitride-Silicon) type memory or the like can be used. For example, a flash memory using a MONOS type memory can be used. Alternatively, as the EEPROM, other types of memories such as a floating gate type can be used. The storage unit 34 may be implemented by, for example, a fuse circuit, as long as it is a memory capable of storing and storing information even when power is not supplied.

The storage unit 34 stores, for example, a system noise constant (V) for setting system noise in the kalman filter process and an observation noise constant (W) for setting observation noise in the kalman filter process. For example, when a product (such as an oscillator) is manufactured or shipped, various information such as an oscillation frequency is measured (checked). Then, the system noise constant and the observation noise constant are determined from the measurement result, and are written into the storage unit 34 implemented by, for example, a nonvolatile memory. In this way, it is possible to set the system noise constant and the observation noise constant with reduced adverse effects due to element variations.

The processing unit 50 includes a hold mode processing unit 52 (circuit or program module for hold mode processing), a kalman filter unit 54 (circuit or program module for kalman filter processing), an aging correction unit 56 (circuit or program module for aging correction processing), and a temperature compensation unit 58 (circuit or program module for temperature compensation processing). The hold mode processing unit 52 performs various processes related to the hold mode. The kalman filter unit 54 performs processing for obtaining a true value of the frequency control data (oscillation frequency) by the kalman filter processing, for example. The aging correction section 56 performs aging correction for compensating for a change in the oscillation frequency with time. The temperature compensation unit 58 performs temperature compensation processing of the oscillation frequency based on the temperature detection data DTD from the a/D conversion unit 20. Specifically, the temperature compensation unit 58 performs temperature compensation processing for reducing the fluctuation of the oscillation frequency when there is a temperature change, based on temperature detection data DTD (temperature-dependent data) that changes in accordance with the temperature, coefficient data for temperature compensation processing (data of a coefficient of an approximation function), and the like.

The reference signal RFCK is input to the circuit device via a terminal TRFCK (pad) which is an external connection terminal of the circuit device. A signal PLOCK that notifies whether or not the external PLL circuit is in a locked state is input to the circuit device via a terminal TPLOCK (pad) that is an external connection terminal of the circuit device. The external PLL circuit is a PLL circuit including an external frequency control data generation unit 200 provided outside the circuit device and an oscillation signal generation circuit 140 provided inside the circuit device.

The frequency control data generating section 40 generates frequency control data DFCI. The frequency control data DFCI is generated by, for example, comparing an input signal based on the oscillation signal OSCK with the reference signal RFCK. The generated frequency control data DFCI is input to the processing unit 50. Here, the input signal based on the oscillation signal OSCK may be the oscillation signal OSCK itself, or may be a signal (for example, a frequency-divided signal) generated from the oscillation signal OSCK. Hereinafter, a case where the input signal is the oscillation signal OSCK itself will be mainly described as an example.

The frequency control data generation unit 40 includes a phase comparison unit 41 and a digital filter unit 44. The phase comparison unit 41 (comparison operation unit) is a circuit that performs phase comparison (comparison operation) between the oscillation signal OSCK as an input signal and the reference signal RFCK, and includes a counter 42 and a TDC 43 (time-to-digital converter).

The counter 42 generates digital data corresponding to an integer part of a result of dividing the reference frequency (for example, 1Hz) of the reference signal RFCK by the oscillation frequency of the oscillation signal OSCK. The TDC 43 generates digital data corresponding to the fractional part of the division result. The TDC 43 includes, for example: a plurality of delay elements; a plurality of latch circuits that latch a plurality of delayed clock signals output by the plurality of delay elements at an edge (high) timing of the reference signal RFCK; and a circuit that generates digital data corresponding to the fractional part of the division result by encoding the output signals of the plurality of latch circuits. The phase comparison unit 41 adds the digital data corresponding to the integer part from the counter 42 and the digital data corresponding to the fractional part from the TDC 43, and detects a phase error with the set frequency. The digital filter unit 44 generates frequency control data DFCI by performing a smoothing process of the phase error. For example, when the frequency of the oscillation signal OSCK is FOS, the frequency of the reference signal RFCK is FRF, and the frequency division number (frequency division ratio) corresponding to the set frequency is FCW, the frequency control data DFCI is generated so that the relationship of FOS ═ FCW × FRF is satisfied. Alternatively, the counter 42 may count the number of clocks of the oscillation signal OSCK. That is, the counter 42 performs a counting operation by an input signal based on the oscillation signal OSCK. The phase comparison unit 41 may compare the count value of the counter 42 in n cycles (n is an integer that can be set to 2 or more) of the reference signal RFCK with the expected value (n × FCW) of the count value by an integer. The phase comparison unit 41 outputs, for example, a difference between the expected value and the count value of the counter 42 as phase error data.

The configuration of the frequency control data generation unit 40 is not limited to the configuration shown in fig. 2, and various modifications can be made. For example, the phase comparison unit 41 may be constituted by a phase comparison circuit of an analog circuit, or the digital filter unit 44 may be constituted by a filter unit (loop filter) of an analog circuit. The processing unit 50 may perform the processing (smoothing processing of the phase error data) of the digital filter unit 44. For example, the processing unit 50 performs the processing of the digital filter unit 44 in time division with other processing (hold mode processing, kalman filter processing, and the like). For example, the processing unit 50 performs a filtering process (smoothing process) on the phase comparison result (phase error data) of the phase comparing unit 41.

In the present embodiment, a loop of the PLL circuit can be formed by the external frequency control data generation unit 200 and the oscillation signal generation circuit 140 provided outside the circuit device. In this case, the frequency control data DFCI from the external frequency control data generation section 200 is input to the processing section 50 via the digital I/F section 30. The processing unit 50 performs signal processing such as temperature compensation processing and aging correction on the frequency control data DFCI from the external frequency control data generation unit 200, and the frequency control data DFCQ after the signal processing is input to the oscillation signal generation circuit 140. Also, the oscillation signal generation circuit 140 generates the oscillation signal OSCK using the frequency control data DFCQ. The generated oscillation signal OSCK is output to the external frequency control data generation unit 200 via the output terminal of the 2 nd terminal group TG 2. The external frequency control data generation unit 200 performs phase comparison (comparison operation) between the oscillation signal OSCK and the reference signal RFCK to generate frequency control data DFCI. The external frequency control data generation unit 200 can be realized by a configuration similar to that of the frequency control data generation unit 40 in the circuit device, and can include, for example, a phase comparison unit having a counter and a TDC, and a digital filter unit.

The reference signal generation circuit 180 generates reference signals such as a reference voltage VRF and a reference current IRF. The reference signal generating circuit 180 may include, for example, a circuit for generating a constant voltage such as a bandgap reference voltage, a circuit for generating a reference voltage VRF from the generated constant voltage, a circuit for generating a reference current IRF from the generated constant voltage, and the like. The generated reference voltage VRF and reference current IRF are supplied to an analog circuit (for example, the a/D conversion unit 20, the D/a conversion unit 80, the thermostat control circuit 190, or the like) of the circuit device. The analog circuit performs analog circuit processing using the reference voltage VRF and the reference current IRF.

The oven control circuit 190 performs oven control of the oven type oscillator XTAL when the oscillator XTAL is an oven type oscillator (a double oven, a single oven, or the like) having an oven. For example, the thermostatic bath control circuit 190 controls heat generation of a heater (heating element) for adjusting the thermostatic bath temperature. Specifically, the heat generation of the heater is controlled by using a temperature sensor for controlling the thermostatic bath provided corresponding to the heater. Then, the temperature is adjusted so that the temperature of the thermostatic bath becomes the set temperature.

The 4 th terminal group TG4 is a terminal group (pad group) for connection (external connection) of the thermostatic bath control circuit 190. The 4 th terminal group TG4 includes a thermostatic bath control terminal of the thermostatic bath type oscillator XTAL. For example, the 4 th terminal group TG4 may include an output terminal of the heater control voltage as a thermostat control terminal. For example, in the case of a double thermostat configuration described later, 2 heater control voltage output terminals corresponding to the respective thermostat controls may be included. The 4 th terminal group TG4 may include a connection terminal of a temperature sensor for thermostat control (2 connection terminals corresponding to 2 temperature sensors in the case of a double thermostat configuration), a connection terminal of a stabilization capacitor for thermostat control, an input terminal of a reference voltage for thermostat control, and the like.

2. Phase noise

As described above, the circuit device of the present embodiment is provided with the digital I/F section 30, and the processing section 50 can perform various signal processing based on data input from an external device via the digital I/F section 30. As an example, as described above, the frequency control data DFCI is input from the external frequency control data generation unit 200 as an external device to the processing unit 50 via the digital I/F unit 30. The oscillation signal generation circuit 140 generates an oscillation signal OSCK from the frequency control data DFCQ after the signal processing, and the oscillation signal OSCK is fed back to the external frequency control data generation unit 200 via the output terminal of the 2 nd terminal group TG2, thereby forming a PLL loop of the external PLL circuit.

In the present embodiment, a clock signal generation circuit 160 is provided that generates a clock signal CK having a frequency obtained by multiplying the oscillation frequency of the oscillation signal OSCK. In this way, the clock signal CK of an arbitrary frequency can be generated by the clock signal generation circuit 160 from the oscillation signal OSCK of a constant oscillation frequency and supplied to each circuit of the electronic device incorporating the circuit device. Taking the electronic device of the base station of fig. 33 described later as an example, the clock signal generation circuit 160 can generate clock signals CK1 to CK5 and supply the clock signals to the respective circuits constituting the base station.

In this case, the oscillation signal OSCK is generated in phase synchronization with the reference signal RFCK of a low frequency (for example, 1Hz) by the frequency control data generation unit 40 (phase comparison unit 41) or a PLL circuit (hereinafter, referred to as a PLL circuit of the 1 st stage) including the external frequency control data generation unit 200 and the oscillation signal generation circuit 140. Therefore, the oscillation signal OSCK generated by the PLL circuit of the 1 st stage locked to the reference signal RFCK of low frequency becomes a signal having small phase noise in the low frequency band but large phase noise in the high frequency band. For example, various noises are superimposed on the reference signal RFCK from the GPS or the like, and the phase noise of the oscillation signal OSCK in the high frequency band increases due to the influence of the noises or the like.

On the other hand, the PLL circuit of the 2 nd stage realized by the clock signal generation circuit 160 generates the clock signal CK in phase synchronization with the oscillation signal OSCK having a higher frequency than the reference signal RFCK, and therefore, phase noise in a high frequency band can be reduced. Therefore, according to the circuit device of the present embodiment in which the oscillation signal OSCK is generated by the PLL circuit of the 1 st stage and the clock signal CK is generated from the oscillation signal OSCK by the PLL circuit of the 2 nd stage (the clock signal generation circuit 160), the phase noise in the low frequency band can be reduced by the PLL circuit of the 1 st stage and the phase noise in the high frequency band can be reduced by the PLL circuit of the 2 nd stage. Therefore, there is an advantage that a clean clock signal CK with small phase noise can be generated in a wide frequency band from a low frequency band to a high frequency band. For example, in the base station of fig. 33 described later, in order to improve the reception performance of the RF circuit 608, it is necessary to reduce the phase noise of the clock signal CK5 supplied to the RF circuit 608. According to the circuit device of the present embodiment, a clock signal CK5 (CK) with low phase noise can be generated and supplied to the RF circuit 608 over a wide frequency band from a low frequency band to a high frequency band, thereby improving reception performance.

As described above, the circuit device according to the present embodiment has the following advantages: by doubly reducing phase noise using a 2-stage PLL circuit, a clean clock signal CK with less noise can be generated.

However, in the present embodiment, since the digital I/F section 30 is provided, the following problems are found: the communication noise generated by the digital I/F section 30 causes an increase in phase noise of the clock signal CK. For example, the communication noise in the terminal group TG1 of the digital I/F section 30 is transmitted to the terminal group TG3 of the clock signal generation circuit 160, and the phase noise of the clock signal CK is increased.

For example, fig. 3 is a diagram showing an example of phase noise of the clock signal CK. The horizontal axis is frequency and the vertical axis is phase noise. G1 of fig. 3 is phase noise corresponding to the frequency of the communication clock of the digital I/F section 30. For example, in the digital I/F section 30, communication is performed using a serial clock line and a serial data line, but phase noise of a communication clock frequency (for example, 100KHz) of the serial clock line is generated in the clock signal CK. Further, large phase noise is generated even in the frequency band of G2 higher than the frequency of G1 and the frequency band indicated by G3 lower than the frequency of G1. Thus, when large phase noise shown in G1, G2, G3 is superimposed on the clock signal CK, problems such as a decrease in the reception performance of the RF circuit 608 of fig. 33 occur, for example.

Also, when noise generated by the terminal group TG2 of the oscillation circuit 150 is transferred to the terminal group TG3 of the clock signal generation circuit 160, or conversely, noise generated by the terminal group TG3 is transferred to the terminal group TG2, phase noise further increases.

3. Layout arrangement

In the present embodiment, in order to solve the above problem, a layout method described below is adopted. For example, fig. 5 shows an example of a layout arrangement of the circuit device according to the present embodiment. The layout arrangement of the circuit device in the present embodiment is not limited to the arrangement shown in fig. 5, and various modifications can be made (for example, fig. 6 to 10 described later).

As shown in fig. 1, 2, and 5, the circuit device according to the present embodiment includes a digital I/F unit 30, a processing unit 50, an oscillation signal generation circuit 140 (oscillation circuit 150), a clock signal generation circuit 160(PLL circuit), and 1 st, 2 nd, and 3 rd terminal groups TG1, TG2, and TG 3. Here, the processing unit 50 receives data (for example, frequency control data DFCI) from an external device (for example, the external frequency control data generation unit 200) via the digital I/F unit 30, and performs signal processing. For example, signal processing such as temperature compensation processing and aging correction is performed. The oscillation signal generation circuit 140 generates the oscillation signal OSCK of the oscillation frequency set by the frequency control data DFCQ using the frequency control data DFCQ and the oscillator XTAL from the processing unit 50. The clock signal generation circuit 160 has at least a phase comparison unit 161, and generates a clock signal CK having a frequency obtained by multiplying the oscillation frequency of the oscillation signal OSCK.

Here, as shown in fig. 5, the side of the circuit device intersecting (perpendicular to) the 1 st side SD1 is the 2 nd side SD2, and the side opposing the 1 st side SD1 is the 3 rd side SD 3. The side opposite to the 2 nd side SD2 is defined as a4 th side SD 4.

In this case, the 1 st terminal group TG1 for connection of the digital I/F section 30 is disposed in the 1 st terminal area AT1 along the 1 st side SD1 of the circuit device. On the other hand, the 3 rd terminal group TG3 for connection of the clock signal generation circuit 160 is disposed in any one of the 2 nd terminal area AT2 along the 2 nd side SD2, the 3 rd terminal area AT3 along the 3 rd side SD3, and the 4 th terminal area AT4 along the 4 th side SD 4. Specifically, in fig. 5, the 2 nd terminal group TG2 for connection of the oscillator circuit 150 is disposed in the 2 nd terminal area AT2 along the 2 nd side SD2, and the 3 rd terminal group TG3 for connection of the clock signal generation circuit 160 is disposed in the 3 rd terminal area AT3 along the 3 rd side SD 3.

As a method of disposing the terminal group and the like in the present embodiment, various modifications can be made as described in fig. 6 to 10 described later. For example, the 2 nd terminal group TG2 may be disposed in the 3 rd terminal area AT3, and the 3 rd terminal group TG3 may be disposed in the 2 nd terminal area AT 2. That is, the 2 nd terminal group TG2 may be disposed in one of the 2 nd and 3 rd terminal regions AT2 and AT3, and the 3 rd terminal group TG3 may be disposed in the other of the AT2 and AT 3. Further, a4 th terminal group TG4 is disposed in a4 th terminal area AT4 along the 4 th side SD 4.

Here, the 1 st to 4 th sides SD1 to SD4 correspond to the edges of the IC of the circuit device. The 1 st to 4 th terminal regions AT1 to AT4 are regions of a predetermined width provided inside the 1 st to 4 th sides SD1 to SD 4. The longitudinal directions of the 1 st to 4 th terminal regions AT1 to AT4 are directions along the 1 st to 4 th sides SD1 to SD4, and the predetermined widths are widths of the 1 st to 4 th terminal regions AT1 to AT4 in the short side direction.

The 1 st to 4 th terminal regions AT1 to AT4 are regions called so-called I/O regions (peripheral regions), and I/O cells may be arranged in addition to the pad groups such as the terminal groups TG1 to TG 4. The I/O cell is an input I/O cell to which a signal is input from the outside via each terminal, an output I/O cell to which a signal is output to the outside via each terminal, an input/output I/O cell for both input and output, or the like. The terminals of the terminal groups TG1 to TG4 and the circuit blocks such as the digital I/F unit 30, the oscillation circuit 150, and the clock signal generation circuit 160 may be connected via these I/O cells, or may not be connected via the I/O cells.

In the present embodiment, as shown in fig. 5, the terminal group TG1 for the digital I/F section 30 is disposed in the terminal area AT1 along the side SD1, while the terminal group TG2 for the oscillation circuit 150 is disposed in the terminal area AT2 along the side SD2 intersecting the side SD 1. Therefore, the distance L12 between the terminal group TG1 and the terminal group TG2 can be increased, and the transmission of communication noise generated in the digital I/F section 30 to the terminal group TG2 can be effectively suppressed. As a result, the phase noise superimposed on the oscillation signal OSCK due to the communication noise can be reduced. Since the phase noise of the oscillation signal OSCK is reduced, the phase noise of the clock signal CK is also reduced.

In the present embodiment, the terminal group TG1 for the digital I/F section 30 is disposed in the terminal area AT1 along the side SD1, while the terminal group TG3 for the clock signal generation circuit 160 is disposed in the terminal area AT3 along the side SD3 opposite to the side SD 1. Therefore, the distance L13 between the terminal group TG1 and the terminal group TG3 can be increased, and the transmission of communication noise generated in the digital I/F section 30 to the terminal group TG3 can be effectively suppressed. As a result, the phase noise superimposed on the clock signal CK due to the communication noise can be reduced.

In the present embodiment, the terminal group TG2 is disposed in the terminal region AT2 along the side SD2, and the terminal group TG3 is disposed in the terminal region AT3 along the side SD3 intersecting the side SD 2. Therefore, L23, which is the distance between the terminal group TG2 and the TG3, can be made longer. Therefore, for example, it is possible to suppress noise generated in the terminal group TG2 due to the oscillation signal OSCK or the like from being transmitted to the terminal group TG3, and it is also possible to suppress noise generated in the terminal group TG3 due to the clock signal CK or the like from being transmitted to the terminal group TG 2.

For example, as described above, the PLL circuit of the 1 st stage (the frequency control

data generating sections

40 and 200 and the oscillation signal generating circuit 140) has a different locking frequency from the PLL circuit of the 2 nd stage (the clock signal generating circuit 160). Further, in this way, when there are 2 PLL circuits different in locking frequency, signal noise is mutually transmitted, whereby superimposed phase noise increases.

In contrast, in fig. 5, the terminal groups TG1, TG2, and TG3 are disposed in different terminal regions AT1, AT2, and AT 3. That is, the terminal groups TG1, TG2, and TG3 are disposed in the terminal regions AT1, AT2, and AT3 provided corresponding to the 3 different sides SD1, SD2, and SD3, respectively. Therefore, not only the distance L12 between the terminal groups TG1 and TG2 and the distance L13 between the terminal groups TG1 and TG3 can be increased, but also the distance L23 between the terminal groups TG2 and TG3 can be increased. Therefore, it is possible to reduce not only phase noise caused by communication noise of the digital I/F unit 30 but also phase noise caused by transmission of signal noise between 2 PLL circuits. Therefore, a circuit device capable of generating the clock signal CK and the oscillation signal OSCK with sufficiently reduced noise can be provided as compared with the conventional circuit device.

For example, fig. 4 shows an example of phase noise of the clock signal CK when the method of the present embodiment is applied. Comparing G1, G2, and G3 in fig. 3 with G4 in fig. 4, it is understood that the present embodiment can reduce the phase noise of the clock signal CK in a wide frequency band from a low frequency band to a high frequency band. Therefore, the clean clock signal CK with less noise can be supplied to each circuit (for example, the RF circuit 608 in fig. 33) of the electronic apparatus in which the circuit device is incorporated.

In fig. 5, the side SD1 is a short side of the circuit device, and the terminal group TG1 is disposed in the terminal area AT1 along the side SD1 as the short side. That is, in fig. 5, sides SD1 and SD3 are short sides of the circuit device, sides SD2 and SD4 are long sides of the circuit device, and a terminal group TG1 for connection of the digital I/F section 30 is disposed in a terminal area AT1 along a side SD1 which is a short side. In this way, the terminal group TG1 can be separated from the other terminal groups by a distance corresponding to the sides SD2 and SD4, which are long sides. For example, the terminal group TG1 for connection of the digital I/F section 30 and the terminal group TG3 for connection of the clock signal generation circuit 160 can be separated by a distance L13 corresponding to the sides SD2 and SD4 which are the long sides. This effectively suppresses the transmission of communication noise generated in the digital I/F section 30 to the terminal group TG 3.

In fig. 5, when the distance between the terminal group TG1 and the terminal group TG2 is L12, the distance between the terminal group TG1 and the terminal group TG3 is L13, and the distance between the terminal group TG2 and the terminal group TG3 is L23, at least one of L12 and L13 is longer than L23. Specifically, in fig. 5, L13 > L23, and the distance L13 between the terminal group TG1 and the terminal group TG3 is long, so that the communication noise generated in the digital I/F section 30 can be effectively suppressed from being transmitted to the terminal group TG 3. In fig. 5, L12 > L23, and the distance L12 between the terminal group TG1 and the terminal group TG2 is long, so that the communication noise generated in the digital I/F section 30 can be effectively suppressed from being transmitted to the terminal group TG 2. As a result, the phase noise superimposed on the clock signal CK and the oscillation signal OSCK due to the communication noise in the digital I/F unit 30 can be sufficiently reduced. The distance between the terminal groups can be set to, for example, the distance between the terminals located at the center among the plurality of terminals included in each terminal group (the distance between the representative terminals). In fig. 5, both L13 and L12 are longer than both L23, but only one of L13 and L12 may be longer than L23.

In the present embodiment, as described with reference to fig. 2, the frequency control data DFCI from the external frequency control data generator 200 is input to the processor 50 via the terminal group TG1 and the digital I/F unit 30, and the external frequency control data generator 200 compares an input signal based on the oscillation signal OSCK (for example, the oscillation signal OSCK itself) with the reference signal RFCK. The oscillation signal generation circuit 140 generates the oscillation signal OSCK based on the frequency control data DFCQ from the external frequency control data generation unit 200 input via the processing unit 50.

In this way, the external frequency control data generation unit 200 provided outside the circuit device can be effectively used to form a PLL circuit together with the internal oscillation signal generation circuit 140, and generate the oscillation signal OSCK. For example, when the external frequency control data generation unit 200 is implemented by a system external to the circuit device, such as a microcomputer, a controller, or a DSP, the hardware resources thereof can be effectively utilized to configure a PLL circuit and generate the oscillation signal OSCK.

In the case where the external frequency control data generation unit 200 is used flexibly in this way, the frequency control data DFCI from the external frequency control data generation unit 200 is input to the processing unit 50 via the digital I/F unit 30. Therefore, large phase noise shown in G1, G2, G3 of fig. 3 may be generated by communication noise based on the input of the frequency control data DFCI.

In contrast, in the present embodiment, as shown in fig. 5, by disposing the terminal groups TG1, TG2, and TG3 in different terminal regions AT1, AT2, and AT3, the distance L12 between TG1 and TG2, and the distance L13 between TG1 and TG3 can be made longer. Therefore, even when the PLL circuit is configured by effectively and flexibly using the external frequency control data generating unit 200 as described above, it is possible to effectively suppress an increase in phase noise due to communication noise of the frequency control data DFCI.

As shown in fig. 2, the circuit device of the present embodiment includes a phase comparison unit 41 (frequency control data generation unit 40) that compares the phases of an input signal based on the oscillation signal OSCK and the reference signal RFCK. The phase comparison unit 41 and the frequency control data generation unit 40 having the phase comparison unit 41 can be formed in an area where the control logic of the processing unit 50 is arranged, for example, in fig. 5. The phase comparison unit 41 and the frequency control data generation unit 40 can be realized by control logic formed by automatically arranging wiring such as a gate array.

In the 1 st mode, the oscillation signal generation circuit 140 generates an oscillation signal based on the frequency control data DFCQ input from the external frequency control data generation unit 200 via the processing unit 50. That is, the processing unit 50 performs signal processing such as temperature compensation processing and aging correction on the frequency control data DFCI input from the external frequency control data generation unit 200, and the frequency control data DFCQ after the signal processing is input to the oscillation signal generation circuit 140 to generate the oscillation signal OSCK.

On the other hand, in the 2 nd mode, the oscillation signal generation circuit 140 generates the oscillation signal OSCK based on the frequency control data DFCQ input from the phase comparison unit 41 (frequency control data generation unit 40) via the processing unit 50. That is, in the 2 nd mode, the processing unit 50 performs signal processing such as temperature compensation processing and aging correction on the frequency control data DFCI based on the phase comparison result in the phase comparison unit 41 inside the circuit device, and the frequency control data DFCQ after the signal processing is input to the oscillation signal generation circuit 140 to generate the oscillation signal OSCK. The frequency control data DFCI filtered by the digital filter unit 44 may be input to the processing unit 50 from the frequency control data generation unit 40. Alternatively, the processing unit 50 may receive the phase comparison result of the phase comparison unit 41 and perform filtering processing on the phase comparison result.

In this way, when the external system includes the external frequency control data generation unit 200, the operation mode of the circuit device is set to the 1 st mode, and the external frequency control data generation unit 200 of the external system can be effectively used to configure the PLL circuit and generate the oscillation signal OSCK.

On the other hand, when the external system does not include the external frequency control data generation unit 200, the operation mode of the circuit device is set to the 2 nd mode, and the phase comparison unit 41 (the frequency control data generation unit 40) provided inside the circuit device forms a PLL circuit, thereby generating the oscillation signal OSCK.

Therefore, it is possible to cope with both the case where the external system has the external frequency control data generation unit 200 and the case where the external frequency control data generation unit 200 is not provided, and convenience is improved.

In the present embodiment, a 2-wire, 3-wire, or 4-wire serial interface circuit including a serial data line and a serial clock line can be used as the digital I/F unit 30. As described above, for example, a serial interface circuit such as I2C or SPI can be used as the digital I/F unit 30. Therefore, when an external device such as a microcomputer or a controller has a serial interface circuit such as I2C or SPI, the serial interface processing by I2C or SPI is performed with the external device, and data (frequency control data) from the external device (external frequency control data generation unit 200) can be input to the processing unit 50.

In fig. 5, the direction from the 1 st side SD1 to the 3 rd side SD3 is the 1 st direction DR1, and the opposite direction to the 1 st direction DR1 is the 2 nd direction DR 2. In addition, a direction intersecting (perpendicular to) the 1 st direction DR1 is defined as a3 rd direction DR3, and a direction opposite to the 3 rd direction DR3 is defined as a4 th direction DR 4. In this case, in the circuit device of the present embodiment, as shown in fig. 5, the processing unit 50 is disposed on the 1 st direction DR1 side of the 1 st terminal group TG1 (1 st terminal region AT 1). For example, the digital I/F section 30 is disposed on the 1 st direction DR1 side of the 1 st terminal group TG1 (the 1 st terminal region AT1), and the processing section 50 is disposed on the 1 st direction DR1 side of the digital I/F section 30.

In this way, data such as frequency control data from an external device, which is input using the terminal of the 1 st terminal group TG1, can be input to the processing unit 50 via the digital I/F unit 30 via a short-path signal path. Thus, for example, the position of the generation source of the communication noise of the data such as the frequency control data can be limited to the vicinity of the position of the 1 st terminal group TG1 or the position of the 2 nd direction DR2 side of the processing unit 50. Therefore, the distances (L12, L13) between the source of the communication noise and the 2 nd and 3 rd terminal groups TG2, TG3 can be increased, and the phase noise caused by the communication noise can be reduced.

In fig. 5, the 2 nd terminal group TG2 is disposed in the 2 nd terminal region AT2, the 3 rd terminal group TG3 is disposed in the 3 rd terminal region AT3, and the clock signal generation circuit 160 is disposed on the 2 nd direction DR2 side of the 3 rd terminal group TG3 (the 3 rd terminal region AT 3). For example, the 3 rd terminal group TG3 and the clock signal generation circuit 160 are disposed adjacent to each other without interposing other circuit blocks (circuit elements).

In this way, the output signal (for example, the clock signal CK and the frequency control voltage signal) from the clock signal generation circuit 160 can be output from the clock signal generation circuit 160 to the terminal of the 3 rd terminal group TG3 through a short-path signal path. Further, the input signal to the terminal of the 3 rd terminal group can be input from the terminal of the 3 rd terminal group TG3 to the clock signal generation circuit 160 by a signal path of a short path. Thus, the position of the generation source of the clock noise based on the signal (clock signal CK, etc.) of the clock signal generation circuit 160 can be limited to the position of the 3 rd terminal group TG3 or the position on the 1 st direction DR1 side of the clock signal generation circuit 160. Therefore, the distance (L23) between the clock noise generation source and the 2 nd terminal group TG2 can be increased, and the phase noise caused by the clock noise can be reduced.

In fig. 5, the processing unit 50 is disposed between the 1 st terminal area AT1 and the clock signal generation circuit 160. For example, the processing unit 50 is disposed on the 1 st direction DR1 side of the 1 st terminal area AT1, and the clock signal generation circuit 160 is disposed on the 1 st direction DR1 side of the processing unit 50. Further, the 3 rd terminal area AT3 is disposed on the 1 st direction DR1 side of the clock signal generating circuit 160.

In this way, the processing unit 50 and the clock signal generation circuit 160 are interposed between the 1 st terminal group TG1 of the 1 st terminal area AT1 and the 3 rd terminal group TG3 of the 3 rd terminal area AT 3. Therefore, as the distance L13 between the 1 st terminal group TG1 and the 3 rd terminal group TG3, at least a distance corresponding to the width of the processing section 50 and the width of the clock signal generation circuit 160 can be secured. That is, as the distance L13, at least a distance corresponding to the width of the processing unit 50 and the clock signal generation circuit 160 in the 1 st direction DR1 can be secured. Therefore, the distance L13 between the 1 st terminal group TG1 and the 3 rd terminal group TG3 can be increased, and phase noise caused by communication noise in the digital I/F section 30 can be reduced.

In fig. 5, the oscillation circuit 150 is disposed between the processing unit 50 and the clock signal generation circuit 160. For example, the oscillation circuit 150 is disposed on the 1 st direction DR1 side of the processing unit 50, and the clock signal generation circuit 160 is disposed on the 1 st direction DR1 side of the oscillation circuit 150. Further, a reference signal generation circuit 180 that generates a reference voltage and a reference current, for example, is disposed between the processing unit 50 and the oscillation circuit 150. The temperature sensor 10 and the a/D converter 20 are disposed between the processing unit 50 and the oscillation circuit 150.

In this way, the processing unit 50, the oscillation circuit 150, and the clock signal generation circuit 160 are interposed between the 1 st terminal group TG1 of the 1 st terminal area AT1 and the 3 rd terminal group TG3 of the 3 rd terminal area AT 3. Therefore, as the distance L13 between the 1 st terminal group TG1 and the 3 rd terminal group TG3, at least a distance corresponding to the width of the processing section 50, the width of the oscillation circuit 150, and the width of the clock signal generation circuit 160 can be secured. Therefore, the distance L13 between the 1 st terminal group TG1 and the 3 rd terminal group TG3 can be further increased, and phase noise caused by communication noise in the digital I/F section 30 can be further reduced.

In fig. 5, the oscillation circuit 150 is disposed on the 3 rd direction DR3 side of the 2 nd terminal group TG 2. For example, the oscillation circuit 150 and the 2 nd terminal group TG2 are disposed adjacent to each other without interposing another circuit block (circuit element).

In this way, the oscillation circuit 150 can be connected to the terminals of the 2 nd terminal group TG2 by a short-path signal path. This can shorten the length of the signal line of the oscillation signal OSCK, for example, and reduce parasitic capacitance parasitic on the signal line of the oscillation signal OSCK. Therefore, the following can be suppressed: the communication noise from the 1 st terminal group TG1 of the digital I/F section 30 is transmitted to the signal line of the oscillation signal OSCK via the parasitic capacitance, and the phase noise of the oscillation signal OSCK increases. Further, the following can also be suppressed: the clock noise from the 3 rd terminal group TG3 of the clock signal generation circuit 160 is transmitted to the signal line of the oscillation signal OSCK via the parasitic capacitance, and the phase noise of the oscillation signal OSCK increases.

In the present embodiment, as the oscillator XTAL, an oven-type oscillator having an oven can be used. In this case, in fig. 5, the 4 th terminal group TG4 of the oven control terminal including the oven-controlled oscillator XTAL is disposed in the 4 th terminal area AT4 along the 4 th side SD 4. For example, a thermostat control terminal such as an output terminal of a heater control voltage or a connection terminal of a temperature sensor is disposed in the 4 th terminal area AT4 as the 4 th terminal group TG 4.

In this way, when the 1 st, 2 nd, and 3 rd terminal groups TG1, TG2, and TG3 for the digital I/F section 30, the oscillator circuit 150, and the clock signal generation circuit 160 are disposed in the 1 st, 2 nd, and 3 rd terminal regions AT1, AT2, and AT3, respectively, the 4 th terminal region AT4 remaining can be effectively used, and the 4 th terminal group TG4 including the oven control terminal can be disposed. That is, the 1 st, 2 nd, and 3 rd terminal groups TG1, TG2, and TG3 are disposed in the 1 st, 2 nd, and 3 rd terminal regions AT1, AT2, and AT3, so that the phase noise can be reduced as described above, and the 4 th terminal group TG4 including the oven control terminal is disposed in the remaining 4 th terminal region AT4, so that the oven control of the oven-type oscillator XTAL can be realized.

The circuit device of the present embodiment includes a thermostat control circuit 190 to which the thermostat control terminal of the 4 th terminal group TG4 is connected and which controls the thermostat of the thermostat-type oscillator XTAL. In fig. 5, the thermostat control circuit 190 is disposed on the 4 th direction DR4 side of the 4 th terminal area AT 4.

In this way, the thermostat control circuit 190 and the thermostat control terminal of the 4 th terminal group TG4 can be connected by a short-path signal path, and more appropriate thermostat control can be achieved. For example, an output terminal of a heater control voltage and a connection terminal of a temperature sensor are provided as the thermostatic bath control terminal. In this case, the thermostat control circuit 190 is disposed on the 4 th direction DR4 side of the 4 th terminal area AT4, and thus the length of a signal wiring connecting the thermostat control circuit 190 and the output terminal of the heater control voltage and the length of a signal wiring connecting the thermostat control circuit 190 and the connection terminal of the temperature sensor can be shortened. Therefore, since the parasitic resistance and the like of the signal wiring can be reduced, the adverse effect of the parasitic resistance and the like on the oven control can be reduced, and more appropriate oven control can be realized.

In fig. 5, the oscillation circuit 150 is disposed between the oven control circuit 190 and the 2 nd terminal area AT 2. For example, the oven chamber control circuit 190 is disposed on the 4 th direction DR4 side of the 4 th terminal area AT4, the oscillation circuit 150 is disposed on the 4 th direction DR4 side of the oven chamber control circuit 190, and the 2 nd terminal area AT2 is provided on the 4 th direction DR4 side of the oscillation circuit 150.

Thus, the region between the 4 th terminal region AT4 and the 2 nd terminal region AT2 can be effectively utilized to lay out the oven control circuit 190 and the oscillator circuit 150. Therefore, it is possible to connect the thermostat control circuit 190 and the 4 th terminal group TG4 with a short path, and efficiently route the thermostat control circuit 190 and the oscillation circuit 150 in the region between the 4 th terminal area AT4 and the 2 nd terminal area AT2 while connecting the oscillation circuit 150 and the 2 nd terminal group TG2 with a short path. Therefore, it is possible to achieve both reduction of phase noise and reduction of the layout area of the circuit device.

In the present embodiment, the processing unit 50 (processor) performs processing for estimating the true value of the frequency control data DFCI by kalman filtering processing, and performs aging correction of the frequency control data DFCI based on the estimated true value.

In this way, if the truth value of the frequency control data DFCI is estimated by the kalman filter process and the aging correction is performed based on the estimated truth value, the accuracy of the aging correction can be greatly improved. That is, aging correction can be realized in consideration of the influence of observation noise and system noise.

More specifically, when the hold mode is detected, the processing unit 50 stores a true value of the time corresponding to the detection time of the hold mode. The time when the true value is stored may be the detection time itself of the hold mode, or may be a time before the detection time. Then, the processing unit 50 performs arithmetic processing based on the stored true values to generate the aging-corrected frequency control data DFCQ. The generated frequency control data DFCQ is output to the oscillation signal generation circuit 140. The generation process of the frequency control data DFCQ after the aging correction is executed by the aging correction section 56.

For example, during the normal operation, the processing unit 50 performs signal processing such as temperature compensation processing on the frequency control data DFCI based on the phase comparison result in the phase comparison unit 41 or the frequency control data DFCI input from the external frequency control data generation unit 200, and outputs the frequency control data DFCQ after the signal processing to the oscillation signal generation circuit 140. The oscillation signal generation circuit 140 generates the oscillation signal OSCK using the frequency control data DFCQ and the oscillator XTAL from the processing unit 50, and outputs the oscillation signal OSCK to the frequency control data generation unit 40 (phase comparison unit 41) or the external frequency control data generation unit 200. This forms a loop of the PLL circuit including the frequency control data generator 40 (phase comparator 41) or the external frequency control data generator 200 and the oscillation signal generator 140, and can generate an accurate oscillation signal in phase synchronization with the reference signal RFCK.

In the present embodiment, the kalman filter unit 54 of the processing unit 50 operates to perform the kalman filter process on the frequency control data DFCI even during the normal operation period before the hold mode is detected.

Namely, the following processing is performed: the true value of the observation value for the frequency control data DFCI is estimated by the kalman filtering process.

When the hold mode is detected, the true value at the time corresponding to the detection time of the hold mode is stored in the processing unit 50. Specifically, the aging correction unit 56 stores the true value. The aging correction unit 56 performs arithmetic processing based on the stored true values, thereby generating the frequency control data DFCQ after the aging correction.

In this way, since the burn-in correction is performed based on the true value at the time corresponding to the detection time of the hold mode, the accuracy of the burn-in correction can be greatly improved. That is, aging correction in consideration of the influence of observation noise and system noise can be realized.

The processing unit 50 performs an arithmetic process of adding a correction value to the stored true value (an arithmetic process of compensating for a frequency change due to aging), thereby generating the frequency control data DFCQ after the aging correction. The frequency control data DFCQ after the aging correction is generated by, for example, sequentially adding a correction value (correction value for canceling the frequency change due to the aging rate) corresponding to the aging rate (gradient of the aging, aging coefficient) and a true value at a time corresponding to the detection time of the hold pattern at each predetermined time. The addition processing in the present embodiment includes subtraction processing, which is processing of adding a negative value.

For example, the correction value at time step k is d (k), and the frequency control data after aging correction at time step k is ac (k). In this case, the processing unit 50 obtains the aging-corrected frequency control data AC (k +1) at time step k +1 from AC (k +1) ═ AC (k) + d (k). The processing unit 50 performs such addition processing of the correction values d (k) at each time step until the time of return from the hold mode (release time).

The processing unit 50 performs an arithmetic operation of adding the correction value after the filter process to the true value. For example, filtering processing such as low-pass filtering processing is performed on correction value D (k), and arithmetic processing is performed by sequentially adding filtered correction value D' (k) to the true value. Specifically, the arithmetic processing of AC (k +1) ═ AC (k) + D' (k) is performed.

The processing unit 50 also obtains a correction value from the observation residual in the kalman filter process. For example, the processing unit 50 performs a process of estimating a correction value of the aging correction from the observation residual until the hold mode is detected. For example, when the observation residual is ek, the correction value D (k) is estimated by performing the processing of D (k) ═ D (k-1) + E · ek. Here, E is a constant, for example, but a kalman gain may be used instead of the constant E. Then, the frequency control data DFCQ after the aging correction is generated by storing the correction value at the time corresponding to the detection time of the hold mode and performing an arithmetic process of adding the stored correction value to the true value.

As a method of disposing the terminal group and the like in the present embodiment, various modifications such as those shown in fig. 6 to 10 can be implemented. For example, in fig. 6, the terminal group TG1 is disposed in the terminal region AT1 along the side SD1, and the terminal group TG3 is disposed in the terminal region AT4 along the side SD 4. The terminal group TG2 is disposed in the terminal region AT2 along the side SD 2. The terminal groups TG3 may be arranged in a dispersed manner in the terminal area AT4 and the terminal area AT3 (arranged in both). Similarly, the terminal group TG2 may be arranged in a dispersed manner in the terminal region AT2 and the terminal region AT 3. As shown in fig. 6, it is desirable that the terminal groups TG2 and TG3 be disposed on the side of the side SD3 with respect to the side SD 1. This makes it possible to further separate the terminal group TG1 from the terminal groups TG2 and TG 3.

In fig. 7, contrary to fig. 6, the terminal group TG3 is disposed in the terminal region AT2, and the terminal group TG2 is disposed in the terminal region AT 4. In other words, in fig. 5 and the like, the side SD2 is the right side and the side SD4 is the left side in a plan view (plan view from the transistor formation region side) viewed from a direction intersecting the substrate (semiconductor substrate) of the circuit device, but the side SD2 may be the left side and the side SD4 may be the right side. Similarly, the sides SD1 and SD3 do not have to be the upper side and the lower side.

In fig. 8, terminal groups TG1 and TG2 are disposed in the terminal area AT1, and a terminal group TG3 is disposed in the terminal area AT 3. That is, the terminal group TG2 may be disposed in a terminal region other than the terminal region AT 2. In this case, the terminal group TG3 may be disposed in the terminal area AT2 or the terminal area AT 4.

In fig. 9 and 10, the terminal group TG1 is disposed in the terminal region AT1, and the terminal group TG2 and the terminal group TG3 are disposed in the terminal region AT 2. In fig. 9, the terminal group TG3 is arranged in a region farther from the terminal group TG1 than the terminal group TG 2. In fig. 10, the terminal group TG2 is arranged in a region farther from the terminal group TG1 than the terminal group TG 3. In addition, the terminal group TG2 and the terminal group TG3 may be disposed in the terminal area AT4 or the terminal area AT 3.

As described above, in the present embodiment, the terminal group TG1 for connection of the digital I/F section 30 is disposed in the terminal region AT1, and the terminal group TG3 for connection of the clock signal generation circuit 160 is disposed in any one of the terminal regions AT2, AT3, and AT 4. The terminal group TG2 for connection of the oscillator circuit 150 is disposed in a terminal region different from the terminal region in which the terminal group TG1 and the terminal group TG3 are disposed, for example. Further, as shown in fig. 9 and 10, it is also possible to perform a modification in which the terminal groups TG2 and TG3 are arranged in the same terminal region.

4. Clock signal generating circuit

Fig. 11 shows a1 st configuration example of the clock signal generation circuit 160. The clock signal generation circuit 160 in fig. 11 includes a phase comparison unit 161, a charge pump circuit 162, a filter unit 163,

frequency dividers

165 and 166, and an output buffer circuit 168. In fig. 11, an oscillator VCXO configured by the oscillation signal generation circuit 164 and the oscillator XTAL2 is provided outside the circuit device. That is, the loop of the PLL circuit is formed using an oscillator VCXO provided as an exterior member. However, a modification may be implemented in which the oscillation signal generation circuit 164 or the like is provided inside the circuit device.

The clock signal CKS generated by the oscillation signal generation circuit 164 of the clock signal generation circuit 160 is input to the frequency divider 165. The frequency divider 165 outputs a clock signal CKN having a frequency of CKS of 1/N. The oscillation signal OSCK generated by the oscillation signal generation circuit 140 in fig. 1 and 2 is input to the frequency divider 166 as a reference signal. The frequency divider 166 outputs a clock signal CKM having an OSCK frequency of 1/M. The phase comparison unit 161 compares the phases of the clock signals CKN and CKM and outputs up/down pulse signals as a result of the phase comparison. The charge pump circuit 162 converts the up/down pulse signal into an up/down current signal, and outputs the up/down current signal to the filter unit 163. The filter unit 163 converts the up/down current signal into a dc voltage, and outputs the dc voltage to the oscillation signal generation circuit 164 as an oscillation control voltage. The oscillation signal generation circuit 164 generates a clock signal CKS having a frequency set by the oscillation control voltage. The clock signal CKS is buffered by the output buffer circuit 168 and is output to the outside as a clock signal CK via the output terminal TCK. In this case, clock division by the frequency divider 169 is performed. The output terminal TCK is a terminal included in the terminal group TG3 in fig. 5.

In this way, the clock signal generation circuit 160 generates the clock signal CK having a frequency obtained by multiplying the oscillation frequency of the oscillation signal OSCK. The frequency multiplier in this case is set by the frequency division ratios of the

frequency dividers

165, 166, 169.

Fig. 12 shows an example of the configuration 2 of the clock signal generation circuit 160. The clock signal generation circuit 160 according to configuration example 2 is realized by a PLL circuit of a direct digital synthesizer system.

The phase comparison unit 380 (comparison operation unit) performs phase comparison (comparison operation) between the oscillation signal OSCK, which is a reference signal, and the clock signal CKS. The digital filter 382 performs a smoothing process of the phase error. The phase comparison unit 380 may include a counter and a TDC (time-to-digital converter) in the same manner as the phase comparison unit 41 of fig. 2. The digital filter unit 382 corresponds to the digital filter unit 44 in fig. 2. The numerical control oscillator 384 is a circuit that digitally synthesizes an arbitrary frequency and waveform using a reference oscillation signal from a reference oscillator 386 having a vibrator XTAL 2. That is, instead of controlling the oscillation frequency based on the control voltage from the D/a converter as in the VCO, the clock signal CKS of an arbitrary oscillation frequency is generated by digital arithmetic processing using digital frequency control data and the reference oscillator 386 (oscillator XTAL 2). The clock signal CKS is buffered by the output buffer circuit 168 and is output to the outside as a clock signal CK via the output terminal TCK. With the configuration of fig. 12, an ADPLL circuit of a direct digital synthesizer system can be realized.

The clock signal generation circuit 160 may not include all circuit elements for generating a clock signal. For example, the following structure may be adopted: a part of the circuit elements is constituted by discrete components provided outside the circuit device 500, and is connected to the clock signal generation circuit 160 via the 3 rd terminal group TG 3.

5. Temperature sensor and oscillation circuit

Fig. 13 shows a configuration example of the temperature sensor 10. The temperature sensor 10 of fig. 13 has a current source IST, and a bipolar transistor TRT whose collector is supplied with a current from the current source IST. The bipolar transistor TRT is diode-connected such that its collector and base are connected, and outputs a temperature detection voltage VTDI having temperature characteristics to a node of the collector of the bipolar transistor TRT. The temperature characteristic of the temperature detection voltage VTDI is generated due to the temperature dependence of the base-emitter voltage of the bipolar transistor TRT. The temperature detection voltage VTDI of the temperature sensor 10 has, for example, a negative temperature characteristic (1 st order temperature characteristic with a negative gradient).

Fig. 14 shows a configuration example of the oscillation circuit 150. The oscillation circuit 150 includes a current source IBX, a bipolar transistor TRX, a resistor RX, a variable capacitance capacitor CX1, and capacitors CX2 and CX 3.

The current source IBX provides a bias current to the collector of the bipolar transistor TRX. The resistor RX is disposed between the collector and the base of the bipolar transistor TRX.

One end of the variable capacitance capacitor CX1 whose capacitance is variable is connected to one end of the oscillator XTAL. Specifically, one end of the variable capacitance capacitor CX1 is connected to one end of the oscillator XTAL via the 1 st oscillator terminal (oscillator pad) of the circuit device. One end of the capacitor CX2 is connected to the other end of the oscillator XTAL. Specifically, one end of capacitor CX2 is connected to the other end of oscillator XTAL via the 2 nd oscillator terminal (oscillator pad) of the circuit device. One end of capacitor CX3 is connected to one end of oscillator XTAL, and the other end is connected to the collector of bipolar transistor TRX. These 1 st and 2 nd transducer terminals are terminals included in the 2 nd terminal group TG2 in fig. 5.

A base-emitter current generated by oscillation of the oscillator XTAL flows in the bipolar transistor TRX. When the base-emitter current increases, the collector-emitter current of the bipolar transistor TRX increases, and the bias current branched from the current source IBX to the resistor RX decreases, so that the collector voltage VCX decreases. On the other hand, when the base-emitter current of the bipolar transistor TRX decreases, the collector-emitter current decreases, and the bias current branched from the current source IBX to the resistor RX increases, so the collector voltage VCX increases. This collector voltage VCX is fed back to the oscillator XTAL via a capacitor CX 3.

The oscillation frequency of the oscillator XTAL has a temperature characteristic compensated by an output voltage VQ (frequency control voltage) of the D/a conversion unit 80. That is, the output voltage VQ is input to the variable capacitance capacitor CX1, and the capacitance value of the variable capacitance capacitor CX1 is controlled by the output voltage VQ. When the capacitance value of the variable capacitance capacitor CX1 changes, the resonance frequency of the oscillation loop changes, and thus the fluctuation of the oscillation frequency due to the temperature characteristic of the oscillator XTAL is compensated. The variable capacitance capacitor CX1 may be implemented by, for example, a variable capacitance diode (varactor).

The oscillation circuit 150 of the present embodiment is not limited to the configuration shown in fig. 14, and various modifications can be made. For example, although the case where CX1 is used as the variable capacitance capacitor in fig. 14 has been described as an example, CX2 or CX3 may be used as the variable capacitance capacitor controlled by the output voltage VQ. In addition, a plurality of CX1 to CX3 may be variable capacitance capacitors controlled by VQ.

The oscillation circuit 150 may not include all circuit elements for oscillating the oscillator XTAL. For example, the following structure may be adopted: a part of the circuit elements is constituted by discrete components provided outside the circuit device 500, and is connected to the oscillation circuit 150 via a2 nd terminal group TG 2.

6. Digital I/F unit, reference signal generation circuit, and thermostat control circuit

Fig. 15 shows a1 st configuration example of the digital I/F section 30. The digital I/F unit 30 of fig. 15 is implemented by a 2-wire serial interface circuit of I2C system, and includes an I2C control circuit 35 and a buffer circuit 36. R1 and R2 are pull-up resistors. The I2C scheme is a synchronous serial communication scheme in which communication is performed via 2 signal lines, i.e., a serial clock line SCL and a bidirectional serial data line SDA. A plurality of slave devices can be connected to the bus of I2C, and the master device communicates with the slave device after selecting the slave device by specifying the address of the individually determined slave device.

Fig. 16 shows a configuration example 2 of the digital I/F section 30. The digital I/F unit 30 shown in fig. 16 is implemented by a 3-wire or 4-wire SPI serial interface circuit, and includes an SPI control circuit 37 and a buffer circuit 38. R3, R4, R5 are pull-up resistors. The SPI system is a synchronous serial communication system that communicates with the 2 unidirectional serial data lines SDI and SDO via the serial clock line SCK. Multiple slave devices can be connected on the SPI bus, and to determine them, the master device needs to select the slave device using a slave device select line, in which case the slave device select line is needed.

Fig. 17 shows a configuration example of the reference signal generating circuit 180. The reference signal generation circuit 180 includes a bandgap reference circuit 182, a reference voltage generation circuit 184, and a reference current generation circuit 186. The bandgap reference circuit 182 includes an operational amplifier OPA1, bipolar transistors BA1, BA2, a transistor TA1, resistors RA1, RA2, and RA3, and generates a constant voltage VBG as a bandgap reference voltage. The bipolar transistors BA1 and BA2 are diode-connected in which the collector and the emitter are connected. The bandgap reference circuit 182 eliminates the temperature dependence of the bandgap voltage using these bipolar transistors BA1, BA2, and generates a constant voltage VBG that is constant with respect to temperature variation.

The reference voltage generation circuit 184 includes an operational amplifier OPA2, a transistor TA2, and resistors RA4 and RA 5. Then, a reference voltage VRF is generated as VRF ═ VBG { (RA4+ RA5)/RA5 }. The reference current generation circuit 186 includes an operational amplifier OPA3, transistors TA3, TA4, and resistors RA6, RA 7. Also, a constant current IRF is generated from the constant voltage VBG.

Fig. 18 shows a configuration example of the constant temperature bath control circuit 190. The oven control circuit 190 includes an operational amplifier OPB and resistors RB1 to RB 6. RB1 to RB5 are resistors whose resistance values are controlled to be variable.

The temperature sensor 193 is a temperature sensor for controlling the thermostatic bath, and is a temperature sensor (460 or 462 in fig. 32 described later) provided in the oscillator. In fig. 18, the temperature sensor 193 is implemented by a thermistor.

The temperature sensor 193 is connected to the thermostatic bath control circuit 190 via a connection terminal TCTS. The connection terminal TCTS is a terminal included in the 4 th terminal group TG4 of fig. 5.

The voltage VB1 for setting the thermostatic bath temperature is generated by resistance division of the power supply voltage by the resistors RB1 and RB 2. Then, the voltage VB2 changes as the resistance value of the thermistor of the temperature sensor 193 changes according to the oven temperature of the oscillator. The operational amplifier OPB operates such that the voltage VB2 becomes the same voltage as the thermostat temperature setting voltage VB1 through virtual grounding, and generates a heater control voltage VBQ.

The heater control voltage VBQ generated by the thermostatic bath control circuit 190 is output to the heater 191 (450, 452 of fig. 32) provided in the oscillator via the output terminal TVBQ. The output terminal TVBQ is a terminal included in the 4 th terminal group TG4 of fig. 5. The heater 191 includes a heat-generating power bipolar transistor 192 as a heat-generating element. The base voltage of the heating power bipolar transistor 192 and the like are controlled by the heater control voltage VBQ, whereby the heating control of the heater 191 is realized.

The thermostat control circuit 190 is not limited to the configuration of fig. 18. For example, the heater control circuit 190 may have a circuit configuration in which a heater is controlled by using a diode as a temperature sensor and a heating heater MOS transistor is provided as a heating element.

7. Oscillation frequency variation due to aging

In oscillators such as OCXO and TCXO, the oscillation frequency fluctuates due to a change with time called aging. In addition, the characteristics of the aging variation of the oscillation frequency among the individual oscillators are different depending on individual variations (hereinafter, referred to as element variations) such as the performance of the components constituting the oscillators, the mounting state of the components and the oscillators, and the use environment of the oscillators.

A1 to a5 in fig. 19 are examples of measurement results of aging characteristics of a plurality of oscillators having the same or different shipment lot numbers. As shown in a1 to a5 in fig. 19, the mode of aging fluctuation varies with variations in the elements.

The cause of the change in oscillation frequency due to aging is considered to be the detachment and adhesion of dust generated in the hermetically sealed container to the vibrator, the change in the environment due to some evolved gas, or the change with time of the adhesive used in the oscillator.

As a countermeasure for suppressing such a variation in oscillation frequency due to aging, there is a method of: the oscillator is initially aged for a predetermined period before shipment, and the oscillation frequency is initially changed before shipment. However, for applications requiring high frequency stability, it is not sufficient to take such measures for initial aging alone, and aging correction is desired to compensate for fluctuations in oscillation frequency caused by aging.

In addition, when an oscillator is used as a reference signal source of a base station, there is a problem of a so-called hold mode. For example, in a base station, a PLL circuit is used to synchronize an oscillation signal (output signal) of an oscillator with a reference signal from a GPS or a network, thereby suppressing frequency variation. However, when a reference signal from a GPS or a network (internet) is generated and a hold mode is lost or abnormal, a reference signal for synchronization cannot be obtained.

When such a hold mode is generated, an oscillation signal generated by the self-oscillation of the oscillator becomes a reference signal source of the base station. Therefore, the following hold mode performance is required: during a hold mode period from a generation timing of the hold mode to a timing (release timing) of recovery from the hold mode, fluctuation of an oscillation frequency due to self-oscillation of an oscillator is suppressed.

However, as described above, since the oscillation frequency of the oscillator varies to an extent that cannot be ignored due to aging, there is a problem that high hold mode performance cannot be realized due to this. For example, when an allowable frequency deviation (Δ f/f) is defined during a holding mode period of 24 hours or the like, if there is a large variation in oscillation frequency due to aging, the allowable frequency deviation cannot be defined.

For example, various communication methods such as FDD (Frequency Division Duplex) and TDD (Time Division Duplex) have been proposed as communication methods between a base station and a communication terminal. In the TDD scheme, data is transmitted and received in a time division manner using the same frequency in the uplink and the downlink, and a guard time is set between time slots allocated to each device. Therefore, in order to realize appropriate communication, time synchronization is required in each device, and accurate absolute time measurement is required.

B1 in fig. 20 shows the characteristic of aging of the ideal oscillation frequency in the case where the hold mode is generated. On the other hand, B2 (dotted line) shows the characteristic of fluctuation of the oscillation frequency due to aging. B3 is the amplitude of variation in the oscillation frequency due to aging. B4 in fig. 21 shows the transition of the frequency control voltage to approximate the characteristic of B1 when the hold mode is generated. On the other hand, B5 (broken line) indicates a state where the frequency control voltage is constant from the time when the reference signal disappears or an abnormality occurs.

In order to perform correction for bringing the characteristic shown in B2 of fig. 20 close to the ideal characteristic shown in B1, aging correction is performed. For example, if the frequency control voltage is changed as shown in B4 of fig. 21 by aging correction, it is possible to perform correction to bring the characteristic shown in B2 of fig. 20 close to the ideal characteristic shown in B1, and for example, if the correction accuracy is improved, it is possible to correct the characteristic shown in B2 to the ideal characteristic shown in B1. On the other hand, if the aging correction is not performed as shown in B5 of fig. 21, the oscillation frequency fluctuates during the holding mode as shown in B2 of fig. 20, and if the specification of the requirement for the holding mode performance is B1 shown in fig. 20, for example, the requirement cannot be satisfied.

Hold mode time θ representing, for example, the amount of time shift (total amount) based on the fluctuation of oscillation frequency during hold mode_totCan be represented by the following formula (1).

Here, T₁Indicating the elapsed time of aging caused by the hold mode. f. of₀Is the nominal oscillation frequency, Δ f/f₀Is the frequency deviation. In the above formula (1), T₁×f₀Representing the total number of clocks, (Δ f/f)₀)×(1/f₀) Indicating the offset of the time within 1 clock. Furthermore, the frequency deviation Δ f/f₀Can use the hold mode time theta_totAnd elapsed time T₁This is represented by the above formula (2).

Here, it is assumed that the frequency deviation Δ f/f₀Varying with a constant slope as a function of 1 with respect to the elapsed time. In this case, as the time T elapses₁Becomes long, and the mode holding time theta_totBecomes longer as a function of degree 2.

For example, in the case of the TDD scheme, in order to prevent overlapping of time slots in which guard times are set, the hold mode time is required to be θ_tot< 1.5. mu.s. Therefore, as can be seen from the above equation (2), the frequency deviation Δ f/f allowable for the oscillator₀Very small values are required. In particular, the elapsed time T₁The longer the allowable frequency deviation requirement is, the smallerThe value of (c). For example, the time assumed as the time from the generation time of the hold mode to the time of recovery from the hold mode by the maintenance job is, for example, T₁In the case of 24 hours, a very small value is required as an allowable frequency deviation. Moreover, the frequency deviation is Δ f/f₀For example, a frequency deviation depending on temperature and a frequency deviation caused by aging are included, and therefore, in order to satisfy the above requirements, aging correction with very high accuracy is required.

8. Aging correction using kalman filtering process

In the present embodiment, an aging correction method using kalman filter processing is employed. Specifically, in the present embodiment, the true value of the observation value for the frequency control data (oscillation frequency) is estimated by the kalman filter process until the hold mode is detected. When the hold mode is detected, the aging correction is realized by storing a true value at a time (time point) corresponding to the time at which the hold mode is detected and performing an arithmetic process based on the stored true value.

Fig. 22 is a graph showing an example of measurement results of the fluctuation of the oscillation frequency due to aging. The horizontal axis represents elapsed time (aging time), and the vertical axis represents frequency deviation (Δ f/f) of oscillation frequency₀). As shown in C1 in fig. 22, a large variation due to system noise or observation noise exists in the measurement value as the observation value. The deviation also includes a deviation caused by the ambient temperature.

In order to accurately obtain a true value in a situation where there is a large variation in the measured values as described above, in the present embodiment, state estimation by kalman filtering (for example, linear kalman filtering) is performed.

Fig. 23 shows a time-series state space model whose discrete time state equations are given by the state equations and observation equations of the following equations (3) and (4).

x(k+1)＝A·x(k)+v(k)···(3)

y(k)＝x(k)+w(k)···(4)

x (k) is the state at time k, and y (k) is the observed value. v (k) is system noise, w (k) is observation noise, and A is the system matrix. In the case where x (k) is an oscillation frequency (frequency control data), a corresponds to, for example, an aging rate (aging coefficient). The aging rate represents the rate of change of the oscillation frequency with respect to the elapsed period.

For example, it is assumed that the hold mode is generated at the time indicated by C2 in fig. 22. In this case, the aging correction is performed based on the true state x (k) at the time of C2 at which the reference signal RFCK is interrupted, and the aging rate (a) equivalent to the slope shown in C3 of fig. 22. Specifically, as compensation (correction) for reducing the frequency change due to the aging rate shown by C3, for example, aging correction is performed in which the true values x (k) of the oscillation frequency (frequency control data) at the time of C2 are sequentially changed so as to cancel (cancel) the frequency change. That is, the frequency change at the aging rate shown in B2 of fig. 20 is canceled, so that the correction value that becomes the ideal characteristic shown in B1 changes the true value x (k). Thus, for example, when the period of the hold mode is 24 hours, the FDV of fig. 22, which is the fluctuation of the oscillation frequency after the elapse of 24 hours, can be compensated by the aging correction.

Here, the fluctuation of the oscillation frequency (frequency deviation) shown in C1 of fig. 22 includes a fluctuation due to temperature fluctuation and a fluctuation due to aging. Therefore, in the present embodiment, for example, by using an oscillator (OCXO) having a thermostat structure with a thermostat, the fluctuation of the oscillation frequency due to the temperature fluctuation is suppressed to the minimum. Further, temperature compensation processing for reducing the fluctuation of the oscillation frequency caused by the temperature fluctuation is performed using the temperature sensor 10 of fig. 2 or the like.

In a period (normal operation period) in which the PLL circuit (internal PLL circuit, external PLL circuit) is synchronized with the reference signal RFCK, the frequency control data (frequency control code) is monitored, and a true value obtained by removing an error (system noise, observation noise) is obtained and stored in the register. When the lock of the PLL circuit is released due to disappearance or abnormality of the reference signal RFCK, the aging correction is performed based on the true value (true value of the observed value of the frequency control data) held at the time of release of the lock. For example, as compensation for reducing the frequency change due to the aging rate which is the slope of C3 in fig. 22, the frequency control data DFCQ at the time of self-oscillation during the hold mode is generated by sequentially adding, for example, correction values for eliminating the frequency change to the true values of the stored frequency control data, and the oscillator XTAL is oscillated. In this way, since the true value of the time when the hold mode is entered can be obtained with the minimum error and the aging correction can be executed, the hold mode performance can be realized in which the adverse effect due to the aging variation is minimized.

9. Structure of processing part

Fig. 24 shows a detailed configuration example of the processing unit 50. As shown in fig. 24, the processing unit 50 includes a kalman filter unit 54, an aging correction unit 56, a temperature compensation unit 58,

selectors

62 and 63, and an adder 65.

The kalman filter 54 receives frequency control data DFCI (frequency control data from which the environment fluctuation component is removed) and performs a kalman filter process. Further, a posterior estimated value x ^ (k) equivalent to a true value estimated by the Kalman filtering process is output. In the present specification, the symbol "^" indicating a hat shape which is an estimated value is described as being appropriately arranged in 2 characters.

The kalman filter process refers to a process of: assuming that noise (error) is included in the observation value and the variable representing the state of the system, the optimal state of the system is estimated using the observation values taken from the past to the present. Specifically, the state is estimated by repeating observation update (observation process) and time update (prediction process). Observation update is the process of updating kalman gain, estimated value, error covariance using the results of the observation and time updates. The time update is a process of predicting an estimated value, an error covariance, at the next time using the result of the observation update. In the present embodiment, the method using the linear kalman filter process has been mainly described, but the extended kalman filter process may be adopted. The kalman filter process according to the present embodiment will be described in detail later.

The aging correction section 56 inputs the posterior estimation value x ^ (k) and the correction value D' (k) from the Kalman filtering section 54. Then, the aging-corrected frequency control data, that is, AC (k), is generated by performing an arithmetic process of adding the correction value D' (k) to the posterior estimate value x ^ (k) corresponding to the true value of the frequency control data. Here, D' (k) is the correction value D (k) after the filter processing (after the low-pass filter processing). That is, when the correction value (the correction value after the filtering process) at time step k (time k) is D '(k) and the frequency control data after the aging correction at time step k is AC (k), the aging correction unit 56 obtains the frequency control data AC (k +1) after the aging correction at time step k +1 (time k +1) from AC (k +1) ═ AC (k) + D' (k).

The temperature compensation unit 58 receives the temperature detection data DTD, performs temperature compensation processing, and generates temperature compensation data TCODE (temperature compensation code) for keeping the oscillation frequency constant with respect to temperature fluctuation.

The temperature characteristic of the oscillation frequency is largely deviated depending on the sample of each product. Therefore, in an inspection process at the time of manufacturing and shipment of a product (oscillator), a temperature characteristic of an oscillation frequency and a change characteristic of temperature detection data corresponding to an ambient temperature are measured. And the coefficient A of a polynomial (approximate function) of the following equation (5) is obtained from the measurement result₀～A₅Coefficient A to be obtained₀～A₅The information (b) is written into the storage unit 34 (nonvolatile memory) in fig. 2 and stored.

TCODE＝A₅·X⁵+A₄·X⁴+A₃·X³+A₂·X²+A₁·X+A₀···(5)

In the above equation (5), X corresponds to the temperature detection data DTD (a/D conversion value) obtained by the a/D conversion unit 20. Since the change in the temperature detection data DTD with respect to the change in the ambient temperature is also measured, the ambient temperature can be associated with the oscillation frequency by the approximate function expressed by the polynomial expression of the above expression (5). Temperature compensation unit 58 reads out coefficient a from storage unit 34₀～A₅According to the coefficient A₀～A₅The arithmetic processing of the above equation (5) is performed with the temperature detection data DTD (═ X), and temperature compensation data TCODE (temperature compensation code) is generated. Thereby, the method for makingAnd a temperature compensation process in which the oscillation frequency is kept constant with respect to the change in the ambient temperature.

When the logic level of the input signal to the selection terminal S is "1" (active), the

selectors

62 and 63 select the input signal to the terminal on the "1" side and output the selected signal as an output signal. When the logic level of the input signal to the selection terminal S is "0" (invalid), the input signal to the terminal on the "0" side is selected and output as the output signal.

The signal KFEN is an enable signal of the kalman filtering process. The kalman filter unit 54 executes the kalman filter process when the signal KFEN is at the logic level "1" (hereinafter, abbreviated as "1"). The signal PLLLOCK is a signal that becomes "1" when the PLL circuit is in a locked state. The signal HOLDOVER is a signal that becomes "1" during the holding mode in which the holding mode is detected.

The signal TCEN is an enable signal of the temperature compensation process. Hereinafter, a case where the signal TCEN is "1" and the selector 63 selects the input signal on the "1" side will be mainly described as an example. Further, the signal KFEN is also "1".

During the normal operation, since the signal HOLDOVER is at the logic level "0" (hereinafter, abbreviated as "0"), the selector 62 selects the frequency control data DFCI on the "0" terminal side, and the adder 65 adds the temperature compensation data TCODE to the frequency control data DFCI, so that the frequency control data DFCQ after the temperature compensation process is output to the oscillation signal generating circuit 140 at the subsequent stage.

On the other hand, during the hold mode, the signal HOLDOVER is "1", and the selector 62 selects ac (k) on the "1" terminal side. Ac (k) is the aging-corrected frequency control data.

Fig. 25 is a truth table for explaining the operation of the kalman filter unit 54. When both the signals PLLLOCK and KFEN are "1", the kalman filter unit 54 executes the truth estimation process (kalman filter process). That is, when the PLL circuit (internal or external PLL circuit) is in a locked state during the normal operation period, the true value estimation process of the frequency control data DFCI as the observation value is continuously performed.

When the lock of the PLL circuit is released and the signal PLLLOCK is "0" in the state of the hold mode, the kalman filter unit 54 holds the previous output state. For example, in fig. 24, the value at the detection timing of the hold mode (the timing of releasing the lock of the PLL circuit) is stored and continuously output as the posterior estimation value x ^ (k) estimated as the true value of the frequency control data DFCI and the correction value D' (k) for the aging correction.

The aging correction unit 56 performs aging correction using the posterior estimation value x ^ (k) and the correction value D' (k) from the Kalman filtering unit 54 during the hold mode. Specifically, the posterior estimate value x ^ (k) and the correction value D' (k) at the detection time of the hold mode are stored, and burn-in correction is performed.

In fig. 24, the kalman filter unit 54 receives frequency control data DFCI from which the temperature fluctuation component (environment fluctuation component in a broad sense) and the aging fluctuation component are removed. The kalman filter 54 performs kalman filtering on the frequency control data DFCI from which the temperature fluctuation component (environment fluctuation component) is removed, and estimates a true value for the frequency control data DFCI. That is, the posterior estimate x ^ (k) is obtained. The aging correction unit 56 performs aging correction based on the estimated truth value, i.e., the posterior estimation value x ^ (k). More specifically, the aging-corrected frequency control data AC (k) is obtained from the posterior estimation value x ^ (k) and the correction value D' (k) from the Kalman filtering unit 54. The frequency control data after the aging correction, i.e., ac (k), is input to the adder 65 via the selector 62, and the adder 65 performs processing of adding the temperature compensation data TCODE (data for compensating for an environmental fluctuation component) to ac (k).

For example, as shown in the schematic diagram of fig. 26, when the temperature varies, the frequency control data also varies in accordance with the variation as shown in E1. Therefore, when the kalman filter process is performed using the frequency control data that fluctuates with temperature fluctuations, such as E1, the true value at the hold pattern detection time fluctuates.

Therefore, in the present embodiment, the frequency control data from which the temperature fluctuation component is removed is acquired and input to the kalman filter unit 54. That is, the frequency control data from which the temperature fluctuation component (environmental fluctuation component) and the aging fluctuation component are removed is input to the kalman filter unit 54. That is, the frequency control data shown in E2 of fig. 26 is input. The frequency control data of E2 is frequency control data from which the temperature fluctuation component is removed and the aging fluctuation component remains.

The kalman filter unit 54 performs kalman filtering on the frequency control data DFCI from which the temperature fluctuation component is removed and the aging fluctuation component remains, thereby obtaining the posterior estimation value x ^ (k) of the estimated true value and the correction value D' (k) of the aging correction. The posterior estimate value x ^ (k) and the correction value D' (k), which are the true values estimated at the detection time of the hold mode, are stored in the aging correction unit 56 and used to perform aging correction.

For example, the adder 65 adds the temperature compensation data TCODE, and the frequency control data DFCQ becomes the frequency control data subjected to the temperature compensation. Therefore, the oscillation signal generation circuit 140 to which the frequency control data DFCQ is input outputs the oscillation signal OSCK of the oscillation frequency after temperature compensation. Therefore, the frequency control data generating unit 40 of fig. 2 (or the external frequency control data generating unit 200, hereinafter the same) which constitutes the PLL circuit together with the oscillation signal generating circuit 140 supplies the frequency control data DFCI from which the temperature fluctuation component is removed to the processing unit 50 as shown in E2 of fig. 26. As shown in E2 in fig. 26, the frequency control data DFCI from which the temperature fluctuation component is removed has an aging fluctuation component remaining therein that changes with time. Therefore, the kalman filter 54 of the processing unit 50 performs the kalman filter process on the frequency control data DFCI in which the aging fluctuation component remains, and if the aging corrector 56 performs the aging correction based on the result of the kalman filter process, it is possible to realize the aging correction with high accuracy.

As a modification of fig. 24, instead of the process of adding the temperature compensation data TCODE to the adder 65, a calculation process of removing the temperature fluctuation component (environment fluctuation component) of the frequency control data DFCI may be performed, and the frequency control data DFCI after the calculation process may be input to the kalman filter unit 54. For example, the adder 65 and the selector 63 in fig. 17 are omitted, a subtractor for subtracting the temperature compensation data TCODE from the frequency control data DFCI is provided in a stage prior to the kalman filter unit 54, and the output of the subtractor is input to the kalman filter unit 54. An adder for adding the output of the aging correction unit 56 and the temperature compensation data TCODE is provided between the aging correction unit 56 and the selector 62, and the output of the adder is input to the terminal on the "1" side of the selector 62. With this configuration, the frequency control data DFCI from which the temperature fluctuation component is removed and only the aging fluctuation component remains can be input to the kalman filter unit 54.

Fig. 27 shows a detailed configuration example of the aging correcting unit 56. During the normal operation, the signal HOLDOVER is "0", and therefore, the

selectors

360 and 361 select the "0" terminal side. Thus, during the normal operation period, the posterior estimated value x ^ (k) and the correction value D' (k) (the correction value after the filtering process) calculated by the kalman filter unit 54 are stored in the

registers

350 and 351, respectively.

When the hold mode is detected and the signal HOLDOVER is "1", the

selectors

360 and 361 select the "1" terminal side. Thus, during the hold mode period, selector 361 continues to output correction value D' (k) stored in register 351 at the detection time of the hold mode.

Furthermore, the adder 340 performs the following processing: at each time step, correction value D' (k) (correction value) output from selector 361 and stored in register 351 is sequentially added to a posterior estimate value x ^ (k) stored in register 350 at the detection time of the hold mode. Thereby, aging correction shown in the following formula (6) is realized.

AC(k+1)＝AC(k)+D′(k)···(6)

That is, the following processing is performed to realize the aging correction: the correction value D' (k) for canceling (compensating) the frequency change caused by the aging rate corresponding to the slope of C3 is sequentially added to the posterior estimation value x ^ (k), which is the true value held at the time of C2 in fig. 22.

10. Kalman filtering process

Next, the kalman filter process according to the present embodiment will be described in detail. The state equation and the observation equation of the kalman filter model are expressed by the following equations (7) and (8).

x(k+1)＝A·x(k)+v(k)···(7)

y(k)＝C^T+x(k)+w(k)···(8)

K denotes a time step as discrete time. x (k) is the state of the system at time step k (time k), e.g., an n-dimensional vector. A is called the system matrix. Specifically, a is an n × n matrix, and relates the state of the system at time step k to the state of the system at time step k +1 when there is no system noise. v (k) is system noise. y (k) is an observed value, and w (k) is observed noise. C is an observation coefficient vector (n-dimensional), and T represents a transposed matrix.

In the kalman filtering process of the models of the above equations (7) and (8), the following equations (9) to (13) are performed to estimate the true value.

P^-(k)＝A·P(k-1)·A^T+v(k)···(10)

P(k)＝(1-G(k)·C^T)·P^-(k)···(13)

x ^ (k): posterior estimate

x^^-(k) The method comprises the following steps A priori estimate

P (k): posterior covariance

P^-(k) The method comprises the following steps Prior covariance

G (k): kalman gain

The above expressions (9) and (10) are expressions of temporal update (prediction process), and the above expressions (11) to (13) are expressions of observation update (observation process). Every time the time step k, which is a discrete time, advances by 1, time updates (expressions (9) and (10)) and observation updates (expressions (11) and (13)) of the kalman filter process are performed 1 time.

And x ^ (k) and x ^ (k-1) are the posterior estimated values of the Kalman filtering processing of time steps k and k-1. x ^ a^-(k) Is a priori estimated value predicted before the observed value is obtained. P (k) is the A posteriori covariance of the Kalman Filter Process, P^-(k) Is the a priori covariance predicted before the observed value is obtained. G (k) is the Kalman gain.

In the kalman filter process, the kalman gain g (k) is obtained by the above equation (11) in the observation update. Furthermore, the posterior estimate x ^ (k) is updated by equation (12) above based on the observed value y (k). Further, the a posteriori covariance p (k) of the error is updated by the above equation (13).

Further, in the Kalman filtering process, in time updating, as shown in the above equation (9), from the posterior estimate value x ^ (k-1) of time step k-1 and the system matrix A, the prior estimate value x ^ of the next time step k is predicted^-(k) In that respect Furthermore, as shown in the above equation (10), the prior covariance P at the next time step k is predicted from the posterior covariance P (k-1) at the time step k-1, the system matrix A, and the system noise v (k)^-(k)。

In addition, when the kalman filter processing of the above equations (9) to (13) is to be executed, the processing load of the processing unit 50 may become excessive, which may lead to a large-scale circuit device. For example, to find x ^ of the above formula (9)^-(k) Ax ^ (k-1) requires extended Kalman filtering. Moreover, the processing load of the extended kalman filter processing is very heavy, and when the processing unit 50 is to be realized by hardware capable of performing the extended kalman filter processing, the circuit area of the processing unit 50 tends to become very large. Therefore, it is not appropriate in a situation where miniaturization is strongly demanded for a circuit device incorporating an oscillator. On the other hand, when a scalar value of a fixed value is used as the system matrix a, the difficulty in achieving appropriate aging correction is increased.

Therefore, as a solution to avoid such a situation, in the present embodiment, the kalman filter process is realized by the processes based on the following expressions (14) to (19) instead of the above expressions (9) to (13). That is, the processing unit 50 (kalman filter unit 54) executes the kalman filter processing based on the following expressions (14) to (19).

P^-(k)＝P(k-1)+v(k)···(15)

P(k)＝(1-G(k))·P^-(k)···(18)

In the present embodiment, x (k) that is the target of the estimation process of the true value is frequency control data, and since the observation value y (k) is also frequency control data, C is 1. Further, since the scalar value of a is infinitely close to 1, the above expression (15) can be used instead of the above expression (10).

As described above, in the Kalman filtering process of the present embodiment, the a priori estimate value x ^ of time k is obtained by adding the a posteriori estimate value x ^ (k-1) at time step k-1 and the correction value D (k-1) as shown in equation (14) above, compared to the case where the extended Kalman filtering process is adopted as the Kalman filtering process^-(k) In that respect Therefore, the extended kalman filter process is not required, and the processing load of the processing unit 50 can be reduced, and an increase in the circuit scale can be suppressed.

In the present embodiment, the above expression (14) is derived by a modification of the following expression.

For example, the above formula (20) can be modified as the above formula (21). Here, since (A-1) in the above expression (21) is a very small number, (A-1). xFalpha (k-1) can be replaced with (A-1). Ff as shown in the above expressions (22) and (23)₀An approximation of. Then, the (A-1) & F₀The correction value D (k-1) is substituted.

As shown in equation (19), when time is updated from time step k-1 to time step k, correction value D (k) ═ D (k-1) + E · (y (k) — x ^ is performed^-(k) D (k-1) + E · ek. Here, ek ═ y (k) -x ^ x^-(k) Referred to as the observation residual in the kalman filtering process. Further, E is a constant. In addition, instead of the constant E, a modification using the kalman gain g (k) may be performed. That is, D (k) may be D (k-1) + g (k) ek.

In this way, in equation (19), when the observation residual is ek and the constant is E, correction value D (k) is obtained from D (k) ═ D (k-1) + E · ek. In this way, the process of updating the correction value d (k) in which the observation residual ek in the kalman filter process is reflected can be performed.

As described above, in the present embodiment, as shown in the above equation (14), the processing unit 50 performs the following processing in the process of updating the prior estimate value (time update) in the kalman filter processing: the a priori estimated value x ^ 1 at the current time is obtained by adding the a posteriori estimated value x ^ (k-1) at the previous time to the correction value D (k-1)^-(k) In that respect Then, aging correction of the frequency control data is performed based on the result of the kalman filter process. That is, the addition processing of the posterior estimated value x ^ (k-1) of the time step k-1 at the previous time and the correction value D (k-1) is performed, and x ^ is used^-(k) X ^ (k-1) + D (k-1) to obtain the prior estimation value x ^ k of the time step k at the moment^-(k)。

Then, the processing unit 50 (aging correction unit 56) performs aging correction based on the result (true value, correction value) of the kalman filter process. That is, when the correction value at time step k is D (k) (or D '(k)) and the frequency control data after aging correction at time step k is AC (k), the frequency control data AC (k +1) after aging correction at time step k +1 is obtained from AC (k +1) ═ AC (k) + D (k) (or AC (k) + D' (k)).

As shown in equation (19), the processing unit 50 obtains the current time correction value D (k) from the previous time correction value D (k-1) and the observation residual ek in the kalman filter process. For example, correction value D (k) at the present time is obtained by adding E · ek (or g (k) · ek) which is a value based on the observation residual to correction value D (k-1) at the previous time. Specifically, correction value D (k) for time step k at the present time is obtained from correction value D (k-1) for time step k-1 at the previous time and observation residual ek in kalman filter processing. For example, when the observation residual is ek and the constant is E, correction value D (k) is obtained from D (k) ═ D (k-1) + E · ek.

For example, in the present embodiment, as described with reference to fig. 26, the environment fluctuation component information such as the temperature fluctuation component information is acquired, and the frequency control data from which the environment fluctuation component out of the environment fluctuation component and the aging fluctuation component is removed is acquired using the acquired environment fluctuation component information. Here, the environment fluctuation component information may be a power supply voltage fluctuation component, an air pressure fluctuation component, a gravity fluctuation component, or the like. Then, aging correction is performed based on the frequency control data from which the environment fluctuation component is removed. Specifically, the environment fluctuation component is defined as temperature. Temperature fluctuation component information, which is environmental fluctuation component information, is acquired from temperature detection data DTD obtained from a temperature detection voltage VTD from the temperature sensor 10 of fig. 2, which is an environmental fluctuation information acquisition unit for acquiring the environmental fluctuation component information. Then, frequency control data from which the temperature fluctuation component is removed is acquired using the acquired temperature fluctuation component information. For example, the temperature compensation unit 58 in fig. 24 acquires the temperature compensation data TCODE, and the adder 65 performs the addition processing of the temperature compensation data TCODE, whereby the frequency control data DFCI from which the temperature variation component is removed is input from the frequency control data generation unit 40 (or the external frequency control data generation unit 200) and acquired by the processing unit 50. That is, as shown in E2 in fig. 26, the frequency control data DFCI from which the temperature fluctuation component is removed and the aging fluctuation component remains is acquired and input to the kalman filter unit 54.

The frequency control data from which the environmental fluctuation component is removed includes frequency control data in an appropriate state from which the environmental fluctuation component is completely removed, and also includes frequency control data in a state in which the environmental fluctuation component is present to a negligible extent in the frequency control data.

For example, the environment fluctuation component information such as the temperature fluctuation component information or the power supply voltage fluctuation component information can be acquired by a temperature sensor, a voltage detection circuit, and the like as the environment fluctuation information acquisition unit that detects the environment fluctuation component information. On the other hand, the aging fluctuation component is a fluctuation component of the oscillation frequency that changes with time, and it is difficult to directly detect information of the aging fluctuation component by a sensor or the like.

Therefore, in the present embodiment, the environment fluctuation component information such as the temperature fluctuation component information detectable by the sensor or the like is acquired, and the frequency control data from which the environment fluctuation component out of the environment fluctuation component and the aging fluctuation component is removed is acquired by using the environment fluctuation component information. That is, by performing a process of removing the environment fluctuation component from the fluctuation component of the frequency control data (for example, an addition process by the adder 65), the frequency control data in which only the aged fluctuation component remains can be acquired as shown in E2 of fig. 26. Then, if kalman filtering or the like is performed on the frequency control data in which the aging fluctuation component remains, it is possible to estimate a true value for the frequency control data. Further, if the burn-in correction is performed based on the truth value estimated in this way, it is possible to realize the burn-in correction with high accuracy which has not been realized in the conventional example.

As described above, in the present embodiment, the frequency control data DFCI from which the temperature fluctuation component (environment fluctuation component) is removed and the aging fluctuation component remains is input to the kalman filter unit 54. As shown in fig. 19 and 22, if the period is limited, it can be assumed that the oscillation frequency changes at a constant aging rate during the period. A constant slope change can be assumed, for example, as shown at C3 of fig. 22.

In the present embodiment, a correction value for compensating (canceling) a frequency change at a constant aging rate due to such an aging fluctuation component is obtained by the expression D (k) ═ D (k-1) + E · ek. That is, the correction value d (k) for compensating for the frequency change caused by the aging rate corresponding to the slope of C3 of fig. 22 is found. Here, the aging rate is not constant, but changes with the passage of time as shown in fig. 19 and 22.

In contrast, in the present embodiment, the observation residual ek ═ y (k) -x ^ according to the kalman filter process, as D (k) ═ D (k-1) + E · ek, is^-(k) The correction value d (k) corresponding to the aging rate is updated. Therefore, it is possible to realize the update processing of the correction value d (k) that also reflects the change in the aging rate corresponding to the elapsed time. Therefore, aging correction with higher accuracy can be realized.

11. Modification example

Next, various modifications of the present embodiment will be described. Fig. 28 shows a configuration example of a circuit device according to a modification of the present embodiment.

In fig. 28, unlike fig. 1 and 2, the oscillation signal generating circuit 140 is not provided with the D/a converter 80. The oscillation frequency of the oscillation signal OSCK generated by the oscillation signal generation circuit 140 is directly controlled based on the frequency control data DFCQ from the processing unit 50. That is, the oscillation frequency of the oscillation signal OSCK is controlled without passing through the D/a conversion unit.

For example, in fig. 28, the oscillation signal generation circuit 140 has a variable capacitance circuit 142 and an oscillation circuit 150. The oscillation signal generating circuit 140 is not provided with the D/a converter 80 shown in fig. 1 and 2. The variable capacitance circuit 142 is provided instead of the variable capacitance capacitor CX1 in fig. 14, and one end of the variable capacitance circuit 142 is connected to one end of the oscillator XTAL.

The capacitance value of the variable capacitance circuit 142 is controlled based on the frequency control data DFCQ from the processing unit 50. For example, the variable capacitance circuit 142 has a plurality of capacitors (capacitor array), and a plurality of switching elements (switch array) that control on and off of each switching element according to the frequency control data DFCQ. Each of the plurality of switching elements is electrically connected to each of the plurality of capacitors. By turning on or off the plurality of switching elements, the number of capacitors, one end of which is connected to one end of the oscillator XTAL, among the plurality of capacitors is changed. Thereby, the capacitance value of the variable capacitance circuit 142 is controlled, and the capacitance value of one end of the oscillator XTAL changes. Therefore, the frequency control data DFCQ can be used to directly control the capacitance value of the variable capacitance circuit 142 and control the oscillation frequency of the oscillation signal OSCK.

12. Oscillator, electronic apparatus, and moving object

Fig. 29 shows a configuration example of an oscillator 400 including the circuit device 500 of the present embodiment. As shown in fig. 29, oscillator 400 includes oscillator 420 and circuit device 500. The vibrator 420 and the circuit device 500 are mounted in the package 410 of the oscillator 400. Terminals of oscillator 420 and terminals (pads) of circuit device 500(IC) are electrically connected by internal wiring of package 410.

Fig. 30 shows a configuration example of an electronic device including the circuit device 500 of the present embodiment. The electronic device includes a circuit device 500 according to this embodiment, an oscillator 420 such as a quartz oscillator, an antenna ANT, a communication unit 510, and a processing unit 520. Further, the operation unit 530, the display unit 540, and the storage unit 550 may be included. Oscillator 400 is configured by oscillator 420 and circuit device 500. The electronic device is not limited to the configuration of fig. 30, and various modifications may be made such as omitting some of the components and adding other components.

As the electronic device in fig. 30, various devices such as a network-related device such as a base station or a router, a high-precision measurement device, a GPS-incorporated clock, a wearable device such as a vital information measurement device (a pulsimeter, a pedometer, or the like) or a head-mounted display device, a smart phone, a mobile phone, a portable game device, a portable information terminal (mobile terminal) such as a notebook PC or a tablet PC, a content providing terminal for delivering content, and a video device such as a digital camera or a video camera can be assumed.

The communication unit 510 (wireless circuit) performs processing for receiving data from the outside or transmitting data to the outside via the antenna ANT. The processing unit 520 performs control processing of the electronic device, various kinds of digital processing of data transmitted and received via the communication unit 510, and the like. The function of the processing unit 520 can be realized by a processor such as a microcomputer.

The operation unit 530 is used for a user to perform an input operation, and may be implemented by operation buttons, a touch panel display, and the like. The display unit 540 is used to display various information, and may be implemented by a display such as a liquid crystal display or an organic EL display. In the case where a touch panel display is used as the operation unit 530, the touch panel display also functions as the operation unit 530 and the display unit 540. The storage unit 550 stores data, and its function can be realized by a semiconductor memory such as a RAM or a ROM, an HDD (hard disk drive), or the like.

Fig. 31 shows an example of a mobile body including the circuit device of the present embodiment. The circuit device (oscillator) according to the present embodiment can be incorporated in various moving bodies such as a vehicle, an airplane, a motorcycle, a bicycle, or a ship, for example. The moving body is, for example, a device or an apparatus that has a driving mechanism such as an engine or a motor, a steering mechanism such as a steering wheel or a rudder, and various electronic devices (vehicle-mounted devices) and that moves on land, in the air, or on the sea. Fig. 31 schematically shows an automobile 206 as a specific example of the moving object. The automobile 206 incorporates an oscillator (not shown) having the circuit device and the vibrator of the present embodiment. The control device 208 operates in accordance with the clock signal generated by the oscillator. The control device 208 controls the hardness of the suspension or the braking of each wheel 209, for example, in accordance with the posture of the vehicle body 207. For example, the control device 208 can be used to automatically operate the vehicle 206. The device incorporating the circuit device or the oscillator according to the present embodiment is not limited to the control device 208, and may be incorporated in various devices (in-vehicle devices) provided in a mobile body such as an automobile 206.

Fig. 32 shows a detailed configuration example of the oscillator 400. The oscillator 400 of fig. 32 is an oscillator of a double oven configuration (oven configuration in a broad sense).

The package 410 is composed of a substrate 411 and a case 412. Various electronic components not shown are mounted on the substrate 411. A2 nd container 414 is provided inside the case 412, and a1 st container 413 is provided inside the 2 nd container 414. Further, a vibrator 420 is attached to an inner surface (lower surface) of the upper surface of the 1 st container 413. Further, the circuit device 500, the heater 450, and the temperature sensor 460 of the present embodiment are mounted on the outer surface (upper surface) of the upper surface of the 1 st container 413. The temperature of the inside of the 2 nd container 414, for example, can be adjusted by the heater 450 (heat generating element). The temperature sensor 460 can detect, for example, the temperature inside the 2 nd container 414.

The 2 nd container 414 is disposed on a base plate 416. The substrate 416 is a circuit board on which various electronic components can be mounted. A heater 452 and a temperature sensor 462 are mounted on the substrate 416 on the side opposite to the side on which the 2 nd container 414 is provided. The temperature of the space between the housing 412 and the 2 nd container 414 can be adjusted by, for example, a heater 452 (heat generating element). The temperature of the space between the housing 412 and the 2 nd container 414 can be detected by the temperature sensor 462.

As the heating elements of the

heaters

450 and 452, for example, a heating power bipolar transistor, a heating type heater MOS transistor, a heating resistor, a peltier element, or the like can be used. The control of the heat generation of the

heaters

450 and 452 can be realized by, for example, a constant temperature bath control circuit of the circuit device 500. As the

temperature sensors

460 and 462, for example, thermistors, diodes, and the like can be used.

In fig. 32, since temperature adjustment of oscillator 420 and the like can be achieved by the oven having the double oven structure, stabilization of the oscillation frequency of oscillator 420 and the like can be achieved.

Fig. 33 shows an example of a configuration of a base station (base station apparatus) which is one of electronic devices. The physical layer circuit 600 performs a physical layer process in a communication process via a network. The network processor 602 performs processing (link layer and the like) at a higher layer than the physical layer. The switch section 604 performs various kinds of switching processing of communication processing. The DSP606 performs various digital signal processing required for communication processing. The RF circuit 608 includes: a receiving circuit composed of a Low Noise Amplifier (LNA); a transmission circuit including a power amplifier; d/a converters, a/D converters, and the like.

The selector 612 outputs any one of the reference signal RFCK1 from the GPS 610 and the reference signal RFCK2 (clock signal from the network) from the physical layer circuit 600 to the circuit device 500 of the present embodiment as the reference signal RFCK. The circuit device 500 performs a process of synchronizing an oscillation signal (an input signal based on the oscillation signal) with the reference signal RFCK. Further, various clock signals CK1, CK2, CK3, CK4, and CK5 having different frequencies are generated and supplied to the physical layer circuit 600, the network processor 602, the switch section 604, the DSP606, and the RF circuit 608.

According to the circuit device 500 of the present embodiment, in the base station shown in fig. 33, the oscillation signal is synchronized with the reference signal RFCK, and the clock signals CK1 to CK5 having high frequency stability generated from the oscillation signal can be supplied to the respective circuits of the base station.

While the present embodiment has been described in detail, those skilled in the art will readily appreciate that many modifications are possible without materially departing from the novel teachings and advantages of this invention. Therefore, all such modifications are included in the scope of the present invention. For example, in the specification or the drawings, a term (temperature fluctuation component or the like) described at least once together with a different term (environmental fluctuation component or the like) having a broader meaning or the same meaning may be replaced with the different term in any part of the specification or the drawings. All combinations of the embodiment and the modifications are also included in the scope of the present invention. Further, the configuration and operation of the circuit device, the oscillator, the electronic apparatus, the moving object, the circuit block, the terminal arrangement method, the aging correction process, the kalman filter process, the hold mode process, the temperature compensation process, and the like are not limited to those described in the present embodiment, and various modifications can be made.

Claims

1. A circuit arrangement, wherein the circuit arrangement comprises:

a digital interface section;

a processing unit connected to the digital interface unit;

an oscillation signal generation circuit that generates an oscillation signal using an oscillator and data from the processing unit;

a clock signal generation circuit that generates a clock signal having a frequency obtained by multiplying an oscillation frequency of the oscillation signal;

a terminal group for connection of the digital interface unit, wherein the terminal group for connection of the digital interface unit is disposed in a1 st region along a1 st side of a circuit device, where a side of the circuit device intersecting the 1 st side is a2 nd side, a side opposite to the 1 st side is a3 rd side, and a side opposite to the 2 nd side is a4 th side; and

and a terminal group for connection of the clock signal generation circuit, which is disposed in any one of a2 nd region along the 2 nd side, a3 rd region along the 3 rd side, and a4 th region along the 4 th side.

2. The circuit arrangement of claim 1,

the circuit device further includes a terminal group for connection of the oscillation signal generation circuit, which is disposed in the 2 nd region.

3. The circuit arrangement of claim 2,

the terminal group for connection of the clock signal generation circuit is disposed in the 3 rd region.

4. The circuit arrangement of claim 1,

the 1 st side is a short side of the circuit device.

5. The circuit arrangement of claim 2,

when a distance between a terminal group for connection of the digital interface unit and a terminal group for connection of the oscillation signal generation circuit is L12, a distance between the terminal group for connection of the digital interface unit and a terminal group for connection of the clock signal generation circuit is L13, and a distance between the terminal group for connection of the oscillation signal generation circuit and the terminal group for connection of the clock signal generation circuit is L23, at least one of L12 and L13 is longer than L23.

6. The circuit arrangement of claim 1,

frequency control data from an external device that compares an input signal based on the oscillation signal with a reference signal is input to the processing unit via the digital interface unit and a terminal group for connection of the digital interface unit,

the processing unit performs signal processing on the frequency control data and outputs the processed frequency control data,

the oscillation signal generation circuit generates the oscillation signal according to the processed frequency control data.

7. The circuit arrangement of claim 6,

the circuit device further includes a phase comparison section that compares a phase of an input signal based on the oscillation signal with a phase of the reference signal,

the oscillation signal generation circuit generates the oscillation signal in accordance with the frequency control data from the external device in a1 st mode,

the oscillation signal generation circuit generates the oscillation signal based on the frequency control data from the phase comparison unit in the 2 nd mode.

8. The circuit arrangement of claim 1,

the digital interface section is a 2-wire, 3-wire or 4-wire serial interface circuit including a serial data line and a serial clock line.

9. The circuit arrangement of claim 1,

the processing unit is disposed between the 1 st region and the clock signal generation circuit.

10. The circuit arrangement according to claim 9,

the oscillation signal generation circuit is disposed between the processing unit and the clock signal generation circuit.

11. The circuit arrangement of claim 1,

the circuit device further includes a terminal group including a thermostat control terminal of a thermostat-type oscillator including the vibrator and the thermostat, the terminal group being disposed in the 4 th region.

12. The circuit arrangement of claim 11,

the circuit device further includes a constant temperature bath control circuit connected to the constant temperature bath control terminal and configured to control the constant temperature bath of the constant temperature bath oscillator.

13. The circuit arrangement of claim 12,

the oscillation signal generation circuit includes an oscillation circuit disposed between the thermostatic bath control circuit and the 2 nd zone.

14. An oscillator, wherein the oscillator comprises a vibrator and a circuit arrangement,

the circuit device comprises:

a digital interface section;

a processing unit connected to the digital interface unit;

15. An electronic device, wherein the electronic device comprises the circuit arrangement of claim 1.

16. A moving body comprising the circuit device according to claim 1.